Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.06 99.10 100.00 99.80 99.68 100.00


Total test records in report: 970
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T767 /workspace/coverage/default/45.gpio_random_dout_din.1378532801 Dec 31 12:25:56 PM PST 23 Dec 31 12:26:05 PM PST 23 65786459 ps
T768 /workspace/coverage/default/49.gpio_alert_test.3232527954 Dec 31 12:28:02 PM PST 23 Dec 31 12:28:18 PM PST 23 35231238 ps
T769 /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.647068076 Dec 31 12:27:27 PM PST 23 Dec 31 12:27:29 PM PST 23 39073428 ps
T770 /workspace/coverage/default/33.gpio_stress_all.4053282588 Dec 31 12:25:24 PM PST 23 Dec 31 12:28:33 PM PST 23 28612760713 ps
T771 /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.324665738 Dec 31 12:25:16 PM PST 23 Dec 31 12:25:26 PM PST 23 136986686 ps
T772 /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.560751525 Dec 31 12:25:06 PM PST 23 Dec 31 12:27:07 PM PST 23 36041742989 ps
T773 /workspace/coverage/default/18.gpio_rand_intr_trigger.2668176992 Dec 31 12:24:35 PM PST 23 Dec 31 12:24:44 PM PST 23 286723353 ps
T774 /workspace/coverage/default/30.gpio_alert_test.1295655791 Dec 31 12:28:00 PM PST 23 Dec 31 12:28:07 PM PST 23 41276260 ps
T775 /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1533671665 Dec 31 12:27:49 PM PST 23 Dec 31 12:27:55 PM PST 23 64550511 ps
T776 /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1659702788 Dec 31 12:25:04 PM PST 23 Dec 31 12:25:11 PM PST 23 96826942 ps
T777 /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2797365818 Dec 31 12:22:21 PM PST 23 Dec 31 12:22:24 PM PST 23 346866084 ps
T778 /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1243669333 Dec 31 12:25:35 PM PST 23 Dec 31 12:25:47 PM PST 23 1144909517 ps
T779 /workspace/coverage/default/5.gpio_full_random.3559820833 Dec 31 12:23:25 PM PST 23 Dec 31 12:23:27 PM PST 23 63841023 ps
T780 /workspace/coverage/default/6.gpio_stress_all.2568023407 Dec 31 12:20:45 PM PST 23 Dec 31 12:21:40 PM PST 23 4881535047 ps
T781 /workspace/coverage/default/28.gpio_full_random.2217884320 Dec 31 12:26:26 PM PST 23 Dec 31 12:26:28 PM PST 23 51831140 ps
T782 /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.62208404 Dec 31 12:24:44 PM PST 23 Dec 31 12:25:01 PM PST 23 91865996 ps
T783 /workspace/coverage/default/18.gpio_random_dout_din.2462887519 Dec 31 12:24:45 PM PST 23 Dec 31 12:24:54 PM PST 23 157114120 ps
T784 /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1643904389 Dec 31 12:24:57 PM PST 23 Dec 31 12:25:02 PM PST 23 56028679 ps
T785 /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3022729271 Dec 31 12:25:13 PM PST 23 Dec 31 12:25:20 PM PST 23 6589927953 ps
T786 /workspace/coverage/default/13.gpio_full_random.3878464448 Dec 31 12:24:12 PM PST 23 Dec 31 12:24:16 PM PST 23 308224858 ps
T787 /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1927394828 Dec 31 12:26:35 PM PST 23 Dec 31 12:26:38 PM PST 23 124394414 ps
T788 /workspace/coverage/default/40.gpio_filter_stress.1675316685 Dec 31 12:26:46 PM PST 23 Dec 31 12:27:06 PM PST 23 2218817847 ps
T789 /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.21784560 Dec 31 12:25:30 PM PST 23 Dec 31 12:25:39 PM PST 23 75497827 ps
T790 /workspace/coverage/default/39.gpio_full_random.380452846 Dec 31 12:26:10 PM PST 23 Dec 31 12:26:15 PM PST 23 74775808 ps
T791 /workspace/coverage/default/46.gpio_filter_stress.1365752245 Dec 31 12:25:49 PM PST 23 Dec 31 12:26:17 PM PST 23 550872731 ps
T792 /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.754605992 Dec 31 12:25:01 PM PST 23 Dec 31 12:25:08 PM PST 23 185880383 ps
T793 /workspace/coverage/default/11.gpio_random_dout_din.1351536909 Dec 31 12:24:56 PM PST 23 Dec 31 12:25:00 PM PST 23 21749001 ps
T794 /workspace/coverage/default/8.gpio_stress_all.2024315420 Dec 31 12:26:08 PM PST 23 Dec 31 12:27:57 PM PST 23 15801467364 ps
T795 /workspace/coverage/default/21.gpio_random_dout_din.1295980979 Dec 31 12:24:39 PM PST 23 Dec 31 12:24:47 PM PST 23 89805814 ps
T796 /workspace/coverage/default/41.gpio_intr_rand_pgm.3763716983 Dec 31 12:25:25 PM PST 23 Dec 31 12:25:32 PM PST 23 47682227 ps
T797 /workspace/coverage/default/40.gpio_rand_intr_trigger.616074035 Dec 31 12:26:51 PM PST 23 Dec 31 12:26:55 PM PST 23 246656942 ps
T798 /workspace/coverage/default/19.gpio_intr_rand_pgm.2903602003 Dec 31 12:25:40 PM PST 23 Dec 31 12:25:54 PM PST 23 56762449 ps
T799 /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3832564297 Dec 31 12:25:48 PM PST 23 Dec 31 12:25:58 PM PST 23 65209004 ps
T800 /workspace/coverage/default/2.gpio_intr_rand_pgm.1330866769 Dec 31 12:24:02 PM PST 23 Dec 31 12:24:09 PM PST 23 192443298 ps
T801 /workspace/coverage/default/9.gpio_stress_all.2999118748 Dec 31 12:23:58 PM PST 23 Dec 31 12:25:34 PM PST 23 6713236132 ps
T802 /workspace/coverage/default/29.gpio_smoke.2903018212 Dec 31 12:25:11 PM PST 23 Dec 31 12:25:16 PM PST 23 36053258 ps
T803 /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3035742817 Dec 31 12:26:44 PM PST 23 Dec 31 12:26:49 PM PST 23 267732595 ps
T804 /workspace/coverage/default/45.gpio_alert_test.3989811041 Dec 31 12:27:13 PM PST 23 Dec 31 12:27:15 PM PST 23 33055652 ps
T805 /workspace/coverage/default/20.gpio_alert_test.1920085143 Dec 31 12:24:37 PM PST 23 Dec 31 12:24:46 PM PST 23 40132540 ps
T806 /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.4103142453 Dec 31 12:26:13 PM PST 23 Dec 31 12:26:17 PM PST 23 112990355 ps
T807 /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1166126388 Dec 31 12:24:50 PM PST 23 Dec 31 12:24:56 PM PST 23 32852391 ps
T808 /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3992504114 Dec 31 12:26:16 PM PST 23 Dec 31 12:26:20 PM PST 23 204832862 ps
T809 /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2459449123 Dec 31 12:24:36 PM PST 23 Dec 31 12:24:45 PM PST 23 43405823 ps
T810 /workspace/coverage/default/45.gpio_smoke.4095320977 Dec 31 12:27:05 PM PST 23 Dec 31 12:27:08 PM PST 23 40892915 ps
T811 /workspace/coverage/default/35.gpio_full_random.765781932 Dec 31 12:26:10 PM PST 23 Dec 31 12:26:15 PM PST 23 62339276 ps
T812 /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3777947556 Dec 31 12:25:20 PM PST 23 Dec 31 12:25:24 PM PST 23 40474507 ps
T813 /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3728577152 Dec 31 12:27:18 PM PST 23 Dec 31 12:27:23 PM PST 23 185630632 ps
T814 /workspace/coverage/default/16.gpio_filter_stress.3826352165 Dec 31 12:25:01 PM PST 23 Dec 31 12:25:14 PM PST 23 1507154521 ps
T66 /workspace/coverage/default/2.gpio_sec_cm.4196989324 Dec 31 12:24:10 PM PST 23 Dec 31 12:24:15 PM PST 23 215677715 ps
T815 /workspace/coverage/default/0.gpio_stress_all.1628619085 Dec 31 12:24:19 PM PST 23 Dec 31 12:27:12 PM PST 23 47275815248 ps
T816 /workspace/coverage/default/3.gpio_random_dout_din.3669892561 Dec 31 12:24:35 PM PST 23 Dec 31 12:24:44 PM PST 23 216960989 ps
T817 /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3692009717 Dec 31 12:26:09 PM PST 23 Dec 31 12:26:14 PM PST 23 55684579 ps
T818 /workspace/coverage/default/8.gpio_full_random.1818946361 Dec 31 12:24:55 PM PST 23 Dec 31 12:25:00 PM PST 23 51567195 ps
T819 /workspace/coverage/default/2.gpio_stress_all.56776698 Dec 31 12:24:34 PM PST 23 Dec 31 12:25:30 PM PST 23 6918664318 ps
T820 /workspace/coverage/default/49.gpio_smoke.809059672 Dec 31 12:26:25 PM PST 23 Dec 31 12:26:27 PM PST 23 170696144 ps
T821 /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1773973625 Dec 31 12:27:06 PM PST 23 Dec 31 12:27:09 PM PST 23 103354557 ps
T822 /workspace/coverage/default/26.gpio_alert_test.2004446328 Dec 31 12:26:16 PM PST 23 Dec 31 12:26:19 PM PST 23 39548250 ps
T823 /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1695060152 Dec 31 12:27:26 PM PST 23 Dec 31 12:27:32 PM PST 23 125466539 ps
T824 /workspace/coverage/default/32.gpio_intr_rand_pgm.933436429 Dec 31 12:26:03 PM PST 23 Dec 31 12:26:10 PM PST 23 224193086 ps
T825 /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1664765027 Dec 31 12:25:55 PM PST 23 Dec 31 12:26:05 PM PST 23 701784294 ps
T826 /workspace/coverage/default/12.gpio_smoke.3175757794 Dec 31 12:27:00 PM PST 23 Dec 31 12:27:03 PM PST 23 36777583 ps
T827 /workspace/coverage/default/31.gpio_full_random.804162476 Dec 31 12:25:10 PM PST 23 Dec 31 12:25:17 PM PST 23 145169494 ps
T828 /workspace/coverage/default/25.gpio_random_dout_din.1172908687 Dec 31 12:25:21 PM PST 23 Dec 31 12:25:27 PM PST 23 100084995 ps
T829 /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2327673727 Dec 31 12:24:54 PM PST 23 Dec 31 12:25:00 PM PST 23 104671108 ps
T830 /workspace/coverage/default/18.gpio_full_random.2605257401 Dec 31 12:24:33 PM PST 23 Dec 31 12:24:42 PM PST 23 45325259 ps
T831 /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2624846590 Dec 31 12:25:55 PM PST 23 Dec 31 12:26:04 PM PST 23 220781274 ps
T832 /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2432626179 Dec 31 12:25:32 PM PST 23 Dec 31 12:28:40 PM PST 23 13340287139 ps
T833 /workspace/coverage/default/4.gpio_filter_stress.1447514844 Dec 31 12:26:08 PM PST 23 Dec 31 12:26:37 PM PST 23 1763960853 ps
T834 /workspace/coverage/default/29.gpio_intr_rand_pgm.1313132703 Dec 31 12:25:45 PM PST 23 Dec 31 12:25:54 PM PST 23 223061837 ps
T835 /workspace/coverage/default/10.gpio_rand_intr_trigger.903371684 Dec 31 12:24:31 PM PST 23 Dec 31 12:24:35 PM PST 23 212360463 ps
T836 /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.169389928 Dec 31 12:27:33 PM PST 23 Dec 31 12:27:34 PM PST 23 68773784 ps
T837 /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3481733594 Dec 31 12:27:41 PM PST 23 Dec 31 12:27:43 PM PST 23 72131944 ps
T838 /workspace/coverage/default/22.gpio_full_random.745838305 Dec 31 12:26:12 PM PST 23 Dec 31 12:26:16 PM PST 23 671485634 ps
T839 /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.989526765 Dec 31 12:25:03 PM PST 23 Dec 31 12:25:08 PM PST 23 76242168 ps
T840 /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2617740858 Dec 31 12:26:48 PM PST 23 Dec 31 12:26:51 PM PST 23 524305764 ps
T841 /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3847496039 Dec 31 12:25:45 PM PST 23 Dec 31 12:25:54 PM PST 23 27377211 ps
T842 /workspace/coverage/default/35.gpio_filter_stress.1824342223 Dec 31 12:26:20 PM PST 23 Dec 31 12:26:51 PM PST 23 3967454350 ps
T843 /workspace/coverage/default/43.gpio_filter_stress.263212497 Dec 31 12:25:35 PM PST 23 Dec 31 12:25:51 PM PST 23 168427361 ps
T844 /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1207788722 Dec 31 12:26:52 PM PST 23 Dec 31 12:26:55 PM PST 23 373922021 ps
T845 /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1372617665 Dec 31 12:27:04 PM PST 23 Dec 31 12:27:07 PM PST 23 58506198 ps
T846 /workspace/coverage/default/48.gpio_alert_test.2630026591 Dec 31 12:26:31 PM PST 23 Dec 31 12:26:36 PM PST 23 35362464 ps
T847 /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.945432395 Dec 31 12:25:40 PM PST 23 Dec 31 12:25:49 PM PST 23 77571589 ps
T848 /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1458595055 Dec 31 12:26:32 PM PST 23 Dec 31 12:26:35 PM PST 23 18492610 ps
T849 /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3337196873 Dec 31 12:25:15 PM PST 23 Dec 31 12:25:21 PM PST 23 69303120 ps
T850 /workspace/coverage/default/26.gpio_stress_all.3309200668 Dec 31 12:25:15 PM PST 23 Dec 31 12:28:15 PM PST 23 126726038717 ps
T851 /workspace/coverage/default/39.gpio_rand_intr_trigger.664232515 Dec 31 12:25:50 PM PST 23 Dec 31 12:26:00 PM PST 23 184762219 ps
T852 /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2102496849 Dec 31 12:24:28 PM PST 23 Dec 31 12:24:31 PM PST 23 32874443 ps
T853 /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.4188483857 Dec 31 12:25:37 PM PST 23 Dec 31 12:25:45 PM PST 23 38982258 ps
T854 /workspace/coverage/default/16.gpio_intr_rand_pgm.4287781125 Dec 31 12:25:17 PM PST 23 Dec 31 12:25:22 PM PST 23 22801539 ps
T855 /workspace/coverage/default/15.gpio_alert_test.3490518285 Dec 31 12:25:03 PM PST 23 Dec 31 12:25:12 PM PST 23 26125527 ps
T856 /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3083323771 Dec 31 12:25:44 PM PST 23 Dec 31 12:25:53 PM PST 23 20126519 ps
T857 /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1716011641 Dec 31 12:22:56 PM PST 23 Dec 31 12:23:02 PM PST 23 868527993 ps
T858 /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2419592152 Dec 31 12:28:16 PM PST 23 Dec 31 12:28:19 PM PST 23 195460600 ps
T859 /workspace/coverage/default/32.gpio_stress_all.3020967963 Dec 31 12:26:40 PM PST 23 Dec 31 12:27:39 PM PST 23 5421336864 ps
T860 /workspace/coverage/default/44.gpio_alert_test.3965883291 Dec 31 12:26:01 PM PST 23 Dec 31 12:26:07 PM PST 23 17202970 ps
T861 /workspace/coverage/default/15.gpio_rand_intr_trigger.2900572941 Dec 31 12:24:53 PM PST 23 Dec 31 12:25:00 PM PST 23 147439987 ps
T862 /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3403507472 Dec 31 12:25:23 PM PST 23 Dec 31 12:25:32 PM PST 23 155759652 ps
T863 /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3600198113 Dec 31 12:25:25 PM PST 23 Dec 31 12:35:50 PM PST 23 241113001744 ps
T864 /workspace/coverage/default/6.gpio_intr_rand_pgm.1874785824 Dec 31 12:23:21 PM PST 23 Dec 31 12:23:23 PM PST 23 340911191 ps
T865 /workspace/coverage/default/19.gpio_full_random.3156745808 Dec 31 12:25:01 PM PST 23 Dec 31 12:25:05 PM PST 23 25086652 ps
T866 /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3169221411 Dec 31 12:25:41 PM PST 23 Dec 31 12:25:51 PM PST 23 179825927 ps
T867 /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.948386302 Dec 31 12:25:40 PM PST 23 Dec 31 12:25:53 PM PST 23 405515219 ps
T868 /workspace/coverage/default/2.gpio_random_dout_din.3823167680 Dec 31 12:26:44 PM PST 23 Dec 31 12:26:51 PM PST 23 239414446 ps
T869 /workspace/coverage/default/48.gpio_smoke.4060769817 Dec 31 12:26:05 PM PST 23 Dec 31 12:26:12 PM PST 23 110549708 ps
T870 /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1875850078 Dec 31 12:26:22 PM PST 23 Dec 31 12:26:24 PM PST 23 40389454 ps
T871 /workspace/coverage/default/45.gpio_full_random.4046158932 Dec 31 12:27:10 PM PST 23 Dec 31 12:27:12 PM PST 23 483008524 ps
T872 /workspace/coverage/default/36.gpio_intr_rand_pgm.1931951231 Dec 31 12:25:43 PM PST 23 Dec 31 12:25:53 PM PST 23 436704184 ps
T873 /workspace/coverage/default/19.gpio_rand_intr_trigger.1549417032 Dec 31 12:24:56 PM PST 23 Dec 31 12:25:02 PM PST 23 320787574 ps
T874 /workspace/coverage/default/7.gpio_smoke.1581232449 Dec 31 12:25:13 PM PST 23 Dec 31 12:25:17 PM PST 23 156864234 ps
T875 /workspace/coverage/default/44.gpio_smoke.3407311262 Dec 31 12:25:58 PM PST 23 Dec 31 12:26:06 PM PST 23 1208069000 ps
T876 /workspace/coverage/default/3.gpio_alert_test.4209412301 Dec 31 12:24:02 PM PST 23 Dec 31 12:24:09 PM PST 23 12874419 ps
T877 /workspace/coverage/default/8.gpio_filter_stress.2913221502 Dec 31 12:23:18 PM PST 23 Dec 31 12:23:31 PM PST 23 1016935073 ps
T878 /workspace/coverage/default/40.gpio_full_random.1305611448 Dec 31 12:27:36 PM PST 23 Dec 31 12:27:37 PM PST 23 80257132 ps
T879 /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3096277107 Dec 31 12:25:54 PM PST 23 Dec 31 12:26:04 PM PST 23 58888644 ps
T880 /workspace/coverage/default/36.gpio_alert_test.2576989156 Dec 31 12:27:06 PM PST 23 Dec 31 12:27:09 PM PST 23 15150855 ps
T881 /workspace/coverage/default/33.gpio_smoke.940324617 Dec 31 12:25:50 PM PST 23 Dec 31 12:25:59 PM PST 23 168557386 ps
T882 /workspace/coverage/default/4.gpio_smoke.2316744263 Dec 31 12:18:44 PM PST 23 Dec 31 12:18:46 PM PST 23 184502212 ps
T883 /workspace/coverage/default/12.gpio_full_random.1283427915 Dec 31 12:26:17 PM PST 23 Dec 31 12:26:20 PM PST 23 97694031 ps
T884 /workspace/coverage/default/17.gpio_intr_rand_pgm.2810360625 Dec 31 12:25:08 PM PST 23 Dec 31 12:25:13 PM PST 23 294884272 ps
T885 /workspace/coverage/default/2.gpio_alert_test.2770342499 Dec 31 12:24:00 PM PST 23 Dec 31 12:24:08 PM PST 23 15455942 ps
T886 /workspace/coverage/default/43.gpio_random_dout_din.2087091474 Dec 31 12:25:32 PM PST 23 Dec 31 12:25:39 PM PST 23 101143061 ps
T887 /workspace/coverage/default/40.gpio_stress_all.1390851429 Dec 31 12:25:53 PM PST 23 Dec 31 12:27:39 PM PST 23 8200086681 ps
T888 /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2503068970 Dec 31 12:26:59 PM PST 23 Dec 31 12:35:59 PM PST 23 148753377158 ps
T889 /workspace/coverage/default/42.gpio_filter_stress.2894202246 Dec 31 12:26:03 PM PST 23 Dec 31 12:26:12 PM PST 23 148542455 ps
T890 /workspace/coverage/default/23.gpio_smoke.2856627339 Dec 31 12:26:10 PM PST 23 Dec 31 12:26:16 PM PST 23 160478501 ps
T891 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.4146177809 Dec 31 12:26:04 PM PST 23 Dec 31 12:26:11 PM PST 23 1582679223 ps
T892 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2585641194 Dec 31 12:19:24 PM PST 23 Dec 31 12:19:26 PM PST 23 18412361 ps
T41 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1651258374 Dec 31 12:24:02 PM PST 23 Dec 31 12:24:09 PM PST 23 185065192 ps
T42 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3003991272 Dec 31 12:23:03 PM PST 23 Dec 31 12:23:05 PM PST 23 373434022 ps
T893 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.4270378746 Dec 31 12:20:58 PM PST 23 Dec 31 12:21:00 PM PST 23 174383703 ps
T894 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1433187367 Dec 31 12:20:15 PM PST 23 Dec 31 12:20:17 PM PST 23 57833586 ps
T895 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.557753757 Dec 31 12:24:30 PM PST 23 Dec 31 12:24:33 PM PST 23 49302169 ps
T36 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1474548139 Dec 31 12:23:03 PM PST 23 Dec 31 12:23:05 PM PST 23 80704938 ps
T896 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.247229623 Dec 31 12:22:32 PM PST 23 Dec 31 12:22:33 PM PST 23 135645295 ps
T897 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3568516694 Dec 31 12:25:41 PM PST 23 Dec 31 12:25:51 PM PST 23 19926770 ps
T898 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.162309134 Dec 31 12:24:40 PM PST 23 Dec 31 12:24:47 PM PST 23 99645627 ps
T899 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1844279740 Dec 31 12:24:05 PM PST 23 Dec 31 12:24:11 PM PST 23 32903073 ps
T900 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1813731796 Dec 31 12:25:30 PM PST 23 Dec 31 12:25:38 PM PST 23 13733750 ps
T901 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2652149753 Dec 31 12:17:46 PM PST 23 Dec 31 12:17:48 PM PST 23 17280843 ps
T902 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1678698650 Dec 31 12:18:10 PM PST 23 Dec 31 12:18:11 PM PST 23 26450309 ps
T903 /workspace/coverage/cover_reg_top/6.gpio_intr_test.857244678 Dec 31 12:28:46 PM PST 23 Dec 31 12:28:53 PM PST 23 21143786 ps
T904 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2627547582 Dec 31 12:18:07 PM PST 23 Dec 31 12:18:08 PM PST 23 116769522 ps
T905 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1726672325 Dec 31 12:22:18 PM PST 23 Dec 31 12:22:19 PM PST 23 59431868 ps
T906 /workspace/coverage/cover_reg_top/30.gpio_intr_test.348548770 Dec 31 12:26:10 PM PST 23 Dec 31 12:26:15 PM PST 23 223680348 ps
T907 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.929552947 Dec 31 12:18:05 PM PST 23 Dec 31 12:18:07 PM PST 23 197962261 ps
T908 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3963624679 Dec 31 12:23:31 PM PST 23 Dec 31 12:23:37 PM PST 23 43019233 ps
T909 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3795747003 Dec 31 12:24:38 PM PST 23 Dec 31 12:24:46 PM PST 23 17611249 ps
T910 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.485183346 Dec 31 12:24:24 PM PST 23 Dec 31 12:24:28 PM PST 23 33682832 ps
T911 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.270456862 Dec 31 12:22:10 PM PST 23 Dec 31 12:22:13 PM PST 23 185850223 ps
T912 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.902824327 Dec 31 12:25:13 PM PST 23 Dec 31 12:25:16 PM PST 23 15420365 ps
T913 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2066687443 Dec 31 12:24:19 PM PST 23 Dec 31 12:24:22 PM PST 23 23559225 ps
T914 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2509430553 Dec 31 12:24:53 PM PST 23 Dec 31 12:25:00 PM PST 23 140097620 ps
T915 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4249071332 Dec 31 12:22:32 PM PST 23 Dec 31 12:22:34 PM PST 23 25088472 ps
T86 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2751157158 Dec 31 12:19:08 PM PST 23 Dec 31 12:19:09 PM PST 23 45064974 ps
T87 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.55039296 Dec 31 12:23:28 PM PST 23 Dec 31 12:23:31 PM PST 23 16623396 ps
T88 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.4064128325 Dec 31 12:23:03 PM PST 23 Dec 31 12:23:04 PM PST 23 145093842 ps
T110 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2915315103 Dec 31 12:22:31 PM PST 23 Dec 31 12:22:33 PM PST 23 150518262 ps
T916 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.461092002 Dec 31 12:24:02 PM PST 23 Dec 31 12:24:09 PM PST 23 128337496 ps
T917 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3144699975 Dec 31 12:23:25 PM PST 23 Dec 31 12:23:27 PM PST 23 59327489 ps
T918 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3388826662 Dec 31 12:22:56 PM PST 23 Dec 31 12:22:59 PM PST 23 174221681 ps
T111 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.603793207 Dec 31 12:21:48 PM PST 23 Dec 31 12:21:51 PM PST 23 379271513 ps
T919 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1036671800 Dec 31 12:24:08 PM PST 23 Dec 31 12:24:14 PM PST 23 40437681 ps
T920 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1107593923 Dec 31 12:24:03 PM PST 23 Dec 31 12:24:11 PM PST 23 23401137 ps
T921 /workspace/coverage/cover_reg_top/32.gpio_intr_test.1583064036 Dec 31 12:26:05 PM PST 23 Dec 31 12:26:11 PM PST 23 98876948 ps
T922 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1448125068 Dec 31 12:23:03 PM PST 23 Dec 31 12:23:05 PM PST 23 68067124 ps
T923 /workspace/coverage/cover_reg_top/38.gpio_intr_test.1419940075 Dec 31 12:26:10 PM PST 23 Dec 31 12:26:15 PM PST 23 39287615 ps
T924 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2296611392 Dec 31 12:25:49 PM PST 23 Dec 31 12:25:58 PM PST 23 38503056 ps
T925 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3756048759 Dec 31 12:25:07 PM PST 23 Dec 31 12:25:13 PM PST 23 157612862 ps
T43 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1245655207 Dec 31 12:21:34 PM PST 23 Dec 31 12:21:38 PM PST 23 131219900 ps
T926 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3788698396 Dec 31 12:24:21 PM PST 23 Dec 31 12:24:26 PM PST 23 10761569 ps
T927 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1995847963 Dec 31 12:24:14 PM PST 23 Dec 31 12:24:18 PM PST 23 14441856 ps
T928 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2337746862 Dec 31 12:23:19 PM PST 23 Dec 31 12:23:22 PM PST 23 280065959 ps
T929 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.489924918 Dec 31 12:25:56 PM PST 23 Dec 31 12:26:04 PM PST 23 254603548 ps
T930 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2237733011 Dec 31 12:22:32 PM PST 23 Dec 31 12:22:33 PM PST 23 35431174 ps
T931 /workspace/coverage/cover_reg_top/16.gpio_intr_test.2565860140 Dec 31 12:26:01 PM PST 23 Dec 31 12:26:08 PM PST 23 34048843 ps
T89 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1198067529 Dec 31 12:25:54 PM PST 23 Dec 31 12:26:02 PM PST 23 11731127 ps
T932 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3933007777 Dec 31 12:19:24 PM PST 23 Dec 31 12:19:26 PM PST 23 88245469 ps
T933 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1545880117 Dec 31 12:23:28 PM PST 23 Dec 31 12:23:32 PM PST 23 400037575 ps
T934 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3599258106 Dec 31 12:24:41 PM PST 23 Dec 31 12:24:50 PM PST 23 78955683 ps
T935 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.709255582 Dec 31 12:27:06 PM PST 23 Dec 31 12:27:13 PM PST 23 60115484 ps
T90 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1272114572 Dec 31 12:19:16 PM PST 23 Dec 31 12:19:18 PM PST 23 51056537 ps
T936 /workspace/coverage/cover_reg_top/42.gpio_intr_test.1612394067 Dec 31 12:23:36 PM PST 23 Dec 31 12:23:41 PM PST 23 14816398 ps
T937 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1855992372 Dec 31 12:20:58 PM PST 23 Dec 31 12:20:59 PM PST 23 21261169 ps
T938 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3908484882 Dec 31 12:26:12 PM PST 23 Dec 31 12:26:16 PM PST 23 62086295 ps
T939 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3129485182 Dec 31 12:24:40 PM PST 23 Dec 31 12:24:49 PM PST 23 453911689 ps
T940 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2368198737 Dec 31 12:26:02 PM PST 23 Dec 31 12:26:09 PM PST 23 274487525 ps
T91 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1154901123 Dec 31 12:20:44 PM PST 23 Dec 31 12:20:45 PM PST 23 49227806 ps
T941 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1385234196 Dec 31 12:26:02 PM PST 23 Dec 31 12:26:09 PM PST 23 534004470 ps
T942 /workspace/coverage/cover_reg_top/1.gpio_intr_test.4049437524 Dec 31 12:24:19 PM PST 23 Dec 31 12:24:22 PM PST 23 16336076 ps
T943 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1170558136 Dec 31 12:22:32 PM PST 23 Dec 31 12:22:34 PM PST 23 420111177 ps
T944 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2608919736 Dec 31 12:27:07 PM PST 23 Dec 31 12:27:10 PM PST 23 49598788 ps
T93 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1172020985 Dec 31 12:24:19 PM PST 23 Dec 31 12:24:22 PM PST 23 17542938 ps
T945 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1019238401 Dec 31 12:34:32 PM PST 23 Dec 31 12:34:35 PM PST 23 50462432 ps
T946 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2302976027 Dec 31 12:26:31 PM PST 23 Dec 31 12:26:36 PM PST 23 2082979657 ps
T947 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1405901835 Dec 31 12:20:15 PM PST 23 Dec 31 12:20:17 PM PST 23 361092497 ps
T948 /workspace/coverage/cover_reg_top/47.gpio_intr_test.4037657940 Dec 31 12:24:03 PM PST 23 Dec 31 12:24:10 PM PST 23 51805812 ps
T949 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.688658101 Dec 31 12:24:32 PM PST 23 Dec 31 12:24:40 PM PST 23 102999712 ps
T950 /workspace/coverage/cover_reg_top/34.gpio_intr_test.4031282184 Dec 31 12:34:37 PM PST 23 Dec 31 12:34:40 PM PST 23 11902754 ps
T951 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3428209766 Dec 31 12:20:55 PM PST 23 Dec 31 12:20:56 PM PST 23 21348887 ps
T952 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1613923949 Dec 31 12:22:56 PM PST 23 Dec 31 12:22:58 PM PST 23 105858446 ps
T953 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3157760654 Dec 31 12:21:47 PM PST 23 Dec 31 12:21:49 PM PST 23 24406149 ps
T954 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1455780055 Dec 31 12:24:19 PM PST 23 Dec 31 12:24:22 PM PST 23 19296365 ps
T955 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.140898482 Dec 31 12:26:36 PM PST 23 Dec 31 12:26:40 PM PST 23 21662546 ps
T94 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.330975362 Dec 31 12:26:32 PM PST 23 Dec 31 12:26:34 PM PST 23 27395139 ps
T956 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2423724654 Dec 31 12:26:27 PM PST 23 Dec 31 12:26:29 PM PST 23 13288140 ps
T103 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3494287906 Dec 31 12:24:14 PM PST 23 Dec 31 12:24:18 PM PST 23 55162971 ps
T957 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.17652927 Dec 31 12:24:02 PM PST 23 Dec 31 12:24:11 PM PST 23 66119008 ps
T958 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3702295342 Dec 31 12:22:54 PM PST 23 Dec 31 12:22:56 PM PST 23 23961732 ps
T959 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1567379446 Dec 31 12:20:21 PM PST 23 Dec 31 12:20:25 PM PST 23 1258018435 ps
T960 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2744731364 Dec 31 12:20:09 PM PST 23 Dec 31 12:20:11 PM PST 23 22177364 ps
T961 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.142752700 Dec 31 12:34:32 PM PST 23 Dec 31 12:34:35 PM PST 23 53015053 ps
T962 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1918404433 Dec 31 12:23:31 PM PST 23 Dec 31 12:23:37 PM PST 23 13103112 ps
T963 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2260717958 Dec 31 12:25:12 PM PST 23 Dec 31 12:25:16 PM PST 23 61742866 ps
T964 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2687837385 Dec 31 12:27:49 PM PST 23 Dec 31 12:27:53 PM PST 23 35194517 ps
T965 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2790949658 Dec 31 12:25:19 PM PST 23 Dec 31 12:25:24 PM PST 23 44869551 ps
T966 /workspace/coverage/cover_reg_top/40.gpio_intr_test.720389500 Dec 31 12:23:36 PM PST 23 Dec 31 12:23:41 PM PST 23 37381278 ps
T967 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.790766995 Dec 31 12:24:41 PM PST 23 Dec 31 12:24:51 PM PST 23 97370352 ps
T968 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1545549465 Dec 31 12:22:07 PM PST 23 Dec 31 12:22:10 PM PST 23 24535887 ps
T969 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3509605551 Dec 31 12:26:01 PM PST 23 Dec 31 12:26:08 PM PST 23 83066286 ps
T970 /workspace/coverage/cover_reg_top/19.gpio_intr_test.871078446 Dec 31 12:19:20 PM PST 23 Dec 31 12:19:25 PM PST 23 13941079 ps

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.818578422
Short name T26
Test name
Test status
Simulation time 236205788 ps
CPU time 1.41 seconds
Started Dec 31 12:24:07 PM PST 23
Finished Dec 31 12:24:15 PM PST 23
Peak memory 198148 kb
Host smart-8be76a7a-4300-4f95-9ae8-7362fb69a4b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818578422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.818578422
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3712846941
Short name T46
Test name
Test status
Simulation time 249262022 ps
CPU time 1.09 seconds
Started Dec 31 12:24:42 PM PST 23
Finished Dec 31 12:24:52 PM PST 23
Peak memory 197480 kb
Host smart-d94072a6-d5ca-4c8f-8eab-78d7ba619d80
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3712846941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3712846941
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1282071220
Short name T48
Test name
Test status
Simulation time 138605737 ps
CPU time 2.63 seconds
Started Dec 31 12:27:21 PM PST 23
Finished Dec 31 12:27:25 PM PST 23
Peak memory 198124 kb
Host smart-941276c4-7c72-4bcc-926b-3f33e4171c67
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282071220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1282071220
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3662750072
Short name T74
Test name
Test status
Simulation time 36683200191 ps
CPU time 478.51 seconds
Started Dec 31 12:25:31 PM PST 23
Finished Dec 31 12:33:37 PM PST 23
Peak memory 198208 kb
Host smart-90527b78-7b81-4842-bc0b-625ba1360f15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3662750072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3662750072
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2759813644
Short name T4
Test name
Test status
Simulation time 88895827 ps
CPU time 1.92 seconds
Started Dec 31 12:22:10 PM PST 23
Finished Dec 31 12:22:13 PM PST 23
Peak memory 195696 kb
Host smart-c26cd312-b847-499e-8ab7-fbf8023a59e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759813644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2759813644
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3996518790
Short name T40
Test name
Test status
Simulation time 22738494 ps
CPU time 0.63 seconds
Started Dec 31 12:23:18 PM PST 23
Finished Dec 31 12:23:20 PM PST 23
Peak memory 195364 kb
Host smart-2ef278ce-9945-4e69-b59a-4691bb96e24d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996518790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3996518790
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.335877936
Short name T25
Test name
Test status
Simulation time 15372369 ps
CPU time 0.59 seconds
Started Dec 31 12:24:36 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 193900 kb
Host smart-5d0d5578-7ea3-4434-8375-4c62107a63b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335877936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.335877936
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2771774437
Short name T29
Test name
Test status
Simulation time 71366336 ps
CPU time 0.75 seconds
Started Dec 31 12:22:52 PM PST 23
Finished Dec 31 12:22:54 PM PST 23
Peak memory 213136 kb
Host smart-b1f6eb2b-e405-44aa-8797-3cc5fd509b64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771774437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2771774437
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.4100725766
Short name T2
Test name
Test status
Simulation time 325701020 ps
CPU time 1.15 seconds
Started Dec 31 12:25:49 PM PST 23
Finished Dec 31 12:25:59 PM PST 23
Peak memory 196812 kb
Host smart-b2962a84-2332-43a3-bef4-40b607c9ebb0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100725766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.4100725766
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.518645478
Short name T18
Test name
Test status
Simulation time 67722129 ps
CPU time 0.78 seconds
Started Dec 31 12:23:41 PM PST 23
Finished Dec 31 12:23:44 PM PST 23
Peak memory 195336 kb
Host smart-4c197acc-aecc-4b88-8adf-128d25089d7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518645478 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.518645478
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3390117731
Short name T45
Test name
Test status
Simulation time 91381456 ps
CPU time 1.37 seconds
Started Dec 31 12:24:08 PM PST 23
Finished Dec 31 12:24:15 PM PST 23
Peak memory 196396 kb
Host smart-5944cab8-c1b4-4d10-a367-a90b188b9fbc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3390117731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3390117731
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1651258374
Short name T41
Test name
Test status
Simulation time 185065192 ps
CPU time 0.94 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 196620 kb
Host smart-22d4d909-6eea-4cd5-aec8-b0e24136f11f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651258374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1651258374
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1066717724
Short name T257
Test name
Test status
Simulation time 14719913 ps
CPU time 0.6 seconds
Started Dec 31 12:26:37 PM PST 23
Finished Dec 31 12:26:40 PM PST 23
Peak memory 194116 kb
Host smart-1f8ff02b-1776-442c-984e-054e93a828d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066717724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1066717724
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.574611926
Short name T22
Test name
Test status
Simulation time 11855992 ps
CPU time 0.62 seconds
Started Dec 31 12:20:41 PM PST 23
Finished Dec 31 12:20:42 PM PST 23
Peak memory 193904 kb
Host smart-39dab3f4-d9bf-4144-acc7-e535fd20c91c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574611926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.574611926
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1145816205
Short name T33
Test name
Test status
Simulation time 33293892 ps
CPU time 1.16 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:22:59 PM PST 23
Peak memory 198104 kb
Host smart-901905d9-7a4a-4b29-897f-4c77913ec6d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145816205 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1145816205
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3206384959
Short name T9
Test name
Test status
Simulation time 101361210 ps
CPU time 0.87 seconds
Started Dec 31 12:22:10 PM PST 23
Finished Dec 31 12:22:12 PM PST 23
Peak memory 196240 kb
Host smart-33b166bd-32ad-4003-8040-922ac3af5fdf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206384959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3206384959
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2466783787
Short name T80
Test name
Test status
Simulation time 18211331 ps
CPU time 0.82 seconds
Started Dec 31 12:17:58 PM PST 23
Finished Dec 31 12:18:00 PM PST 23
Peak memory 196256 kb
Host smart-230f4c2a-56a9-41f8-aff3-3cd301bd6a16
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466783787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2466783787
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2302976027
Short name T946
Test name
Test status
Simulation time 2082979657 ps
CPU time 3.24 seconds
Started Dec 31 12:26:31 PM PST 23
Finished Dec 31 12:26:36 PM PST 23
Peak memory 196988 kb
Host smart-7e0eb70d-dafd-4227-af02-1bee7ebd7e8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302976027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2302976027
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1678698650
Short name T902
Test name
Test status
Simulation time 26450309 ps
CPU time 0.84 seconds
Started Dec 31 12:18:10 PM PST 23
Finished Dec 31 12:18:11 PM PST 23
Peak memory 198488 kb
Host smart-cbcf504a-7e6e-479b-adb9-3b6373909c13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678698650 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1678698650
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.709255582
Short name T935
Test name
Test status
Simulation time 60115484 ps
CPU time 0.59 seconds
Started Dec 31 12:27:06 PM PST 23
Finished Dec 31 12:27:13 PM PST 23
Peak memory 195004 kb
Host smart-2d63d812-8eee-4d61-887b-93871e9bcd76
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709255582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.709255582
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2652189219
Short name T124
Test name
Test status
Simulation time 37660973 ps
CPU time 0.54 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:02 PM PST 23
Peak memory 193308 kb
Host smart-b5239c50-8a8d-4ac2-b156-73ab7f2e1bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652189219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2652189219
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2652149753
Short name T901
Test name
Test status
Simulation time 17280843 ps
CPU time 0.87 seconds
Started Dec 31 12:17:46 PM PST 23
Finished Dec 31 12:17:48 PM PST 23
Peak memory 195252 kb
Host smart-2f166b4d-7669-49bb-8d27-b38edfd4a6da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652149753 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2652149753
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1997341044
Short name T34
Test name
Test status
Simulation time 29707452 ps
CPU time 1.36 seconds
Started Dec 31 12:27:02 PM PST 23
Finished Dec 31 12:27:06 PM PST 23
Peak memory 198264 kb
Host smart-18a430e9-9286-46e7-af67-a8486a5c0d00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997341044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1997341044
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3008158096
Short name T7
Test name
Test status
Simulation time 264163452 ps
CPU time 1.11 seconds
Started Dec 31 12:22:05 PM PST 23
Finished Dec 31 12:22:08 PM PST 23
Peak memory 198176 kb
Host smart-15df7f2e-7e14-4223-8080-f3e245f7bed5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008158096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3008158096
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.330975362
Short name T94
Test name
Test status
Simulation time 27395139 ps
CPU time 0.74 seconds
Started Dec 31 12:26:32 PM PST 23
Finished Dec 31 12:26:34 PM PST 23
Peak memory 196736 kb
Host smart-b405b206-1dc9-4ae1-a46c-72656d2e1b7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330975362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.330975362
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.485183346
Short name T910
Test name
Test status
Simulation time 33682832 ps
CPU time 1.33 seconds
Started Dec 31 12:24:24 PM PST 23
Finished Dec 31 12:24:28 PM PST 23
Peak memory 197700 kb
Host smart-127dcc13-902e-4c2f-924c-34b2471d7269
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485183346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.485183346
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3683770699
Short name T38
Test name
Test status
Simulation time 14840064 ps
CPU time 0.58 seconds
Started Dec 31 12:24:20 PM PST 23
Finished Dec 31 12:24:23 PM PST 23
Peak memory 194276 kb
Host smart-f84227aa-be18-4235-a376-daa66273d01b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683770699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3683770699
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3908484882
Short name T938
Test name
Test status
Simulation time 62086295 ps
CPU time 0.91 seconds
Started Dec 31 12:26:12 PM PST 23
Finished Dec 31 12:26:16 PM PST 23
Peak memory 197024 kb
Host smart-7d1af519-7764-4ef6-af68-31525383b6cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908484882 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3908484882
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1441658132
Short name T96
Test name
Test status
Simulation time 14016290 ps
CPU time 0.63 seconds
Started Dec 31 12:26:59 PM PST 23
Finished Dec 31 12:27:03 PM PST 23
Peak memory 193892 kb
Host smart-a8af3b49-3d43-40f7-8950-c677ddc9af77
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441658132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1441658132
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.4049437524
Short name T942
Test name
Test status
Simulation time 16336076 ps
CPU time 0.55 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:22 PM PST 23
Peak memory 192900 kb
Host smart-2123a9d2-68d0-405c-8cf8-6a1a447ee958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049437524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.4049437524
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3440174825
Short name T3
Test name
Test status
Simulation time 59998417 ps
CPU time 0.73 seconds
Started Dec 31 12:28:25 PM PST 23
Finished Dec 31 12:28:29 PM PST 23
Peak memory 196168 kb
Host smart-4dfb702e-b2cc-40e1-bcd8-09870d454831
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440174825 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3440174825
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2337746862
Short name T928
Test name
Test status
Simulation time 280065959 ps
CPU time 1.96 seconds
Started Dec 31 12:23:19 PM PST 23
Finished Dec 31 12:23:22 PM PST 23
Peak memory 197984 kb
Host smart-9764128e-3482-4053-a2d8-65b7b7592afc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337746862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2337746862
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3252876378
Short name T37
Test name
Test status
Simulation time 772719394 ps
CPU time 1.46 seconds
Started Dec 31 12:24:24 PM PST 23
Finished Dec 31 12:24:29 PM PST 23
Peak memory 197764 kb
Host smart-652d5251-176e-4627-94dc-5033da3c4903
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252876378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3252876378
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.162309134
Short name T898
Test name
Test status
Simulation time 99645627 ps
CPU time 1.27 seconds
Started Dec 31 12:24:40 PM PST 23
Finished Dec 31 12:24:47 PM PST 23
Peak memory 198212 kb
Host smart-55bbfa37-730d-4d16-a6f6-b949ffb77d4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162309134 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.162309134
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1702354796
Short name T99
Test name
Test status
Simulation time 56657428 ps
CPU time 0.55 seconds
Started Dec 31 12:23:41 PM PST 23
Finished Dec 31 12:23:44 PM PST 23
Peak memory 193044 kb
Host smart-8b2d76a7-6c1f-4830-981a-98dc1d1dc1b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702354796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1702354796
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3788698396
Short name T926
Test name
Test status
Simulation time 10761569 ps
CPU time 0.61 seconds
Started Dec 31 12:24:21 PM PST 23
Finished Dec 31 12:24:26 PM PST 23
Peak memory 193516 kb
Host smart-f08ba105-a717-4d8b-a458-4f2ed27b409f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788698396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3788698396
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3599258106
Short name T934
Test name
Test status
Simulation time 78955683 ps
CPU time 0.8 seconds
Started Dec 31 12:24:41 PM PST 23
Finished Dec 31 12:24:50 PM PST 23
Peak memory 196416 kb
Host smart-ad4a2a7b-d6f6-4326-8ff8-7f6a7cc2adcf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599258106 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3599258106
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4100248263
Short name T23
Test name
Test status
Simulation time 448848588 ps
CPU time 1.21 seconds
Started Dec 31 12:23:41 PM PST 23
Finished Dec 31 12:23:45 PM PST 23
Peak memory 197032 kb
Host smart-0dd8ed4e-70a4-4daf-bbc7-e145ff25ecee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100248263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.4100248263
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3129485182
Short name T939
Test name
Test status
Simulation time 453911689 ps
CPU time 1.35 seconds
Started Dec 31 12:24:40 PM PST 23
Finished Dec 31 12:24:49 PM PST 23
Peak memory 198148 kb
Host smart-43288eb6-62e9-4a8e-9855-b569bb98e8f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129485182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3129485182
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2751157158
Short name T86
Test name
Test status
Simulation time 45064974 ps
CPU time 0.62 seconds
Started Dec 31 12:19:08 PM PST 23
Finished Dec 31 12:19:09 PM PST 23
Peak memory 195812 kb
Host smart-b0b26d5d-77bd-457b-b871-0dd23cafec7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751157158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2751157158
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2237733011
Short name T930
Test name
Test status
Simulation time 35431174 ps
CPU time 0.68 seconds
Started Dec 31 12:22:32 PM PST 23
Finished Dec 31 12:22:33 PM PST 23
Peak memory 193864 kb
Host smart-c5bd9d99-4f86-41cd-be3d-2b460b2969a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237733011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2237733011
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2368198737
Short name T940
Test name
Test status
Simulation time 274487525 ps
CPU time 0.82 seconds
Started Dec 31 12:26:02 PM PST 23
Finished Dec 31 12:26:09 PM PST 23
Peak memory 196708 kb
Host smart-00902536-3e74-4f53-abdd-46dfe652d86d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368198737 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2368198737
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.17652927
Short name T957
Test name
Test status
Simulation time 66119008 ps
CPU time 2.61 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:11 PM PST 23
Peak memory 196416 kb
Host smart-480aa3f5-7441-427e-ba2b-32daf5a3b98b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17652927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.17652927
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.461092002
Short name T916
Test name
Test status
Simulation time 128337496 ps
CPU time 0.77 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 195672 kb
Host smart-72a0e302-a5b8-4af3-ba17-b833cd084f80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461092002 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.461092002
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1545549465
Short name T968
Test name
Test status
Simulation time 24535887 ps
CPU time 0.61 seconds
Started Dec 31 12:22:07 PM PST 23
Finished Dec 31 12:22:10 PM PST 23
Peak memory 195268 kb
Host smart-0291d36e-6931-43c1-9d35-b969a306c262
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545549465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1545549465
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1613923949
Short name T952
Test name
Test status
Simulation time 105858446 ps
CPU time 0.62 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:22:58 PM PST 23
Peak memory 193756 kb
Host smart-4080fc77-a543-47fc-89e6-b30315e79515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613923949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1613923949
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2167816508
Short name T106
Test name
Test status
Simulation time 27574503 ps
CPU time 0.83 seconds
Started Dec 31 12:22:10 PM PST 23
Finished Dec 31 12:22:12 PM PST 23
Peak memory 194656 kb
Host smart-a671774f-724b-4662-a5f8-a080d61d784b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167816508 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2167816508
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1170558136
Short name T943
Test name
Test status
Simulation time 420111177 ps
CPU time 1.49 seconds
Started Dec 31 12:22:32 PM PST 23
Finished Dec 31 12:22:34 PM PST 23
Peak memory 198076 kb
Host smart-3aad7df4-4443-4270-b322-5c67cb4a1c5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170558136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1170558136
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4249071332
Short name T915
Test name
Test status
Simulation time 25088472 ps
CPU time 1.24 seconds
Started Dec 31 12:22:32 PM PST 23
Finished Dec 31 12:22:34 PM PST 23
Peak memory 198140 kb
Host smart-9bc52ea5-2e21-4d64-bb3e-2269dd8177a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249071332 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4249071332
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3509605551
Short name T969
Test name
Test status
Simulation time 83066286 ps
CPU time 0.65 seconds
Started Dec 31 12:26:01 PM PST 23
Finished Dec 31 12:26:08 PM PST 23
Peak memory 193460 kb
Host smart-0c37f888-e1fd-468b-86cc-fd7779c39ef1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509605551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3509605551
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.380174855
Short name T8
Test name
Test status
Simulation time 36406075 ps
CPU time 0.63 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 192844 kb
Host smart-5d854340-e024-41b5-9815-fa5135a0ebd8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380174855 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.380174855
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3933007777
Short name T932
Test name
Test status
Simulation time 88245469 ps
CPU time 1.37 seconds
Started Dec 31 12:19:24 PM PST 23
Finished Dec 31 12:19:26 PM PST 23
Peak memory 198216 kb
Host smart-8f24111e-9ff3-4f55-b82f-9b7441a0c9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933007777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3933007777
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1245655207
Short name T43
Test name
Test status
Simulation time 131219900 ps
CPU time 1.5 seconds
Started Dec 31 12:21:34 PM PST 23
Finished Dec 31 12:21:38 PM PST 23
Peak memory 198344 kb
Host smart-403ad2c2-f475-4dee-bd20-e33204c38eb3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245655207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1245655207
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1058402316
Short name T14
Test name
Test status
Simulation time 14873605 ps
CPU time 0.76 seconds
Started Dec 31 12:23:28 PM PST 23
Finished Dec 31 12:23:31 PM PST 23
Peak memory 197812 kb
Host smart-8b2dcb34-02d4-4062-b1d9-374ee7868ecb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058402316 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1058402316
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.55039296
Short name T87
Test name
Test status
Simulation time 16623396 ps
CPU time 0.57 seconds
Started Dec 31 12:23:28 PM PST 23
Finished Dec 31 12:23:31 PM PST 23
Peak memory 193364 kb
Host smart-d24fb7ee-e51a-4d0c-ac0d-7b7ca9cbcd9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55039296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_
csr_rw.55039296
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1726672325
Short name T905
Test name
Test status
Simulation time 59431868 ps
CPU time 0.59 seconds
Started Dec 31 12:22:18 PM PST 23
Finished Dec 31 12:22:19 PM PST 23
Peak memory 194452 kb
Host smart-cf00cb5a-79e0-4b26-8f45-95383e7ebae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726672325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1726672325
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2465021287
Short name T24
Test name
Test status
Simulation time 19281607 ps
CPU time 0.65 seconds
Started Dec 31 12:26:01 PM PST 23
Finished Dec 31 12:26:08 PM PST 23
Peak memory 193644 kb
Host smart-b59a3c6f-9037-4387-b4d2-c69fd027fc38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465021287 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2465021287
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.270456862
Short name T911
Test name
Test status
Simulation time 185850223 ps
CPU time 1.18 seconds
Started Dec 31 12:22:10 PM PST 23
Finished Dec 31 12:22:13 PM PST 23
Peak memory 198540 kb
Host smart-6ebb1eaa-2227-48fd-8a38-d8849478b1b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270456862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.270456862
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1385234196
Short name T941
Test name
Test status
Simulation time 534004470 ps
CPU time 0.99 seconds
Started Dec 31 12:26:02 PM PST 23
Finished Dec 31 12:26:09 PM PST 23
Peak memory 197456 kb
Host smart-9d240a18-6f38-4fa7-b24c-ac08aab3f167
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385234196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1385234196
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2585641194
Short name T892
Test name
Test status
Simulation time 18412361 ps
CPU time 0.73 seconds
Started Dec 31 12:19:24 PM PST 23
Finished Dec 31 12:19:26 PM PST 23
Peak memory 197988 kb
Host smart-99ade291-47fe-4558-8062-2bde40b98979
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585641194 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2585641194
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3232892283
Short name T11
Test name
Test status
Simulation time 39107846 ps
CPU time 0.67 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:22:58 PM PST 23
Peak memory 194592 kb
Host smart-40fe8630-e2cd-473e-a6a6-3f3363996e8c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232892283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3232892283
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1918404433
Short name T962
Test name
Test status
Simulation time 13103112 ps
CPU time 0.59 seconds
Started Dec 31 12:23:31 PM PST 23
Finished Dec 31 12:23:37 PM PST 23
Peak memory 193824 kb
Host smart-92a99338-2257-4f6f-bdda-829d09bb72df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918404433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1918404433
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.557753757
Short name T895
Test name
Test status
Simulation time 49302169 ps
CPU time 0.72 seconds
Started Dec 31 12:24:30 PM PST 23
Finished Dec 31 12:24:33 PM PST 23
Peak memory 195912 kb
Host smart-766d289a-d21c-4f05-aa8e-711dd002a0b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557753757 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.557753757
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1405901835
Short name T947
Test name
Test status
Simulation time 361092497 ps
CPU time 1.94 seconds
Started Dec 31 12:20:15 PM PST 23
Finished Dec 31 12:20:17 PM PST 23
Peak memory 198420 kb
Host smart-e603bde3-6ee1-40db-ba46-d1bebfa412c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405901835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1405901835
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.247229623
Short name T896
Test name
Test status
Simulation time 135645295 ps
CPU time 0.91 seconds
Started Dec 31 12:22:32 PM PST 23
Finished Dec 31 12:22:33 PM PST 23
Peak memory 197960 kb
Host smart-c3d0b705-3291-451c-9bf8-5bcd3a128be0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247229623 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.247229623
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1272114572
Short name T90
Test name
Test status
Simulation time 51056537 ps
CPU time 0.61 seconds
Started Dec 31 12:19:16 PM PST 23
Finished Dec 31 12:19:18 PM PST 23
Peak memory 194988 kb
Host smart-b9b5bae6-62f5-42df-90ad-9e301d97e33a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272114572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1272114572
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2565860140
Short name T931
Test name
Test status
Simulation time 34048843 ps
CPU time 0.6 seconds
Started Dec 31 12:26:01 PM PST 23
Finished Dec 31 12:26:08 PM PST 23
Peak memory 193460 kb
Host smart-19d61ec4-e1e3-411b-9e96-f819766bccdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565860140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2565860140
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2649087927
Short name T79
Test name
Test status
Simulation time 16002940 ps
CPU time 0.64 seconds
Started Dec 31 12:20:27 PM PST 23
Finished Dec 31 12:20:29 PM PST 23
Peak memory 194780 kb
Host smart-f932c34f-1646-447d-a65d-aa60d8d42885
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649087927 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2649087927
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1433187367
Short name T894
Test name
Test status
Simulation time 57833586 ps
CPU time 1.31 seconds
Started Dec 31 12:20:15 PM PST 23
Finished Dec 31 12:20:17 PM PST 23
Peak memory 198368 kb
Host smart-ef81e55c-705d-4986-b052-274294677984
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433187367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1433187367
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1545880117
Short name T933
Test name
Test status
Simulation time 400037575 ps
CPU time 1.4 seconds
Started Dec 31 12:23:28 PM PST 23
Finished Dec 31 12:23:32 PM PST 23
Peak memory 197948 kb
Host smart-f8248217-11a2-4bef-a54c-d3ce82b6a717
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545880117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1545880117
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3702295342
Short name T958
Test name
Test status
Simulation time 23961732 ps
CPU time 1.05 seconds
Started Dec 31 12:22:54 PM PST 23
Finished Dec 31 12:22:56 PM PST 23
Peak memory 198136 kb
Host smart-1d9a17c3-b24b-4aae-b188-9a197f3f4676
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702295342 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3702295342
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.902824327
Short name T912
Test name
Test status
Simulation time 15420365 ps
CPU time 0.56 seconds
Started Dec 31 12:25:13 PM PST 23
Finished Dec 31 12:25:16 PM PST 23
Peak memory 194280 kb
Host smart-024e8d85-1967-4cb6-b93e-3bde81e9e5c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902824327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.902824327
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.217907939
Short name T19
Test name
Test status
Simulation time 59373066 ps
CPU time 0.66 seconds
Started Dec 31 12:22:29 PM PST 23
Finished Dec 31 12:22:31 PM PST 23
Peak memory 192436 kb
Host smart-2907afe6-0948-48f8-8e53-8287dc5c4059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217907939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.217907939
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2260717958
Short name T963
Test name
Test status
Simulation time 61742866 ps
CPU time 0.71 seconds
Started Dec 31 12:25:12 PM PST 23
Finished Dec 31 12:25:16 PM PST 23
Peak memory 195976 kb
Host smart-f97edfba-1e59-49d1-89d7-384dc352d855
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260717958 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2260717958
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3500981527
Short name T5
Test name
Test status
Simulation time 963073970 ps
CPU time 2.65 seconds
Started Dec 31 12:25:24 PM PST 23
Finished Dec 31 12:25:33 PM PST 23
Peak memory 197404 kb
Host smart-70c88b13-de5e-4b5e-81bc-0cd4e6c6a428
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500981527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3500981527
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2392617221
Short name T116
Test name
Test status
Simulation time 20606639 ps
CPU time 0.63 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:02 PM PST 23
Peak memory 196392 kb
Host smart-8a46126c-5b1a-4729-9da6-be6434d96e27
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392617221 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2392617221
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2608919736
Short name T944
Test name
Test status
Simulation time 49598788 ps
CPU time 0.61 seconds
Started Dec 31 12:27:07 PM PST 23
Finished Dec 31 12:27:10 PM PST 23
Peak memory 193372 kb
Host smart-0a5c5815-9a3b-4aa7-acee-279ecd3df728
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608919736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2608919736
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3795747003
Short name T909
Test name
Test status
Simulation time 17611249 ps
CPU time 0.62 seconds
Started Dec 31 12:24:38 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 193544 kb
Host smart-0188f702-5621-4aef-a1dc-455d3ed86d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795747003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3795747003
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1419178099
Short name T107
Test name
Test status
Simulation time 63302792 ps
CPU time 0.7 seconds
Started Dec 31 12:25:15 PM PST 23
Finished Dec 31 12:25:19 PM PST 23
Peak memory 196204 kb
Host smart-e5a7423d-9172-4ca7-af6a-39bd94833fd7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419178099 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1419178099
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2790949658
Short name T965
Test name
Test status
Simulation time 44869551 ps
CPU time 1.23 seconds
Started Dec 31 12:25:19 PM PST 23
Finished Dec 31 12:25:24 PM PST 23
Peak memory 198212 kb
Host smart-f800a111-f321-4249-a446-9ed7657497ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790949658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2790949658
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1036671800
Short name T919
Test name
Test status
Simulation time 40437681 ps
CPU time 0.86 seconds
Started Dec 31 12:24:08 PM PST 23
Finished Dec 31 12:24:14 PM PST 23
Peak memory 197288 kb
Host smart-f6a3867d-7177-4257-8474-42a224b138b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036671800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1036671800
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.489924918
Short name T929
Test name
Test status
Simulation time 254603548 ps
CPU time 1.06 seconds
Started Dec 31 12:25:56 PM PST 23
Finished Dec 31 12:26:04 PM PST 23
Peak memory 197988 kb
Host smart-6727a6fc-bcb7-4de9-a59d-3ddc671b9ef4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489924918 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.489924918
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2627547582
Short name T904
Test name
Test status
Simulation time 116769522 ps
CPU time 0.61 seconds
Started Dec 31 12:18:07 PM PST 23
Finished Dec 31 12:18:08 PM PST 23
Peak memory 195456 kb
Host smart-e818ac3e-7f91-48f9-a029-f1dd7ceeabf2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627547582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2627547582
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.871078446
Short name T970
Test name
Test status
Simulation time 13941079 ps
CPU time 0.62 seconds
Started Dec 31 12:19:20 PM PST 23
Finished Dec 31 12:19:25 PM PST 23
Peak memory 193800 kb
Host smart-975c8b5f-e5b8-40de-9712-bb27912d6e4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871078446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.871078446
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3568516694
Short name T897
Test name
Test status
Simulation time 19926770 ps
CPU time 0.67 seconds
Started Dec 31 12:25:41 PM PST 23
Finished Dec 31 12:25:51 PM PST 23
Peak memory 195832 kb
Host smart-6b6ad2c2-2a3f-479e-bbe1-ab1c9530bafb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568516694 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3568516694
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.4146177809
Short name T891
Test name
Test status
Simulation time 1582679223 ps
CPU time 1.85 seconds
Started Dec 31 12:26:04 PM PST 23
Finished Dec 31 12:26:11 PM PST 23
Peak memory 198212 kb
Host smart-bd9ccdbe-ee61-4b5b-82e1-b191842a90ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146177809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.4146177809
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3963624679
Short name T908
Test name
Test status
Simulation time 43019233 ps
CPU time 0.83 seconds
Started Dec 31 12:23:31 PM PST 23
Finished Dec 31 12:23:37 PM PST 23
Peak memory 197196 kb
Host smart-2426e81e-095e-433a-9c3b-d3616aaf497a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963624679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3963624679
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4089427777
Short name T10
Test name
Test status
Simulation time 127357185 ps
CPU time 0.83 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:24:27 PM PST 23
Peak memory 194908 kb
Host smart-3c17a7aa-3361-436c-abdf-e365438a6b38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089427777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.4089427777
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2805543992
Short name T128
Test name
Test status
Simulation time 262075435 ps
CPU time 3.12 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:25 PM PST 23
Peak memory 196804 kb
Host smart-3fcde3f2-4ee0-437a-aa9a-f2c520fec91d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805543992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2805543992
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3201915199
Short name T39
Test name
Test status
Simulation time 128495200 ps
CPU time 0.63 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:22 PM PST 23
Peak memory 194940 kb
Host smart-52eaff26-b603-4983-8788-9c8d49ac314f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201915199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3201915199
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3144699975
Short name T917
Test name
Test status
Simulation time 59327489 ps
CPU time 0.65 seconds
Started Dec 31 12:23:25 PM PST 23
Finished Dec 31 12:23:27 PM PST 23
Peak memory 197684 kb
Host smart-b9204b65-46dd-4bae-9665-925eb3ad0649
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144699975 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3144699975
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3040206340
Short name T108
Test name
Test status
Simulation time 16168235 ps
CPU time 0.59 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 12:27:19 PM PST 23
Peak memory 195256 kb
Host smart-88c4e11d-a489-4dbd-99b5-87bb1b9d8dd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040206340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3040206340
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1028077616
Short name T12
Test name
Test status
Simulation time 14519393 ps
CPU time 0.6 seconds
Started Dec 31 12:20:55 PM PST 23
Finished Dec 31 12:20:56 PM PST 23
Peak memory 193832 kb
Host smart-39e50dba-17f1-476f-be98-87d6ec688649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028077616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1028077616
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2111170181
Short name T105
Test name
Test status
Simulation time 211701677 ps
CPU time 0.74 seconds
Started Dec 31 12:23:18 PM PST 23
Finished Dec 31 12:23:20 PM PST 23
Peak memory 194736 kb
Host smart-0ccd98e8-7348-4148-b8b7-1a29c79a980c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111170181 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2111170181
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2606286486
Short name T32
Test name
Test status
Simulation time 36578360 ps
CPU time 1.05 seconds
Started Dec 31 12:25:42 PM PST 23
Finished Dec 31 12:25:51 PM PST 23
Peak memory 197720 kb
Host smart-d9305222-b5a0-4a2c-9a53-5e685d905fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606286486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2606286486
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2641809243
Short name T27
Test name
Test status
Simulation time 23397624 ps
CPU time 0.59 seconds
Started Dec 31 12:24:45 PM PST 23
Finished Dec 31 12:24:53 PM PST 23
Peak memory 193244 kb
Host smart-67caedac-abf3-4f91-9aa7-b360d74bf9f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641809243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2641809243
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.976366830
Short name T122
Test name
Test status
Simulation time 50743919 ps
CPU time 0.64 seconds
Started Dec 31 12:24:59 PM PST 23
Finished Dec 31 12:25:03 PM PST 23
Peak memory 193760 kb
Host smart-82be8889-d75c-498d-a589-c30966d9167c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976366830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.976366830
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1413929970
Short name T17
Test name
Test status
Simulation time 47200178 ps
CPU time 0.65 seconds
Started Dec 31 12:22:54 PM PST 23
Finished Dec 31 12:22:56 PM PST 23
Peak memory 193524 kb
Host smart-14ee63af-8310-4257-8ab2-126f66d7057a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413929970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1413929970
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.4194696269
Short name T95
Test name
Test status
Simulation time 40735636 ps
CPU time 0.57 seconds
Started Dec 31 12:26:58 PM PST 23
Finished Dec 31 12:27:00 PM PST 23
Peak memory 193848 kb
Host smart-2890572e-ba38-485b-b139-e55b30aec78d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194696269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.4194696269
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2423724654
Short name T956
Test name
Test status
Simulation time 13288140 ps
CPU time 0.6 seconds
Started Dec 31 12:26:27 PM PST 23
Finished Dec 31 12:26:29 PM PST 23
Peak memory 192996 kb
Host smart-11609f59-67ab-4d86-b0c0-d2123ddcba8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423724654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2423724654
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1032122312
Short name T125
Test name
Test status
Simulation time 44367793 ps
CPU time 0.62 seconds
Started Dec 31 12:24:45 PM PST 23
Finished Dec 31 12:24:53 PM PST 23
Peak memory 192768 kb
Host smart-9b1be434-f6f6-4a7c-8648-b13ba520f976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032122312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1032122312
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1737985835
Short name T121
Test name
Test status
Simulation time 15647919 ps
CPU time 0.59 seconds
Started Dec 31 12:25:01 PM PST 23
Finished Dec 31 12:25:05 PM PST 23
Peak memory 193020 kb
Host smart-f3e4dfe7-f86e-4d16-b1d7-bbc6b9df0a44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737985835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1737985835
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.125556697
Short name T28
Test name
Test status
Simulation time 44333217 ps
CPU time 0.58 seconds
Started Dec 31 12:25:33 PM PST 23
Finished Dec 31 12:25:40 PM PST 23
Peak memory 193960 kb
Host smart-48a7d607-b85b-4d43-9352-b73a95a16b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125556697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.125556697
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3218192255
Short name T82
Test name
Test status
Simulation time 28300242 ps
CPU time 0.55 seconds
Started Dec 31 12:19:40 PM PST 23
Finished Dec 31 12:19:46 PM PST 23
Peak memory 193784 kb
Host smart-461d6ef3-00fd-433e-b325-e8849c07dc31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218192255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3218192255
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2013794521
Short name T98
Test name
Test status
Simulation time 31063080 ps
CPU time 0.66 seconds
Started Dec 31 12:23:36 PM PST 23
Finished Dec 31 12:23:41 PM PST 23
Peak memory 193264 kb
Host smart-01a2f606-945e-4043-a839-2bf3ea144c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013794521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2013794521
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1855992372
Short name T937
Test name
Test status
Simulation time 21261169 ps
CPU time 0.68 seconds
Started Dec 31 12:20:58 PM PST 23
Finished Dec 31 12:20:59 PM PST 23
Peak memory 194732 kb
Host smart-07365034-864b-4711-97c9-838b089e4ae2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855992372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1855992372
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1024056457
Short name T1
Test name
Test status
Simulation time 451150796 ps
CPU time 1.48 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:24:28 PM PST 23
Peak memory 196964 kb
Host smart-cbcbbe6e-f435-4ac0-bf2a-5472577551ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024056457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1024056457
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1172020985
Short name T93
Test name
Test status
Simulation time 17542938 ps
CPU time 0.64 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:22 PM PST 23
Peak memory 195352 kb
Host smart-d42d5b8b-46f7-488e-a19c-879f48440e7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172020985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1172020985
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2744731364
Short name T960
Test name
Test status
Simulation time 22177364 ps
CPU time 0.74 seconds
Started Dec 31 12:20:09 PM PST 23
Finished Dec 31 12:20:11 PM PST 23
Peak memory 198372 kb
Host smart-abaa70a3-305f-4fe6-8a9e-48107bc44315
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744731364 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2744731364
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3428209766
Short name T951
Test name
Test status
Simulation time 21348887 ps
CPU time 0.6 seconds
Started Dec 31 12:20:55 PM PST 23
Finished Dec 31 12:20:56 PM PST 23
Peak memory 194660 kb
Host smart-887c87a6-6c01-43df-84c9-4c10d60f4627
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428209766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3428209766
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.4109473778
Short name T119
Test name
Test status
Simulation time 12187802 ps
CPU time 0.61 seconds
Started Dec 31 12:23:57 PM PST 23
Finished Dec 31 12:24:02 PM PST 23
Peak memory 193912 kb
Host smart-f1734441-59df-4c12-addc-2e317cf256e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109473778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.4109473778
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.463392284
Short name T104
Test name
Test status
Simulation time 18766912 ps
CPU time 0.72 seconds
Started Dec 31 12:31:20 PM PST 23
Finished Dec 31 12:31:30 PM PST 23
Peak memory 196296 kb
Host smart-698166b8-cbdb-4bbb-9159-a595ee0b63f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463392284 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.463392284
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.140898482
Short name T955
Test name
Test status
Simulation time 21662546 ps
CPU time 1.07 seconds
Started Dec 31 12:26:36 PM PST 23
Finished Dec 31 12:26:40 PM PST 23
Peak memory 198164 kb
Host smart-071bd605-d03e-40e0-841e-cfc439e1f9b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140898482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.140898482
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2915315103
Short name T110
Test name
Test status
Simulation time 150518262 ps
CPU time 0.9 seconds
Started Dec 31 12:22:31 PM PST 23
Finished Dec 31 12:22:33 PM PST 23
Peak memory 197036 kb
Host smart-6bb5b852-1af6-4a64-b673-ab1905d17ebf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915315103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2915315103
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.348548770
Short name T906
Test name
Test status
Simulation time 223680348 ps
CPU time 0.62 seconds
Started Dec 31 12:26:10 PM PST 23
Finished Dec 31 12:26:15 PM PST 23
Peak memory 192744 kb
Host smart-8542c2a5-6429-495a-a6f5-9515366ddfdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348548770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.348548770
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.4261142382
Short name T126
Test name
Test status
Simulation time 22185786 ps
CPU time 0.61 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:24:27 PM PST 23
Peak memory 193792 kb
Host smart-e94d243a-4cd4-4c10-8284-26df2990ae4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261142382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.4261142382
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1583064036
Short name T921
Test name
Test status
Simulation time 98876948 ps
CPU time 0.57 seconds
Started Dec 31 12:26:05 PM PST 23
Finished Dec 31 12:26:11 PM PST 23
Peak memory 194568 kb
Host smart-1b5fa606-811f-46b8-afb5-e949b3440ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583064036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1583064036
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1463341706
Short name T16
Test name
Test status
Simulation time 26838895 ps
CPU time 0.57 seconds
Started Dec 31 12:27:05 PM PST 23
Finished Dec 31 12:27:08 PM PST 23
Peak memory 193800 kb
Host smart-79018a5e-47fa-4965-8b41-42db543a1e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463341706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1463341706
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.4031282184
Short name T950
Test name
Test status
Simulation time 11902754 ps
CPU time 0.59 seconds
Started Dec 31 12:34:37 PM PST 23
Finished Dec 31 12:34:40 PM PST 23
Peak memory 193952 kb
Host smart-8ef6a51e-d5ba-4986-9424-8e30b8fcf995
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031282184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.4031282184
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2066687443
Short name T913
Test name
Test status
Simulation time 23559225 ps
CPU time 0.69 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:22 PM PST 23
Peak memory 192188 kb
Host smart-4e375605-8150-486b-aef7-72aaa3e78fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066687443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2066687443
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3337089001
Short name T83
Test name
Test status
Simulation time 26248322 ps
CPU time 0.56 seconds
Started Dec 31 12:21:03 PM PST 23
Finished Dec 31 12:21:04 PM PST 23
Peak memory 193872 kb
Host smart-bfaa9854-12d5-419b-a2e1-34a23c2a3857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337089001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3337089001
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3182550367
Short name T21
Test name
Test status
Simulation time 85063309 ps
CPU time 0.63 seconds
Started Dec 31 12:23:36 PM PST 23
Finished Dec 31 12:23:41 PM PST 23
Peak memory 193560 kb
Host smart-98680e05-c7cc-426b-b604-d95b114f11dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182550367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3182550367
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1419940075
Short name T923
Test name
Test status
Simulation time 39287615 ps
CPU time 0.56 seconds
Started Dec 31 12:26:10 PM PST 23
Finished Dec 31 12:26:15 PM PST 23
Peak memory 193576 kb
Host smart-f3d7e22c-75b7-459a-93bb-1889bdea525c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419940075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1419940075
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1107593923
Short name T920
Test name
Test status
Simulation time 23401137 ps
CPU time 0.59 seconds
Started Dec 31 12:24:03 PM PST 23
Finished Dec 31 12:24:11 PM PST 23
Peak memory 193848 kb
Host smart-b826ebb8-e14e-4ae5-8f0f-f2131b29739b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107593923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1107593923
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1154901123
Short name T91
Test name
Test status
Simulation time 49227806 ps
CPU time 0.76 seconds
Started Dec 31 12:20:44 PM PST 23
Finished Dec 31 12:20:45 PM PST 23
Peak memory 195712 kb
Host smart-1869d0a8-a776-4187-ae44-8c04670d8f0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154901123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1154901123
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1567379446
Short name T959
Test name
Test status
Simulation time 1258018435 ps
CPU time 3.33 seconds
Started Dec 31 12:20:21 PM PST 23
Finished Dec 31 12:20:25 PM PST 23
Peak memory 197156 kb
Host smart-283fc56c-6c20-4aac-8ea2-ad466e9442fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567379446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1567379446
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3494287906
Short name T103
Test name
Test status
Simulation time 55162971 ps
CPU time 0.67 seconds
Started Dec 31 12:24:14 PM PST 23
Finished Dec 31 12:24:18 PM PST 23
Peak memory 193844 kb
Host smart-ac2d1590-69fe-4ae2-8a38-a01199b106fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494287906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3494287906
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2809955094
Short name T6
Test name
Test status
Simulation time 26376915 ps
CPU time 0.83 seconds
Started Dec 31 12:26:51 PM PST 23
Finished Dec 31 12:26:54 PM PST 23
Peak memory 197192 kb
Host smart-195b509c-5e90-42a1-89ea-92e002b30529
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809955094 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2809955094
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2170793838
Short name T114
Test name
Test status
Simulation time 51147453 ps
CPU time 0.58 seconds
Started Dec 31 12:26:39 PM PST 23
Finished Dec 31 12:26:41 PM PST 23
Peak memory 195120 kb
Host smart-4045a7e4-72c9-4a50-9e56-d9393325e8da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170793838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2170793838
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1105536399
Short name T100
Test name
Test status
Simulation time 15682999 ps
CPU time 0.62 seconds
Started Dec 31 12:18:07 PM PST 23
Finished Dec 31 12:18:08 PM PST 23
Peak memory 194236 kb
Host smart-878bcf8d-51ef-459b-95e1-5d54c73760eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105536399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1105536399
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4199363611
Short name T81
Test name
Test status
Simulation time 45016413 ps
CPU time 0.77 seconds
Started Dec 31 12:25:51 PM PST 23
Finished Dec 31 12:25:59 PM PST 23
Peak memory 196624 kb
Host smart-99e48761-9980-41b3-a209-49ff05ad1795
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199363611 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4199363611
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3388826662
Short name T918
Test name
Test status
Simulation time 174221681 ps
CPU time 1.33 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:22:59 PM PST 23
Peak memory 198088 kb
Host smart-e3532c4e-4886-4a64-b969-9d79e87eb94d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388826662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3388826662
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.603793207
Short name T111
Test name
Test status
Simulation time 379271513 ps
CPU time 1.21 seconds
Started Dec 31 12:21:48 PM PST 23
Finished Dec 31 12:21:51 PM PST 23
Peak memory 198120 kb
Host smart-adf3d39c-bffe-414d-914c-a7a9a3e14795
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603793207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.603793207
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.720389500
Short name T966
Test name
Test status
Simulation time 37381278 ps
CPU time 0.63 seconds
Started Dec 31 12:23:36 PM PST 23
Finished Dec 31 12:23:41 PM PST 23
Peak memory 193464 kb
Host smart-e5276e35-67d3-41ce-b401-b6add3bedfbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720389500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.720389500
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.196677522
Short name T123
Test name
Test status
Simulation time 18543697 ps
CPU time 0.63 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:24:26 PM PST 23
Peak memory 193640 kb
Host smart-025b000a-6c29-42aa-a97f-e528bd58b6b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196677522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.196677522
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1612394067
Short name T936
Test name
Test status
Simulation time 14816398 ps
CPU time 0.66 seconds
Started Dec 31 12:23:36 PM PST 23
Finished Dec 31 12:23:41 PM PST 23
Peak memory 193488 kb
Host smart-55cbadc9-d283-4280-8acb-5fc956f7a9db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612394067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1612394067
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1813731796
Short name T900
Test name
Test status
Simulation time 13733750 ps
CPU time 0.54 seconds
Started Dec 31 12:25:30 PM PST 23
Finished Dec 31 12:25:38 PM PST 23
Peak memory 194460 kb
Host smart-c8f2729d-cddf-49f3-a347-db1e8947ec55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813731796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1813731796
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1455780055
Short name T954
Test name
Test status
Simulation time 19296365 ps
CPU time 0.74 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:22 PM PST 23
Peak memory 192480 kb
Host smart-2b2a009a-4336-4885-91aa-635d723f0304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455780055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1455780055
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.67164295
Short name T20
Test name
Test status
Simulation time 45519578 ps
CPU time 0.64 seconds
Started Dec 31 12:23:12 PM PST 23
Finished Dec 31 12:23:13 PM PST 23
Peak memory 192972 kb
Host smart-6d12b113-fa55-4457-98cf-466be9c18fa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67164295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.67164295
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1123338644
Short name T85
Test name
Test status
Simulation time 11773037 ps
CPU time 0.58 seconds
Started Dec 31 12:24:22 PM PST 23
Finished Dec 31 12:24:25 PM PST 23
Peak memory 193520 kb
Host smart-2cc72991-b15a-4c93-8efc-7588d33ca2ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123338644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1123338644
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.4037657940
Short name T948
Test name
Test status
Simulation time 51805812 ps
CPU time 0.6 seconds
Started Dec 31 12:24:03 PM PST 23
Finished Dec 31 12:24:10 PM PST 23
Peak memory 193764 kb
Host smart-38ab871b-7033-4243-b611-93b05afdc0c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037657940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.4037657940
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.4142492304
Short name T84
Test name
Test status
Simulation time 11742215 ps
CPU time 0.54 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:22 PM PST 23
Peak memory 193188 kb
Host smart-8b0e99f0-29e1-4d38-84b6-6f5329512d48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142492304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.4142492304
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.285746871
Short name T101
Test name
Test status
Simulation time 44322022 ps
CPU time 0.63 seconds
Started Dec 31 12:23:36 PM PST 23
Finished Dec 31 12:23:39 PM PST 23
Peak memory 193904 kb
Host smart-878b2039-8abd-41b7-a8d4-703c1f6774d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285746871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.285746871
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1166534832
Short name T78
Test name
Test status
Simulation time 16150752 ps
CPU time 0.66 seconds
Started Dec 31 12:24:24 PM PST 23
Finished Dec 31 12:24:28 PM PST 23
Peak memory 196620 kb
Host smart-3d90ce32-fb70-41cb-b904-e55a239f6fb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166534832 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1166534832
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1198067529
Short name T89
Test name
Test status
Simulation time 11731127 ps
CPU time 0.58 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:02 PM PST 23
Peak memory 194004 kb
Host smart-ec5b6832-a2c0-40cd-9688-d67797bd035c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198067529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1198067529
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3849141234
Short name T13
Test name
Test status
Simulation time 14709997 ps
CPU time 0.58 seconds
Started Dec 31 12:29:08 PM PST 23
Finished Dec 31 12:29:14 PM PST 23
Peak memory 193956 kb
Host smart-7809fe41-1adf-4458-baa9-adebe4841012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849141234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3849141234
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2296611392
Short name T924
Test name
Test status
Simulation time 38503056 ps
CPU time 0.69 seconds
Started Dec 31 12:25:49 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 194336 kb
Host smart-b836ce07-2586-473a-866b-1a508d95ee3a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296611392 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2296611392
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1858039939
Short name T102
Test name
Test status
Simulation time 416592981 ps
CPU time 2 seconds
Started Dec 31 12:23:57 PM PST 23
Finished Dec 31 12:24:03 PM PST 23
Peak memory 197456 kb
Host smart-ea374391-7d0b-428b-a16f-2e4dffe1ec5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858039939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1858039939
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.929552947
Short name T907
Test name
Test status
Simulation time 197962261 ps
CPU time 0.86 seconds
Started Dec 31 12:18:05 PM PST 23
Finished Dec 31 12:18:07 PM PST 23
Peak memory 198060 kb
Host smart-24473d3c-b166-4c16-8df1-59737a8b1464
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929552947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.929552947
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.14287705
Short name T127
Test name
Test status
Simulation time 20096299 ps
CPU time 0.68 seconds
Started Dec 31 12:21:56 PM PST 23
Finished Dec 31 12:21:57 PM PST 23
Peak memory 198092 kb
Host smart-02a88921-5246-4756-8aab-56e2f98eb774
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14287705 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.14287705
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3306788072
Short name T115
Test name
Test status
Simulation time 54952241 ps
CPU time 0.63 seconds
Started Dec 31 12:27:49 PM PST 23
Finished Dec 31 12:27:53 PM PST 23
Peak memory 193108 kb
Host smart-858c629f-16ca-4e90-a85b-3dff2445cd78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306788072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3306788072
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.857244678
Short name T903
Test name
Test status
Simulation time 21143786 ps
CPU time 0.54 seconds
Started Dec 31 12:28:46 PM PST 23
Finished Dec 31 12:28:53 PM PST 23
Peak memory 193872 kb
Host smart-5cfbcf1b-1992-472e-81bd-31b7a48ef170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857244678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.857244678
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1844279740
Short name T899
Test name
Test status
Simulation time 32903073 ps
CPU time 0.69 seconds
Started Dec 31 12:24:05 PM PST 23
Finished Dec 31 12:24:11 PM PST 23
Peak memory 193268 kb
Host smart-dd72b8e5-2f60-4c53-af05-c569ab294a36
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844279740 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1844279740
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1846725134
Short name T15
Test name
Test status
Simulation time 330938345 ps
CPU time 1.17 seconds
Started Dec 31 12:24:05 PM PST 23
Finished Dec 31 12:24:12 PM PST 23
Peak memory 196684 kb
Host smart-3c714b18-f535-4c40-bac6-23eadad702fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846725134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1846725134
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.756834709
Short name T35
Test name
Test status
Simulation time 490614280 ps
CPU time 1.08 seconds
Started Dec 31 12:24:06 PM PST 23
Finished Dec 31 12:24:12 PM PST 23
Peak memory 197740 kb
Host smart-718ea0eb-028d-41d1-8d32-359b456a665d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756834709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.756834709
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1019238401
Short name T945
Test name
Test status
Simulation time 50462432 ps
CPU time 0.89 seconds
Started Dec 31 12:34:32 PM PST 23
Finished Dec 31 12:34:35 PM PST 23
Peak memory 198020 kb
Host smart-10508e81-0c5d-486a-9bd9-a23f6ddc4603
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019238401 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1019238401
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2687837385
Short name T964
Test name
Test status
Simulation time 35194517 ps
CPU time 0.68 seconds
Started Dec 31 12:27:49 PM PST 23
Finished Dec 31 12:27:53 PM PST 23
Peak memory 193048 kb
Host smart-bc09e2ab-190e-4bb3-8c85-c67cfed7e223
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687837385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2687837385
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2129979144
Short name T120
Test name
Test status
Simulation time 12240438 ps
CPU time 0.65 seconds
Started Dec 31 12:25:07 PM PST 23
Finished Dec 31 12:25:11 PM PST 23
Peak memory 193676 kb
Host smart-beace4e9-2ac0-44f3-8a57-0490181a6adb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129979144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2129979144
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.142752700
Short name T961
Test name
Test status
Simulation time 53015053 ps
CPU time 0.65 seconds
Started Dec 31 12:34:32 PM PST 23
Finished Dec 31 12:34:35 PM PST 23
Peak memory 194708 kb
Host smart-04dfeaed-965d-41e3-9dca-869c2f39c270
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142752700 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.142752700
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3756048759
Short name T925
Test name
Test status
Simulation time 157612862 ps
CPU time 2.34 seconds
Started Dec 31 12:25:07 PM PST 23
Finished Dec 31 12:25:13 PM PST 23
Peak memory 197844 kb
Host smart-6ce0020d-2ca9-4026-9539-9e37bcf1602d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756048759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3756048759
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1474548139
Short name T36
Test name
Test status
Simulation time 80704938 ps
CPU time 1.18 seconds
Started Dec 31 12:23:03 PM PST 23
Finished Dec 31 12:23:05 PM PST 23
Peak memory 197952 kb
Host smart-9ddece1a-9304-4d51-9a25-c9516fa6adbc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474548139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1474548139
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.4270378746
Short name T893
Test name
Test status
Simulation time 174383703 ps
CPU time 0.92 seconds
Started Dec 31 12:20:58 PM PST 23
Finished Dec 31 12:21:00 PM PST 23
Peak memory 198076 kb
Host smart-2e4bdcd0-d025-411b-81df-be94db529cf6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270378746 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.4270378746
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.4064128325
Short name T88
Test name
Test status
Simulation time 145093842 ps
CPU time 0.66 seconds
Started Dec 31 12:23:03 PM PST 23
Finished Dec 31 12:23:04 PM PST 23
Peak memory 195392 kb
Host smart-b372cd97-e88e-4e18-9023-e836f91b2013
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064128325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.4064128325
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1448125068
Short name T922
Test name
Test status
Simulation time 68067124 ps
CPU time 0.89 seconds
Started Dec 31 12:23:03 PM PST 23
Finished Dec 31 12:23:05 PM PST 23
Peak memory 197032 kb
Host smart-1d626198-5f5f-41c4-90dd-2185fe044728
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448125068 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1448125068
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4160840757
Short name T97
Test name
Test status
Simulation time 210654808 ps
CPU time 2.34 seconds
Started Dec 31 12:23:03 PM PST 23
Finished Dec 31 12:23:06 PM PST 23
Peak memory 198172 kb
Host smart-56036dca-68e0-42f1-9daa-4e49f558c798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160840757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.4160840757
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3003991272
Short name T42
Test name
Test status
Simulation time 373434022 ps
CPU time 1.43 seconds
Started Dec 31 12:23:03 PM PST 23
Finished Dec 31 12:23:05 PM PST 23
Peak memory 198152 kb
Host smart-fc9adf11-4770-4b48-bdcc-d8e5318931a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003991272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3003991272
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3157760654
Short name T953
Test name
Test status
Simulation time 24406149 ps
CPU time 0.77 seconds
Started Dec 31 12:21:47 PM PST 23
Finished Dec 31 12:21:49 PM PST 23
Peak memory 198072 kb
Host smart-11acc77f-6a36-4c6d-945c-fe0a890d3c03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157760654 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3157760654
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.688658101
Short name T949
Test name
Test status
Simulation time 102999712 ps
CPU time 0.58 seconds
Started Dec 31 12:24:32 PM PST 23
Finished Dec 31 12:24:40 PM PST 23
Peak memory 194996 kb
Host smart-dc5158d0-5314-44bc-9c51-db1cf3b368cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688658101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.688658101
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1995847963
Short name T927
Test name
Test status
Simulation time 14441856 ps
CPU time 0.67 seconds
Started Dec 31 12:24:14 PM PST 23
Finished Dec 31 12:24:18 PM PST 23
Peak memory 192780 kb
Host smart-6a7fe78b-95d1-4964-8698-1f1ab21a9344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995847963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1995847963
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2509430553
Short name T914
Test name
Test status
Simulation time 140097620 ps
CPU time 1.74 seconds
Started Dec 31 12:24:53 PM PST 23
Finished Dec 31 12:25:00 PM PST 23
Peak memory 198220 kb
Host smart-c1c9137b-109f-49ad-92c1-f1fc9fd6eea3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509430553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2509430553
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.790766995
Short name T967
Test name
Test status
Simulation time 97370352 ps
CPU time 1.37 seconds
Started Dec 31 12:24:41 PM PST 23
Finished Dec 31 12:24:51 PM PST 23
Peak memory 198084 kb
Host smart-44f6c2b3-a87e-4f72-b8fa-847f9ef0edd7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790766995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.790766995
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.451740332
Short name T610
Test name
Test status
Simulation time 14923150 ps
CPU time 0.59 seconds
Started Dec 31 12:22:03 PM PST 23
Finished Dec 31 12:22:07 PM PST 23
Peak memory 193892 kb
Host smart-3850c405-e474-4366-81ba-b15a2121c4db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451740332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.451740332
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.4022576446
Short name T533
Test name
Test status
Simulation time 227614752 ps
CPU time 0.6 seconds
Started Dec 31 12:23:24 PM PST 23
Finished Dec 31 12:23:25 PM PST 23
Peak memory 194548 kb
Host smart-d805b412-baa1-40f8-9cbb-1186ec21c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022576446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.4022576446
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3974603101
Short name T226
Test name
Test status
Simulation time 913508004 ps
CPU time 22.88 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:26:11 PM PST 23
Peak memory 198008 kb
Host smart-8f0ef5e3-f473-4951-a550-38820c4777f2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974603101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3974603101
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1760491077
Short name T268
Test name
Test status
Simulation time 64455865 ps
CPU time 0.93 seconds
Started Dec 31 12:24:46 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 196868 kb
Host smart-94929b2b-bc9c-49b1-a999-113abb9e4fc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760491077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1760491077
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1211244754
Short name T692
Test name
Test status
Simulation time 88397780 ps
CPU time 0.66 seconds
Started Dec 31 12:25:36 PM PST 23
Finished Dec 31 12:25:45 PM PST 23
Peak memory 193908 kb
Host smart-2c602b42-e647-4a15-bf13-17a074fd0bee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211244754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1211244754
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3485528084
Short name T303
Test name
Test status
Simulation time 283972038 ps
CPU time 1.81 seconds
Started Dec 31 12:25:35 PM PST 23
Finished Dec 31 12:25:46 PM PST 23
Peak memory 198104 kb
Host smart-5a3dbb56-d103-4345-844b-9b98aa04aa23
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485528084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3485528084
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2546245941
Short name T228
Test name
Test status
Simulation time 73713977 ps
CPU time 1.54 seconds
Started Dec 31 12:25:46 PM PST 23
Finished Dec 31 12:25:56 PM PST 23
Peak memory 196036 kb
Host smart-43e2d7f1-de8b-4b0b-ba05-42310b25701b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546245941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2546245941
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2285107912
Short name T235
Test name
Test status
Simulation time 51123125 ps
CPU time 0.67 seconds
Started Dec 31 12:22:55 PM PST 23
Finished Dec 31 12:22:58 PM PST 23
Peak memory 193972 kb
Host smart-e754f300-d0e3-4d9f-8a9a-3def74e432d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285107912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2285107912
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.829382598
Short name T264
Test name
Test status
Simulation time 128024672 ps
CPU time 1.17 seconds
Started Dec 31 12:27:00 PM PST 23
Finished Dec 31 12:27:03 PM PST 23
Peak memory 196456 kb
Host smart-308b8250-c2d5-4468-8507-6e6825e067b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829382598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.829382598
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2961084574
Short name T408
Test name
Test status
Simulation time 97939475 ps
CPU time 3.82 seconds
Started Dec 31 12:26:08 PM PST 23
Finished Dec 31 12:26:16 PM PST 23
Peak memory 197684 kb
Host smart-71ec30c3-2531-4730-bedf-07e2313f54e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961084574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2961084574
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3963519349
Short name T31
Test name
Test status
Simulation time 358035984 ps
CPU time 0.92 seconds
Started Dec 31 12:24:04 PM PST 23
Finished Dec 31 12:24:11 PM PST 23
Peak memory 214516 kb
Host smart-2cdcf12d-db1c-455a-9e34-2821d587685b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963519349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3963519349
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.3081670005
Short name T642
Test name
Test status
Simulation time 171614785 ps
CPU time 1.13 seconds
Started Dec 31 12:24:45 PM PST 23
Finished Dec 31 12:24:53 PM PST 23
Peak memory 194536 kb
Host smart-d3041030-8b42-40e8-98ec-7215ccbc628a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081670005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3081670005
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1043764893
Short name T279
Test name
Test status
Simulation time 67529044 ps
CPU time 1.18 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:22:58 PM PST 23
Peak memory 196060 kb
Host smart-58702435-f29a-4627-8093-ac666827748d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043764893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1043764893
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1628619085
Short name T815
Test name
Test status
Simulation time 47275815248 ps
CPU time 170.8 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:27:12 PM PST 23
Peak memory 198108 kb
Host smart-60ea94f4-d713-455f-8ec1-8d98b19dcb97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628619085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1628619085
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3203839098
Short name T309
Test name
Test status
Simulation time 247638011022 ps
CPU time 199.7 seconds
Started Dec 31 12:25:02 PM PST 23
Finished Dec 31 12:28:26 PM PST 23
Peak memory 198016 kb
Host smart-82f5ca33-91f1-4113-b478-57e5f9034a54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3203839098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3203839098
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1381082816
Short name T726
Test name
Test status
Simulation time 27110076 ps
CPU time 0.56 seconds
Started Dec 31 12:25:59 PM PST 23
Finished Dec 31 12:26:06 PM PST 23
Peak memory 194052 kb
Host smart-964d4589-f5fc-4964-9045-636e51299cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381082816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1381082816
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1225914030
Short name T573
Test name
Test status
Simulation time 56508390 ps
CPU time 0.68 seconds
Started Dec 31 12:24:00 PM PST 23
Finished Dec 31 12:24:08 PM PST 23
Peak memory 193944 kb
Host smart-84eb7d10-46c0-4017-8b37-f330d4c41de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225914030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1225914030
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1979842574
Short name T231
Test name
Test status
Simulation time 714605857 ps
CPU time 5.91 seconds
Started Dec 31 12:23:26 PM PST 23
Finished Dec 31 12:23:33 PM PST 23
Peak memory 195208 kb
Host smart-3e129dd6-79fd-4b0f-97c0-c8d441427eed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979842574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1979842574
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.93310842
Short name T721
Test name
Test status
Simulation time 230689462 ps
CPU time 0.69 seconds
Started Dec 31 12:25:20 PM PST 23
Finished Dec 31 12:25:24 PM PST 23
Peak memory 195388 kb
Host smart-0af429f7-5346-4964-9df7-a48eb35f6774
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93310842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.93310842
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.64973716
Short name T223
Test name
Test status
Simulation time 315982432 ps
CPU time 1.36 seconds
Started Dec 31 12:23:44 PM PST 23
Finished Dec 31 12:23:47 PM PST 23
Peak memory 196624 kb
Host smart-b1c6c7eb-f081-4086-96e6-492c7728f4a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64973716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.64973716
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2085687908
Short name T335
Test name
Test status
Simulation time 261640503 ps
CPU time 2.44 seconds
Started Dec 31 12:24:52 PM PST 23
Finished Dec 31 12:25:01 PM PST 23
Peak memory 197968 kb
Host smart-d4c1c3c8-e751-4cbf-a178-45896a3ca16e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085687908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2085687908
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3885859405
Short name T577
Test name
Test status
Simulation time 91491170 ps
CPU time 0.88 seconds
Started Dec 31 12:24:49 PM PST 23
Finished Dec 31 12:24:55 PM PST 23
Peak memory 193376 kb
Host smart-6df5a1fa-44be-4cc3-af8f-9a97dd315431
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885859405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3885859405
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2261488177
Short name T702
Test name
Test status
Simulation time 238354612 ps
CPU time 0.96 seconds
Started Dec 31 12:22:27 PM PST 23
Finished Dec 31 12:22:28 PM PST 23
Peak memory 195680 kb
Host smart-ade80e8a-2200-4c74-a266-305cd842c35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261488177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2261488177
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2943152287
Short name T484
Test name
Test status
Simulation time 130912189 ps
CPU time 0.83 seconds
Started Dec 31 12:24:37 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 195860 kb
Host smart-cb3788db-c782-457e-b674-630efafd16f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943152287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2943152287
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3276666769
Short name T489
Test name
Test status
Simulation time 912515756 ps
CPU time 1.29 seconds
Started Dec 31 12:26:49 PM PST 23
Finished Dec 31 12:26:52 PM PST 23
Peak memory 197740 kb
Host smart-cf1e8873-25a5-4b89-bc29-e58c7dc83ea9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276666769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3276666769
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3665359013
Short name T65
Test name
Test status
Simulation time 322157006 ps
CPU time 0.9 seconds
Started Dec 31 12:26:27 PM PST 23
Finished Dec 31 12:26:35 PM PST 23
Peak memory 214548 kb
Host smart-17019890-f6b7-46f9-814c-5e320b73815f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665359013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3665359013
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2195621944
Short name T753
Test name
Test status
Simulation time 38523856 ps
CPU time 1.04 seconds
Started Dec 31 12:24:55 PM PST 23
Finished Dec 31 12:25:00 PM PST 23
Peak memory 195404 kb
Host smart-59d21c89-18e5-4761-8985-f39bc2f0a2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195621944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2195621944
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3871522242
Short name T764
Test name
Test status
Simulation time 163031169 ps
CPU time 0.84 seconds
Started Dec 31 12:26:21 PM PST 23
Finished Dec 31 12:26:23 PM PST 23
Peak memory 195304 kb
Host smart-18c501b1-b52d-4a46-82eb-8cec36343478
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871522242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3871522242
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.482049866
Short name T233
Test name
Test status
Simulation time 16356778840 ps
CPU time 170.85 seconds
Started Dec 31 12:23:56 PM PST 23
Finished Dec 31 12:26:52 PM PST 23
Peak memory 198016 kb
Host smart-d7abfddc-411f-48df-bd36-32b8e78196b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482049866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.482049866
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.4053268652
Short name T763
Test name
Test status
Simulation time 35661875690 ps
CPU time 770.25 seconds
Started Dec 31 12:23:59 PM PST 23
Finished Dec 31 12:36:57 PM PST 23
Peak memory 197184 kb
Host smart-66e70a3f-d14e-4eb6-8f8f-95077b321168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4053268652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.4053268652
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3285667515
Short name T383
Test name
Test status
Simulation time 20013048 ps
CPU time 0.54 seconds
Started Dec 31 12:24:48 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 193848 kb
Host smart-554e70c8-6be8-4862-9dc6-e0979838b902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285667515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3285667515
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1320322562
Short name T505
Test name
Test status
Simulation time 106675414 ps
CPU time 0.71 seconds
Started Dec 31 12:24:04 PM PST 23
Finished Dec 31 12:24:11 PM PST 23
Peak memory 195088 kb
Host smart-2d60852e-32a2-46ea-bc4c-694279b62936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320322562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1320322562
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2440064336
Short name T260
Test name
Test status
Simulation time 223886967 ps
CPU time 3.4 seconds
Started Dec 31 12:25:44 PM PST 23
Finished Dec 31 12:25:56 PM PST 23
Peak memory 195484 kb
Host smart-d8abe3b8-4b53-4f19-833d-065b908c2a1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440064336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2440064336
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3108385326
Short name T92
Test name
Test status
Simulation time 175114181 ps
CPU time 0.85 seconds
Started Dec 31 12:25:16 PM PST 23
Finished Dec 31 12:25:21 PM PST 23
Peak memory 195100 kb
Host smart-bc74208f-1cab-47d5-bd09-ce23d276df8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108385326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3108385326
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1411786916
Short name T338
Test name
Test status
Simulation time 160949555 ps
CPU time 0.95 seconds
Started Dec 31 12:23:58 PM PST 23
Finished Dec 31 12:24:03 PM PST 23
Peak memory 196516 kb
Host smart-d49ef7b0-3a9d-44ee-bc2f-bbc574c928c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411786916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1411786916
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3403507472
Short name T862
Test name
Test status
Simulation time 155759652 ps
CPU time 1.66 seconds
Started Dec 31 12:25:23 PM PST 23
Finished Dec 31 12:25:32 PM PST 23
Peak memory 197900 kb
Host smart-9c972d75-f8ae-4831-8318-0c136f231ecc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403507472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3403507472
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.903371684
Short name T835
Test name
Test status
Simulation time 212360463 ps
CPU time 1.81 seconds
Started Dec 31 12:24:31 PM PST 23
Finished Dec 31 12:24:35 PM PST 23
Peak memory 196036 kb
Host smart-6a25bf62-1b40-4e14-9f74-a0eca9cadd75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903371684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
903371684
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2647796026
Short name T689
Test name
Test status
Simulation time 59138008 ps
CPU time 1.28 seconds
Started Dec 31 12:24:44 PM PST 23
Finished Dec 31 12:24:53 PM PST 23
Peak memory 198004 kb
Host smart-9bce5804-ce72-4345-accc-85b1a2d29217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647796026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2647796026
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1252173452
Short name T660
Test name
Test status
Simulation time 303068905 ps
CPU time 1.39 seconds
Started Dec 31 12:24:22 PM PST 23
Finished Dec 31 12:24:27 PM PST 23
Peak memory 197120 kb
Host smart-6a532dfb-7f0c-4530-88d6-82df867908bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252173452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1252173452
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3022729271
Short name T785
Test name
Test status
Simulation time 6589927953 ps
CPU time 5.03 seconds
Started Dec 31 12:25:13 PM PST 23
Finished Dec 31 12:25:20 PM PST 23
Peak memory 197920 kb
Host smart-98b504b6-25b6-4a93-b314-ebebbfb3745d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022729271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3022729271
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2163409464
Short name T740
Test name
Test status
Simulation time 368555942 ps
CPU time 1.34 seconds
Started Dec 31 12:24:10 PM PST 23
Finished Dec 31 12:24:15 PM PST 23
Peak memory 196728 kb
Host smart-222132a9-138b-4cda-90d7-9665c651546c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163409464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2163409464
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3962512246
Short name T299
Test name
Test status
Simulation time 197316051 ps
CPU time 1 seconds
Started Dec 31 12:24:29 PM PST 23
Finished Dec 31 12:24:33 PM PST 23
Peak memory 195004 kb
Host smart-9b9411d7-bb57-4e99-941c-1926e7c7b65c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962512246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3962512246
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2835466402
Short name T693
Test name
Test status
Simulation time 41901039535 ps
CPU time 104.07 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:27:23 PM PST 23
Peak memory 198048 kb
Host smart-e2fc25c4-7f33-4f30-9d89-8aa22d68ee68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835466402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2835466402
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.485117646
Short name T437
Test name
Test status
Simulation time 1032634651913 ps
CPU time 1408.39 seconds
Started Dec 31 12:24:30 PM PST 23
Finished Dec 31 12:48:01 PM PST 23
Peak memory 198160 kb
Host smart-f32f4502-9e5e-4bd9-8dff-4e9c8c2537cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=485117646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.485117646
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2376877086
Short name T370
Test name
Test status
Simulation time 27198246 ps
CPU time 0.6 seconds
Started Dec 31 12:25:15 PM PST 23
Finished Dec 31 12:25:19 PM PST 23
Peak memory 193716 kb
Host smart-3991fcbf-4c8d-499a-a3e2-fd62d259cf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376877086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2376877086
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1180466841
Short name T451
Test name
Test status
Simulation time 1151031745 ps
CPU time 8.84 seconds
Started Dec 31 12:25:00 PM PST 23
Finished Dec 31 12:25:13 PM PST 23
Peak memory 196180 kb
Host smart-30b2381b-fb4b-4211-b559-0cc49dcb5855
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180466841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1180466841
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3591328496
Short name T586
Test name
Test status
Simulation time 56209410 ps
CPU time 0.86 seconds
Started Dec 31 12:24:14 PM PST 23
Finished Dec 31 12:24:18 PM PST 23
Peak memory 196968 kb
Host smart-55b54624-a4a6-42d7-b12f-c05c54162c91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591328496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3591328496
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.961107571
Short name T109
Test name
Test status
Simulation time 105596870 ps
CPU time 0.98 seconds
Started Dec 31 12:25:01 PM PST 23
Finished Dec 31 12:25:05 PM PST 23
Peak memory 196804 kb
Host smart-da74989d-8d95-44e7-bf0d-22540d54eb29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961107571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.961107571
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2870921382
Short name T542
Test name
Test status
Simulation time 90346529 ps
CPU time 3.4 seconds
Started Dec 31 12:25:11 PM PST 23
Finished Dec 31 12:25:17 PM PST 23
Peak memory 197912 kb
Host smart-0a6310ff-b483-45d7-b6d1-6462acfa8630
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870921382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2870921382
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.656742251
Short name T418
Test name
Test status
Simulation time 127410479 ps
CPU time 1.9 seconds
Started Dec 31 12:25:48 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 196976 kb
Host smart-bbc4affa-701b-4a56-9a0e-79cd1b6a2b49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656742251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
656742251
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1351536909
Short name T793
Test name
Test status
Simulation time 21749001 ps
CPU time 0.63 seconds
Started Dec 31 12:24:56 PM PST 23
Finished Dec 31 12:25:00 PM PST 23
Peak memory 194180 kb
Host smart-d66f1d9d-8306-422f-9030-3c9cd24bb320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351536909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1351536909
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3847496039
Short name T841
Test name
Test status
Simulation time 27377211 ps
CPU time 0.77 seconds
Started Dec 31 12:25:45 PM PST 23
Finished Dec 31 12:25:54 PM PST 23
Peak memory 195876 kb
Host smart-77d5adea-5a8d-49ba-a7a2-4f857decbc86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847496039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3847496039
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2265424039
Short name T674
Test name
Test status
Simulation time 32175179 ps
CPU time 1.51 seconds
Started Dec 31 12:25:27 PM PST 23
Finished Dec 31 12:25:35 PM PST 23
Peak memory 197844 kb
Host smart-c2c5df41-f387-4365-8c33-effb4e95e521
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265424039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2265424039
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.743995172
Short name T340
Test name
Test status
Simulation time 288715607 ps
CPU time 1.08 seconds
Started Dec 31 12:25:19 PM PST 23
Finished Dec 31 12:25:24 PM PST 23
Peak memory 195400 kb
Host smart-7388e4a6-53e2-4118-954c-4c0b4b713576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743995172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.743995172
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2942489790
Short name T590
Test name
Test status
Simulation time 401095944 ps
CPU time 1.38 seconds
Started Dec 31 12:24:37 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 196492 kb
Host smart-7fd63b1e-f8ce-455a-a184-2b71f465dea9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942489790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2942489790
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.586133663
Short name T629
Test name
Test status
Simulation time 12982165988 ps
CPU time 100.85 seconds
Started Dec 31 12:26:07 PM PST 23
Finished Dec 31 12:27:52 PM PST 23
Peak memory 197968 kb
Host smart-a24879b9-30bb-48f2-a4b7-19944f318095
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586133663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.586133663
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.492991735
Short name T75
Test name
Test status
Simulation time 74106791874 ps
CPU time 714.19 seconds
Started Dec 31 12:25:41 PM PST 23
Finished Dec 31 12:37:44 PM PST 23
Peak memory 198212 kb
Host smart-e20b0034-edda-4253-96d7-293027a48088
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=492991735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.492991735
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3034825549
Short name T376
Test name
Test status
Simulation time 11704374 ps
CPU time 0.57 seconds
Started Dec 31 12:26:15 PM PST 23
Finished Dec 31 12:26:18 PM PST 23
Peak memory 194016 kb
Host smart-e1e439b0-fd85-4641-9439-b19476fd62d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034825549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3034825549
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2585809387
Short name T707
Test name
Test status
Simulation time 51241343 ps
CPU time 0.77 seconds
Started Dec 31 12:24:57 PM PST 23
Finished Dec 31 12:25:01 PM PST 23
Peak memory 195316 kb
Host smart-607d2b84-54ab-4d70-95f4-64c1807b8623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585809387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2585809387
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1397427694
Short name T232
Test name
Test status
Simulation time 269841219 ps
CPU time 4.25 seconds
Started Dec 31 12:24:12 PM PST 23
Finished Dec 31 12:24:19 PM PST 23
Peak memory 195964 kb
Host smart-c2dc3849-cebc-4be6-b6d6-eb62ec6678ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397427694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1397427694
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1283427915
Short name T883
Test name
Test status
Simulation time 97694031 ps
CPU time 0.66 seconds
Started Dec 31 12:26:17 PM PST 23
Finished Dec 31 12:26:20 PM PST 23
Peak memory 195224 kb
Host smart-6ed1cc55-0c43-4d69-8d64-bc26440b285b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283427915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1283427915
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.4057082443
Short name T424
Test name
Test status
Simulation time 407704870 ps
CPU time 1.32 seconds
Started Dec 31 12:27:04 PM PST 23
Finished Dec 31 12:27:08 PM PST 23
Peak memory 197004 kb
Host smart-7739e684-98ff-4b06-b4ac-15a54b1bfbf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057082443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.4057082443
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1474914307
Short name T560
Test name
Test status
Simulation time 251390084 ps
CPU time 1.53 seconds
Started Dec 31 12:26:01 PM PST 23
Finished Dec 31 12:26:09 PM PST 23
Peak memory 196632 kb
Host smart-4e16f531-d3ea-4997-a6c7-d06bc1e8439c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474914307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1474914307
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2390250448
Short name T453
Test name
Test status
Simulation time 684623646 ps
CPU time 2.08 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:25:51 PM PST 23
Peak memory 197940 kb
Host smart-08f2f238-d331-48ee-b860-78d28a824a8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390250448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2390250448
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.387935049
Short name T413
Test name
Test status
Simulation time 40013314 ps
CPU time 0.83 seconds
Started Dec 31 12:28:05 PM PST 23
Finished Dec 31 12:28:10 PM PST 23
Peak memory 196012 kb
Host smart-0a4bf7aa-161f-4cf6-b02e-9f37611a07dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387935049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.387935049
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3857675372
Short name T643
Test name
Test status
Simulation time 42681514 ps
CPU time 0.95 seconds
Started Dec 31 12:25:57 PM PST 23
Finished Dec 31 12:26:05 PM PST 23
Peak memory 195712 kb
Host smart-e9354fae-be38-4022-afa3-51445e515934
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857675372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3857675372
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3816680732
Short name T290
Test name
Test status
Simulation time 198857856 ps
CPU time 4.67 seconds
Started Dec 31 12:27:36 PM PST 23
Finished Dec 31 12:27:41 PM PST 23
Peak memory 197972 kb
Host smart-85cbae7d-7e87-487c-ba83-c842c6115acf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816680732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3816680732
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3175757794
Short name T826
Test name
Test status
Simulation time 36777583 ps
CPU time 1.04 seconds
Started Dec 31 12:27:00 PM PST 23
Finished Dec 31 12:27:03 PM PST 23
Peak memory 195680 kb
Host smart-8b16f6ec-85e3-43a6-a31f-a720fb045af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175757794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3175757794
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.194688235
Short name T681
Test name
Test status
Simulation time 65040015 ps
CPU time 1.02 seconds
Started Dec 31 12:25:59 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 195736 kb
Host smart-c7743683-839f-41f8-a9ee-98f2053b8363
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194688235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.194688235
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3401412171
Short name T319
Test name
Test status
Simulation time 15566547408 ps
CPU time 76.81 seconds
Started Dec 31 12:25:37 PM PST 23
Finished Dec 31 12:27:02 PM PST 23
Peak memory 198048 kb
Host smart-bcef38a1-62bc-4414-a938-f4731ab48b57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401412171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3401412171
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.301957140
Short name T307
Test name
Test status
Simulation time 119300002972 ps
CPU time 1314.7 seconds
Started Dec 31 12:29:06 PM PST 23
Finished Dec 31 12:51:07 PM PST 23
Peak memory 198192 kb
Host smart-ced67c5b-24bf-4408-b407-127bb7d84911
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=301957140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.301957140
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1787249791
Short name T500
Test name
Test status
Simulation time 13429781 ps
CPU time 0.53 seconds
Started Dec 31 12:29:44 PM PST 23
Finished Dec 31 12:29:47 PM PST 23
Peak memory 193956 kb
Host smart-2e2f96e9-b795-4e85-80d6-8d9f0624e429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787249791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1787249791
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3255840515
Short name T766
Test name
Test status
Simulation time 25889544 ps
CPU time 0.7 seconds
Started Dec 31 12:27:02 PM PST 23
Finished Dec 31 12:27:10 PM PST 23
Peak memory 195072 kb
Host smart-3b05d53a-1e67-4775-b6de-fe7a3ffd7a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255840515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3255840515
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1595038509
Short name T267
Test name
Test status
Simulation time 149728228 ps
CPU time 7.15 seconds
Started Dec 31 12:25:58 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 196328 kb
Host smart-815648ee-342c-4a15-ae3c-9f6eb1582d86
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595038509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1595038509
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3878464448
Short name T786
Test name
Test status
Simulation time 308224858 ps
CPU time 0.88 seconds
Started Dec 31 12:24:12 PM PST 23
Finished Dec 31 12:24:16 PM PST 23
Peak memory 195844 kb
Host smart-cfdbaf26-ec35-49b4-b56e-859fa26b799d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878464448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3878464448
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1818566049
Short name T607
Test name
Test status
Simulation time 338411222 ps
CPU time 1.35 seconds
Started Dec 31 12:24:58 PM PST 23
Finished Dec 31 12:25:03 PM PST 23
Peak memory 198068 kb
Host smart-c0ff2286-74b4-4dac-8d19-7bdd7df54baa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818566049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1818566049
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.4009862141
Short name T570
Test name
Test status
Simulation time 150170935 ps
CPU time 2.9 seconds
Started Dec 31 12:26:47 PM PST 23
Finished Dec 31 12:26:51 PM PST 23
Peak memory 197172 kb
Host smart-20d68666-1ac6-4fdc-8c61-739deca52d3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009862141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.4009862141
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3269674681
Short name T417
Test name
Test status
Simulation time 87956208 ps
CPU time 1.95 seconds
Started Dec 31 12:26:42 PM PST 23
Finished Dec 31 12:26:46 PM PST 23
Peak memory 196728 kb
Host smart-b395f4ab-00da-47d0-9e27-0520e59a1130
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269674681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3269674681
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.404769252
Short name T239
Test name
Test status
Simulation time 32836360 ps
CPU time 0.75 seconds
Started Dec 31 12:25:51 PM PST 23
Finished Dec 31 12:25:59 PM PST 23
Peak memory 195216 kb
Host smart-d126968d-d4f7-4527-a769-cb08ce442daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404769252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.404769252
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3624516058
Short name T650
Test name
Test status
Simulation time 26348404 ps
CPU time 0.88 seconds
Started Dec 31 12:26:18 PM PST 23
Finished Dec 31 12:26:21 PM PST 23
Peak memory 196628 kb
Host smart-fe6cb59c-a087-4910-b420-ade0cc0897ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624516058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3624516058
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3272506156
Short name T555
Test name
Test status
Simulation time 1537991647 ps
CPU time 4.38 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 12:27:24 PM PST 23
Peak memory 197924 kb
Host smart-f8c52096-08f3-42f1-ae07-42ac741ca246
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272506156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3272506156
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.653093316
Short name T717
Test name
Test status
Simulation time 84344724 ps
CPU time 1.03 seconds
Started Dec 31 12:25:50 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 195708 kb
Host smart-d0bdc4e3-2df2-4bf9-8708-1def1860656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653093316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.653093316
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1782426798
Short name T302
Test name
Test status
Simulation time 40401022 ps
CPU time 0.99 seconds
Started Dec 31 12:26:12 PM PST 23
Finished Dec 31 12:26:16 PM PST 23
Peak memory 195436 kb
Host smart-e8e16e0b-4f72-4128-beab-7b6a79539b47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782426798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1782426798
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.520620418
Short name T683
Test name
Test status
Simulation time 28741774293 ps
CPU time 96.41 seconds
Started Dec 31 12:25:51 PM PST 23
Finished Dec 31 12:27:34 PM PST 23
Peak memory 198008 kb
Host smart-f811931f-acc1-42d0-8a06-a5891c4bddf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520620418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.520620418
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.265101684
Short name T587
Test name
Test status
Simulation time 258606465457 ps
CPU time 956.95 seconds
Started Dec 31 12:26:46 PM PST 23
Finished Dec 31 12:42:45 PM PST 23
Peak memory 198532 kb
Host smart-65772870-7c49-4ef6-92aa-b44bbee6112c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=265101684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.265101684
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.645261754
Short name T556
Test name
Test status
Simulation time 39701286 ps
CPU time 0.56 seconds
Started Dec 31 12:24:38 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 194668 kb
Host smart-fd93ffc3-1bfa-425f-8152-72040a188c3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645261754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.645261754
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2109312089
Short name T360
Test name
Test status
Simulation time 46128840 ps
CPU time 0.88 seconds
Started Dec 31 12:25:20 PM PST 23
Finished Dec 31 12:25:24 PM PST 23
Peak memory 197108 kb
Host smart-8d1fb8ff-c1ce-4c9e-9168-ae58387f5ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109312089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2109312089
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.504877196
Short name T243
Test name
Test status
Simulation time 3106061303 ps
CPU time 23.72 seconds
Started Dec 31 12:27:19 PM PST 23
Finished Dec 31 12:27:44 PM PST 23
Peak memory 198044 kb
Host smart-2a011ed3-a2aa-477d-a9d2-f1cdd113e118
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504877196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.504877196
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3752493177
Short name T658
Test name
Test status
Simulation time 143436900 ps
CPU time 0.69 seconds
Started Dec 31 12:26:15 PM PST 23
Finished Dec 31 12:26:18 PM PST 23
Peak memory 194592 kb
Host smart-8205025a-4395-41ab-9389-c5c3d68ec85d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752493177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3752493177
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3385581694
Short name T515
Test name
Test status
Simulation time 57286456 ps
CPU time 1.28 seconds
Started Dec 31 12:26:27 PM PST 23
Finished Dec 31 12:26:30 PM PST 23
Peak memory 197072 kb
Host smart-557a2d14-fcf3-49d1-87fb-cf8b7b68ef4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385581694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3385581694
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.976420405
Short name T314
Test name
Test status
Simulation time 472878018 ps
CPU time 1.49 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:47 PM PST 23
Peak memory 198000 kb
Host smart-7cef40d3-1b42-45b8-9c36-cf5dfd2bc475
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976420405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.976420405
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1475823792
Short name T649
Test name
Test status
Simulation time 87723181 ps
CPU time 0.89 seconds
Started Dec 31 12:25:13 PM PST 23
Finished Dec 31 12:25:18 PM PST 23
Peak memory 196120 kb
Host smart-446e7b32-1e9e-4f2a-95f1-41443f79c4d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475823792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1475823792
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3345813101
Short name T492
Test name
Test status
Simulation time 22810691 ps
CPU time 0.92 seconds
Started Dec 31 12:24:05 PM PST 23
Finished Dec 31 12:24:12 PM PST 23
Peak memory 196620 kb
Host smart-dea0243a-d9eb-4d52-b1a1-a01c71e88c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345813101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3345813101
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1931739990
Short name T543
Test name
Test status
Simulation time 136421927 ps
CPU time 1.34 seconds
Started Dec 31 12:26:28 PM PST 23
Finished Dec 31 12:26:32 PM PST 23
Peak memory 197072 kb
Host smart-cdae7155-82b3-4f6f-a10a-4297925d222d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931739990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1931739990
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.4181682061
Short name T454
Test name
Test status
Simulation time 1668970150 ps
CPU time 4.7 seconds
Started Dec 31 12:26:09 PM PST 23
Finished Dec 31 12:26:19 PM PST 23
Peak memory 198060 kb
Host smart-01c1e323-a459-40f7-9e8a-bc4a2c7c0428
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181682061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.4181682061
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1882109541
Short name T511
Test name
Test status
Simulation time 34094636 ps
CPU time 0.74 seconds
Started Dec 31 12:26:40 PM PST 23
Finished Dec 31 12:26:42 PM PST 23
Peak memory 195172 kb
Host smart-2d447dcf-e8f0-48c1-9ed1-2ddebe24b1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882109541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1882109541
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.4180393386
Short name T278
Test name
Test status
Simulation time 152203741 ps
CPU time 1.16 seconds
Started Dec 31 12:26:29 PM PST 23
Finished Dec 31 12:26:31 PM PST 23
Peak memory 196364 kb
Host smart-3fb85411-0c29-4ce4-a369-8fe509648b6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180393386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.4180393386
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2627789651
Short name T336
Test name
Test status
Simulation time 43018915505 ps
CPU time 106.36 seconds
Started Dec 31 12:25:22 PM PST 23
Finished Dec 31 12:27:13 PM PST 23
Peak memory 197988 kb
Host smart-6f9d8cd9-84ac-4b9c-a3ce-bc317a43c6f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627789651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2627789651
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3164300013
Short name T480
Test name
Test status
Simulation time 58246466889 ps
CPU time 1707.41 seconds
Started Dec 31 12:26:12 PM PST 23
Finished Dec 31 12:54:43 PM PST 23
Peak memory 198292 kb
Host smart-987619ca-8b3f-42ed-a4d9-07b6bebdc75d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3164300013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3164300013
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3490518285
Short name T855
Test name
Test status
Simulation time 26125527 ps
CPU time 0.56 seconds
Started Dec 31 12:25:03 PM PST 23
Finished Dec 31 12:25:12 PM PST 23
Peak memory 193884 kb
Host smart-b46360bc-c8c1-4dcf-96bd-1f0f5f60a433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490518285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3490518285
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3538890939
Short name T615
Test name
Test status
Simulation time 18534876 ps
CPU time 0.65 seconds
Started Dec 31 12:26:01 PM PST 23
Finished Dec 31 12:26:08 PM PST 23
Peak memory 194048 kb
Host smart-29d19bcd-09df-4516-a3fd-574999125b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538890939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3538890939
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.243116386
Short name T686
Test name
Test status
Simulation time 1016438403 ps
CPU time 26.85 seconds
Started Dec 31 12:24:30 PM PST 23
Finished Dec 31 12:25:00 PM PST 23
Peak memory 196712 kb
Host smart-33b529f4-e543-4163-b820-d7987a96b6dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243116386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.243116386
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.4025760786
Short name T559
Test name
Test status
Simulation time 48000193 ps
CPU time 0.75 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:31 PM PST 23
Peak memory 196504 kb
Host smart-3ae27fef-42db-450b-8068-b34a55b247e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025760786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.4025760786
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.406439495
Short name T361
Test name
Test status
Simulation time 51810921 ps
CPU time 1.04 seconds
Started Dec 31 12:24:58 PM PST 23
Finished Dec 31 12:25:03 PM PST 23
Peak memory 196604 kb
Host smart-c109911a-f7e2-4bb6-8a5e-8bd5e3e36625
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406439495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.406439495
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2459449123
Short name T809
Test name
Test status
Simulation time 43405823 ps
CPU time 0.97 seconds
Started Dec 31 12:24:36 PM PST 23
Finished Dec 31 12:24:45 PM PST 23
Peak memory 195752 kb
Host smart-f3b13219-44dd-4cc1-8fb2-7e421dda8c16
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459449123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2459449123
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2900572941
Short name T861
Test name
Test status
Simulation time 147439987 ps
CPU time 1.17 seconds
Started Dec 31 12:24:53 PM PST 23
Finished Dec 31 12:25:00 PM PST 23
Peak memory 196040 kb
Host smart-5068074a-f4f6-4852-b117-cfda6cbae2cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900572941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2900572941
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.679224219
Short name T220
Test name
Test status
Simulation time 25586851 ps
CPU time 0.69 seconds
Started Dec 31 12:25:33 PM PST 23
Finished Dec 31 12:25:41 PM PST 23
Peak memory 195212 kb
Host smart-76ec20cb-1490-4fac-b9fa-976e08750cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679224219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.679224219
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3035742817
Short name T803
Test name
Test status
Simulation time 267732595 ps
CPU time 0.75 seconds
Started Dec 31 12:26:44 PM PST 23
Finished Dec 31 12:26:49 PM PST 23
Peak memory 195172 kb
Host smart-212c4ab9-94f4-464e-a041-17ce5fd591be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035742817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3035742817
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3131171615
Short name T524
Test name
Test status
Simulation time 1017641740 ps
CPU time 4.12 seconds
Started Dec 31 12:25:05 PM PST 23
Finished Dec 31 12:25:13 PM PST 23
Peak memory 197980 kb
Host smart-3e5038b8-b4ac-4575-a05e-7aec70f4db81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131171615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3131171615
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3956575796
Short name T329
Test name
Test status
Simulation time 130339472 ps
CPU time 0.99 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:03 PM PST 23
Peak memory 195568 kb
Host smart-942f298d-6c04-4ff9-9852-1948def861b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956575796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3956575796
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3369358244
Short name T728
Test name
Test status
Simulation time 190834413 ps
CPU time 0.87 seconds
Started Dec 31 12:26:32 PM PST 23
Finished Dec 31 12:26:34 PM PST 23
Peak memory 196100 kb
Host smart-9c2e52e1-24cf-4ffd-926b-6041a74ee398
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369358244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3369358244
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3747070609
Short name T286
Test name
Test status
Simulation time 18236166981 ps
CPU time 125.6 seconds
Started Dec 31 12:25:42 PM PST 23
Finished Dec 31 12:27:56 PM PST 23
Peak memory 197988 kb
Host smart-ab7824eb-391e-4729-b5c2-8bafa3e1dc1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747070609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3747070609
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.128482445
Short name T411
Test name
Test status
Simulation time 185344083044 ps
CPU time 1319.21 seconds
Started Dec 31 12:26:21 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 198164 kb
Host smart-2f0cc4b5-8998-45a9-abc0-4b4e965a507d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=128482445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.128482445
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1613431048
Short name T51
Test name
Test status
Simulation time 34601523 ps
CPU time 0.57 seconds
Started Dec 31 12:25:08 PM PST 23
Finished Dec 31 12:25:16 PM PST 23
Peak memory 194496 kb
Host smart-e63123af-fd29-42c2-a8ce-a7dd513758aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613431048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1613431048
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4158071269
Short name T392
Test name
Test status
Simulation time 14839370 ps
CPU time 0.58 seconds
Started Dec 31 12:24:21 PM PST 23
Finished Dec 31 12:24:25 PM PST 23
Peak memory 193936 kb
Host smart-462c871e-fe3e-4550-a7a0-a8ebd99f3f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158071269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4158071269
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3826352165
Short name T814
Test name
Test status
Simulation time 1507154521 ps
CPU time 9.45 seconds
Started Dec 31 12:25:01 PM PST 23
Finished Dec 31 12:25:14 PM PST 23
Peak memory 195800 kb
Host smart-19b9cefe-f5e0-4251-8162-0a09f0167cac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826352165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3826352165
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3422481615
Short name T711
Test name
Test status
Simulation time 83306411 ps
CPU time 0.99 seconds
Started Dec 31 12:25:29 PM PST 23
Finished Dec 31 12:25:37 PM PST 23
Peak memory 196588 kb
Host smart-0e42fcec-8a5b-4bb4-a6f9-c38f067a5e16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422481615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3422481615
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.4287781125
Short name T854
Test name
Test status
Simulation time 22801539 ps
CPU time 0.74 seconds
Started Dec 31 12:25:17 PM PST 23
Finished Dec 31 12:25:22 PM PST 23
Peak memory 195232 kb
Host smart-36a6f54e-5ad0-4e28-a1eb-2e5f61957f9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287781125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.4287781125
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2756377976
Short name T72
Test name
Test status
Simulation time 148224100 ps
CPU time 3 seconds
Started Dec 31 12:24:32 PM PST 23
Finished Dec 31 12:24:37 PM PST 23
Peak memory 197964 kb
Host smart-d9b7b2ab-3bd1-4662-9eea-9aead8bd9bd7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756377976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2756377976
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3759689400
Short name T358
Test name
Test status
Simulation time 333359260 ps
CPU time 2.51 seconds
Started Dec 31 12:25:49 PM PST 23
Finished Dec 31 12:25:59 PM PST 23
Peak memory 196800 kb
Host smart-9ef53501-620d-4004-9b67-039a5be8a334
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759689400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3759689400
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3625210611
Short name T562
Test name
Test status
Simulation time 352637205 ps
CPU time 0.73 seconds
Started Dec 31 12:26:52 PM PST 23
Finished Dec 31 12:26:54 PM PST 23
Peak memory 195972 kb
Host smart-8f99db04-23ab-4985-add4-b05df8e2ed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625210611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3625210611
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.364454153
Short name T606
Test name
Test status
Simulation time 270800379 ps
CPU time 1.14 seconds
Started Dec 31 12:26:53 PM PST 23
Finished Dec 31 12:26:56 PM PST 23
Peak memory 196976 kb
Host smart-0271cfe7-64ca-4051-97d5-d3820b6cf9d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364454153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.364454153
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3105282110
Short name T579
Test name
Test status
Simulation time 592813945 ps
CPU time 4.73 seconds
Started Dec 31 12:26:11 PM PST 23
Finished Dec 31 12:26:19 PM PST 23
Peak memory 197860 kb
Host smart-819ecb1d-9441-4df4-bdff-64137c473df8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105282110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3105282110
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.322091517
Short name T410
Test name
Test status
Simulation time 76558920 ps
CPU time 1.16 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:25:41 PM PST 23
Peak memory 195772 kb
Host smart-c93ef3b5-d408-42d1-90a2-281c5ef6a229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322091517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.322091517
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3532183575
Short name T712
Test name
Test status
Simulation time 179723649 ps
CPU time 0.92 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:47 PM PST 23
Peak memory 195672 kb
Host smart-5925216b-3fb9-43c5-ad81-415d31581e09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532183575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3532183575
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3363207017
Short name T563
Test name
Test status
Simulation time 22072095815 ps
CPU time 57.54 seconds
Started Dec 31 12:25:07 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 198076 kb
Host smart-6452209d-ed67-40b5-bf3b-8e5783fc574f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363207017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3363207017
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1122500658
Short name T457
Test name
Test status
Simulation time 67050600163 ps
CPU time 313.91 seconds
Started Dec 31 12:25:33 PM PST 23
Finished Dec 31 12:30:54 PM PST 23
Peak memory 198284 kb
Host smart-eab53a0c-8c7b-4c12-9c13-8ec152197a4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1122500658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1122500658
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3386151432
Short name T253
Test name
Test status
Simulation time 35263434 ps
CPU time 0.55 seconds
Started Dec 31 12:26:21 PM PST 23
Finished Dec 31 12:26:22 PM PST 23
Peak memory 194020 kb
Host smart-8fb1db54-9c01-47ba-8304-65aa4675167f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386151432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3386151432
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1948951517
Short name T425
Test name
Test status
Simulation time 22294948 ps
CPU time 0.71 seconds
Started Dec 31 12:27:21 PM PST 23
Finished Dec 31 12:27:32 PM PST 23
Peak memory 195912 kb
Host smart-44780e8a-13b8-4291-988f-21b0494cd32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948951517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1948951517
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2370032161
Short name T644
Test name
Test status
Simulation time 1142219148 ps
CPU time 21 seconds
Started Dec 31 12:25:48 PM PST 23
Finished Dec 31 12:26:19 PM PST 23
Peak memory 198068 kb
Host smart-80ee8b3b-1126-4c99-8a5b-0c36a1eb97ec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370032161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2370032161
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1556605815
Short name T70
Test name
Test status
Simulation time 1039642140 ps
CPU time 0.8 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:31 PM PST 23
Peak memory 195636 kb
Host smart-1f2a9631-2744-461e-a57c-aaccbd30754e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556605815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1556605815
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2810360625
Short name T884
Test name
Test status
Simulation time 294884272 ps
CPU time 1.27 seconds
Started Dec 31 12:25:08 PM PST 23
Finished Dec 31 12:25:13 PM PST 23
Peak memory 197064 kb
Host smart-c8975ab6-7daa-4465-8740-d35433f88541
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810360625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2810360625
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2826091950
Short name T332
Test name
Test status
Simulation time 76680619 ps
CPU time 2.42 seconds
Started Dec 31 12:26:18 PM PST 23
Finished Dec 31 12:26:23 PM PST 23
Peak memory 198060 kb
Host smart-5a60193e-9028-4a56-89ac-cddc59c3071b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826091950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2826091950
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2320991694
Short name T291
Test name
Test status
Simulation time 69077050 ps
CPU time 1.43 seconds
Started Dec 31 12:27:43 PM PST 23
Finished Dec 31 12:27:45 PM PST 23
Peak memory 195684 kb
Host smart-e0a2897f-f474-46b5-b2ef-8841228fd7c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320991694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2320991694
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2861325844
Short name T708
Test name
Test status
Simulation time 109073106 ps
CPU time 1.17 seconds
Started Dec 31 12:25:17 PM PST 23
Finished Dec 31 12:25:22 PM PST 23
Peak memory 198080 kb
Host smart-c12c83ed-b159-46d8-84b5-e1d8c90204d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861325844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2861325844
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2003608411
Short name T409
Test name
Test status
Simulation time 27731605 ps
CPU time 0.73 seconds
Started Dec 31 12:27:27 PM PST 23
Finished Dec 31 12:27:28 PM PST 23
Peak memory 195204 kb
Host smart-17763658-3dab-42b9-ba76-4c54e20fec6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003608411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2003608411
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3268098081
Short name T621
Test name
Test status
Simulation time 130933816 ps
CPU time 2.16 seconds
Started Dec 31 12:27:38 PM PST 23
Finished Dec 31 12:27:41 PM PST 23
Peak memory 197720 kb
Host smart-af4d2f0f-dba7-4810-afe9-b0a84df3ec5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268098081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3268098081
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3126031599
Short name T585
Test name
Test status
Simulation time 108428813 ps
CPU time 0.93 seconds
Started Dec 31 12:25:08 PM PST 23
Finished Dec 31 12:25:14 PM PST 23
Peak memory 195540 kb
Host smart-12982c5b-a7af-449f-8060-214b1fff3b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126031599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3126031599
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3870130503
Short name T535
Test name
Test status
Simulation time 41439872 ps
CPU time 1.13 seconds
Started Dec 31 12:24:44 PM PST 23
Finished Dec 31 12:24:53 PM PST 23
Peak memory 196768 kb
Host smart-7d76698b-2e3a-4519-a9c0-9dc675a016c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870130503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3870130503
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3279688634
Short name T294
Test name
Test status
Simulation time 27751117084 ps
CPU time 171.65 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:28:38 PM PST 23
Peak memory 198124 kb
Host smart-aa8dd102-3427-431a-a643-6c214313e10f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279688634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3279688634
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.817622011
Short name T245
Test name
Test status
Simulation time 17388612801 ps
CPU time 235.42 seconds
Started Dec 31 12:25:17 PM PST 23
Finished Dec 31 12:29:17 PM PST 23
Peak memory 198244 kb
Host smart-d323abbe-9350-465f-911a-42aa8679f80c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=817622011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.817622011
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1427544274
Short name T389
Test name
Test status
Simulation time 18576116 ps
CPU time 0.6 seconds
Started Dec 31 12:25:11 PM PST 23
Finished Dec 31 12:25:15 PM PST 23
Peak memory 195216 kb
Host smart-db0089ba-44fc-4940-a260-96cbe0b20c0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427544274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1427544274
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1972085504
Short name T645
Test name
Test status
Simulation time 59217591 ps
CPU time 0.62 seconds
Started Dec 31 12:25:02 PM PST 23
Finished Dec 31 12:25:07 PM PST 23
Peak memory 193908 kb
Host smart-7176b57e-d8c4-488d-9399-2e42c3477a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972085504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1972085504
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1882544013
Short name T673
Test name
Test status
Simulation time 420082335 ps
CPU time 23.37 seconds
Started Dec 31 12:24:35 PM PST 23
Finished Dec 31 12:25:07 PM PST 23
Peak memory 197872 kb
Host smart-ed653315-0001-4d12-86ac-3c599343278e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882544013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1882544013
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2605257401
Short name T830
Test name
Test status
Simulation time 45325259 ps
CPU time 0.73 seconds
Started Dec 31 12:24:33 PM PST 23
Finished Dec 31 12:24:42 PM PST 23
Peak memory 195636 kb
Host smart-48e467dc-e6d3-4105-8a71-a1ec967710c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605257401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2605257401
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1986019493
Short name T584
Test name
Test status
Simulation time 565985589 ps
CPU time 1.4 seconds
Started Dec 31 12:24:32 PM PST 23
Finished Dec 31 12:24:37 PM PST 23
Peak memory 196784 kb
Host smart-79c77c7a-f683-40f5-bb48-3b60d1b76d8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986019493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1986019493
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3096277107
Short name T879
Test name
Test status
Simulation time 58888644 ps
CPU time 1.94 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:04 PM PST 23
Peak memory 198072 kb
Host smart-2326a911-ae59-4d4e-a26c-1a9806d78c7c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096277107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3096277107
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2668176992
Short name T773
Test name
Test status
Simulation time 286723353 ps
CPU time 1.35 seconds
Started Dec 31 12:24:35 PM PST 23
Finished Dec 31 12:24:44 PM PST 23
Peak memory 196040 kb
Host smart-0d98fb83-8663-4856-a67c-43cba2804e8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668176992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2668176992
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2462887519
Short name T783
Test name
Test status
Simulation time 157114120 ps
CPU time 1.13 seconds
Started Dec 31 12:24:45 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 197240 kb
Host smart-0471f526-1b88-4cbd-aad1-0b9ad25dcf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462887519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2462887519
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3481733594
Short name T837
Test name
Test status
Simulation time 72131944 ps
CPU time 1.17 seconds
Started Dec 31 12:27:41 PM PST 23
Finished Dec 31 12:27:43 PM PST 23
Peak memory 196868 kb
Host smart-d141b8ec-30fb-4eba-a7f2-311500fc0cd9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481733594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3481733594
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3525828598
Short name T493
Test name
Test status
Simulation time 1626994894 ps
CPU time 6.04 seconds
Started Dec 31 12:25:04 PM PST 23
Finished Dec 31 12:25:14 PM PST 23
Peak memory 197920 kb
Host smart-c19f9fdf-55d0-48a2-8401-a8f4b9c55a1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525828598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3525828598
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.69668307
Short name T735
Test name
Test status
Simulation time 110196186 ps
CPU time 1.13 seconds
Started Dec 31 12:27:41 PM PST 23
Finished Dec 31 12:27:43 PM PST 23
Peak memory 196300 kb
Host smart-1b80cc55-8fe8-4078-b307-23ebeee26de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69668307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.69668307
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2624846590
Short name T831
Test name
Test status
Simulation time 220781274 ps
CPU time 1.01 seconds
Started Dec 31 12:25:55 PM PST 23
Finished Dec 31 12:26:04 PM PST 23
Peak memory 196196 kb
Host smart-4154a722-3bd9-44e3-8330-048ac6b4ab81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624846590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2624846590
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3001513993
Short name T441
Test name
Test status
Simulation time 8563027345 ps
CPU time 47.57 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:26:33 PM PST 23
Peak memory 198060 kb
Host smart-40be4ec4-4a6d-4aa4-8fd0-b58034d03fb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001513993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3001513993
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2428284126
Short name T317
Test name
Test status
Simulation time 105028677227 ps
CPU time 316.15 seconds
Started Dec 31 12:24:36 PM PST 23
Finished Dec 31 12:30:01 PM PST 23
Peak memory 206360 kb
Host smart-00e360c7-4c49-4109-8069-e24c6306a612
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2428284126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2428284126
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3970738490
Short name T330
Test name
Test status
Simulation time 21607178 ps
CPU time 0.57 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:25:49 PM PST 23
Peak memory 193992 kb
Host smart-55cd9ebe-d956-46e5-bcc0-f7fb213934fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970738490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3970738490
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.971541227
Short name T557
Test name
Test status
Simulation time 34510641 ps
CPU time 0.67 seconds
Started Dec 31 12:24:52 PM PST 23
Finished Dec 31 12:24:59 PM PST 23
Peak memory 195020 kb
Host smart-36961521-9450-4bd5-bedf-6f466c46091a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971541227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.971541227
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2043996571
Short name T646
Test name
Test status
Simulation time 3296803963 ps
CPU time 9.32 seconds
Started Dec 31 12:25:10 PM PST 23
Finished Dec 31 12:25:23 PM PST 23
Peak memory 196552 kb
Host smart-46bf3ee9-60d1-4b46-85f7-07130368904c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043996571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2043996571
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3156745808
Short name T865
Test name
Test status
Simulation time 25086652 ps
CPU time 0.64 seconds
Started Dec 31 12:25:01 PM PST 23
Finished Dec 31 12:25:05 PM PST 23
Peak memory 194648 kb
Host smart-61f80266-2fd5-4ad5-aa0a-ca9f4b8a6e80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156745808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3156745808
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2903602003
Short name T798
Test name
Test status
Simulation time 56762449 ps
CPU time 1.03 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:25:54 PM PST 23
Peak memory 195780 kb
Host smart-ac83aae1-3711-4f2f-a809-57355a880fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903602003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2903602003
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1779284937
Short name T117
Test name
Test status
Simulation time 80868835 ps
CPU time 2.81 seconds
Started Dec 31 12:24:40 PM PST 23
Finished Dec 31 12:24:50 PM PST 23
Peak memory 197980 kb
Host smart-9fd584a4-4200-4908-8403-22b1dbbb4b83
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779284937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1779284937
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1549417032
Short name T873
Test name
Test status
Simulation time 320787574 ps
CPU time 2.15 seconds
Started Dec 31 12:24:56 PM PST 23
Finished Dec 31 12:25:02 PM PST 23
Peak memory 197020 kb
Host smart-2f8969e6-87ef-483a-be9f-3a3da8a47e30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549417032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1549417032
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2281386665
Short name T386
Test name
Test status
Simulation time 121207455 ps
CPU time 0.84 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:25:40 PM PST 23
Peak memory 197288 kb
Host smart-4d40c48b-2031-4b6b-ab1b-4d3ebb706773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281386665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2281386665
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3759031606
Short name T757
Test name
Test status
Simulation time 35392264 ps
CPU time 0.81 seconds
Started Dec 31 12:25:02 PM PST 23
Finished Dec 31 12:25:07 PM PST 23
Peak memory 196220 kb
Host smart-34819fbb-5651-4708-8793-dd969415a2ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759031606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3759031606
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.903494337
Short name T722
Test name
Test status
Simulation time 444038491 ps
CPU time 5.41 seconds
Started Dec 31 12:24:35 PM PST 23
Finished Dec 31 12:24:49 PM PST 23
Peak memory 197940 kb
Host smart-3314b287-f7b6-4d1a-b354-da2cb4c68e26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903494337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.903494337
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1293629696
Short name T298
Test name
Test status
Simulation time 163365291 ps
CPU time 1.01 seconds
Started Dec 31 12:24:47 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 195488 kb
Host smart-ab92b66a-9541-47f3-a20f-393446063edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293629696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1293629696
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1166126388
Short name T807
Test name
Test status
Simulation time 32852391 ps
CPU time 0.75 seconds
Started Dec 31 12:24:50 PM PST 23
Finished Dec 31 12:24:56 PM PST 23
Peak memory 195848 kb
Host smart-985bf117-1f4e-418b-85d2-36aeac01eb7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166126388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1166126388
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3141208110
Short name T514
Test name
Test status
Simulation time 8876315551 ps
CPU time 114.35 seconds
Started Dec 31 12:24:52 PM PST 23
Finished Dec 31 12:26:53 PM PST 23
Peak memory 198012 kb
Host smart-4849e3b9-ed19-4fe6-928e-1cc73f8705ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141208110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3141208110
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.2405091244
Short name T541
Test name
Test status
Simulation time 166654353860 ps
CPU time 526.58 seconds
Started Dec 31 12:25:14 PM PST 23
Finished Dec 31 12:34:04 PM PST 23
Peak memory 198220 kb
Host smart-7c6b1065-f038-4dc5-82a5-41c832a5b888
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2405091244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.2405091244
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2770342499
Short name T885
Test name
Test status
Simulation time 15455942 ps
CPU time 0.64 seconds
Started Dec 31 12:24:00 PM PST 23
Finished Dec 31 12:24:08 PM PST 23
Peak memory 193748 kb
Host smart-572687bc-86c2-43ac-a3a8-509e3c5251cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770342499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2770342499
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.235587588
Short name T436
Test name
Test status
Simulation time 31347960 ps
CPU time 0.76 seconds
Started Dec 31 12:25:06 PM PST 23
Finished Dec 31 12:25:10 PM PST 23
Peak memory 195076 kb
Host smart-e64f4b6f-0b05-4987-ae59-eb20be214eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235587588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.235587588
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2865022316
Short name T322
Test name
Test status
Simulation time 532934545 ps
CPU time 27.42 seconds
Started Dec 31 12:25:18 PM PST 23
Finished Dec 31 12:25:49 PM PST 23
Peak memory 198064 kb
Host smart-e09349d7-c2e1-41af-994c-30c32d61ddcf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865022316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2865022316
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2067160375
Short name T648
Test name
Test status
Simulation time 40087357 ps
CPU time 0.93 seconds
Started Dec 31 12:21:16 PM PST 23
Finished Dec 31 12:21:17 PM PST 23
Peak memory 195892 kb
Host smart-9418c7bd-a230-4e77-9606-55a7e71970d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067160375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2067160375
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1330866769
Short name T800
Test name
Test status
Simulation time 192443298 ps
CPU time 0.79 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 195292 kb
Host smart-e6301bd8-8d35-4279-92d3-96431fd64abe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330866769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1330866769
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1533671665
Short name T775
Test name
Test status
Simulation time 64550511 ps
CPU time 2.47 seconds
Started Dec 31 12:27:49 PM PST 23
Finished Dec 31 12:27:55 PM PST 23
Peak memory 194680 kb
Host smart-a838ced1-0ae0-41e3-86f1-c6801fa7f7b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533671665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1533671665
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3105594331
Short name T738
Test name
Test status
Simulation time 44486070 ps
CPU time 1.38 seconds
Started Dec 31 12:23:10 PM PST 23
Finished Dec 31 12:23:12 PM PST 23
Peak memory 195928 kb
Host smart-adfc6c76-c01e-4e5a-8b0e-1ab7d36655ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105594331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3105594331
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3823167680
Short name T868
Test name
Test status
Simulation time 239414446 ps
CPU time 0.79 seconds
Started Dec 31 12:26:44 PM PST 23
Finished Dec 31 12:26:51 PM PST 23
Peak memory 196024 kb
Host smart-7c84d557-45b0-4c12-b696-ed4d2d0f34b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823167680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3823167680
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1779924536
Short name T523
Test name
Test status
Simulation time 62393652 ps
CPU time 1.09 seconds
Started Dec 31 12:24:42 PM PST 23
Finished Dec 31 12:24:52 PM PST 23
Peak memory 195904 kb
Host smart-3ed40f9d-e65e-4717-b404-dcd8f856c24a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779924536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1779924536
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1716011641
Short name T857
Test name
Test status
Simulation time 868527993 ps
CPU time 3.62 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:23:02 PM PST 23
Peak memory 197944 kb
Host smart-e83f7baf-139a-468e-8c6c-4357e1225a47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716011641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1716011641
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.4196989324
Short name T66
Test name
Test status
Simulation time 215677715 ps
CPU time 0.85 seconds
Started Dec 31 12:24:10 PM PST 23
Finished Dec 31 12:24:15 PM PST 23
Peak memory 213316 kb
Host smart-0971096d-85b6-47ba-ad8b-8cabf45e29f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196989324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.4196989324
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1216982363
Short name T612
Test name
Test status
Simulation time 286779616 ps
CPU time 1.1 seconds
Started Dec 31 12:26:45 PM PST 23
Finished Dec 31 12:26:47 PM PST 23
Peak memory 195472 kb
Host smart-4197304d-cfa0-4552-8e8a-4820134b881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216982363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1216982363
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3467972014
Short name T439
Test name
Test status
Simulation time 521261721 ps
CPU time 1.32 seconds
Started Dec 31 12:25:02 PM PST 23
Finished Dec 31 12:25:08 PM PST 23
Peak memory 195384 kb
Host smart-b2adbfcf-e9b0-47f5-9b16-782e726f3e21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467972014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3467972014
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.56776698
Short name T819
Test name
Test status
Simulation time 6918664318 ps
CPU time 48.36 seconds
Started Dec 31 12:24:34 PM PST 23
Finished Dec 31 12:25:30 PM PST 23
Peak memory 198052 kb
Host smart-5dfb1af4-af65-40e2-a4ab-a17a537d348d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56776698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpi
o_stress_all.56776698
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.833455310
Short name T247
Test name
Test status
Simulation time 364855568328 ps
CPU time 1080.07 seconds
Started Dec 31 12:24:22 PM PST 23
Finished Dec 31 12:42:25 PM PST 23
Peak memory 198156 kb
Host smart-b8b20c63-0252-4c74-baf2-e81cf650ab5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=833455310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.833455310
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1920085143
Short name T805
Test name
Test status
Simulation time 40132540 ps
CPU time 0.56 seconds
Started Dec 31 12:24:37 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 194268 kb
Host smart-c586c492-63e5-453e-b033-8261b1828871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920085143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1920085143
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3628954321
Short name T272
Test name
Test status
Simulation time 175161523 ps
CPU time 0.7 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 195016 kb
Host smart-5972f554-7435-453f-92a1-98e46f0b1018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628954321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3628954321
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.74370575
Short name T538
Test name
Test status
Simulation time 8662938421 ps
CPU time 29.35 seconds
Started Dec 31 12:25:08 PM PST 23
Finished Dec 31 12:25:40 PM PST 23
Peak memory 197840 kb
Host smart-d05f89b3-2642-406a-abf5-7355c3e49de6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74370575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stress
.74370575
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2494808091
Short name T595
Test name
Test status
Simulation time 155191189 ps
CPU time 0.92 seconds
Started Dec 31 12:24:37 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 197424 kb
Host smart-f080f101-3353-47f1-a6a1-0e31e2580c2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494808091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2494808091
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2143926684
Short name T445
Test name
Test status
Simulation time 99242652 ps
CPU time 0.78 seconds
Started Dec 31 12:25:50 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 195508 kb
Host smart-a72ba13e-d9e9-4296-b964-c1ec39b8e26e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143926684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2143926684
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.754990912
Short name T118
Test name
Test status
Simulation time 89965384 ps
CPU time 0.99 seconds
Started Dec 31 12:25:02 PM PST 23
Finished Dec 31 12:25:08 PM PST 23
Peak memory 196124 kb
Host smart-0d7784f3-2e31-4893-94bb-7f0f78d0416a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754990912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.754990912
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3218004518
Short name T765
Test name
Test status
Simulation time 99647638 ps
CPU time 1.06 seconds
Started Dec 31 12:25:41 PM PST 23
Finished Dec 31 12:25:51 PM PST 23
Peak memory 196344 kb
Host smart-a2a65257-2642-4a51-ab99-418cd1a44d74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218004518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3218004518
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3845986170
Short name T394
Test name
Test status
Simulation time 48434314 ps
CPU time 0.71 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:25:40 PM PST 23
Peak memory 195264 kb
Host smart-ef0f7b12-a7b4-43f2-afde-bec5c59865dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845986170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3845986170
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2102496849
Short name T852
Test name
Test status
Simulation time 32874443 ps
CPU time 0.78 seconds
Started Dec 31 12:24:28 PM PST 23
Finished Dec 31 12:24:31 PM PST 23
Peak memory 195276 kb
Host smart-6ced76f2-4d94-4739-9808-9ea4b352ad0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102496849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2102496849
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2424902438
Short name T255
Test name
Test status
Simulation time 775428851 ps
CPU time 4.64 seconds
Started Dec 31 12:24:32 PM PST 23
Finished Dec 31 12:24:40 PM PST 23
Peak memory 198000 kb
Host smart-ef775b4b-4d4f-4eb4-9a00-bd8b248c3897
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424902438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2424902438
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.873037295
Short name T328
Test name
Test status
Simulation time 61580436 ps
CPU time 1.02 seconds
Started Dec 31 12:25:06 PM PST 23
Finished Dec 31 12:25:10 PM PST 23
Peak memory 196468 kb
Host smart-5d30a39e-030f-4e76-b445-fcec00b18363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873037295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.873037295
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.939294867
Short name T669
Test name
Test status
Simulation time 53890382 ps
CPU time 1.36 seconds
Started Dec 31 12:25:57 PM PST 23
Finished Dec 31 12:26:05 PM PST 23
Peak memory 195596 kb
Host smart-20b29bad-16a3-4197-8335-daa885107f20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939294867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.939294867
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2006187194
Short name T281
Test name
Test status
Simulation time 26358851595 ps
CPU time 134.18 seconds
Started Dec 31 12:24:37 PM PST 23
Finished Dec 31 12:26:59 PM PST 23
Peak memory 197984 kb
Host smart-02fd5f20-d349-4db0-864a-628dccf9a934
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006187194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2006187194
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.560751525
Short name T772
Test name
Test status
Simulation time 36041742989 ps
CPU time 118.31 seconds
Started Dec 31 12:25:06 PM PST 23
Finished Dec 31 12:27:07 PM PST 23
Peak memory 198216 kb
Host smart-e2a09009-fe33-403d-9c10-8b41f6a8a5d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=560751525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.560751525
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.34015678
Short name T470
Test name
Test status
Simulation time 14799427 ps
CPU time 0.56 seconds
Started Dec 31 12:25:16 PM PST 23
Finished Dec 31 12:25:20 PM PST 23
Peak memory 194536 kb
Host smart-57f57eb8-8bf3-4eb9-b7f2-108427693adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34015678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.34015678
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2282761015
Short name T57
Test name
Test status
Simulation time 415729058 ps
CPU time 0.72 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:25:49 PM PST 23
Peak memory 195036 kb
Host smart-6eb4da93-8945-40f5-9e61-d40c7fe24d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282761015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2282761015
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1544821497
Short name T284
Test name
Test status
Simulation time 1888222998 ps
CPU time 6.7 seconds
Started Dec 31 12:25:43 PM PST 23
Finished Dec 31 12:25:59 PM PST 23
Peak memory 195444 kb
Host smart-ed3b7762-d109-4cac-bfb6-a2fea28f9958
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544821497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1544821497
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3074858143
Short name T355
Test name
Test status
Simulation time 330640204 ps
CPU time 1.04 seconds
Started Dec 31 12:25:31 PM PST 23
Finished Dec 31 12:25:40 PM PST 23
Peak memory 196316 kb
Host smart-d4a6af38-56b4-44a4-9b48-c2ed405ac2ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074858143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3074858143
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3161839410
Short name T569
Test name
Test status
Simulation time 159568552 ps
CPU time 1.29 seconds
Started Dec 31 12:24:37 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 197120 kb
Host smart-f38984fe-7781-4b40-98e8-587b3a9ada33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161839410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3161839410
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3284514100
Short name T365
Test name
Test status
Simulation time 309350259 ps
CPU time 2.89 seconds
Started Dec 31 12:26:41 PM PST 23
Finished Dec 31 12:26:45 PM PST 23
Peak memory 197960 kb
Host smart-6b7ac8ca-e526-44bf-90d5-eec545585902
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284514100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3284514100
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1101960318
Short name T321
Test name
Test status
Simulation time 687077254 ps
CPU time 3.04 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:50 PM PST 23
Peak memory 196948 kb
Host smart-7d7f2798-6706-4890-936a-da73c9926733
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101960318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1101960318
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1295980979
Short name T795
Test name
Test status
Simulation time 89805814 ps
CPU time 1.21 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:47 PM PST 23
Peak memory 195764 kb
Host smart-c4787226-ec76-4807-a8be-9b33b2b098f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295980979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1295980979
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3396558314
Short name T631
Test name
Test status
Simulation time 39835813 ps
CPU time 0.65 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:25:49 PM PST 23
Peak memory 194336 kb
Host smart-d22a838a-abc0-41b6-bf33-79a8600235e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396558314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3396558314
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1950670752
Short name T222
Test name
Test status
Simulation time 586342726 ps
CPU time 2.55 seconds
Started Dec 31 12:25:52 PM PST 23
Finished Dec 31 12:26:02 PM PST 23
Peak memory 197832 kb
Host smart-0ccf87dc-4cd7-439d-9cd1-30ae02fc9867
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950670752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1950670752
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2165772809
Short name T422
Test name
Test status
Simulation time 81346356 ps
CPU time 1.28 seconds
Started Dec 31 12:25:43 PM PST 23
Finished Dec 31 12:25:53 PM PST 23
Peak memory 194848 kb
Host smart-c00ed093-985e-403d-a301-f87893a44f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165772809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2165772809
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3079718707
Short name T725
Test name
Test status
Simulation time 147352689 ps
CPU time 1.09 seconds
Started Dec 31 12:26:19 PM PST 23
Finished Dec 31 12:26:22 PM PST 23
Peak memory 195528 kb
Host smart-4b68ce50-1bcb-4be5-a43c-241e64dba44b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079718707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3079718707
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.21618638
Short name T266
Test name
Test status
Simulation time 8495544336 ps
CPU time 58.23 seconds
Started Dec 31 12:25:51 PM PST 23
Finished Dec 31 12:26:56 PM PST 23
Peak memory 198028 kb
Host smart-46c553bf-cc49-4d13-9c4c-ffc14606c483
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21618638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gp
io_stress_all.21618638
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2666424955
Short name T296
Test name
Test status
Simulation time 278179584737 ps
CPU time 880.86 seconds
Started Dec 31 12:26:38 PM PST 23
Finished Dec 31 12:41:21 PM PST 23
Peak memory 198160 kb
Host smart-5b8051c3-43d4-45fd-a7bc-a8df77e24079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2666424955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2666424955
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1529477579
Short name T592
Test name
Test status
Simulation time 76512945 ps
CPU time 0.55 seconds
Started Dec 31 12:24:48 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 193816 kb
Host smart-6f9915bd-bfd6-4025-924a-4f238ff21017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529477579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1529477579
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1717486134
Short name T733
Test name
Test status
Simulation time 476320747 ps
CPU time 0.76 seconds
Started Dec 31 12:25:47 PM PST 23
Finished Dec 31 12:25:56 PM PST 23
Peak memory 196012 kb
Host smart-18b69948-d05e-4f62-90b7-9f9930ccf5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717486134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1717486134
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.821685214
Short name T352
Test name
Test status
Simulation time 469346232 ps
CPU time 21.82 seconds
Started Dec 31 12:25:02 PM PST 23
Finished Dec 31 12:25:28 PM PST 23
Peak memory 196836 kb
Host smart-f1ec0b4e-b125-48f8-83e0-b91e7a58bab3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821685214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.821685214
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.745838305
Short name T838
Test name
Test status
Simulation time 671485634 ps
CPU time 0.96 seconds
Started Dec 31 12:26:12 PM PST 23
Finished Dec 31 12:26:16 PM PST 23
Peak memory 196712 kb
Host smart-7d9a4013-8ae7-422b-adf9-7f096d28b2c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745838305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.745838305
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2232051040
Short name T293
Test name
Test status
Simulation time 211516394 ps
CPU time 0.82 seconds
Started Dec 31 12:26:13 PM PST 23
Finished Dec 31 12:26:17 PM PST 23
Peak memory 196472 kb
Host smart-fac6baf9-f4f0-45c4-8830-cc2c04106d67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232051040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2232051040
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3107998302
Short name T706
Test name
Test status
Simulation time 74641249 ps
CPU time 2.61 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:33 PM PST 23
Peak memory 198056 kb
Host smart-a3ea4d11-4695-4510-b8a0-b95fb2b4d0c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107998302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3107998302
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.891373710
Short name T331
Test name
Test status
Simulation time 93326517 ps
CPU time 1.17 seconds
Started Dec 31 12:26:54 PM PST 23
Finished Dec 31 12:26:57 PM PST 23
Peak memory 197388 kb
Host smart-eb7a2b21-6b31-4f4a-859a-772b5646485c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891373710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
891373710
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3779760890
Short name T327
Test name
Test status
Simulation time 79731557 ps
CPU time 0.64 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:25:49 PM PST 23
Peak memory 194908 kb
Host smart-34cfd788-d055-4b6f-9445-6082710f99ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779760890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3779760890
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2525025509
Short name T251
Test name
Test status
Simulation time 18406552 ps
CPU time 0.71 seconds
Started Dec 31 12:24:36 PM PST 23
Finished Dec 31 12:24:45 PM PST 23
Peak memory 195248 kb
Host smart-123b610d-a387-41ab-adec-df7da7f20b3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525025509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2525025509
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1579404050
Short name T593
Test name
Test status
Simulation time 108058797 ps
CPU time 4.39 seconds
Started Dec 31 12:26:31 PM PST 23
Finished Dec 31 12:26:37 PM PST 23
Peak memory 198004 kb
Host smart-ff0ea476-722c-4221-aff2-0bfbae26eb88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579404050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1579404050
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1134083357
Short name T499
Test name
Test status
Simulation time 46003361 ps
CPU time 0.89 seconds
Started Dec 31 12:27:01 PM PST 23
Finished Dec 31 12:27:05 PM PST 23
Peak memory 196940 kb
Host smart-3d05b872-3268-4431-b7b0-1ba046723096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134083357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1134083357
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1207788722
Short name T844
Test name
Test status
Simulation time 373922021 ps
CPU time 1.35 seconds
Started Dec 31 12:26:52 PM PST 23
Finished Dec 31 12:26:55 PM PST 23
Peak memory 197928 kb
Host smart-c44443d6-518b-4582-8f28-8bb4508988f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207788722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1207788722
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1665488593
Short name T605
Test name
Test status
Simulation time 55890243514 ps
CPU time 145.26 seconds
Started Dec 31 12:25:02 PM PST 23
Finished Dec 31 12:27:32 PM PST 23
Peak memory 197992 kb
Host smart-1140eb5a-d8f7-4d0e-911a-bc3ede1b1a17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665488593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1665488593
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3372789230
Short name T300
Test name
Test status
Simulation time 411052888712 ps
CPU time 689.46 seconds
Started Dec 31 12:26:26 PM PST 23
Finished Dec 31 12:37:57 PM PST 23
Peak memory 206316 kb
Host smart-0f68f19f-e484-4661-bcd4-4f6f549e0f0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3372789230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3372789230
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3104028197
Short name T52
Test name
Test status
Simulation time 33614034 ps
CPU time 0.55 seconds
Started Dec 31 12:24:43 PM PST 23
Finished Dec 31 12:24:52 PM PST 23
Peak memory 194484 kb
Host smart-c5e27d35-b086-4d5d-a767-492ab4706bf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104028197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3104028197
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2717702547
Short name T486
Test name
Test status
Simulation time 27783987 ps
CPU time 0.87 seconds
Started Dec 31 12:24:58 PM PST 23
Finished Dec 31 12:25:03 PM PST 23
Peak memory 195876 kb
Host smart-a2378632-7323-4263-aed4-96c15ed926f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717702547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2717702547
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2988597501
Short name T729
Test name
Test status
Simulation time 85916942 ps
CPU time 4.01 seconds
Started Dec 31 12:24:52 PM PST 23
Finished Dec 31 12:25:02 PM PST 23
Peak memory 195684 kb
Host smart-46165f6e-8373-4721-b3e6-5edbd158da24
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988597501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2988597501
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3375146549
Short name T393
Test name
Test status
Simulation time 78853280 ps
CPU time 0.92 seconds
Started Dec 31 12:26:18 PM PST 23
Finished Dec 31 12:26:21 PM PST 23
Peak memory 197012 kb
Host smart-3d41d764-1af5-45ee-869a-c2ff8b3e8175
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375146549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3375146549
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2167249514
Short name T545
Test name
Test status
Simulation time 246037967 ps
CPU time 1.05 seconds
Started Dec 31 12:25:00 PM PST 23
Finished Dec 31 12:25:04 PM PST 23
Peak memory 195948 kb
Host smart-a4eab1ae-0f3e-44ef-9b10-59934f4f62f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167249514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2167249514
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3074011866
Short name T653
Test name
Test status
Simulation time 71925440 ps
CPU time 1.48 seconds
Started Dec 31 12:25:00 PM PST 23
Finished Dec 31 12:25:05 PM PST 23
Peak memory 196744 kb
Host smart-e0ff143b-d09e-4024-82c4-6a35af9e8dcd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074011866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3074011866
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1923711655
Short name T737
Test name
Test status
Simulation time 37883134 ps
CPU time 0.95 seconds
Started Dec 31 12:25:06 PM PST 23
Finished Dec 31 12:25:10 PM PST 23
Peak memory 196252 kb
Host smart-d9874cc4-839c-4277-bbaa-0f1623fc1996
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923711655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1923711655
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3026458099
Short name T324
Test name
Test status
Simulation time 874156706 ps
CPU time 1.03 seconds
Started Dec 31 12:25:08 PM PST 23
Finished Dec 31 12:25:12 PM PST 23
Peak memory 196136 kb
Host smart-482ef708-8375-462c-831b-fee764e0bc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026458099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3026458099
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3354842611
Short name T575
Test name
Test status
Simulation time 72272184 ps
CPU time 1.19 seconds
Started Dec 31 12:24:44 PM PST 23
Finished Dec 31 12:24:53 PM PST 23
Peak memory 196996 kb
Host smart-6236ae17-4ffb-460b-8dd0-ef2052e208ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354842611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3354842611
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2341368069
Short name T320
Test name
Test status
Simulation time 120942906 ps
CPU time 3.65 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:50 PM PST 23
Peak memory 198216 kb
Host smart-a2f78076-0c48-4cea-b50e-e6656fe48954
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341368069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2341368069
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2856627339
Short name T890
Test name
Test status
Simulation time 160478501 ps
CPU time 1.13 seconds
Started Dec 31 12:26:10 PM PST 23
Finished Dec 31 12:26:16 PM PST 23
Peak memory 196500 kb
Host smart-0cfce229-9c1d-4000-b7de-ab7edbbc972f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856627339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2856627339
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1057874172
Short name T640
Test name
Test status
Simulation time 98895587 ps
CPU time 0.8 seconds
Started Dec 31 12:25:52 PM PST 23
Finished Dec 31 12:26:05 PM PST 23
Peak memory 195044 kb
Host smart-ef34326c-2322-4ce0-b5e6-9a3f0a3f063d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057874172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1057874172
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2292840856
Short name T657
Test name
Test status
Simulation time 13170202312 ps
CPU time 125.2 seconds
Started Dec 31 12:26:24 PM PST 23
Finished Dec 31 12:28:30 PM PST 23
Peak memory 198020 kb
Host smart-2d002918-8124-46f2-bcbd-b80a0a8dabc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292840856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2292840856
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2548419850
Short name T613
Test name
Test status
Simulation time 239958663347 ps
CPU time 1653.26 seconds
Started Dec 31 12:25:13 PM PST 23
Finished Dec 31 12:52:49 PM PST 23
Peak memory 198260 kb
Host smart-132de7da-2e14-47c9-a32a-b47da380ce90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2548419850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2548419850
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3929181069
Short name T423
Test name
Test status
Simulation time 33260541 ps
CPU time 0.62 seconds
Started Dec 31 12:24:53 PM PST 23
Finished Dec 31 12:24:59 PM PST 23
Peak memory 193900 kb
Host smart-c878b5f8-a64c-4beb-91b4-ba78d631e028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929181069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3929181069
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.57305271
Short name T240
Test name
Test status
Simulation time 132396295 ps
CPU time 0.7 seconds
Started Dec 31 12:25:16 PM PST 23
Finished Dec 31 12:25:20 PM PST 23
Peak memory 195148 kb
Host smart-271c5a2d-0459-406a-86f1-8213698b3e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57305271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.57305271
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2666115652
Short name T705
Test name
Test status
Simulation time 717286039 ps
CPU time 24.74 seconds
Started Dec 31 12:25:00 PM PST 23
Finished Dec 31 12:25:28 PM PST 23
Peak memory 195548 kb
Host smart-7e3dcee9-4aca-480c-9066-5a930f77426e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666115652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2666115652
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3471458977
Short name T285
Test name
Test status
Simulation time 81065317 ps
CPU time 0.9 seconds
Started Dec 31 12:25:52 PM PST 23
Finished Dec 31 12:26:01 PM PST 23
Peak memory 196524 kb
Host smart-c925bb8a-933f-4d31-86b9-16eab0b31e1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471458977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3471458977
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3037818721
Short name T467
Test name
Test status
Simulation time 161544949 ps
CPU time 1.19 seconds
Started Dec 31 12:25:11 PM PST 23
Finished Dec 31 12:25:16 PM PST 23
Peak memory 197160 kb
Host smart-da9a272e-f579-4cb1-af9c-ea842cb43263
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037818721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3037818721
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1328510853
Short name T671
Test name
Test status
Simulation time 50437482 ps
CPU time 1.88 seconds
Started Dec 31 12:25:01 PM PST 23
Finished Dec 31 12:25:06 PM PST 23
Peak memory 198084 kb
Host smart-37967765-7da9-461b-8312-0a0118108e4e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328510853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1328510853
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.243979218
Short name T578
Test name
Test status
Simulation time 172495004 ps
CPU time 1.16 seconds
Started Dec 31 12:25:15 PM PST 23
Finished Dec 31 12:25:20 PM PST 23
Peak memory 196692 kb
Host smart-bfdd240e-3bd2-47cd-8a29-362bdec891e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243979218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
243979218
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.44958944
Short name T312
Test name
Test status
Simulation time 106243718 ps
CPU time 1.07 seconds
Started Dec 31 12:25:24 PM PST 23
Finished Dec 31 12:25:31 PM PST 23
Peak memory 196996 kb
Host smart-74c8b769-348d-4eed-bb76-841c2e45dfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44958944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.44958944
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.989526765
Short name T839
Test name
Test status
Simulation time 76242168 ps
CPU time 0.72 seconds
Started Dec 31 12:25:03 PM PST 23
Finished Dec 31 12:25:08 PM PST 23
Peak memory 195248 kb
Host smart-5a87fd6e-b629-4108-9261-eb79e1862195
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989526765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.989526765
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.624398271
Short name T375
Test name
Test status
Simulation time 1899148923 ps
CPU time 3.17 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:10 PM PST 23
Peak memory 197808 kb
Host smart-d10fc072-838d-4d09-8d77-5794e4c1088d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624398271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.624398271
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.996689883
Short name T461
Test name
Test status
Simulation time 94025886 ps
CPU time 0.94 seconds
Started Dec 31 12:25:15 PM PST 23
Finished Dec 31 12:25:19 PM PST 23
Peak memory 196252 kb
Host smart-5936790d-4f41-4aef-9c3c-57018f8be5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996689883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.996689883
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.4103399793
Short name T381
Test name
Test status
Simulation time 547864637 ps
CPU time 1.13 seconds
Started Dec 31 12:25:18 PM PST 23
Finished Dec 31 12:25:23 PM PST 23
Peak memory 195384 kb
Host smart-8532f043-ab3e-45ef-bfb0-a58897d7a3cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103399793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.4103399793
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1973243852
Short name T254
Test name
Test status
Simulation time 4989538962 ps
CPU time 129.02 seconds
Started Dec 31 12:25:27 PM PST 23
Finished Dec 31 12:27:42 PM PST 23
Peak memory 198044 kb
Host smart-182474b3-46b1-4dd4-9054-7078d8d155af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973243852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1973243852
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3772008974
Short name T747
Test name
Test status
Simulation time 376646443039 ps
CPU time 673.11 seconds
Started Dec 31 12:25:52 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 198216 kb
Host smart-cd8ae328-5b27-4e00-963b-d7ee6bb024ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3772008974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3772008974
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3484796869
Short name T510
Test name
Test status
Simulation time 13436467 ps
CPU time 0.55 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 194804 kb
Host smart-a3054d12-83c5-497e-9dd1-e633628a4f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484796869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3484796869
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3472987519
Short name T246
Test name
Test status
Simulation time 43187777 ps
CPU time 0.66 seconds
Started Dec 31 12:25:43 PM PST 23
Finished Dec 31 12:25:53 PM PST 23
Peak memory 194776 kb
Host smart-abf405a1-4d41-4dea-9eb8-1ec9109d8d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472987519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3472987519
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1721365433
Short name T509
Test name
Test status
Simulation time 1907855887 ps
CPU time 24.59 seconds
Started Dec 31 12:25:43 PM PST 23
Finished Dec 31 12:26:17 PM PST 23
Peak memory 196284 kb
Host smart-2e4e6192-897d-4721-b8a2-7c1941e5225e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721365433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1721365433
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2670425586
Short name T639
Test name
Test status
Simulation time 60098912 ps
CPU time 0.83 seconds
Started Dec 31 12:25:08 PM PST 23
Finished Dec 31 12:25:12 PM PST 23
Peak memory 196012 kb
Host smart-69ab0b44-3a34-4877-b114-cdca4cac7f05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670425586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2670425586
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3986676374
Short name T271
Test name
Test status
Simulation time 49876189 ps
CPU time 1.01 seconds
Started Dec 31 12:25:07 PM PST 23
Finished Dec 31 12:25:11 PM PST 23
Peak memory 195876 kb
Host smart-8c71efe2-f9ef-46be-add4-b485e7c13217
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986676374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3986676374
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1404793991
Short name T426
Test name
Test status
Simulation time 54974671 ps
CPU time 1.93 seconds
Started Dec 31 12:26:52 PM PST 23
Finished Dec 31 12:26:56 PM PST 23
Peak memory 196252 kb
Host smart-4ee94bb4-3653-4d44-8c68-4707f4710a68
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404793991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1404793991
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2957041288
Short name T490
Test name
Test status
Simulation time 430477303 ps
CPU time 2.43 seconds
Started Dec 31 12:25:11 PM PST 23
Finished Dec 31 12:25:17 PM PST 23
Peak memory 197980 kb
Host smart-5df773ed-4bdf-4d56-acc4-80faf853ba88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957041288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2957041288
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1172908687
Short name T828
Test name
Test status
Simulation time 100084995 ps
CPU time 0.97 seconds
Started Dec 31 12:25:21 PM PST 23
Finished Dec 31 12:25:27 PM PST 23
Peak memory 196436 kb
Host smart-38b72eb9-b2b0-45fc-af66-5058b2341fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172908687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1172908687
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3054626273
Short name T762
Test name
Test status
Simulation time 39762828 ps
CPU time 0.87 seconds
Started Dec 31 12:25:11 PM PST 23
Finished Dec 31 12:25:15 PM PST 23
Peak memory 195448 kb
Host smart-4c7c74c2-6f6f-45c0-8f76-40fdb5530797
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054626273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3054626273
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.333289821
Short name T670
Test name
Test status
Simulation time 314893417 ps
CPU time 4.75 seconds
Started Dec 31 12:25:17 PM PST 23
Finished Dec 31 12:25:25 PM PST 23
Peak memory 197916 kb
Host smart-70752464-e8d8-4a86-bc3e-5a0c12a4b26b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333289821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.333289821
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3286069495
Short name T564
Test name
Test status
Simulation time 389843003 ps
CPU time 0.98 seconds
Started Dec 31 12:24:53 PM PST 23
Finished Dec 31 12:25:00 PM PST 23
Peak memory 195476 kb
Host smart-2aadd7a7-3a51-46b1-b80a-5feeef3899a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286069495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3286069495
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2678971598
Short name T406
Test name
Test status
Simulation time 345188775 ps
CPU time 0.85 seconds
Started Dec 31 12:25:24 PM PST 23
Finished Dec 31 12:25:32 PM PST 23
Peak memory 196276 kb
Host smart-4e57f016-a545-4678-a77d-8a5c5de1835a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678971598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2678971598
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1113305629
Short name T724
Test name
Test status
Simulation time 3170604836 ps
CPU time 82.9 seconds
Started Dec 31 12:25:44 PM PST 23
Finished Dec 31 12:27:15 PM PST 23
Peak memory 198076 kb
Host smart-cbde28b4-4874-42c6-927d-af5708480c77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113305629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1113305629
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1218009615
Short name T581
Test name
Test status
Simulation time 116494692454 ps
CPU time 689 seconds
Started Dec 31 12:25:58 PM PST 23
Finished Dec 31 12:37:34 PM PST 23
Peak memory 198100 kb
Host smart-df7437e7-14e3-4eb9-b8d9-162b6c5edf7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1218009615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1218009615
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2004446328
Short name T822
Test name
Test status
Simulation time 39548250 ps
CPU time 0.56 seconds
Started Dec 31 12:26:16 PM PST 23
Finished Dec 31 12:26:19 PM PST 23
Peak memory 193816 kb
Host smart-547ac8bc-c0a3-46c4-9fe1-027d48f2522b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004446328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2004446328
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.4220183488
Short name T558
Test name
Test status
Simulation time 33014276 ps
CPU time 0.71 seconds
Started Dec 31 12:25:20 PM PST 23
Finished Dec 31 12:25:25 PM PST 23
Peak memory 195084 kb
Host smart-3d38f8ea-12be-4f3b-a106-4c6d23f74a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220183488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.4220183488
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.435458314
Short name T522
Test name
Test status
Simulation time 421631112 ps
CPU time 13.32 seconds
Started Dec 31 12:26:43 PM PST 23
Finished Dec 31 12:26:58 PM PST 23
Peak memory 195508 kb
Host smart-730c18cc-b66c-493e-9c05-a1eda23d29b8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435458314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.435458314
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1413221497
Short name T259
Test name
Test status
Simulation time 47073605 ps
CPU time 0.79 seconds
Started Dec 31 12:25:48 PM PST 23
Finished Dec 31 12:25:57 PM PST 23
Peak memory 195748 kb
Host smart-3bed2370-67c2-4c55-8a54-2efcec785470
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413221497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1413221497
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2105461941
Short name T654
Test name
Test status
Simulation time 84934816 ps
CPU time 0.61 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:03 PM PST 23
Peak memory 194092 kb
Host smart-835f81b2-6aa6-40b9-8fa3-20c1d5e7e0af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105461941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2105461941
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3728577152
Short name T813
Test name
Test status
Simulation time 185630632 ps
CPU time 3.42 seconds
Started Dec 31 12:27:18 PM PST 23
Finished Dec 31 12:27:23 PM PST 23
Peak memory 197960 kb
Host smart-76dd207a-a846-48ff-a515-cb41fdc956ae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728577152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3728577152
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3747404206
Short name T472
Test name
Test status
Simulation time 133487778 ps
CPU time 2.41 seconds
Started Dec 31 12:25:37 PM PST 23
Finished Dec 31 12:25:47 PM PST 23
Peak memory 196976 kb
Host smart-811eb1fa-9b26-41d6-8208-c0b2a20672b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747404206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3747404206
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1788454278
Short name T435
Test name
Test status
Simulation time 128257922 ps
CPU time 1.28 seconds
Started Dec 31 12:25:36 PM PST 23
Finished Dec 31 12:25:45 PM PST 23
Peak memory 196876 kb
Host smart-275d5f5a-14f8-4205-a166-199a7a55f804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788454278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1788454278
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2828111975
Short name T345
Test name
Test status
Simulation time 125076805 ps
CPU time 0.76 seconds
Started Dec 31 12:25:13 PM PST 23
Finished Dec 31 12:25:17 PM PST 23
Peak memory 195236 kb
Host smart-fd8f8a8a-8953-4546-8ae6-9cb1ffbb6597
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828111975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2828111975
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2246374338
Short name T508
Test name
Test status
Simulation time 963955341 ps
CPU time 3.81 seconds
Started Dec 31 12:25:19 PM PST 23
Finished Dec 31 12:25:27 PM PST 23
Peak memory 198052 kb
Host smart-87130c3f-3bcb-4ed6-a212-fd63f2d0adb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246374338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2246374338
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3678484740
Short name T387
Test name
Test status
Simulation time 77877209 ps
CPU time 1.14 seconds
Started Dec 31 12:25:19 PM PST 23
Finished Dec 31 12:25:24 PM PST 23
Peak memory 198052 kb
Host smart-bc2cfa43-da75-4bb0-8f3d-63f7b65dac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678484740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3678484740
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1105753939
Short name T616
Test name
Test status
Simulation time 27980407 ps
CPU time 0.9 seconds
Started Dec 31 12:26:26 PM PST 23
Finished Dec 31 12:26:27 PM PST 23
Peak memory 195532 kb
Host smart-3407ba65-9477-4358-ac4d-cf347f263d9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105753939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1105753939
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3309200668
Short name T850
Test name
Test status
Simulation time 126726038717 ps
CPU time 176.35 seconds
Started Dec 31 12:25:15 PM PST 23
Finished Dec 31 12:28:15 PM PST 23
Peak memory 198372 kb
Host smart-e0d5fe92-1e58-42a9-8f8b-0a15600cb268
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309200668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3309200668
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.892071032
Short name T580
Test name
Test status
Simulation time 178121693001 ps
CPU time 543.62 seconds
Started Dec 31 12:25:37 PM PST 23
Finished Dec 31 12:34:49 PM PST 23
Peak memory 198180 kb
Host smart-46a9a556-852a-454e-84b5-047b8ced8c03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=892071032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.892071032
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.555895330
Short name T604
Test name
Test status
Simulation time 13126495 ps
CPU time 0.55 seconds
Started Dec 31 12:26:12 PM PST 23
Finished Dec 31 12:26:16 PM PST 23
Peak memory 193740 kb
Host smart-c626ebff-e921-44ec-a569-7ee1a8056fa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555895330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.555895330
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1554113744
Short name T263
Test name
Test status
Simulation time 99108942 ps
CPU time 0.92 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:48 PM PST 23
Peak memory 196200 kb
Host smart-d16e1413-98b3-4723-b03b-ff85d011f0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554113744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1554113744
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3311876418
Short name T608
Test name
Test status
Simulation time 2471404403 ps
CPU time 19.87 seconds
Started Dec 31 12:25:14 PM PST 23
Finished Dec 31 12:25:37 PM PST 23
Peak memory 196976 kb
Host smart-b9607d55-5fee-4b73-a17c-ae9ac9bcfdd5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311876418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3311876418
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3355032779
Short name T655
Test name
Test status
Simulation time 73196281 ps
CPU time 0.69 seconds
Started Dec 31 12:26:52 PM PST 23
Finished Dec 31 12:26:54 PM PST 23
Peak memory 194480 kb
Host smart-45966916-1501-4555-9f18-bd6f6de4d235
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355032779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3355032779
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3664680634
Short name T759
Test name
Test status
Simulation time 125952909 ps
CPU time 0.76 seconds
Started Dec 31 12:26:26 PM PST 23
Finished Dec 31 12:26:28 PM PST 23
Peak memory 195388 kb
Host smart-c70160a7-f1b9-4dbd-aa30-4e76123c0cb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664680634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3664680634
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2764923980
Short name T551
Test name
Test status
Simulation time 155293643 ps
CPU time 2.98 seconds
Started Dec 31 12:25:30 PM PST 23
Finished Dec 31 12:25:41 PM PST 23
Peak memory 198052 kb
Host smart-228838e2-a7b1-44a1-9f10-9cfa1f9457e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764923980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2764923980
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1200188812
Short name T544
Test name
Test status
Simulation time 111276113 ps
CPU time 2.99 seconds
Started Dec 31 12:25:24 PM PST 23
Finished Dec 31 12:25:32 PM PST 23
Peak memory 196924 kb
Host smart-3f49f149-8897-4d7f-a186-3507fa4966e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200188812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1200188812
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2763071238
Short name T502
Test name
Test status
Simulation time 144882090 ps
CPU time 0.95 seconds
Started Dec 31 12:25:45 PM PST 23
Finished Dec 31 12:25:54 PM PST 23
Peak memory 195896 kb
Host smart-e6ab9bb9-f0fb-407c-ad68-ce84fd306d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763071238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2763071238
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.4188483857
Short name T853
Test name
Test status
Simulation time 38982258 ps
CPU time 0.71 seconds
Started Dec 31 12:25:37 PM PST 23
Finished Dec 31 12:25:45 PM PST 23
Peak memory 195404 kb
Host smart-707974cc-cb21-425c-99fb-d81235a65cc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188483857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.4188483857
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1695060152
Short name T823
Test name
Test status
Simulation time 125466539 ps
CPU time 5.29 seconds
Started Dec 31 12:27:26 PM PST 23
Finished Dec 31 12:27:32 PM PST 23
Peak memory 197868 kb
Host smart-359a1b7e-0ac4-4e78-9c2a-a33d333fdc33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695060152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1695060152
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3154925785
Short name T591
Test name
Test status
Simulation time 245748098 ps
CPU time 1.23 seconds
Started Dec 31 12:25:21 PM PST 23
Finished Dec 31 12:25:26 PM PST 23
Peak memory 196896 kb
Host smart-31cf3bd8-ddd5-4e1c-94c5-008066ffc4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154925785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3154925785
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4086655065
Short name T623
Test name
Test status
Simulation time 118186545 ps
CPU time 0.82 seconds
Started Dec 31 12:26:17 PM PST 23
Finished Dec 31 12:26:20 PM PST 23
Peak memory 195200 kb
Host smart-2882fb33-fc0d-4c06-9544-c2e7d8262cf6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086655065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4086655065
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2001966490
Short name T67
Test name
Test status
Simulation time 16605404601 ps
CPU time 180.33 seconds
Started Dec 31 12:25:55 PM PST 23
Finished Dec 31 12:29:03 PM PST 23
Peak memory 197968 kb
Host smart-50322d0a-8ac6-4129-913a-412a79360c1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001966490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2001966490
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2432626179
Short name T832
Test name
Test status
Simulation time 13340287139 ps
CPU time 180.46 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:28:40 PM PST 23
Peak memory 198348 kb
Host smart-bca3d811-6976-43ec-b401-9877ac0e8fea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2432626179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2432626179
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1539811228
Short name T715
Test name
Test status
Simulation time 13844864 ps
CPU time 0.56 seconds
Started Dec 31 12:26:40 PM PST 23
Finished Dec 31 12:26:42 PM PST 23
Peak memory 193816 kb
Host smart-e0c9db9e-6753-4f12-896f-d4169b6f24d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539811228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1539811228
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3943267513
Short name T665
Test name
Test status
Simulation time 39758721 ps
CPU time 0.74 seconds
Started Dec 31 12:27:18 PM PST 23
Finished Dec 31 12:27:20 PM PST 23
Peak memory 195188 kb
Host smart-c898498b-2af5-4448-90fe-35f40c394deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943267513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3943267513
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3543817120
Short name T371
Test name
Test status
Simulation time 521733545 ps
CPU time 14.3 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:21 PM PST 23
Peak memory 196924 kb
Host smart-e0519eb1-e12b-423b-84b9-2c0e680a4a42
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543817120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3543817120
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2217884320
Short name T781
Test name
Test status
Simulation time 51831140 ps
CPU time 0.87 seconds
Started Dec 31 12:26:26 PM PST 23
Finished Dec 31 12:26:28 PM PST 23
Peak memory 197148 kb
Host smart-e93446c1-1ebc-4f3b-897a-85c37f5c0212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217884320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2217884320
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.228493657
Short name T602
Test name
Test status
Simulation time 587769796 ps
CPU time 1.06 seconds
Started Dec 31 12:26:03 PM PST 23
Finished Dec 31 12:26:10 PM PST 23
Peak memory 196624 kb
Host smart-309f2da5-14ff-40e0-8c41-36f5cf3d491a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228493657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.228493657
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1593269664
Short name T402
Test name
Test status
Simulation time 320457589 ps
CPU time 2.98 seconds
Started Dec 31 12:27:04 PM PST 23
Finished Dec 31 12:27:10 PM PST 23
Peak memory 198072 kb
Host smart-eb74be15-fac8-4ac1-9628-8057ea7e4bbc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593269664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1593269664
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1326032933
Short name T404
Test name
Test status
Simulation time 180843131 ps
CPU time 1.64 seconds
Started Dec 31 12:26:07 PM PST 23
Finished Dec 31 12:26:14 PM PST 23
Peak memory 196592 kb
Host smart-d29b5950-3970-4e93-90a8-deefc57afd76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326032933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1326032933
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1824061908
Short name T434
Test name
Test status
Simulation time 103875386 ps
CPU time 0.99 seconds
Started Dec 31 12:25:00 PM PST 23
Finished Dec 31 12:25:05 PM PST 23
Peak memory 195796 kb
Host smart-42068794-7970-4193-bd21-01a6f5ae7d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824061908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1824061908
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.4103142453
Short name T806
Test name
Test status
Simulation time 112990355 ps
CPU time 1.14 seconds
Started Dec 31 12:26:13 PM PST 23
Finished Dec 31 12:26:17 PM PST 23
Peak memory 196820 kb
Host smart-1abb816f-8a93-4641-b734-1ff4b6ee2153
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103142453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.4103142453
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3864176037
Short name T368
Test name
Test status
Simulation time 1136935978 ps
CPU time 4.85 seconds
Started Dec 31 12:26:30 PM PST 23
Finished Dec 31 12:26:36 PM PST 23
Peak memory 197800 kb
Host smart-089a212d-d4af-45b4-97f6-4f3957d74465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864176037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3864176037
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3543628547
Short name T690
Test name
Test status
Simulation time 188200451 ps
CPU time 1.33 seconds
Started Dec 31 12:26:21 PM PST 23
Finished Dec 31 12:26:24 PM PST 23
Peak memory 195988 kb
Host smart-d6b7cebe-f187-4fbe-95a5-0fa18f250835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543628547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3543628547
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3692009717
Short name T817
Test name
Test status
Simulation time 55684579 ps
CPU time 0.81 seconds
Started Dec 31 12:26:09 PM PST 23
Finished Dec 31 12:26:14 PM PST 23
Peak memory 195316 kb
Host smart-e1ce0b61-cdf0-4159-a504-1fe4180179c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692009717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3692009717
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.639215815
Short name T287
Test name
Test status
Simulation time 12813353116 ps
CPU time 133 seconds
Started Dec 31 12:26:40 PM PST 23
Finished Dec 31 12:28:54 PM PST 23
Peak memory 198092 kb
Host smart-01f39afe-97f6-475d-8952-4fd3b2c5880e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639215815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.639215815
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.1326477700
Short name T679
Test name
Test status
Simulation time 111270447209 ps
CPU time 1358.82 seconds
Started Dec 31 12:25:30 PM PST 23
Finished Dec 31 12:48:16 PM PST 23
Peak memory 198248 kb
Host smart-96e34fb3-e824-4617-a4ff-1d1bc6a5fcb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1326477700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.1326477700
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4131154961
Short name T682
Test name
Test status
Simulation time 66684905 ps
CPU time 0.57 seconds
Started Dec 31 12:26:42 PM PST 23
Finished Dec 31 12:26:44 PM PST 23
Peak memory 193840 kb
Host smart-5fe16884-4cf5-4417-8083-9fac83fed3dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131154961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4131154961
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3680597957
Short name T568
Test name
Test status
Simulation time 198984088 ps
CPU time 0.93 seconds
Started Dec 31 12:25:55 PM PST 23
Finished Dec 31 12:26:03 PM PST 23
Peak memory 195904 kb
Host smart-f9657824-5da7-43c8-931c-20442bb130aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680597957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3680597957
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3414156829
Short name T50
Test name
Test status
Simulation time 98092487 ps
CPU time 4.39 seconds
Started Dec 31 12:26:28 PM PST 23
Finished Dec 31 12:26:33 PM PST 23
Peak memory 195504 kb
Host smart-771e7e6f-bb7f-4a4f-a127-7eb0eefb4f98
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414156829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3414156829
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.696873953
Short name T664
Test name
Test status
Simulation time 57901971 ps
CPU time 0.63 seconds
Started Dec 31 12:26:07 PM PST 23
Finished Dec 31 12:26:13 PM PST 23
Peak memory 195204 kb
Host smart-3660ee41-895b-4d34-a50d-cf2f83c9025e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696873953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.696873953
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1313132703
Short name T834
Test name
Test status
Simulation time 223061837 ps
CPU time 0.93 seconds
Started Dec 31 12:25:45 PM PST 23
Finished Dec 31 12:25:54 PM PST 23
Peak memory 195684 kb
Host smart-a5a91aba-cce4-41aa-8b83-ce71462c2276
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313132703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1313132703
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3337196873
Short name T849
Test name
Test status
Simulation time 69303120 ps
CPU time 2.55 seconds
Started Dec 31 12:25:15 PM PST 23
Finished Dec 31 12:25:21 PM PST 23
Peak memory 197932 kb
Host smart-b241fe97-61fb-420d-8b64-89c3e80bedf2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337196873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3337196873
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3444463906
Short name T277
Test name
Test status
Simulation time 812592983 ps
CPU time 2.99 seconds
Started Dec 31 12:26:36 PM PST 23
Finished Dec 31 12:26:41 PM PST 23
Peak memory 195724 kb
Host smart-26cf0b9e-b793-4bdd-9ae9-1852e4f88256
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444463906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3444463906
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2723368925
Short name T252
Test name
Test status
Simulation time 83505575 ps
CPU time 0.98 seconds
Started Dec 31 12:25:26 PM PST 23
Finished Dec 31 12:25:33 PM PST 23
Peak memory 195836 kb
Host smart-d5ea2b44-419c-49cb-82e2-79957a29abc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723368925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2723368925
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3837471111
Short name T350
Test name
Test status
Simulation time 19734237 ps
CPU time 0.66 seconds
Started Dec 31 12:26:41 PM PST 23
Finished Dec 31 12:26:43 PM PST 23
Peak memory 194928 kb
Host smart-cd929137-2339-4fee-b631-57fdc9de3695
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837471111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3837471111
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1036880140
Short name T237
Test name
Test status
Simulation time 31484185 ps
CPU time 1.35 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:25:49 PM PST 23
Peak memory 197872 kb
Host smart-acb94331-d9f1-4950-af3b-cef676d7cf8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036880140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1036880140
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2903018212
Short name T802
Test name
Test status
Simulation time 36053258 ps
CPU time 1 seconds
Started Dec 31 12:25:11 PM PST 23
Finished Dec 31 12:25:16 PM PST 23
Peak memory 195724 kb
Host smart-8f748c97-0ea8-4711-b499-7e6fb5f9dccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903018212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2903018212
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.34226195
Short name T633
Test name
Test status
Simulation time 109087331 ps
CPU time 1.07 seconds
Started Dec 31 12:26:13 PM PST 23
Finished Dec 31 12:26:17 PM PST 23
Peak memory 195612 kb
Host smart-62800e5a-a8d0-49da-8cd9-19ca18a9b485
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34226195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.34226195
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3430217756
Short name T318
Test name
Test status
Simulation time 4501151350 ps
CPU time 111.71 seconds
Started Dec 31 12:25:26 PM PST 23
Finished Dec 31 12:27:23 PM PST 23
Peak memory 198036 kb
Host smart-de52a2d4-b102-4ccf-bd81-aaccc22562f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430217756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3430217756
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.536980834
Short name T731
Test name
Test status
Simulation time 20995388294 ps
CPU time 283.71 seconds
Started Dec 31 12:26:43 PM PST 23
Finished Dec 31 12:31:29 PM PST 23
Peak memory 198128 kb
Host smart-85f517d5-c244-4cc2-8eab-378f8d613589
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=536980834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.536980834
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.4209412301
Short name T876
Test name
Test status
Simulation time 12874419 ps
CPU time 0.54 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 193420 kb
Host smart-d224dccb-fd77-4429-a04d-f794faf8a3c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209412301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.4209412301
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1860281856
Short name T661
Test name
Test status
Simulation time 340043982 ps
CPU time 0.74 seconds
Started Dec 31 12:23:08 PM PST 23
Finished Dec 31 12:23:09 PM PST 23
Peak memory 195980 kb
Host smart-af6407c3-0596-4548-b4a1-f8dad6675b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860281856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1860281856
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1623809927
Short name T229
Test name
Test status
Simulation time 575069676 ps
CPU time 6.35 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 198004 kb
Host smart-423fd426-41d9-489e-9ad3-4256a573bbc6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623809927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1623809927
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2222166349
Short name T49
Test name
Test status
Simulation time 42573961 ps
CPU time 0.62 seconds
Started Dec 31 12:34:38 PM PST 23
Finished Dec 31 12:34:42 PM PST 23
Peak memory 195232 kb
Host smart-6d376cc2-5fa7-41f3-9a61-7a4f5550513b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222166349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2222166349
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3808190496
Short name T219
Test name
Test status
Simulation time 49493457 ps
CPU time 0.77 seconds
Started Dec 31 12:26:31 PM PST 23
Finished Dec 31 12:26:34 PM PST 23
Peak memory 196224 kb
Host smart-0764b0b2-b497-4fa3-8c68-316f942aa35c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808190496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3808190496
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1659702788
Short name T776
Test name
Test status
Simulation time 96826942 ps
CPU time 3.19 seconds
Started Dec 31 12:25:04 PM PST 23
Finished Dec 31 12:25:11 PM PST 23
Peak memory 195880 kb
Host smart-856e4b50-bc6c-487a-aa29-3deff9ce70a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659702788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1659702788
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2725266539
Short name T225
Test name
Test status
Simulation time 65889531 ps
CPU time 1.76 seconds
Started Dec 31 12:23:29 PM PST 23
Finished Dec 31 12:23:32 PM PST 23
Peak memory 197988 kb
Host smart-af0b9600-4403-4d89-bf8e-e5d9b4cd2961
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725266539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2725266539
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3669892561
Short name T816
Test name
Test status
Simulation time 216960989 ps
CPU time 1.21 seconds
Started Dec 31 12:24:35 PM PST 23
Finished Dec 31 12:24:44 PM PST 23
Peak memory 196864 kb
Host smart-65aacedd-10b6-4c27-8a76-85322ef8f045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669892561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3669892561
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1643904389
Short name T784
Test name
Test status
Simulation time 56028679 ps
CPU time 0.7 seconds
Started Dec 31 12:24:57 PM PST 23
Finished Dec 31 12:25:02 PM PST 23
Peak memory 194456 kb
Host smart-216613e8-9e99-49f3-9be0-5e100ce7f2fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643904389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1643904389
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1243669333
Short name T778
Test name
Test status
Simulation time 1144909517 ps
CPU time 3.37 seconds
Started Dec 31 12:25:35 PM PST 23
Finished Dec 31 12:25:47 PM PST 23
Peak memory 197868 kb
Host smart-8a67e53c-b4f9-477b-a73d-6fe055206ae1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243669333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1243669333
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1960555062
Short name T30
Test name
Test status
Simulation time 102073374 ps
CPU time 0.81 seconds
Started Dec 31 12:26:09 PM PST 23
Finished Dec 31 12:26:14 PM PST 23
Peak memory 213476 kb
Host smart-64a5e558-d7c9-4f72-8621-5a01ec053519
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960555062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1960555062
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.11301916
Short name T473
Test name
Test status
Simulation time 182860968 ps
CPU time 1.34 seconds
Started Dec 31 12:26:05 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 196772 kb
Host smart-77df9b8d-cfa0-4f07-8704-4af5339929c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11301916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.11301916
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.592827110
Short name T760
Test name
Test status
Simulation time 286909451 ps
CPU time 1.17 seconds
Started Dec 31 12:20:39 PM PST 23
Finished Dec 31 12:20:40 PM PST 23
Peak memory 196224 kb
Host smart-3fdbc416-42f9-4b5c-a9bc-7a37ea8141a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592827110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.592827110
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.721638925
Short name T667
Test name
Test status
Simulation time 6300184636 ps
CPU time 47.86 seconds
Started Dec 31 12:19:43 PM PST 23
Finished Dec 31 12:20:34 PM PST 23
Peak memory 198468 kb
Host smart-bb492be2-1813-45cb-a656-e721bd9b5336
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721638925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.721638925
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.673250316
Short name T69
Test name
Test status
Simulation time 45775352285 ps
CPU time 143.65 seconds
Started Dec 31 12:24:52 PM PST 23
Finished Dec 31 12:27:22 PM PST 23
Peak memory 205556 kb
Host smart-8f1443e5-eedf-4ea0-8ae6-7fa3a2d3c3a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=673250316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.673250316
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1295655791
Short name T774
Test name
Test status
Simulation time 41276260 ps
CPU time 0.54 seconds
Started Dec 31 12:28:00 PM PST 23
Finished Dec 31 12:28:07 PM PST 23
Peak memory 193896 kb
Host smart-4261d3c8-0c0e-426d-97a0-a687e9c6c23e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295655791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1295655791
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.837652788
Short name T276
Test name
Test status
Simulation time 111015454 ps
CPU time 0.64 seconds
Started Dec 31 12:25:56 PM PST 23
Finished Dec 31 12:26:04 PM PST 23
Peak memory 194008 kb
Host smart-8850db7e-73dc-40e6-b34c-c0d71cd4adfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837652788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.837652788
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.676607101
Short name T429
Test name
Test status
Simulation time 491525462 ps
CPU time 13.24 seconds
Started Dec 31 12:25:59 PM PST 23
Finished Dec 31 12:26:19 PM PST 23
Peak memory 196768 kb
Host smart-13788b1d-47f3-4e58-a655-e4cee4cac303
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676607101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.676607101
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2002451477
Short name T432
Test name
Test status
Simulation time 253824962 ps
CPU time 0.93 seconds
Started Dec 31 12:24:53 PM PST 23
Finished Dec 31 12:24:59 PM PST 23
Peak memory 196336 kb
Host smart-afbf3d05-218b-4c18-9a27-9e6369fbf1b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002451477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2002451477
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3524075541
Short name T242
Test name
Test status
Simulation time 61380930 ps
CPU time 0.63 seconds
Started Dec 31 12:28:07 PM PST 23
Finished Dec 31 12:28:11 PM PST 23
Peak memory 194128 kb
Host smart-3794507a-e3d1-4a29-af41-cbd781c8ff07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524075541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3524075541
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1311285209
Short name T662
Test name
Test status
Simulation time 208680507 ps
CPU time 2.14 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:25:52 PM PST 23
Peak memory 197980 kb
Host smart-5f501593-b77e-4ac5-9d83-151c739e0d44
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311285209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1311285209
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.182205842
Short name T628
Test name
Test status
Simulation time 86327531 ps
CPU time 1.64 seconds
Started Dec 31 12:25:44 PM PST 23
Finished Dec 31 12:25:54 PM PST 23
Peak memory 196096 kb
Host smart-8e3675e5-046c-4302-829e-02722e6728cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182205842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
182205842
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3740182201
Short name T341
Test name
Test status
Simulation time 50014544 ps
CPU time 0.64 seconds
Started Dec 31 12:26:46 PM PST 23
Finished Dec 31 12:26:48 PM PST 23
Peak memory 195224 kb
Host smart-654905e1-ff9d-4643-ada5-44bbacf4a335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740182201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3740182201
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3356349342
Short name T366
Test name
Test status
Simulation time 30971060 ps
CPU time 1.06 seconds
Started Dec 31 12:27:28 PM PST 23
Finished Dec 31 12:27:35 PM PST 23
Peak memory 195684 kb
Host smart-d5c5c52f-8bfa-4362-9bb2-05ba5389ee19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356349342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3356349342
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.754605992
Short name T792
Test name
Test status
Simulation time 185880383 ps
CPU time 3.06 seconds
Started Dec 31 12:25:01 PM PST 23
Finished Dec 31 12:25:08 PM PST 23
Peak memory 197948 kb
Host smart-78d7735f-1a2d-4a80-8868-c1320977b3b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754605992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.754605992
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1184839021
Short name T401
Test name
Test status
Simulation time 45310340 ps
CPU time 0.94 seconds
Started Dec 31 12:26:50 PM PST 23
Finished Dec 31 12:26:53 PM PST 23
Peak memory 196504 kb
Host smart-19d47166-0c14-4545-a5ac-582b703a2696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184839021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1184839021
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3680833233
Short name T396
Test name
Test status
Simulation time 42082333 ps
CPU time 0.74 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 12:27:19 PM PST 23
Peak memory 195212 kb
Host smart-70784ef3-88d2-470e-bcb4-5faf6f2619cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680833233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3680833233
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2840760566
Short name T385
Test name
Test status
Simulation time 8326079725 ps
CPU time 19.26 seconds
Started Dec 31 12:25:34 PM PST 23
Finished Dec 31 12:26:02 PM PST 23
Peak memory 197984 kb
Host smart-b4ae3ac0-128d-4c57-8f2e-8fb8d30f0bd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840760566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2840760566
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.269657175
Short name T694
Test name
Test status
Simulation time 170076924851 ps
CPU time 980.24 seconds
Started Dec 31 12:26:25 PM PST 23
Finished Dec 31 12:42:47 PM PST 23
Peak memory 198224 kb
Host smart-e2992086-a02d-4c47-889c-26522dfb4ae6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=269657175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.269657175
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3201367577
Short name T632
Test name
Test status
Simulation time 10550362 ps
CPU time 0.55 seconds
Started Dec 31 12:25:20 PM PST 23
Finished Dec 31 12:25:25 PM PST 23
Peak memory 193868 kb
Host smart-ee518b77-4d48-40f9-89da-c5d147af9be0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201367577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3201367577
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1913261985
Short name T609
Test name
Test status
Simulation time 34268254 ps
CPU time 0.71 seconds
Started Dec 31 12:25:12 PM PST 23
Finished Dec 31 12:25:15 PM PST 23
Peak memory 195140 kb
Host smart-acb8a752-3840-41c0-a1da-bd0e14b8797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913261985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1913261985
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1220272491
Short name T536
Test name
Test status
Simulation time 408258578 ps
CPU time 20.15 seconds
Started Dec 31 12:25:05 PM PST 23
Finished Dec 31 12:25:29 PM PST 23
Peak memory 195428 kb
Host smart-34ea0b50-b38a-482b-9450-a82f58f07328
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220272491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1220272491
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.804162476
Short name T827
Test name
Test status
Simulation time 145169494 ps
CPU time 0.93 seconds
Started Dec 31 12:25:10 PM PST 23
Finished Dec 31 12:25:17 PM PST 23
Peak memory 197852 kb
Host smart-a1fecd96-7081-4ebb-a831-c2be7c749466
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804162476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.804162476
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3491260923
Short name T576
Test name
Test status
Simulation time 122975687 ps
CPU time 0.73 seconds
Started Dec 31 12:25:09 PM PST 23
Finished Dec 31 12:25:14 PM PST 23
Peak memory 196184 kb
Host smart-1c16c6bc-1e75-49ec-b5dd-46026c4cead6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491260923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3491260923
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3123810029
Short name T561
Test name
Test status
Simulation time 45560771 ps
CPU time 1.88 seconds
Started Dec 31 12:25:16 PM PST 23
Finished Dec 31 12:25:21 PM PST 23
Peak memory 198124 kb
Host smart-5932a2a7-bc1e-454f-b8cb-e6ebae1f8045
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123810029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3123810029
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2609469428
Short name T527
Test name
Test status
Simulation time 92079727 ps
CPU time 1.88 seconds
Started Dec 31 12:25:14 PM PST 23
Finished Dec 31 12:25:19 PM PST 23
Peak memory 196452 kb
Host smart-a6dd3710-b455-4a76-ab59-38d1cdcdf59d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609469428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2609469428
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.912649162
Short name T261
Test name
Test status
Simulation time 50653827 ps
CPU time 0.95 seconds
Started Dec 31 12:25:18 PM PST 23
Finished Dec 31 12:25:23 PM PST 23
Peak memory 196464 kb
Host smart-6521b077-9b13-4860-83fa-498c9fa9041d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912649162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.912649162
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3054838916
Short name T741
Test name
Test status
Simulation time 27162414 ps
CPU time 0.8 seconds
Started Dec 31 12:25:13 PM PST 23
Finished Dec 31 12:25:17 PM PST 23
Peak memory 195932 kb
Host smart-54107090-e6da-4bb7-a6c5-c5c0022b86be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054838916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3054838916
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.142078624
Short name T415
Test name
Test status
Simulation time 1600112621 ps
CPU time 5.09 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:35 PM PST 23
Peak memory 197948 kb
Host smart-432251b5-393a-41d5-97f7-bf8b3bfbabaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142078624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.142078624
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2590544422
Short name T732
Test name
Test status
Simulation time 49570940 ps
CPU time 1.2 seconds
Started Dec 31 12:25:07 PM PST 23
Finished Dec 31 12:25:11 PM PST 23
Peak memory 196764 kb
Host smart-5bbc357b-7df8-40b7-91ac-563f62fd8b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590544422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2590544422
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.324665738
Short name T771
Test name
Test status
Simulation time 136986686 ps
CPU time 1.42 seconds
Started Dec 31 12:25:16 PM PST 23
Finished Dec 31 12:25:26 PM PST 23
Peak memory 197968 kb
Host smart-f180b43f-b4c8-4c2d-bf56-5a2c939fd251
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324665738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.324665738
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3267956899
Short name T534
Test name
Test status
Simulation time 33075313891 ps
CPU time 232.41 seconds
Started Dec 31 12:25:00 PM PST 23
Finished Dec 31 12:28:56 PM PST 23
Peak memory 198072 kb
Host smart-d1eaae2c-64ba-4fbf-8b8c-f42d25df47f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267956899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3267956899
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.50194643
Short name T465
Test name
Test status
Simulation time 22705109770 ps
CPU time 674.43 seconds
Started Dec 31 12:25:02 PM PST 23
Finished Dec 31 12:36:22 PM PST 23
Peak memory 198296 kb
Host smart-06fafe00-2205-4545-a246-e672bde00c65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=50194643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.50194643
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3126482814
Short name T367
Test name
Test status
Simulation time 29665742 ps
CPU time 0.54 seconds
Started Dec 31 12:26:02 PM PST 23
Finished Dec 31 12:26:08 PM PST 23
Peak memory 193908 kb
Host smart-ba22c670-fa7c-4cbe-8f7e-78609b7fb19f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126482814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3126482814
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.128413290
Short name T405
Test name
Test status
Simulation time 19645895 ps
CPU time 0.65 seconds
Started Dec 31 12:25:18 PM PST 23
Finished Dec 31 12:25:23 PM PST 23
Peak memory 194652 kb
Host smart-5dd088a5-6325-4f52-a7bb-3a764960ba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128413290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.128413290
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3669755217
Short name T68
Test name
Test status
Simulation time 1631128125 ps
CPU time 20.99 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:26:10 PM PST 23
Peak memory 196220 kb
Host smart-c5e7e693-a04e-4a05-b731-05e7c348e780
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669755217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3669755217
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1539463113
Short name T498
Test name
Test status
Simulation time 401287439 ps
CPU time 0.96 seconds
Started Dec 31 12:25:15 PM PST 23
Finished Dec 31 12:25:19 PM PST 23
Peak memory 197528 kb
Host smart-14756e5e-c6ff-41fe-a655-afb7f6f297da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539463113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1539463113
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.933436429
Short name T824
Test name
Test status
Simulation time 224193086 ps
CPU time 0.88 seconds
Started Dec 31 12:26:03 PM PST 23
Finished Dec 31 12:26:10 PM PST 23
Peak memory 197016 kb
Host smart-70cb11a8-8c3a-4b8f-b29a-b167979dcc6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933436429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.933436429
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.298268592
Short name T622
Test name
Test status
Simulation time 107860372 ps
CPU time 1.17 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:25:41 PM PST 23
Peak memory 197896 kb
Host smart-32373b01-024a-4d49-9c96-f9427a85dfba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298268592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.298268592
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2863398558
Short name T652
Test name
Test status
Simulation time 65077662 ps
CPU time 1.85 seconds
Started Dec 31 12:25:45 PM PST 23
Finished Dec 31 12:25:55 PM PST 23
Peak memory 197168 kb
Host smart-abeb0b41-57e7-4222-ae94-aea74008669a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863398558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2863398558
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1851100226
Short name T636
Test name
Test status
Simulation time 39605379 ps
CPU time 0.77 seconds
Started Dec 31 12:25:27 PM PST 23
Finished Dec 31 12:25:34 PM PST 23
Peak memory 197140 kb
Host smart-cae472ec-b330-476f-b982-43e5a3f4f888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851100226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1851100226
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2475505265
Short name T637
Test name
Test status
Simulation time 31503506 ps
CPU time 0.77 seconds
Started Dec 31 12:26:12 PM PST 23
Finished Dec 31 12:26:16 PM PST 23
Peak memory 196104 kb
Host smart-1f7f05b9-56ed-4ca5-99ab-fb0bbda12b7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475505265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2475505265
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.4081994298
Short name T619
Test name
Test status
Simulation time 128628026 ps
CPU time 5.5 seconds
Started Dec 31 12:26:13 PM PST 23
Finished Dec 31 12:26:21 PM PST 23
Peak memory 197948 kb
Host smart-26084ad5-743d-4ad7-bd4e-ee7e01d96a6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081994298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.4081994298
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.548033669
Short name T346
Test name
Test status
Simulation time 112777456 ps
CPU time 1.17 seconds
Started Dec 31 12:26:47 PM PST 23
Finished Dec 31 12:26:49 PM PST 23
Peak memory 197892 kb
Host smart-a407085d-49db-4369-acb0-07d0308f44b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548033669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.548033669
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1208125664
Short name T695
Test name
Test status
Simulation time 309592841 ps
CPU time 1.42 seconds
Started Dec 31 12:26:03 PM PST 23
Finished Dec 31 12:26:10 PM PST 23
Peak memory 197900 kb
Host smart-f571b6fd-8162-4052-a0e1-dfe86c512a80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208125664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1208125664
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3020967963
Short name T859
Test name
Test status
Simulation time 5421336864 ps
CPU time 57.83 seconds
Started Dec 31 12:26:40 PM PST 23
Finished Dec 31 12:27:39 PM PST 23
Peak memory 198040 kb
Host smart-3ef66617-41ec-402c-b848-72dfb7850244
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020967963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3020967963
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2566239107
Short name T495
Test name
Test status
Simulation time 253062173465 ps
CPU time 1272.16 seconds
Started Dec 31 12:25:21 PM PST 23
Finished Dec 31 12:46:38 PM PST 23
Peak memory 198164 kb
Host smart-4d32da65-dacf-4630-a029-eb097a072cfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2566239107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2566239107
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.773992261
Short name T369
Test name
Test status
Simulation time 21706386 ps
CPU time 0.56 seconds
Started Dec 31 12:26:21 PM PST 23
Finished Dec 31 12:26:23 PM PST 23
Peak memory 194488 kb
Host smart-79cc565f-1b6f-4eeb-99ff-c3b71c9035e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773992261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.773992261
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1782401726
Short name T742
Test name
Test status
Simulation time 222335488 ps
CPU time 0.81 seconds
Started Dec 31 12:26:03 PM PST 23
Finished Dec 31 12:26:09 PM PST 23
Peak memory 195472 kb
Host smart-c7c381c0-5dc7-41ea-917f-f2526147dac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782401726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1782401726
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1094033038
Short name T620
Test name
Test status
Simulation time 6254317861 ps
CPU time 11.94 seconds
Started Dec 31 12:26:23 PM PST 23
Finished Dec 31 12:26:36 PM PST 23
Peak memory 197084 kb
Host smart-fb59cd51-8376-45bc-955a-fa0289ad18f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094033038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1094033038
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2628056787
Short name T531
Test name
Test status
Simulation time 44830330 ps
CPU time 0.77 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 195620 kb
Host smart-f174dcdc-5346-4992-8f02-2cd95458ac93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628056787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2628056787
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1153398383
Short name T407
Test name
Test status
Simulation time 136540726 ps
CPU time 1.18 seconds
Started Dec 31 12:26:09 PM PST 23
Finished Dec 31 12:26:22 PM PST 23
Peak memory 196100 kb
Host smart-1449ffa5-11eb-47e7-9967-0e22d35e6616
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153398383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1153398383
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2560598797
Short name T532
Test name
Test status
Simulation time 80647603 ps
CPU time 1.8 seconds
Started Dec 31 12:25:49 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 197960 kb
Host smart-c7590d26-2a76-402e-aa6f-64511cc09b04
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560598797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2560598797
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3738736944
Short name T647
Test name
Test status
Simulation time 464660524 ps
CPU time 3.02 seconds
Started Dec 31 12:26:01 PM PST 23
Finished Dec 31 12:26:10 PM PST 23
Peak memory 197052 kb
Host smart-d0bea26e-83a7-4f83-a1b7-828fcb921e24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738736944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3738736944
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1070845592
Short name T716
Test name
Test status
Simulation time 23772966 ps
CPU time 0.9 seconds
Started Dec 31 12:26:06 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 195968 kb
Host smart-5b85f96f-c693-4d07-9e71-059d1f9c7259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070845592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1070845592
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2390370369
Short name T626
Test name
Test status
Simulation time 16346682 ps
CPU time 0.61 seconds
Started Dec 31 12:26:02 PM PST 23
Finished Dec 31 12:26:08 PM PST 23
Peak memory 194764 kb
Host smart-119103fd-04a5-443f-b748-37112ff97296
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390370369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2390370369
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3832564297
Short name T799
Test name
Test status
Simulation time 65209004 ps
CPU time 2.65 seconds
Started Dec 31 12:25:48 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 197872 kb
Host smart-e54e9c59-617b-4e6a-a724-0ba7f243475f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832564297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3832564297
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.940324617
Short name T881
Test name
Test status
Simulation time 168557386 ps
CPU time 1.42 seconds
Started Dec 31 12:25:50 PM PST 23
Finished Dec 31 12:25:59 PM PST 23
Peak memory 197936 kb
Host smart-02577c03-2325-4bc1-9c2b-ddcf816dad7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940324617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.940324617
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1368803890
Short name T217
Test name
Test status
Simulation time 46010985 ps
CPU time 1.26 seconds
Started Dec 31 12:26:49 PM PST 23
Finished Dec 31 12:26:52 PM PST 23
Peak memory 195536 kb
Host smart-684de6c8-8995-4a14-8cf5-a5e91650a87f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368803890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1368803890
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.4053282588
Short name T770
Test name
Test status
Simulation time 28612760713 ps
CPU time 183.9 seconds
Started Dec 31 12:25:24 PM PST 23
Finished Dec 31 12:28:33 PM PST 23
Peak memory 198076 kb
Host smart-d5fa1880-f12f-46c3-84c2-caf07efb52ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053282588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.4053282588
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.3462158531
Short name T666
Test name
Test status
Simulation time 177543744831 ps
CPU time 557.45 seconds
Started Dec 31 12:25:33 PM PST 23
Finished Dec 31 12:34:59 PM PST 23
Peak memory 206384 kb
Host smart-38c9d627-d50e-4bc5-b72c-6e145618f4c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3462158531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.3462158531
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3928925467
Short name T519
Test name
Test status
Simulation time 14914856 ps
CPU time 0.57 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:31 PM PST 23
Peak memory 194568 kb
Host smart-a05ed03c-c941-415e-8764-1392181a16ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928925467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3928925467
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3068679093
Short name T351
Test name
Test status
Simulation time 16079940 ps
CPU time 0.66 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:25:40 PM PST 23
Peak memory 194004 kb
Host smart-5e73c104-a3c1-4dce-85fc-f3c513f253c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068679093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3068679093
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2174661267
Short name T295
Test name
Test status
Simulation time 977906376 ps
CPU time 14.66 seconds
Started Dec 31 12:26:21 PM PST 23
Finished Dec 31 12:26:37 PM PST 23
Peak memory 195484 kb
Host smart-c73aa318-48be-4e10-aa48-a086002834fa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174661267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2174661267
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1276176813
Short name T698
Test name
Test status
Simulation time 71462754 ps
CPU time 0.92 seconds
Started Dec 31 12:26:31 PM PST 23
Finished Dec 31 12:26:34 PM PST 23
Peak memory 196336 kb
Host smart-cf31c45f-28e9-4321-a9e0-0baa951e11b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276176813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1276176813
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1790439736
Short name T704
Test name
Test status
Simulation time 52609950 ps
CPU time 1.3 seconds
Started Dec 31 12:25:00 PM PST 23
Finished Dec 31 12:25:05 PM PST 23
Peak memory 196640 kb
Host smart-5ed88dad-f1bb-4d7a-9122-9535c59e1d13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790439736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1790439736
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.756392646
Short name T325
Test name
Test status
Simulation time 26445892 ps
CPU time 1.03 seconds
Started Dec 31 12:25:47 PM PST 23
Finished Dec 31 12:25:55 PM PST 23
Peak memory 196024 kb
Host smart-d1b1bb3f-f20c-4a56-a9b8-01999ef373bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756392646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.756392646
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.4199849700
Short name T419
Test name
Test status
Simulation time 177942256 ps
CPU time 1.16 seconds
Started Dec 31 12:25:41 PM PST 23
Finished Dec 31 12:25:51 PM PST 23
Peak memory 196512 kb
Host smart-799c2c6f-a78b-4f0e-abb5-9902f07bdf92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199849700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.4199849700
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2971507915
Short name T304
Test name
Test status
Simulation time 172808696 ps
CPU time 0.94 seconds
Started Dec 31 12:25:46 PM PST 23
Finished Dec 31 12:25:55 PM PST 23
Peak memory 195872 kb
Host smart-15dcb8d4-1a4a-4a0b-be34-87a003aa08f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971507915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2971507915
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2057436853
Short name T462
Test name
Test status
Simulation time 163152832 ps
CPU time 1.35 seconds
Started Dec 31 12:26:09 PM PST 23
Finished Dec 31 12:26:15 PM PST 23
Peak memory 196876 kb
Host smart-897f80ae-3e03-4ad8-a389-d8966536fc15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057436853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2057436853
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2092347853
Short name T750
Test name
Test status
Simulation time 58789436 ps
CPU time 1.3 seconds
Started Dec 31 12:27:03 PM PST 23
Finished Dec 31 12:27:07 PM PST 23
Peak memory 197616 kb
Host smart-b5bffb19-0ffc-47bd-8db9-c80231275bb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092347853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2092347853
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.4119417643
Short name T356
Test name
Test status
Simulation time 40400669 ps
CPU time 1.18 seconds
Started Dec 31 12:26:51 PM PST 23
Finished Dec 31 12:26:53 PM PST 23
Peak memory 195764 kb
Host smart-ac859161-9391-42dd-a05f-cc53e44a2c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119417643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.4119417643
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.970902373
Short name T354
Test name
Test status
Simulation time 83052458 ps
CPU time 0.92 seconds
Started Dec 31 12:26:08 PM PST 23
Finished Dec 31 12:26:14 PM PST 23
Peak memory 195656 kb
Host smart-2f5c8efd-c132-404a-b3a0-08ef26b85523
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970902373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.970902373
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1680522581
Short name T491
Test name
Test status
Simulation time 20234821447 ps
CPU time 121.79 seconds
Started Dec 31 12:26:30 PM PST 23
Finished Dec 31 12:28:34 PM PST 23
Peak memory 198072 kb
Host smart-8572eee1-b472-4e9c-b66a-24ef00cc1c21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680522581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1680522581
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.171703329
Short name T525
Test name
Test status
Simulation time 60937914836 ps
CPU time 366.53 seconds
Started Dec 31 12:26:33 PM PST 23
Finished Dec 31 12:32:43 PM PST 23
Peak memory 198156 kb
Host smart-30f68f1e-d374-465e-921d-9124c81ffe7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=171703329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.171703329
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1539409210
Short name T362
Test name
Test status
Simulation time 130767120 ps
CPU time 0.53 seconds
Started Dec 31 12:25:36 PM PST 23
Finished Dec 31 12:25:44 PM PST 23
Peak memory 192636 kb
Host smart-4d4923b3-22fe-46a0-b75a-3d2862954dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539409210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1539409210
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2330343342
Short name T513
Test name
Test status
Simulation time 36878662 ps
CPU time 0.82 seconds
Started Dec 31 12:29:04 PM PST 23
Finished Dec 31 12:29:12 PM PST 23
Peak memory 195288 kb
Host smart-31b1d26b-70c8-4cd4-b747-5c42c15bf8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330343342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2330343342
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1824342223
Short name T842
Test name
Test status
Simulation time 3967454350 ps
CPU time 24.72 seconds
Started Dec 31 12:26:20 PM PST 23
Finished Dec 31 12:26:51 PM PST 23
Peak memory 198012 kb
Host smart-b9c1774f-1b60-4605-9eab-a1f6066db16d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824342223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1824342223
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.765781932
Short name T811
Test name
Test status
Simulation time 62339276 ps
CPU time 0.9 seconds
Started Dec 31 12:26:10 PM PST 23
Finished Dec 31 12:26:15 PM PST 23
Peak memory 197164 kb
Host smart-6bcc279c-e606-440c-b859-377cd10db8ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765781932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.765781932
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1993992677
Short name T521
Test name
Test status
Simulation time 154952301 ps
CPU time 0.87 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:25:53 PM PST 23
Peak memory 196016 kb
Host smart-24bf2354-42b3-483d-a018-367692258485
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993992677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1993992677
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3869040836
Short name T497
Test name
Test status
Simulation time 154148738 ps
CPU time 2.69 seconds
Started Dec 31 12:26:49 PM PST 23
Finished Dec 31 12:26:54 PM PST 23
Peak memory 196256 kb
Host smart-2226ed18-c71d-432e-bed1-887b46da4510
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869040836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3869040836
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3383540864
Short name T431
Test name
Test status
Simulation time 654701534 ps
CPU time 1.43 seconds
Started Dec 31 12:26:45 PM PST 23
Finished Dec 31 12:26:48 PM PST 23
Peak memory 195768 kb
Host smart-67dbed4e-76e1-4362-a77c-7d7fd87e1d29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383540864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3383540864
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1960512351
Short name T71
Test name
Test status
Simulation time 67466930 ps
CPU time 0.93 seconds
Started Dec 31 12:26:48 PM PST 23
Finished Dec 31 12:26:51 PM PST 23
Peak memory 196068 kb
Host smart-42141df4-e7df-4db3-ae18-676e2aa9cfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960512351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1960512351
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2100740917
Short name T305
Test name
Test status
Simulation time 183951870 ps
CPU time 1.06 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:25:40 PM PST 23
Peak memory 196872 kb
Host smart-9085c016-aa1a-45a0-adaa-d9d407b92019
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100740917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2100740917
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.407807092
Short name T478
Test name
Test status
Simulation time 152448378 ps
CPU time 1.99 seconds
Started Dec 31 12:25:35 PM PST 23
Finished Dec 31 12:25:45 PM PST 23
Peak memory 197892 kb
Host smart-f2bc0572-c3cb-4119-9ae4-e0ee2bec977f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407807092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.407807092
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2746094492
Short name T755
Test name
Test status
Simulation time 163709041 ps
CPU time 1.01 seconds
Started Dec 31 12:25:55 PM PST 23
Finished Dec 31 12:26:04 PM PST 23
Peak memory 195748 kb
Host smart-59dc2c01-c2ec-408b-91f5-bc2f4c42950e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746094492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2746094492
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.945432395
Short name T847
Test name
Test status
Simulation time 77571589 ps
CPU time 0.76 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:25:49 PM PST 23
Peak memory 195212 kb
Host smart-ee2ef999-d4fc-4b8e-a407-7bae671cf6f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945432395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.945432395
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.989715396
Short name T343
Test name
Test status
Simulation time 46859500772 ps
CPU time 130.79 seconds
Started Dec 31 12:27:05 PM PST 23
Finished Dec 31 12:29:18 PM PST 23
Peak memory 197884 kb
Host smart-e05d13af-07bd-4ad8-ae08-088ba3f42c4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989715396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.989715396
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.1956694816
Short name T357
Test name
Test status
Simulation time 302686880744 ps
CPU time 1151.79 seconds
Started Dec 31 12:27:08 PM PST 23
Finished Dec 31 12:46:24 PM PST 23
Peak memory 206428 kb
Host smart-0d40c738-6cf8-4777-93e2-ee5362c0b630
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1956694816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.1956694816
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2576989156
Short name T880
Test name
Test status
Simulation time 15150855 ps
CPU time 0.55 seconds
Started Dec 31 12:27:06 PM PST 23
Finished Dec 31 12:27:09 PM PST 23
Peak memory 194076 kb
Host smart-8332f14d-9aeb-4ab7-bcf0-03615f98469d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576989156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2576989156
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1657032118
Short name T397
Test name
Test status
Simulation time 36107632 ps
CPU time 0.62 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:48 PM PST 23
Peak memory 193872 kb
Host smart-c24bc886-9192-40fb-92b6-5c4863f34770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657032118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1657032118
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.231626491
Short name T603
Test name
Test status
Simulation time 2568764363 ps
CPU time 16.36 seconds
Started Dec 31 12:25:47 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 197096 kb
Host smart-cc88076b-e28a-40c7-ae34-1e8564992b68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231626491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.231626491
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1374330183
Short name T265
Test name
Test status
Simulation time 133297140 ps
CPU time 0.64 seconds
Started Dec 31 12:25:43 PM PST 23
Finished Dec 31 12:25:53 PM PST 23
Peak memory 195168 kb
Host smart-41532050-9726-4076-a935-cb1fafbdb512
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374330183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1374330183
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1931951231
Short name T872
Test name
Test status
Simulation time 436704184 ps
CPU time 1.33 seconds
Started Dec 31 12:25:43 PM PST 23
Finished Dec 31 12:25:53 PM PST 23
Peak memory 197968 kb
Host smart-6d19c203-eb01-4b96-a872-bb7b9fecc952
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931951231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1931951231
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3068498741
Short name T459
Test name
Test status
Simulation time 73361626 ps
CPU time 2.76 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:49 PM PST 23
Peak memory 198040 kb
Host smart-10e2310a-ea23-4311-89fe-4cf26a356fe2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068498741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3068498741
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2675814905
Short name T530
Test name
Test status
Simulation time 154608139 ps
CPU time 2.53 seconds
Started Dec 31 12:25:18 PM PST 23
Finished Dec 31 12:25:31 PM PST 23
Peak memory 197172 kb
Host smart-70b36803-2c48-405b-93a8-8a9d27878cd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675814905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2675814905
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2745246559
Short name T676
Test name
Test status
Simulation time 101676204 ps
CPU time 0.81 seconds
Started Dec 31 12:27:45 PM PST 23
Finished Dec 31 12:27:47 PM PST 23
Peak memory 196492 kb
Host smart-6beb3ce8-df7e-4c16-bcd6-800131797008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745246559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2745246559
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.646416307
Short name T384
Test name
Test status
Simulation time 65321783 ps
CPU time 0.71 seconds
Started Dec 31 12:26:05 PM PST 23
Finished Dec 31 12:26:11 PM PST 23
Peak memory 195352 kb
Host smart-da0b601a-e5ae-4b26-ae09-8435e9077d65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646416307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.646416307
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2013905265
Short name T589
Test name
Test status
Simulation time 1935773383 ps
CPU time 3.11 seconds
Started Dec 31 12:25:43 PM PST 23
Finished Dec 31 12:25:55 PM PST 23
Peak memory 197824 kb
Host smart-6b6a74f2-d6eb-45f7-bf2b-16e057bfb0f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013905265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2013905265
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.4083362753
Short name T550
Test name
Test status
Simulation time 23003319 ps
CPU time 0.66 seconds
Started Dec 31 12:25:49 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 194040 kb
Host smart-89a4d734-84eb-4427-893e-8e95318985c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083362753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.4083362753
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1322387672
Short name T718
Test name
Test status
Simulation time 33390865 ps
CPU time 0.95 seconds
Started Dec 31 12:26:06 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 195480 kb
Host smart-b9d9087d-0e1e-4a57-89d6-0f12030a1d9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322387672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1322387672
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2254723493
Short name T273
Test name
Test status
Simulation time 66430321321 ps
CPU time 236.57 seconds
Started Dec 31 12:25:43 PM PST 23
Finished Dec 31 12:29:48 PM PST 23
Peak memory 198052 kb
Host smart-b9122cf0-ff21-46c0-a533-2f0a0f469e12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254723493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2254723493
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1873624596
Short name T627
Test name
Test status
Simulation time 267421519154 ps
CPU time 2475.74 seconds
Started Dec 31 12:25:30 PM PST 23
Finished Dec 31 01:06:53 PM PST 23
Peak memory 198188 kb
Host smart-d18cce60-1351-41a3-9280-3984ed761027
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1873624596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1873624596
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1992286821
Short name T73
Test name
Test status
Simulation time 13156477 ps
CPU time 0.58 seconds
Started Dec 31 12:25:52 PM PST 23
Finished Dec 31 12:26:00 PM PST 23
Peak memory 194548 kb
Host smart-0b3336e5-e74e-46d6-8353-e17a4ce47bd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992286821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1992286821
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2706382263
Short name T438
Test name
Test status
Simulation time 89346118 ps
CPU time 0.85 seconds
Started Dec 31 12:25:35 PM PST 23
Finished Dec 31 12:25:44 PM PST 23
Peak memory 196076 kb
Host smart-1ce2f116-460b-4073-ac00-54a27c854b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706382263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2706382263
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3480376494
Short name T672
Test name
Test status
Simulation time 323931480 ps
CPU time 16.94 seconds
Started Dec 31 12:26:36 PM PST 23
Finished Dec 31 12:26:55 PM PST 23
Peak memory 196620 kb
Host smart-01290015-1952-4a5e-a10b-14a2f982fafc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480376494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3480376494
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2642276537
Short name T234
Test name
Test status
Simulation time 827459452 ps
CPU time 0.89 seconds
Started Dec 31 12:25:33 PM PST 23
Finished Dec 31 12:25:42 PM PST 23
Peak memory 196700 kb
Host smart-2637d89c-82cd-4973-9576-8eeac4acf8a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642276537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2642276537
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2049676274
Short name T599
Test name
Test status
Simulation time 58431821 ps
CPU time 0.78 seconds
Started Dec 31 12:27:48 PM PST 23
Finished Dec 31 12:27:50 PM PST 23
Peak memory 195520 kb
Host smart-0c2e6fd0-3778-45a3-bd34-7d0e4080e36a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049676274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2049676274
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2879398768
Short name T743
Test name
Test status
Simulation time 63564663 ps
CPU time 1.33 seconds
Started Dec 31 12:25:23 PM PST 23
Finished Dec 31 12:25:32 PM PST 23
Peak memory 196732 kb
Host smart-57b3bed3-df71-4d2d-b1f5-62da1bdf67b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879398768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2879398768
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.154400439
Short name T337
Test name
Test status
Simulation time 74092640 ps
CPU time 1.7 seconds
Started Dec 31 12:26:22 PM PST 23
Finished Dec 31 12:26:25 PM PST 23
Peak memory 195928 kb
Host smart-0868b5c2-51db-4b4f-9c24-e80a9de21595
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154400439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
154400439
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2423620772
Short name T501
Test name
Test status
Simulation time 19640370 ps
CPU time 0.74 seconds
Started Dec 31 12:25:46 PM PST 23
Finished Dec 31 12:25:55 PM PST 23
Peak memory 196104 kb
Host smart-e42540bc-c0f6-449f-97c6-63273010561b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423620772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2423620772
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1050440668
Short name T398
Test name
Test status
Simulation time 58157043 ps
CPU time 0.71 seconds
Started Dec 31 12:25:22 PM PST 23
Finished Dec 31 12:25:27 PM PST 23
Peak memory 195332 kb
Host smart-84228df9-ee13-41c0-a1a4-f6b413bc3fec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050440668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1050440668
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2545331024
Short name T474
Test name
Test status
Simulation time 358355985 ps
CPU time 5.2 seconds
Started Dec 31 12:26:53 PM PST 23
Finished Dec 31 12:27:10 PM PST 23
Peak memory 197720 kb
Host smart-418a5c7a-3324-4f53-8883-29099b9ad933
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545331024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2545331024
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2193593096
Short name T446
Test name
Test status
Simulation time 28378823 ps
CPU time 0.67 seconds
Started Dec 31 12:27:28 PM PST 23
Finished Dec 31 12:27:30 PM PST 23
Peak memory 194048 kb
Host smart-079f100d-2e55-4a33-bb52-b280edf73a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193593096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2193593096
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.4169154483
Short name T485
Test name
Test status
Simulation time 71217576 ps
CPU time 1.09 seconds
Started Dec 31 12:26:21 PM PST 23
Finished Dec 31 12:26:24 PM PST 23
Peak memory 195708 kb
Host smart-cdc3b6ce-b3b2-4c46-b7b5-ffcfa77bb769
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169154483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.4169154483
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3251631168
Short name T475
Test name
Test status
Simulation time 15657050536 ps
CPU time 158.74 seconds
Started Dec 31 12:25:37 PM PST 23
Finished Dec 31 12:28:24 PM PST 23
Peak memory 198044 kb
Host smart-19e5be9b-5b40-433d-a4bb-98ad3f218848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251631168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3251631168
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.1471275728
Short name T236
Test name
Test status
Simulation time 109923866199 ps
CPU time 442.99 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:33:10 PM PST 23
Peak memory 206376 kb
Host smart-9d70cbd5-1ccf-4243-a23c-9d3c2d8d2d38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1471275728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.1471275728
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1564047999
Short name T262
Test name
Test status
Simulation time 57156076 ps
CPU time 0.54 seconds
Started Dec 31 12:25:11 PM PST 23
Finished Dec 31 12:25:15 PM PST 23
Peak memory 193836 kb
Host smart-4f5c4ec9-6a84-431d-b244-9ca2b3d4b7e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564047999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1564047999
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1684003394
Short name T238
Test name
Test status
Simulation time 44714514 ps
CPU time 0.85 seconds
Started Dec 31 12:25:18 PM PST 23
Finished Dec 31 12:25:22 PM PST 23
Peak memory 196460 kb
Host smart-b8b39f31-f015-48d3-bbac-a709572d5a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684003394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1684003394
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2249287612
Short name T697
Test name
Test status
Simulation time 817335983 ps
CPU time 12.15 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:26:01 PM PST 23
Peak memory 198020 kb
Host smart-41aabdde-f113-44f0-b1fc-66d732e9cd76
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249287612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2249287612
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1203275677
Short name T403
Test name
Test status
Simulation time 259474866 ps
CPU time 0.88 seconds
Started Dec 31 12:26:50 PM PST 23
Finished Dec 31 12:26:52 PM PST 23
Peak memory 196992 kb
Host smart-8ae2274e-ccb5-4f34-9a8f-5dc0402d034a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203275677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1203275677
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3348601605
Short name T487
Test name
Test status
Simulation time 37336096 ps
CPU time 0.77 seconds
Started Dec 31 12:27:15 PM PST 23
Finished Dec 31 12:27:17 PM PST 23
Peak memory 195504 kb
Host smart-53974d57-eb3e-4c33-9649-86241f7845a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348601605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3348601605
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.4118159709
Short name T447
Test name
Test status
Simulation time 215695511 ps
CPU time 3.3 seconds
Started Dec 31 12:25:33 PM PST 23
Finished Dec 31 12:25:44 PM PST 23
Peak memory 198008 kb
Host smart-391aab62-da86-486d-81d3-ed0faf656c0a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118159709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.4118159709
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1521532989
Short name T684
Test name
Test status
Simulation time 777197569 ps
CPU time 3.56 seconds
Started Dec 31 12:25:20 PM PST 23
Finished Dec 31 12:25:27 PM PST 23
Peak memory 197500 kb
Host smart-2e825149-f39a-40aa-8bac-5b3d54c5ac8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521532989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1521532989
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.4511503
Short name T380
Test name
Test status
Simulation time 55139539 ps
CPU time 1.16 seconds
Started Dec 31 12:27:02 PM PST 23
Finished Dec 31 12:27:10 PM PST 23
Peak memory 196672 kb
Host smart-82d604cc-116d-4fc8-85ba-4180ff039f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4511503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.4511503
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.21784560
Short name T789
Test name
Test status
Simulation time 75497827 ps
CPU time 0.99 seconds
Started Dec 31 12:25:30 PM PST 23
Finished Dec 31 12:25:39 PM PST 23
Peak memory 196376 kb
Host smart-63835b0e-fd8c-4f43-962b-a3f481be8248
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21784560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup_
pulldown.21784560
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.4124495623
Short name T377
Test name
Test status
Simulation time 910090028 ps
CPU time 4.65 seconds
Started Dec 31 12:25:45 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 197888 kb
Host smart-cbec0e3b-94c2-4816-aa43-afd6c0b99280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124495623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.4124495623
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3388226974
Short name T549
Test name
Test status
Simulation time 56320500 ps
CPU time 1.17 seconds
Started Dec 31 12:26:23 PM PST 23
Finished Dec 31 12:26:26 PM PST 23
Peak memory 196344 kb
Host smart-ca5a9f2e-5d47-427d-ab64-c9646c7fe0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388226974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3388226974
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3151961292
Short name T218
Test name
Test status
Simulation time 118378187 ps
CPU time 0.72 seconds
Started Dec 31 12:25:42 PM PST 23
Finished Dec 31 12:25:51 PM PST 23
Peak memory 195144 kb
Host smart-7bb7ef9d-89df-4e41-9906-ec5f797d9525
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151961292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3151961292
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3772244242
Short name T685
Test name
Test status
Simulation time 7850863568 ps
CPU time 83.52 seconds
Started Dec 31 12:26:44 PM PST 23
Finished Dec 31 12:28:14 PM PST 23
Peak memory 198060 kb
Host smart-b28d6cee-f288-42a2-b5ed-aa0520b89a45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772244242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3772244242
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1073422079
Short name T481
Test name
Test status
Simulation time 51995864560 ps
CPU time 353.93 seconds
Started Dec 31 12:25:46 PM PST 23
Finished Dec 31 12:31:48 PM PST 23
Peak memory 198156 kb
Host smart-f89ce107-05a1-48ce-94fb-d177b132dca8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1073422079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1073422079
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2454488338
Short name T378
Test name
Test status
Simulation time 12848478 ps
CPU time 0.56 seconds
Started Dec 31 12:25:29 PM PST 23
Finished Dec 31 12:25:36 PM PST 23
Peak memory 193844 kb
Host smart-0b560efa-ab61-4e82-956d-57d479f4e2a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454488338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2454488338
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.481871797
Short name T748
Test name
Test status
Simulation time 81028906 ps
CPU time 0.76 seconds
Started Dec 31 12:26:17 PM PST 23
Finished Dec 31 12:26:20 PM PST 23
Peak memory 195348 kb
Host smart-07eedf78-8297-433a-9b68-726fb0d66cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481871797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.481871797
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3073398199
Short name T468
Test name
Test status
Simulation time 497140941 ps
CPU time 6.67 seconds
Started Dec 31 12:26:46 PM PST 23
Finished Dec 31 12:26:55 PM PST 23
Peak memory 196896 kb
Host smart-e360961f-1746-4617-9eb6-16430df9513d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073398199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3073398199
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.380452846
Short name T790
Test name
Test status
Simulation time 74775808 ps
CPU time 0.94 seconds
Started Dec 31 12:26:10 PM PST 23
Finished Dec 31 12:26:15 PM PST 23
Peak memory 196264 kb
Host smart-d9127fbb-be09-4e04-a574-99e383820ab6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380452846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.380452846
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2578541887
Short name T364
Test name
Test status
Simulation time 86119988 ps
CPU time 1.42 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:32 PM PST 23
Peak memory 198104 kb
Host smart-eab2fb04-9c04-4f88-b4f0-40bde2577cf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578541887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2578541887
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1875850078
Short name T870
Test name
Test status
Simulation time 40389454 ps
CPU time 0.88 seconds
Started Dec 31 12:26:22 PM PST 23
Finished Dec 31 12:26:24 PM PST 23
Peak memory 196760 kb
Host smart-b12f995d-9bb1-4b07-9ccc-21f5d44a02c1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875850078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1875850078
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.664232515
Short name T851
Test name
Test status
Simulation time 184762219 ps
CPU time 2.44 seconds
Started Dec 31 12:25:50 PM PST 23
Finished Dec 31 12:26:00 PM PST 23
Peak memory 197100 kb
Host smart-4bfa1199-5376-4337-8fb7-daaf77ef62c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664232515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
664232515
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3871289572
Short name T730
Test name
Test status
Simulation time 12960470 ps
CPU time 0.6 seconds
Started Dec 31 12:25:52 PM PST 23
Finished Dec 31 12:25:59 PM PST 23
Peak memory 194080 kb
Host smart-8da411dc-50c3-451f-a9c3-a70aff000895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871289572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3871289572
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2807822020
Short name T714
Test name
Test status
Simulation time 89723794 ps
CPU time 0.9 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:25:40 PM PST 23
Peak memory 195984 kb
Host smart-a7203c1d-5740-4b9c-8e58-32c5003a2645
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807822020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2807822020
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.948386302
Short name T867
Test name
Test status
Simulation time 405515219 ps
CPU time 4.39 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:25:53 PM PST 23
Peak memory 197828 kb
Host smart-2ef5710a-6d5e-4329-bfd2-5e93c9a5c214
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948386302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.948386302
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.971227446
Short name T399
Test name
Test status
Simulation time 201643843 ps
CPU time 0.94 seconds
Started Dec 31 12:25:33 PM PST 23
Finished Dec 31 12:25:42 PM PST 23
Peak memory 196424 kb
Host smart-43195571-488d-4a5c-89f0-87e356b40052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971227446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.971227446
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1907563869
Short name T412
Test name
Test status
Simulation time 30588890 ps
CPU time 0.76 seconds
Started Dec 31 12:26:43 PM PST 23
Finished Dec 31 12:26:45 PM PST 23
Peak memory 194068 kb
Host smart-6476f1dc-3c7c-4c9a-9b6a-58d3a076d0a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907563869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1907563869
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2070552780
Short name T442
Test name
Test status
Simulation time 10363153428 ps
CPU time 134.15 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:28:20 PM PST 23
Peak memory 198076 kb
Host smart-2ade029d-7550-484b-b381-808733bc00a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070552780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2070552780
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2999617161
Short name T230
Test name
Test status
Simulation time 88621692065 ps
CPU time 1675.32 seconds
Started Dec 31 12:25:36 PM PST 23
Finished Dec 31 12:53:40 PM PST 23
Peak memory 198156 kb
Host smart-1779be2e-e2f6-42ed-869a-5616cf70849b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2999617161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2999617161
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2455058546
Short name T315
Test name
Test status
Simulation time 111984521 ps
CPU time 0.65 seconds
Started Dec 31 12:23:25 PM PST 23
Finished Dec 31 12:23:27 PM PST 23
Peak memory 193372 kb
Host smart-c4dcae7d-f6af-4329-8d9c-23916d282a46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455058546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2455058546
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3381632485
Short name T311
Test name
Test status
Simulation time 20586452 ps
CPU time 0.71 seconds
Started Dec 31 12:26:01 PM PST 23
Finished Dec 31 12:26:08 PM PST 23
Peak memory 194024 kb
Host smart-9e2bbef9-16bb-4986-ba3e-a9039eae627b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381632485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3381632485
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1447514844
Short name T833
Test name
Test status
Simulation time 1763960853 ps
CPU time 23.5 seconds
Started Dec 31 12:26:08 PM PST 23
Finished Dec 31 12:26:37 PM PST 23
Peak memory 197064 kb
Host smart-688a6160-65e5-4770-90fb-3929f2965fae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447514844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1447514844
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3271681988
Short name T518
Test name
Test status
Simulation time 363460240 ps
CPU time 0.8 seconds
Started Dec 31 12:18:41 PM PST 23
Finished Dec 31 12:18:43 PM PST 23
Peak memory 195780 kb
Host smart-d153c53b-812e-4d47-bfe3-556d0b95a08d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271681988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3271681988
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3474911379
Short name T638
Test name
Test status
Simulation time 90631985 ps
CPU time 1.38 seconds
Started Dec 31 12:20:09 PM PST 23
Finished Dec 31 12:20:11 PM PST 23
Peak memory 196256 kb
Host smart-b05d6fc4-6034-42ef-8ad4-803c7d9a9b2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474911379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3474911379
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1223816414
Short name T379
Test name
Test status
Simulation time 94286654 ps
CPU time 2.69 seconds
Started Dec 31 12:25:59 PM PST 23
Finished Dec 31 12:26:08 PM PST 23
Peak memory 197924 kb
Host smart-358e8fb6-ab26-4bdf-9ec4-a30d9d6a3f09
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223816414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1223816414
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.589833480
Short name T323
Test name
Test status
Simulation time 329311788 ps
CPU time 1.32 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 196316 kb
Host smart-d0de9d0e-90f5-49fe-9dfc-0b3370852d5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589833480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.589833480
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1240659781
Short name T390
Test name
Test status
Simulation time 124743729 ps
CPU time 0.81 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:25:50 PM PST 23
Peak memory 196060 kb
Host smart-3ae95477-f9c9-4a38-b5dd-8a2103c8a8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240659781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1240659781
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1254878816
Short name T373
Test name
Test status
Simulation time 20838225 ps
CPU time 0.72 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:02 PM PST 23
Peak memory 195448 kb
Host smart-5bdbb204-05f8-4c6c-8814-8905b1b030fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254878816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1254878816
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3558547816
Short name T537
Test name
Test status
Simulation time 121932031 ps
CPU time 5.63 seconds
Started Dec 31 12:21:54 PM PST 23
Finished Dec 31 12:22:01 PM PST 23
Peak memory 198332 kb
Host smart-ab50946a-ae61-4ff8-8221-bc8130f97cce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558547816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3558547816
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_smoke.2316744263
Short name T882
Test name
Test status
Simulation time 184502212 ps
CPU time 1.41 seconds
Started Dec 31 12:18:44 PM PST 23
Finished Dec 31 12:18:46 PM PST 23
Peak memory 195376 kb
Host smart-b5e972e3-e9c2-49de-b5e8-e147c545ce53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316744263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2316744263
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.534081412
Short name T359
Test name
Test status
Simulation time 183120435 ps
CPU time 1.02 seconds
Started Dec 31 12:23:21 PM PST 23
Finished Dec 31 12:23:23 PM PST 23
Peak memory 196300 kb
Host smart-f08b6be3-8ec9-4370-ab13-edf921e64013
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534081412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.534081412
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.4058971557
Short name T416
Test name
Test status
Simulation time 47591610438 ps
CPU time 130.91 seconds
Started Dec 31 12:24:03 PM PST 23
Finished Dec 31 12:26:19 PM PST 23
Peak memory 197656 kb
Host smart-9bf938fd-705b-4e90-bbe2-fc37b928ae1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058971557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.4058971557
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1432543320
Short name T76
Test name
Test status
Simulation time 41183804685 ps
CPU time 789.6 seconds
Started Dec 31 12:26:05 PM PST 23
Finished Dec 31 12:39:20 PM PST 23
Peak memory 198176 kb
Host smart-e719122f-35c1-4604-befc-bb58bfc150bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1432543320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1432543320
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2813155731
Short name T297
Test name
Test status
Simulation time 42418662 ps
CPU time 0.56 seconds
Started Dec 31 12:25:55 PM PST 23
Finished Dec 31 12:26:03 PM PST 23
Peak memory 194000 kb
Host smart-81da2350-bd49-431a-bc9a-b363bb95df4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813155731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2813155731
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1927394828
Short name T787
Test name
Test status
Simulation time 124394414 ps
CPU time 0.78 seconds
Started Dec 31 12:26:35 PM PST 23
Finished Dec 31 12:26:38 PM PST 23
Peak memory 195956 kb
Host smart-475dbab6-aded-400d-82f4-171923ed944e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927394828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1927394828
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1675316685
Short name T788
Test name
Test status
Simulation time 2218817847 ps
CPU time 18.22 seconds
Started Dec 31 12:26:46 PM PST 23
Finished Dec 31 12:27:06 PM PST 23
Peak memory 195472 kb
Host smart-caedab4f-4369-4a1a-800d-2df6b592c0b2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675316685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1675316685
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1305611448
Short name T878
Test name
Test status
Simulation time 80257132 ps
CPU time 0.6 seconds
Started Dec 31 12:27:36 PM PST 23
Finished Dec 31 12:27:37 PM PST 23
Peak memory 194292 kb
Host smart-4e5aaf18-c1f3-4377-9ced-6eaf8dc2d204
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305611448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1305611448
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3473529082
Short name T719
Test name
Test status
Simulation time 18818627 ps
CPU time 0.64 seconds
Started Dec 31 12:25:50 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 194204 kb
Host smart-3457419f-79e2-4d7c-b735-b6179fba2736
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473529082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3473529082
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1860019659
Short name T630
Test name
Test status
Simulation time 62274709 ps
CPU time 2.23 seconds
Started Dec 31 12:26:43 PM PST 23
Finished Dec 31 12:26:47 PM PST 23
Peak memory 197300 kb
Host smart-030ea8ba-6b16-46a7-a81d-53fbbf5370a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860019659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1860019659
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.616074035
Short name T797
Test name
Test status
Simulation time 246656942 ps
CPU time 2.32 seconds
Started Dec 31 12:26:51 PM PST 23
Finished Dec 31 12:26:55 PM PST 23
Peak memory 198004 kb
Host smart-1929c3a2-98db-4ebf-994b-2d0ec776febb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616074035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
616074035
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2717532633
Short name T594
Test name
Test status
Simulation time 40265603 ps
CPU time 0.63 seconds
Started Dec 31 12:26:29 PM PST 23
Finished Dec 31 12:26:32 PM PST 23
Peak memory 194140 kb
Host smart-f19a73fc-ea57-4f8a-9d64-3f2311e4142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717532633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2717532633
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3288136961
Short name T520
Test name
Test status
Simulation time 120404737 ps
CPU time 1.27 seconds
Started Dec 31 12:26:56 PM PST 23
Finished Dec 31 12:26:59 PM PST 23
Peak memory 198012 kb
Host smart-58a29892-04fd-453e-b17e-01bf125e04c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288136961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3288136961
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1735754273
Short name T677
Test name
Test status
Simulation time 842936059 ps
CPU time 3.46 seconds
Started Dec 31 12:26:40 PM PST 23
Finished Dec 31 12:26:45 PM PST 23
Peak memory 197912 kb
Host smart-49cad263-c18b-4afa-92e3-3cc0de41f88c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735754273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1735754273
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.145274739
Short name T420
Test name
Test status
Simulation time 39177402 ps
CPU time 1.18 seconds
Started Dec 31 12:26:50 PM PST 23
Finished Dec 31 12:26:53 PM PST 23
Peak memory 196660 kb
Host smart-d5cfc934-fd3a-44b2-b822-e38db2008883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145274739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.145274739
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3777947556
Short name T812
Test name
Test status
Simulation time 40474507 ps
CPU time 0.89 seconds
Started Dec 31 12:25:20 PM PST 23
Finished Dec 31 12:25:24 PM PST 23
Peak memory 197192 kb
Host smart-9808897b-aaf3-49c0-8b30-a39c9ea836e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777947556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3777947556
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1390851429
Short name T887
Test name
Test status
Simulation time 8200086681 ps
CPU time 98.65 seconds
Started Dec 31 12:25:53 PM PST 23
Finished Dec 31 12:27:39 PM PST 23
Peak memory 198128 kb
Host smart-751d3051-69f7-4ac6-9ef5-6293041de8cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390851429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1390851429
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.283188013
Short name T611
Test name
Test status
Simulation time 1276177248062 ps
CPU time 1888.19 seconds
Started Dec 31 12:27:05 PM PST 23
Finished Dec 31 12:58:36 PM PST 23
Peak memory 198212 kb
Host smart-47b66385-cd3b-4ded-8e01-ac5b230720ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=283188013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.283188013
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.4031545759
Short name T761
Test name
Test status
Simulation time 48030388 ps
CPU time 0.55 seconds
Started Dec 31 12:26:16 PM PST 23
Finished Dec 31 12:26:19 PM PST 23
Peak memory 193868 kb
Host smart-a4e08260-0f34-497e-8e72-da8a61517897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031545759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.4031545759
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2870317199
Short name T651
Test name
Test status
Simulation time 37836615 ps
CPU time 0.67 seconds
Started Dec 31 12:25:35 PM PST 23
Finished Dec 31 12:25:44 PM PST 23
Peak memory 194716 kb
Host smart-dac4a9b9-051b-4107-be76-98aefbbc0b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870317199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2870317199
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3263881287
Short name T224
Test name
Test status
Simulation time 605492505 ps
CPU time 15.11 seconds
Started Dec 31 12:26:53 PM PST 23
Finished Dec 31 12:27:10 PM PST 23
Peak memory 196172 kb
Host smart-5a2bc2a4-f019-40a0-b225-c26bdd817202
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263881287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3263881287
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.6260823
Short name T476
Test name
Test status
Simulation time 172021029 ps
CPU time 0.76 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:25:39 PM PST 23
Peak memory 195904 kb
Host smart-4a35f9c9-393f-4676-87c3-f211abb47ede
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6260823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.6260823
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3763716983
Short name T796
Test name
Test status
Simulation time 47682227 ps
CPU time 1.22 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:32 PM PST 23
Peak memory 197276 kb
Host smart-567ab94b-77aa-48fb-b9dc-07164f2acff4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763716983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3763716983
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.4041161811
Short name T452
Test name
Test status
Simulation time 240539038 ps
CPU time 2.22 seconds
Started Dec 31 12:26:31 PM PST 23
Finished Dec 31 12:26:35 PM PST 23
Peak memory 197892 kb
Host smart-fdf87529-a40e-4f88-b745-b0ec63215f8c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041161811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.4041161811
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1841673928
Short name T526
Test name
Test status
Simulation time 315135357 ps
CPU time 1 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:48 PM PST 23
Peak memory 195432 kb
Host smart-6c42dc32-3ad3-458a-85ec-9d54c98f1921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841673928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1841673928
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1059744378
Short name T618
Test name
Test status
Simulation time 33736026 ps
CPU time 0.81 seconds
Started Dec 31 12:26:06 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 197148 kb
Host smart-6f511306-f569-41e5-b926-d44d9ae6cf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059744378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1059744378
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3992504114
Short name T808
Test name
Test status
Simulation time 204832862 ps
CPU time 1.22 seconds
Started Dec 31 12:26:16 PM PST 23
Finished Dec 31 12:26:20 PM PST 23
Peak memory 197996 kb
Host smart-6fb64750-0572-435b-aaf1-f16f5457e6b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992504114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3992504114
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.54427096
Short name T363
Test name
Test status
Simulation time 1408169805 ps
CPU time 4.38 seconds
Started Dec 31 12:26:15 PM PST 23
Finished Dec 31 12:26:22 PM PST 23
Peak memory 197852 kb
Host smart-bd848ecf-9eb1-4fdd-b156-5ae7108c50a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54427096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand
om_long_reg_writes_reg_reads.54427096
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.262727045
Short name T663
Test name
Test status
Simulation time 41823202 ps
CPU time 0.91 seconds
Started Dec 31 12:26:10 PM PST 23
Finished Dec 31 12:26:15 PM PST 23
Peak memory 196112 kb
Host smart-4f81b2c5-6642-4613-87e0-1927de6c6b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262727045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.262727045
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1249137454
Short name T443
Test name
Test status
Simulation time 132295158 ps
CPU time 1.09 seconds
Started Dec 31 12:26:13 PM PST 23
Finished Dec 31 12:26:17 PM PST 23
Peak memory 195468 kb
Host smart-f590962a-1520-4906-8440-709feec0a67a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249137454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1249137454
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.611774010
Short name T496
Test name
Test status
Simulation time 29577995812 ps
CPU time 200.88 seconds
Started Dec 31 12:26:28 PM PST 23
Finished Dec 31 12:29:51 PM PST 23
Peak memory 198060 kb
Host smart-5e00da9c-ddf3-41cc-ad73-749ce3f80ae1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611774010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.611774010
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.1072396497
Short name T280
Test name
Test status
Simulation time 34541330498 ps
CPU time 887.56 seconds
Started Dec 31 12:26:57 PM PST 23
Finished Dec 31 12:41:46 PM PST 23
Peak memory 198204 kb
Host smart-d62649e4-9774-4fe3-a273-c8ca5909c35a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1072396497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.1072396497
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2823554494
Short name T316
Test name
Test status
Simulation time 20800239 ps
CPU time 0.56 seconds
Started Dec 31 12:26:01 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 193796 kb
Host smart-a7be9699-b21b-482c-9254-36775fdd947c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823554494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2823554494
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1712933358
Short name T347
Test name
Test status
Simulation time 103129208 ps
CPU time 0.87 seconds
Started Dec 31 12:26:50 PM PST 23
Finished Dec 31 12:26:52 PM PST 23
Peak memory 195988 kb
Host smart-eb32d6fa-e597-4386-bcbc-fa55a39c831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712933358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1712933358
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2894202246
Short name T889
Test name
Test status
Simulation time 148542455 ps
CPU time 4.12 seconds
Started Dec 31 12:26:03 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 195876 kb
Host smart-8cd0b743-2e58-4f2d-99bc-a3d4b96a9a2c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894202246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2894202246
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3811880053
Short name T571
Test name
Test status
Simulation time 627118914 ps
CPU time 1.01 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:25:40 PM PST 23
Peak memory 196324 kb
Host smart-3c9331a7-f193-45a7-8875-d2c3cf715bda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811880053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3811880053
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2451258205
Short name T283
Test name
Test status
Simulation time 17784165 ps
CPU time 0.64 seconds
Started Dec 31 12:26:19 PM PST 23
Finished Dec 31 12:26:22 PM PST 23
Peak memory 194952 kb
Host smart-9001414e-82a7-4168-9e10-75e52568cf3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451258205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2451258205
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3169221411
Short name T866
Test name
Test status
Simulation time 179825927 ps
CPU time 1.24 seconds
Started Dec 31 12:25:41 PM PST 23
Finished Dec 31 12:25:51 PM PST 23
Peak memory 196512 kb
Host smart-e279d81e-87d2-4124-a6c3-4c7a4406544f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169221411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3169221411
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.4225546707
Short name T464
Test name
Test status
Simulation time 440380711 ps
CPU time 1.58 seconds
Started Dec 31 12:25:24 PM PST 23
Finished Dec 31 12:25:31 PM PST 23
Peak memory 196628 kb
Host smart-95f456cb-223f-41d2-a6d1-6da55b9412d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225546707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.4225546707
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1071333152
Short name T391
Test name
Test status
Simulation time 110611292 ps
CPU time 0.7 seconds
Started Dec 31 12:26:05 PM PST 23
Finished Dec 31 12:26:11 PM PST 23
Peak memory 195292 kb
Host smart-49e65ad0-3433-48e7-86b4-a44bc5a5af3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071333152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1071333152
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3503608184
Short name T701
Test name
Test status
Simulation time 81373871 ps
CPU time 1.2 seconds
Started Dec 31 12:25:52 PM PST 23
Finished Dec 31 12:26:00 PM PST 23
Peak memory 195776 kb
Host smart-753ac637-2566-41f2-aedf-56b1f8b1c688
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503608184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3503608184
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2150921598
Short name T274
Test name
Test status
Simulation time 1314662065 ps
CPU time 3.65 seconds
Started Dec 31 12:30:09 PM PST 23
Finished Dec 31 12:30:17 PM PST 23
Peak memory 197868 kb
Host smart-dd13d213-eac2-4196-8209-358f748f30a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150921598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2150921598
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3486305435
Short name T428
Test name
Test status
Simulation time 87561914 ps
CPU time 1.29 seconds
Started Dec 31 12:26:28 PM PST 23
Finished Dec 31 12:26:30 PM PST 23
Peak memory 195436 kb
Host smart-8f3b7d67-b4b3-4df8-aa11-060b4d4a3aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486305435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3486305435
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.647068076
Short name T769
Test name
Test status
Simulation time 39073428 ps
CPU time 0.84 seconds
Started Dec 31 12:27:27 PM PST 23
Finished Dec 31 12:27:29 PM PST 23
Peak memory 195200 kb
Host smart-dba78feb-1078-4a28-985c-d5709f20b236
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647068076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.647068076
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2569959043
Short name T739
Test name
Test status
Simulation time 31775287281 ps
CPU time 81.61 seconds
Started Dec 31 12:25:33 PM PST 23
Finished Dec 31 12:27:03 PM PST 23
Peak memory 198028 kb
Host smart-d0a936c7-821b-4669-ba76-b7c93c44c2e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569959043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2569959043
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.502225511
Short name T746
Test name
Test status
Simulation time 99522498 ps
CPU time 0.56 seconds
Started Dec 31 12:25:56 PM PST 23
Finished Dec 31 12:26:04 PM PST 23
Peak memory 193920 kb
Host smart-ea44efc2-8822-4da4-97de-e5a40c790ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502225511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.502225511
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1597218423
Short name T334
Test name
Test status
Simulation time 40929259 ps
CPU time 0.64 seconds
Started Dec 31 12:26:21 PM PST 23
Finished Dec 31 12:26:23 PM PST 23
Peak memory 194060 kb
Host smart-5dc363ed-886e-4747-85ff-60b40a5f74e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597218423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1597218423
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.263212497
Short name T843
Test name
Test status
Simulation time 168427361 ps
CPU time 7.39 seconds
Started Dec 31 12:25:35 PM PST 23
Finished Dec 31 12:25:51 PM PST 23
Peak memory 196952 kb
Host smart-2b6f699f-4274-416e-8776-b136c9dbdbfe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263212497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.263212497
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.4226395753
Short name T745
Test name
Test status
Simulation time 202043989 ps
CPU time 0.76 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 196464 kb
Host smart-59861179-852e-42d8-8bf8-23696190ddcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226395753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.4226395753
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.196495594
Short name T288
Test name
Test status
Simulation time 73129931 ps
CPU time 1.09 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:47 PM PST 23
Peak memory 196060 kb
Host smart-beb4cfcf-9a7d-4875-9a68-1b078404a713
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196495594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.196495594
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.704051686
Short name T600
Test name
Test status
Simulation time 66472968 ps
CPU time 2.49 seconds
Started Dec 31 12:25:49 PM PST 23
Finished Dec 31 12:25:59 PM PST 23
Peak memory 198016 kb
Host smart-a528a63e-2b7d-4d3a-bdc7-f5174974f23e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704051686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.704051686
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.643725834
Short name T269
Test name
Test status
Simulation time 105488135 ps
CPU time 2.82 seconds
Started Dec 31 12:25:48 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 197928 kb
Host smart-b5276aa4-516b-4281-842d-52b394046cce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643725834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
643725834
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2087091474
Short name T886
Test name
Test status
Simulation time 101143061 ps
CPU time 0.72 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:25:39 PM PST 23
Peak memory 195264 kb
Host smart-fc689ae5-610e-4760-bc9b-400ba4978caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087091474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2087091474
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.296695390
Short name T374
Test name
Test status
Simulation time 330086074 ps
CPU time 1.11 seconds
Started Dec 31 12:27:54 PM PST 23
Finished Dec 31 12:28:03 PM PST 23
Peak memory 198092 kb
Host smart-e599707f-f95e-4003-a43a-35cab9b8c9bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296695390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.296695390
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2848174666
Short name T516
Test name
Test status
Simulation time 29449201 ps
CPU time 1.29 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:03 PM PST 23
Peak memory 198000 kb
Host smart-599d7171-ff26-48de-9ccb-d66f25613bf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848174666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2848174666
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2425655472
Short name T688
Test name
Test status
Simulation time 237679271 ps
CPU time 1 seconds
Started Dec 31 12:28:13 PM PST 23
Finished Dec 31 12:28:15 PM PST 23
Peak memory 195812 kb
Host smart-1436455a-f0f7-4ef6-8b91-b58b096f878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425655472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2425655472
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1791696761
Short name T659
Test name
Test status
Simulation time 51144860 ps
CPU time 0.99 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 195496 kb
Host smart-7ed75faa-9cf0-4943-b2a5-b849909fd28d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791696761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1791696761
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.938821666
Short name T250
Test name
Test status
Simulation time 15720543985 ps
CPU time 193.75 seconds
Started Dec 31 12:25:42 PM PST 23
Finished Dec 31 12:29:05 PM PST 23
Peak memory 198068 kb
Host smart-85bfff9b-cbc5-46f2-a50a-42ebba26b741
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938821666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.938821666
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.741544198
Short name T687
Test name
Test status
Simulation time 233079894831 ps
CPU time 1489.6 seconds
Started Dec 31 12:25:34 PM PST 23
Finished Dec 31 12:50:32 PM PST 23
Peak memory 198192 kb
Host smart-5c8beed2-ff6e-426a-8a46-ddec6673e08f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=741544198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.741544198
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3965883291
Short name T860
Test name
Test status
Simulation time 17202970 ps
CPU time 0.55 seconds
Started Dec 31 12:26:01 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 194052 kb
Host smart-fd3556e1-a954-4af0-96fa-82f628c922bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965883291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3965883291
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1519839211
Short name T488
Test name
Test status
Simulation time 183748613 ps
CPU time 0.85 seconds
Started Dec 31 12:25:33 PM PST 23
Finished Dec 31 12:25:41 PM PST 23
Peak memory 196528 kb
Host smart-9ec05a7d-a1e7-4a8e-8ac6-76d65e79afbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519839211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1519839211
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1264053301
Short name T539
Test name
Test status
Simulation time 788228537 ps
CPU time 22.21 seconds
Started Dec 31 12:25:50 PM PST 23
Finished Dec 31 12:26:19 PM PST 23
Peak memory 196900 kb
Host smart-b953d31f-7b64-4fca-9c9e-4ed206fcc27e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264053301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1264053301
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2967781723
Short name T388
Test name
Test status
Simulation time 29466056 ps
CPU time 0.69 seconds
Started Dec 31 12:26:06 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 194392 kb
Host smart-5abb307a-eb28-4e26-aa2a-d2f33c5b8a8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967781723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2967781723
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1359961910
Short name T710
Test name
Test status
Simulation time 31171342 ps
CPU time 0.83 seconds
Started Dec 31 12:26:05 PM PST 23
Finished Dec 31 12:26:11 PM PST 23
Peak memory 196540 kb
Host smart-5d8f85ac-346a-4c2c-b68b-24c153fd0c75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359961910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1359961910
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3083323771
Short name T856
Test name
Test status
Simulation time 20126519 ps
CPU time 0.85 seconds
Started Dec 31 12:25:44 PM PST 23
Finished Dec 31 12:25:53 PM PST 23
Peak memory 196212 kb
Host smart-b7b2c630-5555-4a45-9590-4c365678b5cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083323771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3083323771
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1248248071
Short name T727
Test name
Test status
Simulation time 142091024 ps
CPU time 2.86 seconds
Started Dec 31 12:25:47 PM PST 23
Finished Dec 31 12:25:57 PM PST 23
Peak memory 197920 kb
Host smart-cb387270-66c9-4c05-a75e-c19924cad1c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248248071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1248248071
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.318332002
Short name T55
Test name
Test status
Simulation time 80365325 ps
CPU time 0.84 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:32 PM PST 23
Peak memory 196028 kb
Host smart-53be985e-00a2-42c2-9711-eec642d18cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318332002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.318332002
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1202554472
Short name T720
Test name
Test status
Simulation time 20547654 ps
CPU time 0.78 seconds
Started Dec 31 12:25:47 PM PST 23
Finished Dec 31 12:25:56 PM PST 23
Peak memory 195220 kb
Host smart-acacc160-35b3-444f-a25b-0691bb604ff1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202554472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1202554472
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3194591397
Short name T482
Test name
Test status
Simulation time 407497662 ps
CPU time 3.55 seconds
Started Dec 31 12:26:22 PM PST 23
Finished Dec 31 12:26:27 PM PST 23
Peak memory 197924 kb
Host smart-4cd9a659-9dd2-4865-ba5c-009b578b7f16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194591397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3194591397
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3407311262
Short name T875
Test name
Test status
Simulation time 1208069000 ps
CPU time 1.16 seconds
Started Dec 31 12:25:58 PM PST 23
Finished Dec 31 12:26:06 PM PST 23
Peak memory 195820 kb
Host smart-1472ce0f-efc3-4f25-b362-ae38e077d70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407311262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3407311262
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1546037314
Short name T216
Test name
Test status
Simulation time 416870757 ps
CPU time 1.37 seconds
Started Dec 31 12:26:14 PM PST 23
Finished Dec 31 12:26:18 PM PST 23
Peak memory 196776 kb
Host smart-2c552099-4f34-4eb9-8789-96b367d65715
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546037314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1546037314
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3499716508
Short name T313
Test name
Test status
Simulation time 7229580830 ps
CPU time 157.28 seconds
Started Dec 31 12:26:20 PM PST 23
Finished Dec 31 12:28:59 PM PST 23
Peak memory 197948 kb
Host smart-3f46c7e5-8b65-4dfd-a764-69760ad580ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499716508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3499716508
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.1542960621
Short name T507
Test name
Test status
Simulation time 346438310567 ps
CPU time 1042.76 seconds
Started Dec 31 12:25:45 PM PST 23
Finished Dec 31 12:43:16 PM PST 23
Peak memory 198296 kb
Host smart-2884218c-4362-4e80-a1d1-e1bbd018abf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1542960621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.1542960621
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3989811041
Short name T804
Test name
Test status
Simulation time 33055652 ps
CPU time 0.56 seconds
Started Dec 31 12:27:13 PM PST 23
Finished Dec 31 12:27:15 PM PST 23
Peak memory 194300 kb
Host smart-cd9c5210-ef25-4ee6-863e-aa2fb906fd9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989811041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3989811041
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3094390234
Short name T566
Test name
Test status
Simulation time 60716620 ps
CPU time 0.71 seconds
Started Dec 31 12:26:16 PM PST 23
Finished Dec 31 12:26:19 PM PST 23
Peak memory 195824 kb
Host smart-c43ba196-8e82-4bad-8018-9ea4f3a198ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094390234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3094390234
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3341714426
Short name T450
Test name
Test status
Simulation time 499598689 ps
CPU time 8.59 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 197836 kb
Host smart-c37cc306-4024-4b29-92b4-af4d786dd3bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341714426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3341714426
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.4046158932
Short name T871
Test name
Test status
Simulation time 483008524 ps
CPU time 1.04 seconds
Started Dec 31 12:27:10 PM PST 23
Finished Dec 31 12:27:12 PM PST 23
Peak memory 198156 kb
Host smart-84ed1327-9c66-4140-a375-ba526e806d78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046158932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.4046158932
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.645881303
Short name T456
Test name
Test status
Simulation time 19052387 ps
CPU time 0.67 seconds
Started Dec 31 12:25:43 PM PST 23
Finished Dec 31 12:25:52 PM PST 23
Peak memory 195276 kb
Host smart-eec90c09-327e-4ada-9587-4d897ceeb812
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645881303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.645881303
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3615434157
Short name T617
Test name
Test status
Simulation time 106684393 ps
CPU time 1.31 seconds
Started Dec 31 12:25:50 PM PST 23
Finished Dec 31 12:25:59 PM PST 23
Peak memory 196412 kb
Host smart-249dcff8-85a1-43be-aa70-dd2c17cfe21f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615434157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3615434157
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1557198279
Short name T699
Test name
Test status
Simulation time 319016146 ps
CPU time 2.84 seconds
Started Dec 31 12:26:30 PM PST 23
Finished Dec 31 12:26:34 PM PST 23
Peak memory 195688 kb
Host smart-778952b5-db24-4a1e-9c47-f00961d737ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557198279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1557198279
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1378532801
Short name T767
Test name
Test status
Simulation time 65786459 ps
CPU time 0.94 seconds
Started Dec 31 12:25:56 PM PST 23
Finished Dec 31 12:26:05 PM PST 23
Peak memory 195968 kb
Host smart-4d6c6210-0016-4576-b7f2-08bf515c8ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378532801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1378532801
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2617740858
Short name T840
Test name
Test status
Simulation time 524305764 ps
CPU time 1.06 seconds
Started Dec 31 12:26:48 PM PST 23
Finished Dec 31 12:26:51 PM PST 23
Peak memory 195912 kb
Host smart-b1cbf089-34a1-4453-b630-0a1b14cafdda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617740858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2617740858
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.4190675260
Short name T56
Test name
Test status
Simulation time 1696729481 ps
CPU time 5.81 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:25:45 PM PST 23
Peak memory 197916 kb
Host smart-240477d7-3018-423c-9185-7ea5f1d15d87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190675260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.4190675260
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.4095320977
Short name T810
Test name
Test status
Simulation time 40892915 ps
CPU time 1.07 seconds
Started Dec 31 12:27:05 PM PST 23
Finished Dec 31 12:27:08 PM PST 23
Peak memory 196232 kb
Host smart-045e74aa-ef13-4aa6-bca5-cad1f28de7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095320977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.4095320977
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3048467246
Short name T567
Test name
Test status
Simulation time 60093074 ps
CPU time 0.87 seconds
Started Dec 31 12:26:30 PM PST 23
Finished Dec 31 12:26:33 PM PST 23
Peak memory 196304 kb
Host smart-ced55f27-91ed-40fe-b5e6-d94aee97b6fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048467246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3048467246
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1892754129
Short name T547
Test name
Test status
Simulation time 3166415742 ps
CPU time 40.99 seconds
Started Dec 31 12:26:24 PM PST 23
Finished Dec 31 12:27:06 PM PST 23
Peak memory 197984 kb
Host smart-e4fe98b5-c597-4c50-a112-30c71b658ed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892754129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1892754129
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.782487890
Short name T582
Test name
Test status
Simulation time 84684903004 ps
CPU time 2254.82 seconds
Started Dec 31 12:26:35 PM PST 23
Finished Dec 31 01:04:13 PM PST 23
Peak memory 198176 kb
Host smart-4dc44be8-af1e-443b-9711-a491c1c6bd96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=782487890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.782487890
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2588082756
Short name T54
Test name
Test status
Simulation time 12974679 ps
CPU time 0.54 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:47 PM PST 23
Peak memory 194712 kb
Host smart-f8d13f1a-3d13-4053-8465-5a1792cd8180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588082756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2588082756
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2886479230
Short name T306
Test name
Test status
Simulation time 32644867 ps
CPU time 0.74 seconds
Started Dec 31 12:25:36 PM PST 23
Finished Dec 31 12:25:45 PM PST 23
Peak memory 196036 kb
Host smart-2c762c40-22d8-46a9-9b1f-99066a9c595a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886479230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2886479230
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1365752245
Short name T791
Test name
Test status
Simulation time 550872731 ps
CPU time 20.17 seconds
Started Dec 31 12:25:49 PM PST 23
Finished Dec 31 12:26:17 PM PST 23
Peak memory 197040 kb
Host smart-3f14f8e0-5f04-45d2-b04f-f3571f89dbdf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365752245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1365752245
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.751839297
Short name T427
Test name
Test status
Simulation time 85177738 ps
CPU time 0.74 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 195620 kb
Host smart-501cef0d-d4c9-47a5-9ba3-ea16738f4172
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751839297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.751839297
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2652035182
Short name T758
Test name
Test status
Simulation time 110852900 ps
CPU time 0.79 seconds
Started Dec 31 12:26:24 PM PST 23
Finished Dec 31 12:26:26 PM PST 23
Peak memory 195524 kb
Host smart-700cdf11-4298-417f-b52b-bc3d410552aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652035182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2652035182
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2859997841
Short name T421
Test name
Test status
Simulation time 298631184 ps
CPU time 2.95 seconds
Started Dec 31 12:26:52 PM PST 23
Finished Dec 31 12:26:57 PM PST 23
Peak memory 198104 kb
Host smart-19ee5ba9-55c7-48b0-9e11-b8e5538f2093
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859997841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2859997841
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3737598799
Short name T241
Test name
Test status
Simulation time 323058174 ps
CPU time 3.06 seconds
Started Dec 31 12:26:15 PM PST 23
Finished Dec 31 12:26:26 PM PST 23
Peak memory 198000 kb
Host smart-c6470f90-93ff-4ac6-8580-fb382fbaa0b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737598799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3737598799
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.101078570
Short name T449
Test name
Test status
Simulation time 69377740 ps
CPU time 0.85 seconds
Started Dec 31 12:26:42 PM PST 23
Finished Dec 31 12:26:44 PM PST 23
Peak memory 196536 kb
Host smart-c6c189ec-f714-4fa2-8d82-9ee6c99caf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101078570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.101078570
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2024166991
Short name T292
Test name
Test status
Simulation time 411410578 ps
CPU time 0.83 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 196420 kb
Host smart-a27806d9-5c36-4391-b966-07cab0be523c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024166991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2024166991
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1786923521
Short name T749
Test name
Test status
Simulation time 431588642 ps
CPU time 2.05 seconds
Started Dec 31 12:25:41 PM PST 23
Finished Dec 31 12:25:52 PM PST 23
Peak memory 197876 kb
Host smart-312a4ba3-266b-4704-b9b5-82ec7339843b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786923521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1786923521
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3755370958
Short name T528
Test name
Test status
Simulation time 115813102 ps
CPU time 0.95 seconds
Started Dec 31 12:26:51 PM PST 23
Finished Dec 31 12:26:54 PM PST 23
Peak memory 195704 kb
Host smart-715ffa09-ec5e-4875-9ee7-2dbca821b3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755370958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3755370958
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1417654074
Short name T572
Test name
Test status
Simulation time 146837211 ps
CPU time 0.79 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:02 PM PST 23
Peak memory 194964 kb
Host smart-6677d35c-bef0-4264-a80c-f2fafd027952
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417654074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1417654074
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3122677528
Short name T414
Test name
Test status
Simulation time 99088711144 ps
CPU time 86.7 seconds
Started Dec 31 12:27:03 PM PST 23
Finished Dec 31 12:28:32 PM PST 23
Peak memory 198136 kb
Host smart-d6e65539-3c8e-4406-bb47-6664ffd9c378
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122677528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3122677528
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1325683141
Short name T614
Test name
Test status
Simulation time 76150959984 ps
CPU time 964.4 seconds
Started Dec 31 12:27:34 PM PST 23
Finished Dec 31 12:43:40 PM PST 23
Peak memory 198156 kb
Host smart-dfb62727-a159-4a3f-a3d3-7fe41e815d38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1325683141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1325683141
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3918775367
Short name T275
Test name
Test status
Simulation time 19264687 ps
CPU time 0.55 seconds
Started Dec 31 12:26:05 PM PST 23
Finished Dec 31 12:26:11 PM PST 23
Peak memory 194592 kb
Host smart-3d0c976b-d400-43d5-a17b-62a64e73adc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918775367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3918775367
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1528422427
Short name T348
Test name
Test status
Simulation time 191574702 ps
CPU time 0.84 seconds
Started Dec 31 12:26:43 PM PST 23
Finished Dec 31 12:26:50 PM PST 23
Peak memory 195900 kb
Host smart-3a262b24-bbfe-4de5-916e-5855fff540ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528422427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1528422427
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2650921297
Short name T574
Test name
Test status
Simulation time 299343844 ps
CPU time 10.47 seconds
Started Dec 31 12:27:28 PM PST 23
Finished Dec 31 12:27:39 PM PST 23
Peak memory 198016 kb
Host smart-a518edb1-6bb3-4958-9eac-2ebb7ae4feff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650921297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2650921297
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2889798820
Short name T339
Test name
Test status
Simulation time 186250668 ps
CPU time 1.05 seconds
Started Dec 31 12:26:32 PM PST 23
Finished Dec 31 12:26:37 PM PST 23
Peak memory 196360 kb
Host smart-f29fba3d-5723-4497-b771-7ee827335cd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889798820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2889798820
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3625072312
Short name T583
Test name
Test status
Simulation time 17920971 ps
CPU time 0.61 seconds
Started Dec 31 12:27:23 PM PST 23
Finished Dec 31 12:27:24 PM PST 23
Peak memory 194216 kb
Host smart-414d7d0a-c092-4ecd-90d7-de7764454d71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625072312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3625072312
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.339891345
Short name T463
Test name
Test status
Simulation time 73716384 ps
CPU time 2.76 seconds
Started Dec 31 12:26:45 PM PST 23
Finished Dec 31 12:26:49 PM PST 23
Peak memory 198036 kb
Host smart-87714ee7-d944-4f38-aae9-063d1d1bc50d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339891345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.339891345
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.4247082293
Short name T624
Test name
Test status
Simulation time 177119312 ps
CPU time 2.15 seconds
Started Dec 31 12:27:10 PM PST 23
Finished Dec 31 12:27:14 PM PST 23
Peak memory 197060 kb
Host smart-4fba5af6-bcda-4993-b846-864f139e7ce3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247082293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.4247082293
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3105444447
Short name T494
Test name
Test status
Simulation time 36865418 ps
CPU time 0.7 seconds
Started Dec 31 12:26:13 PM PST 23
Finished Dec 31 12:26:17 PM PST 23
Peak memory 195984 kb
Host smart-5fe90a47-f757-4e6c-ba94-58b0c3aa2e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105444447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3105444447
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1458595055
Short name T848
Test name
Test status
Simulation time 18492610 ps
CPU time 0.69 seconds
Started Dec 31 12:26:32 PM PST 23
Finished Dec 31 12:26:35 PM PST 23
Peak memory 195896 kb
Host smart-042d9007-e92a-4516-85b8-10253b153fb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458595055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1458595055
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1229212963
Short name T289
Test name
Test status
Simulation time 128705569 ps
CPU time 1.68 seconds
Started Dec 31 12:27:35 PM PST 23
Finished Dec 31 12:27:38 PM PST 23
Peak memory 197968 kb
Host smart-4b829b19-cc4b-42c2-8691-d1cbd608fbac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229212963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1229212963
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1297058535
Short name T641
Test name
Test status
Simulation time 42986867 ps
CPU time 1.18 seconds
Started Dec 31 12:26:57 PM PST 23
Finished Dec 31 12:27:00 PM PST 23
Peak memory 196544 kb
Host smart-c2ba9c86-17b6-483e-8423-a35be62fa9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297058535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1297058535
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1881656172
Short name T634
Test name
Test status
Simulation time 357583991 ps
CPU time 0.9 seconds
Started Dec 31 12:26:25 PM PST 23
Finished Dec 31 12:26:27 PM PST 23
Peak memory 196352 kb
Host smart-3600d55d-03d8-40f5-9bb5-2a0f73db4d82
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881656172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1881656172
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1574218650
Short name T656
Test name
Test status
Simulation time 9702226179 ps
CPU time 30.85 seconds
Started Dec 31 12:28:00 PM PST 23
Finished Dec 31 12:28:38 PM PST 23
Peak memory 198068 kb
Host smart-ea44f4e8-5bf4-4a96-99b8-2bcf830b1041
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574218650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1574218650
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.4268132389
Short name T460
Test name
Test status
Simulation time 385999272310 ps
CPU time 1249.42 seconds
Started Dec 31 12:26:07 PM PST 23
Finished Dec 31 12:47:02 PM PST 23
Peak memory 198216 kb
Host smart-fe1cdbc0-95f0-4cb4-ab3c-e41a981491fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4268132389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.4268132389
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2630026591
Short name T846
Test name
Test status
Simulation time 35362464 ps
CPU time 0.55 seconds
Started Dec 31 12:26:31 PM PST 23
Finished Dec 31 12:26:36 PM PST 23
Peak memory 193928 kb
Host smart-8253ddd9-19ea-41a8-a79d-ba8b5c31c235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630026591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2630026591
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1266110290
Short name T678
Test name
Test status
Simulation time 15274858 ps
CPU time 0.59 seconds
Started Dec 31 12:26:03 PM PST 23
Finished Dec 31 12:26:09 PM PST 23
Peak memory 193860 kb
Host smart-dbc6399b-1bde-46e8-b672-e328799af71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266110290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1266110290
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.695351421
Short name T668
Test name
Test status
Simulation time 347974640 ps
CPU time 17.46 seconds
Started Dec 31 12:26:06 PM PST 23
Finished Dec 31 12:26:29 PM PST 23
Peak memory 196792 kb
Host smart-18a00f5c-a658-451d-8b8b-9da78131c97c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695351421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.695351421
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.4129791409
Short name T479
Test name
Test status
Simulation time 74290178 ps
CPU time 0.85 seconds
Started Dec 31 12:25:59 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 196656 kb
Host smart-96461c56-29db-4f15-85cf-c71c456d5f17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129791409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.4129791409
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.615275633
Short name T635
Test name
Test status
Simulation time 84147286 ps
CPU time 1.28 seconds
Started Dec 31 12:26:51 PM PST 23
Finished Dec 31 12:26:53 PM PST 23
Peak memory 197988 kb
Host smart-9cc7fc6e-eaea-40ba-b0eb-0ce4b656b86b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615275633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.615275633
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2530474860
Short name T751
Test name
Test status
Simulation time 35165092 ps
CPU time 1.03 seconds
Started Dec 31 12:26:19 PM PST 23
Finished Dec 31 12:26:22 PM PST 23
Peak memory 195296 kb
Host smart-e0b444cd-dd92-475b-a0b8-cd3aef552bf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530474860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2530474860
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.695963241
Short name T529
Test name
Test status
Simulation time 18939980 ps
CPU time 0.72 seconds
Started Dec 31 12:26:50 PM PST 23
Finished Dec 31 12:26:52 PM PST 23
Peak memory 195152 kb
Host smart-7d6675c8-1e54-4f89-a5a6-beb0580c2ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695963241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.695963241
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1281094299
Short name T477
Test name
Test status
Simulation time 20375901 ps
CPU time 0.61 seconds
Started Dec 31 12:26:40 PM PST 23
Finished Dec 31 12:26:42 PM PST 23
Peak memory 194740 kb
Host smart-36da5a17-d934-4b01-b960-661aa2ac843a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281094299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1281094299
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1755197121
Short name T744
Test name
Test status
Simulation time 187289873 ps
CPU time 4.16 seconds
Started Dec 31 12:26:18 PM PST 23
Finished Dec 31 12:26:34 PM PST 23
Peak memory 197972 kb
Host smart-e5fbf3ad-5ded-4b69-9d7d-81aded24ded1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755197121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1755197121
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.4060769817
Short name T869
Test name
Test status
Simulation time 110549708 ps
CPU time 1.22 seconds
Started Dec 31 12:26:05 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 196708 kb
Host smart-d4e2b68e-2265-467c-9a8b-4f2cfd198929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060769817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.4060769817
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.139538225
Short name T483
Test name
Test status
Simulation time 39918335 ps
CPU time 1.08 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:03 PM PST 23
Peak memory 196416 kb
Host smart-7a979fa7-38d0-4cc9-b279-4d35b266a942
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139538225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.139538225
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.677440731
Short name T703
Test name
Test status
Simulation time 19207069573 ps
CPU time 101.19 seconds
Started Dec 31 12:26:34 PM PST 23
Finished Dec 31 12:28:18 PM PST 23
Peak memory 197876 kb
Host smart-88321fe6-4fdb-469d-866a-19a19d203271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677440731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.677440731
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.4172154083
Short name T444
Test name
Test status
Simulation time 109240934713 ps
CPU time 1283.3 seconds
Started Dec 31 12:26:53 PM PST 23
Finished Dec 31 12:48:18 PM PST 23
Peak memory 198228 kb
Host smart-c9ba71a0-189b-4e4d-b734-6f3752971423
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4172154083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.4172154083
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3232527954
Short name T768
Test name
Test status
Simulation time 35231238 ps
CPU time 0.58 seconds
Started Dec 31 12:28:02 PM PST 23
Finished Dec 31 12:28:18 PM PST 23
Peak memory 194600 kb
Host smart-3b8abaa2-e054-411c-a5a9-bb2712ce1539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232527954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3232527954
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.169389928
Short name T836
Test name
Test status
Simulation time 68773784 ps
CPU time 0.63 seconds
Started Dec 31 12:27:33 PM PST 23
Finished Dec 31 12:27:34 PM PST 23
Peak memory 194044 kb
Host smart-f6ef24ea-5889-4b98-a28b-53fbfc799da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169389928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.169389928
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2391771209
Short name T301
Test name
Test status
Simulation time 483944138 ps
CPU time 24.42 seconds
Started Dec 31 12:27:37 PM PST 23
Finished Dec 31 12:28:02 PM PST 23
Peak memory 195356 kb
Host smart-3358d051-0b96-4acf-8d43-15d05a16ce52
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391771209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2391771209
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1826457459
Short name T342
Test name
Test status
Simulation time 148745426 ps
CPU time 0.69 seconds
Started Dec 31 12:29:46 PM PST 23
Finished Dec 31 12:29:49 PM PST 23
Peak memory 196428 kb
Host smart-3a50f6ae-58f1-45d6-b805-0c7ec3c4af26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826457459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1826457459
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1725231462
Short name T554
Test name
Test status
Simulation time 889397009 ps
CPU time 1.19 seconds
Started Dec 31 12:26:59 PM PST 23
Finished Dec 31 12:27:03 PM PST 23
Peak memory 196060 kb
Host smart-478207da-9215-4138-82ff-8c274a2d6565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725231462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1725231462
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2751204629
Short name T754
Test name
Test status
Simulation time 60215149 ps
CPU time 2.34 seconds
Started Dec 31 12:27:42 PM PST 23
Finished Dec 31 12:27:45 PM PST 23
Peak memory 198056 kb
Host smart-4f01fc06-15d7-4ff8-a865-712e0e98a26e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751204629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2751204629
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.882617688
Short name T565
Test name
Test status
Simulation time 109506974 ps
CPU time 2.88 seconds
Started Dec 31 12:26:55 PM PST 23
Finished Dec 31 12:27:00 PM PST 23
Peak memory 197032 kb
Host smart-4896509e-f6d8-41d0-ac42-0b0ef70a2d62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882617688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
882617688
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2664799333
Short name T221
Test name
Test status
Simulation time 191242793 ps
CPU time 1.08 seconds
Started Dec 31 12:27:44 PM PST 23
Finished Dec 31 12:27:46 PM PST 23
Peak memory 196556 kb
Host smart-13ef3308-8078-4ade-bef9-c37728b93c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664799333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2664799333
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1372617665
Short name T845
Test name
Test status
Simulation time 58506198 ps
CPU time 0.84 seconds
Started Dec 31 12:27:04 PM PST 23
Finished Dec 31 12:27:07 PM PST 23
Peak memory 196084 kb
Host smart-485a8043-0824-4961-9621-3699527824df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372617665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1372617665
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.889901826
Short name T395
Test name
Test status
Simulation time 637735796 ps
CPU time 3.61 seconds
Started Dec 31 12:27:18 PM PST 23
Finished Dec 31 12:27:23 PM PST 23
Peak memory 197840 kb
Host smart-2e869fcb-c27a-4d3f-8f37-be5e83bb0253
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889901826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.889901826
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.809059672
Short name T820
Test name
Test status
Simulation time 170696144 ps
CPU time 0.88 seconds
Started Dec 31 12:26:25 PM PST 23
Finished Dec 31 12:26:27 PM PST 23
Peak memory 197004 kb
Host smart-103427fa-e17f-43bc-8ca7-48a88be60ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809059672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.809059672
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2419592152
Short name T858
Test name
Test status
Simulation time 195460600 ps
CPU time 1.04 seconds
Started Dec 31 12:28:16 PM PST 23
Finished Dec 31 12:28:19 PM PST 23
Peak memory 195668 kb
Host smart-1dfbeb5b-bb8b-4d22-874d-8fb0ef01fb92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419592152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2419592152
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1134339789
Short name T430
Test name
Test status
Simulation time 5483236736 ps
CPU time 129.94 seconds
Started Dec 31 12:27:51 PM PST 23
Finished Dec 31 12:30:03 PM PST 23
Peak memory 197976 kb
Host smart-48725661-013a-45c7-b895-30f2b9781d1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134339789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1134339789
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2383183499
Short name T466
Test name
Test status
Simulation time 161171934217 ps
CPU time 980.39 seconds
Started Dec 31 12:26:03 PM PST 23
Finished Dec 31 12:42:29 PM PST 23
Peak memory 198180 kb
Host smart-db847fc2-8a99-493e-ac11-92d12f3bf1a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2383183499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2383183499
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3695280067
Short name T680
Test name
Test status
Simulation time 12301386 ps
CPU time 0.55 seconds
Started Dec 31 12:25:05 PM PST 23
Finished Dec 31 12:25:09 PM PST 23
Peak memory 193748 kb
Host smart-3fa69e86-554d-465d-816f-41d7d3a3c5d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695280067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3695280067
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3631767081
Short name T734
Test name
Test status
Simulation time 159096024 ps
CPU time 0.74 seconds
Started Dec 31 12:24:49 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 194616 kb
Host smart-6062115b-edd4-4dba-97a2-c0f9aa969c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631767081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3631767081
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3259750481
Short name T248
Test name
Test status
Simulation time 1204790810 ps
CPU time 16.12 seconds
Started Dec 31 12:23:55 PM PST 23
Finished Dec 31 12:24:17 PM PST 23
Peak memory 197040 kb
Host smart-475b6ada-473b-44c2-9e01-ad2bb3ede3cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259750481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3259750481
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3559820833
Short name T779
Test name
Test status
Simulation time 63841023 ps
CPU time 0.74 seconds
Started Dec 31 12:23:25 PM PST 23
Finished Dec 31 12:23:27 PM PST 23
Peak memory 194300 kb
Host smart-a15db517-cfb6-483d-8f8e-ed9d96688f82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559820833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3559820833
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.4031654056
Short name T249
Test name
Test status
Simulation time 32219746 ps
CPU time 0.77 seconds
Started Dec 31 12:22:52 PM PST 23
Finished Dec 31 12:22:53 PM PST 23
Peak memory 194532 kb
Host smart-c99f2a47-184f-4ea8-8d97-29227ab1d2a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031654056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.4031654056
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4236206547
Short name T333
Test name
Test status
Simulation time 53267946 ps
CPU time 2.12 seconds
Started Dec 31 12:20:45 PM PST 23
Finished Dec 31 12:20:48 PM PST 23
Peak memory 198000 kb
Host smart-bd185ccb-5558-4cc8-9996-a2e61181adf5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236206547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.4236206547
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3681406076
Short name T372
Test name
Test status
Simulation time 665963419 ps
CPU time 2.46 seconds
Started Dec 31 12:24:32 PM PST 23
Finished Dec 31 12:24:41 PM PST 23
Peak memory 196176 kb
Host smart-4c503625-31df-4512-87b1-6652a075ed7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681406076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3681406076
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1721367632
Short name T723
Test name
Test status
Simulation time 16432419 ps
CPU time 0.7 seconds
Started Dec 31 12:25:50 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 195180 kb
Host smart-df1c6961-6ccc-446d-86ff-e7081bba2886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721367632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1721367632
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1268793236
Short name T517
Test name
Test status
Simulation time 220556640 ps
CPU time 1.15 seconds
Started Dec 31 12:27:34 PM PST 23
Finished Dec 31 12:27:37 PM PST 23
Peak memory 195796 kb
Host smart-098521f1-d338-4b17-a02d-3ec8fcae12d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268793236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1268793236
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1704310104
Short name T455
Test name
Test status
Simulation time 277010950 ps
CPU time 1.45 seconds
Started Dec 31 12:24:18 PM PST 23
Finished Dec 31 12:24:21 PM PST 23
Peak memory 197928 kb
Host smart-85e4eae0-67f3-4b76-b240-80a5e49a0813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704310104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1704310104
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.4205196195
Short name T344
Test name
Test status
Simulation time 74491061 ps
CPU time 1.06 seconds
Started Dec 31 12:24:24 PM PST 23
Finished Dec 31 12:24:29 PM PST 23
Peak memory 197024 kb
Host smart-d1ea3cdf-8ebf-4f5a-9422-b7834c7e8b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205196195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.4205196195
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1585170643
Short name T244
Test name
Test status
Simulation time 199836052 ps
CPU time 1.03 seconds
Started Dec 31 12:24:20 PM PST 23
Finished Dec 31 12:24:25 PM PST 23
Peak memory 195828 kb
Host smart-c4075e08-b956-40af-b254-1c130a6bac4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585170643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1585170643
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2603492052
Short name T540
Test name
Test status
Simulation time 85831497696 ps
CPU time 194.61 seconds
Started Dec 31 12:26:33 PM PST 23
Finished Dec 31 12:29:50 PM PST 23
Peak memory 197924 kb
Host smart-01f0f9f4-a9ab-4a5f-b460-695cefff08ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603492052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2603492052
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.3182398623
Short name T588
Test name
Test status
Simulation time 54028277295 ps
CPU time 1319.91 seconds
Started Dec 31 12:23:18 PM PST 23
Finished Dec 31 12:45:19 PM PST 23
Peak memory 197808 kb
Host smart-1a24d04b-9c18-40b6-8461-f8ec3b04cfc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3182398623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.3182398623
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3005010660
Short name T53
Test name
Test status
Simulation time 70737300 ps
CPU time 0.58 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 193844 kb
Host smart-dc2a1f63-bb3e-4c6c-a3f3-44fd988eb7a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005010660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3005010660
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1773973625
Short name T821
Test name
Test status
Simulation time 103354557 ps
CPU time 0.67 seconds
Started Dec 31 12:27:06 PM PST 23
Finished Dec 31 12:27:09 PM PST 23
Peak memory 194988 kb
Host smart-998f8b87-22a2-4fb8-9f89-189b2e56096f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773973625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1773973625
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2703968897
Short name T625
Test name
Test status
Simulation time 302253534 ps
CPU time 4.18 seconds
Started Dec 31 12:24:31 PM PST 23
Finished Dec 31 12:24:38 PM PST 23
Peak memory 195776 kb
Host smart-5bd0cb2c-958a-4144-8855-1cd983e5b8ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703968897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2703968897
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.191551242
Short name T709
Test name
Test status
Simulation time 169184283 ps
CPU time 0.82 seconds
Started Dec 31 12:23:29 PM PST 23
Finished Dec 31 12:23:32 PM PST 23
Peak memory 196008 kb
Host smart-b2c2a85e-1923-4fff-aa91-015938e51742
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191551242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.191551242
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1874785824
Short name T864
Test name
Test status
Simulation time 340911191 ps
CPU time 1.21 seconds
Started Dec 31 12:23:21 PM PST 23
Finished Dec 31 12:23:23 PM PST 23
Peak memory 195376 kb
Host smart-185ce778-784f-4f22-93e8-e79b8735377e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874785824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1874785824
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1898206953
Short name T713
Test name
Test status
Simulation time 482340547 ps
CPU time 2.25 seconds
Started Dec 31 12:27:28 PM PST 23
Finished Dec 31 12:27:31 PM PST 23
Peak memory 197956 kb
Host smart-d606c94c-8c76-417e-b421-20f16b49f07a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898206953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1898206953
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3955975053
Short name T458
Test name
Test status
Simulation time 1307740868 ps
CPU time 2.31 seconds
Started Dec 31 12:25:22 PM PST 23
Finished Dec 31 12:25:29 PM PST 23
Peak memory 196948 kb
Host smart-85e42bb5-9e81-4ef5-850d-d3004fcffccd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955975053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3955975053
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3748451784
Short name T597
Test name
Test status
Simulation time 61701662 ps
CPU time 0.75 seconds
Started Dec 31 12:24:48 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 195264 kb
Host smart-933eb123-d641-4a3c-be9d-d29d897e1a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748451784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3748451784
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.351319639
Short name T736
Test name
Test status
Simulation time 139116047 ps
CPU time 0.93 seconds
Started Dec 31 12:24:47 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 195332 kb
Host smart-860b28c2-4597-470b-bd5f-788cbeaee28a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351319639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.351319639
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2797365818
Short name T777
Test name
Test status
Simulation time 346866084 ps
CPU time 3 seconds
Started Dec 31 12:22:21 PM PST 23
Finished Dec 31 12:22:24 PM PST 23
Peak memory 197196 kb
Host smart-78003481-7fb1-4101-a2bc-78d783f0d0b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797365818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2797365818
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3722834483
Short name T691
Test name
Test status
Simulation time 120776531 ps
CPU time 1.03 seconds
Started Dec 31 12:23:38 PM PST 23
Finished Dec 31 12:23:43 PM PST 23
Peak memory 195604 kb
Host smart-d5b56332-7408-4efd-96d8-a4ee319b9706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722834483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3722834483
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1376732757
Short name T506
Test name
Test status
Simulation time 950532565 ps
CPU time 1.46 seconds
Started Dec 31 12:25:52 PM PST 23
Finished Dec 31 12:26:00 PM PST 23
Peak memory 194420 kb
Host smart-af22ee42-ab4b-4bec-b8f7-7eae4d2570a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376732757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1376732757
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2568023407
Short name T780
Test name
Test status
Simulation time 4881535047 ps
CPU time 53.92 seconds
Started Dec 31 12:20:45 PM PST 23
Finished Dec 31 12:21:40 PM PST 23
Peak memory 197984 kb
Host smart-e6e8baed-ae77-4952-be2f-50977426bc2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568023407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2568023407
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3600198113
Short name T863
Test name
Test status
Simulation time 241113001744 ps
CPU time 619.74 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:35:50 PM PST 23
Peak memory 198232 kb
Host smart-891470c8-2fef-4ae2-b4cc-71e468f427d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3600198113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3600198113
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1369895563
Short name T596
Test name
Test status
Simulation time 13648987 ps
CPU time 0.55 seconds
Started Dec 31 12:25:13 PM PST 23
Finished Dec 31 12:25:16 PM PST 23
Peak memory 193792 kb
Host smart-4550530d-1604-45f9-a016-914b7c9986c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369895563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1369895563
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1231671655
Short name T553
Test name
Test status
Simulation time 134075632 ps
CPU time 0.75 seconds
Started Dec 31 12:22:02 PM PST 23
Finished Dec 31 12:22:07 PM PST 23
Peak memory 195136 kb
Host smart-c43dc4d7-7520-4b46-90be-e3e88183b0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231671655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1231671655
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2429156487
Short name T256
Test name
Test status
Simulation time 896821900 ps
CPU time 14.73 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:36 PM PST 23
Peak memory 196848 kb
Host smart-fec583df-2a5e-4c4f-813c-6c2a4399d36a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429156487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2429156487
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1754294435
Short name T598
Test name
Test status
Simulation time 36203529 ps
CPU time 0.7 seconds
Started Dec 31 12:25:22 PM PST 23
Finished Dec 31 12:25:27 PM PST 23
Peak memory 195620 kb
Host smart-84e27531-6b23-4430-b3ac-30aaa007e203
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754294435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1754294435
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.391265027
Short name T504
Test name
Test status
Simulation time 40548971 ps
CPU time 0.76 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:31 PM PST 23
Peak memory 195196 kb
Host smart-fe91070c-7468-4288-a4c5-fe63404e288b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391265027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.391265027
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.62208404
Short name T782
Test name
Test status
Simulation time 91865996 ps
CPU time 3.41 seconds
Started Dec 31 12:24:44 PM PST 23
Finished Dec 31 12:25:01 PM PST 23
Peak memory 197164 kb
Host smart-5362de36-43e9-450f-bf28-df26ad94fcf9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62208404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.gpio_intr_with_filter_rand_intr_event.62208404
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1906757216
Short name T227
Test name
Test status
Simulation time 29871483 ps
CPU time 1.04 seconds
Started Dec 31 12:20:09 PM PST 23
Finished Dec 31 12:20:11 PM PST 23
Peak memory 196116 kb
Host smart-bfe1e7a2-4acd-4cbc-92ec-2467a316c178
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906757216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1906757216
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2482897168
Short name T349
Test name
Test status
Simulation time 233102209 ps
CPU time 1.07 seconds
Started Dec 31 12:20:57 PM PST 23
Finished Dec 31 12:20:59 PM PST 23
Peak memory 195868 kb
Host smart-2fe2461f-bb59-40ac-b129-2d0e5ac82287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482897168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2482897168
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2682672834
Short name T552
Test name
Test status
Simulation time 44493421 ps
CPU time 1.04 seconds
Started Dec 31 12:23:39 PM PST 23
Finished Dec 31 12:23:44 PM PST 23
Peak memory 196548 kb
Host smart-0465f26b-c611-4e22-be23-40d5e5e00111
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682672834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2682672834
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1664765027
Short name T825
Test name
Test status
Simulation time 701784294 ps
CPU time 2.9 seconds
Started Dec 31 12:25:55 PM PST 23
Finished Dec 31 12:26:05 PM PST 23
Peak memory 197996 kb
Host smart-cbe95730-f195-47bf-938e-1701e3e2aa43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664765027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1664765027
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1581232449
Short name T874
Test name
Test status
Simulation time 156864234 ps
CPU time 0.92 seconds
Started Dec 31 12:25:13 PM PST 23
Finished Dec 31 12:25:17 PM PST 23
Peak memory 195576 kb
Host smart-b0b501f5-3c6b-4c51-9583-1d68bc4d7acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581232449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1581232449
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1261587228
Short name T326
Test name
Test status
Simulation time 51067988 ps
CPU time 1.07 seconds
Started Dec 31 12:23:52 PM PST 23
Finished Dec 31 12:23:55 PM PST 23
Peak memory 195512 kb
Host smart-44007631-8667-45ab-b612-c12ad202de8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261587228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1261587228
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.208515112
Short name T512
Test name
Test status
Simulation time 21075570892 ps
CPU time 127.95 seconds
Started Dec 31 12:24:27 PM PST 23
Finished Dec 31 12:26:37 PM PST 23
Peak memory 197992 kb
Host smart-8105c25b-779e-4448-9b5f-599d63b4ea22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208515112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.208515112
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.4052599717
Short name T752
Test name
Test status
Simulation time 68663164121 ps
CPU time 977.87 seconds
Started Dec 31 12:25:22 PM PST 23
Finished Dec 31 12:41:44 PM PST 23
Peak memory 198208 kb
Host smart-f0558b8e-029d-41cd-9c01-6fbf706ba122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4052599717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.4052599717
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.4096133498
Short name T756
Test name
Test status
Simulation time 65335268 ps
CPU time 0.6 seconds
Started Dec 31 12:20:27 PM PST 23
Finished Dec 31 12:20:29 PM PST 23
Peak memory 194764 kb
Host smart-9e894750-87e1-40b5-bbd4-d5a32d61c162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096133498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.4096133498
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1460161457
Short name T382
Test name
Test status
Simulation time 63375938 ps
CPU time 0.66 seconds
Started Dec 31 12:22:11 PM PST 23
Finished Dec 31 12:22:12 PM PST 23
Peak memory 194772 kb
Host smart-931e7ee5-4efd-4fa4-8ea4-0c4dcb75514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460161457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1460161457
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2913221502
Short name T877
Test name
Test status
Simulation time 1016935073 ps
CPU time 12.19 seconds
Started Dec 31 12:23:18 PM PST 23
Finished Dec 31 12:23:31 PM PST 23
Peak memory 197080 kb
Host smart-b44ca975-1bce-49c0-a491-c60efaab787b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913221502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2913221502
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1818946361
Short name T818
Test name
Test status
Simulation time 51567195 ps
CPU time 0.79 seconds
Started Dec 31 12:24:55 PM PST 23
Finished Dec 31 12:25:00 PM PST 23
Peak memory 196632 kb
Host smart-0a00a7a9-285c-48dc-859b-928b35c9613a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818946361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1818946361
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.682564375
Short name T601
Test name
Test status
Simulation time 489635640 ps
CPU time 0.88 seconds
Started Dec 31 12:28:35 PM PST 23
Finished Dec 31 12:28:44 PM PST 23
Peak memory 195952 kb
Host smart-5c512b3f-44eb-46ca-99ae-bd69e6cdf47c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682564375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.682564375
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3379412142
Short name T47
Test name
Test status
Simulation time 28386380 ps
CPU time 1.12 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:22:59 PM PST 23
Peak memory 196124 kb
Host smart-97e47705-8b1e-4dcb-b9db-d789802f2d76
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379412142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3379412142
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2979833790
Short name T675
Test name
Test status
Simulation time 394426192 ps
CPU time 1.96 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:24:28 PM PST 23
Peak memory 195704 kb
Host smart-38f5aac4-d8bd-483b-8ec8-01fb9b70248d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979833790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2979833790
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1446898
Short name T546
Test name
Test status
Simulation time 227636204 ps
CPU time 1.24 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 197508 kb
Host smart-048f8a1f-6a88-4eab-a5a2-f7ad8f3ae1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1446898
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3470634541
Short name T258
Test name
Test status
Simulation time 106468976 ps
CPU time 1.24 seconds
Started Dec 31 12:24:08 PM PST 23
Finished Dec 31 12:24:15 PM PST 23
Peak memory 197916 kb
Host smart-4eadd475-4ea5-4b04-93f6-b3fb8b45cc1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470634541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3470634541
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1171159585
Short name T282
Test name
Test status
Simulation time 1714447596 ps
CPU time 4.51 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:23:03 PM PST 23
Peak memory 197696 kb
Host smart-4febbe93-b0ae-413d-a143-218a888bde47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171159585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1171159585
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3844330521
Short name T440
Test name
Test status
Simulation time 118317434 ps
CPU time 0.88 seconds
Started Dec 31 12:34:30 PM PST 23
Finished Dec 31 12:34:32 PM PST 23
Peak memory 195448 kb
Host smart-d50fdb1b-2668-432e-b3a3-6c5a79a1e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844330521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3844330521
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.345506948
Short name T700
Test name
Test status
Simulation time 40953758 ps
CPU time 1.22 seconds
Started Dec 31 12:18:29 PM PST 23
Finished Dec 31 12:18:31 PM PST 23
Peak memory 196264 kb
Host smart-b3735b39-c8b3-45e0-99a4-33eaf632e2c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345506948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.345506948
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2024315420
Short name T794
Test name
Test status
Simulation time 15801467364 ps
CPU time 103.48 seconds
Started Dec 31 12:26:08 PM PST 23
Finished Dec 31 12:27:57 PM PST 23
Peak memory 197652 kb
Host smart-576ba50c-b035-4894-96bb-cc9fc27ef71a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024315420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2024315420
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2503068970
Short name T888
Test name
Test status
Simulation time 148753377158 ps
CPU time 537.41 seconds
Started Dec 31 12:26:59 PM PST 23
Finished Dec 31 12:35:59 PM PST 23
Peak memory 206364 kb
Host smart-ffee255e-926b-4fae-8f16-5d39aa4eeb62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2503068970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2503068970
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3143045633
Short name T696
Test name
Test status
Simulation time 97230452 ps
CPU time 0.6 seconds
Started Dec 31 12:23:58 PM PST 23
Finished Dec 31 12:24:04 PM PST 23
Peak memory 193876 kb
Host smart-22514037-7ba3-4f55-8ea1-217b052e1e9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143045633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3143045633
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3743042127
Short name T270
Test name
Test status
Simulation time 219005708 ps
CPU time 0.65 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:31 PM PST 23
Peak memory 195012 kb
Host smart-65a9f07a-b388-4e44-90cd-ea5b9292ce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743042127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3743042127
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3034002826
Short name T503
Test name
Test status
Simulation time 458807314 ps
CPU time 14.87 seconds
Started Dec 31 12:24:03 PM PST 23
Finished Dec 31 12:24:25 PM PST 23
Peak memory 197924 kb
Host smart-7777a0dc-6281-4eaf-ab3e-8ffca7b0c06a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034002826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3034002826
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.4185306493
Short name T310
Test name
Test status
Simulation time 636774947 ps
CPU time 1.01 seconds
Started Dec 31 12:26:14 PM PST 23
Finished Dec 31 12:26:18 PM PST 23
Peak memory 196668 kb
Host smart-2dfae2f4-3cb8-480b-b2fc-88bbb7ab7fad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185306493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.4185306493
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1677193489
Short name T400
Test name
Test status
Simulation time 27221725 ps
CPU time 0.9 seconds
Started Dec 31 12:19:33 PM PST 23
Finished Dec 31 12:19:34 PM PST 23
Peak memory 197280 kb
Host smart-07bba72f-c2de-4068-bc70-190b72200f65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677193489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1677193489
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.594629906
Short name T469
Test name
Test status
Simulation time 28142397 ps
CPU time 1.16 seconds
Started Dec 31 12:23:54 PM PST 23
Finished Dec 31 12:24:01 PM PST 23
Peak memory 197360 kb
Host smart-d1257633-9eb8-4a9a-bbda-4b1b21e55c1e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594629906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.594629906
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1106925206
Short name T353
Test name
Test status
Simulation time 27746792 ps
CPU time 0.82 seconds
Started Dec 31 12:23:58 PM PST 23
Finished Dec 31 12:24:04 PM PST 23
Peak memory 194308 kb
Host smart-01f664d8-2262-4219-8745-8cd38bb7e07d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106925206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1106925206
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1190281450
Short name T308
Test name
Test status
Simulation time 16569477 ps
CPU time 0.66 seconds
Started Dec 31 12:26:05 PM PST 23
Finished Dec 31 12:26:11 PM PST 23
Peak memory 194244 kb
Host smart-33e38d08-16c8-4199-8213-fa9b0215f5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190281450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1190281450
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2327673727
Short name T829
Test name
Test status
Simulation time 104671108 ps
CPU time 1.04 seconds
Started Dec 31 12:24:54 PM PST 23
Finished Dec 31 12:25:00 PM PST 23
Peak memory 196548 kb
Host smart-576e5d4d-0c5a-4571-b287-2484e4a24bf6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327673727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2327673727
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1977026983
Short name T448
Test name
Test status
Simulation time 532380876 ps
CPU time 3.32 seconds
Started Dec 31 12:24:29 PM PST 23
Finished Dec 31 12:24:35 PM PST 23
Peak memory 197576 kb
Host smart-7404562f-62ca-4621-b071-95530809e7e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977026983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1977026983
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2491343567
Short name T548
Test name
Test status
Simulation time 53160892 ps
CPU time 1.01 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 12:27:19 PM PST 23
Peak memory 196496 kb
Host smart-89883acb-e813-475f-b247-a3d5aed68edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491343567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2491343567
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3295870009
Short name T471
Test name
Test status
Simulation time 539053514 ps
CPU time 1.39 seconds
Started Dec 31 12:23:58 PM PST 23
Finished Dec 31 12:24:04 PM PST 23
Peak memory 197924 kb
Host smart-024b0fde-9e78-4e0c-81f5-15700c74e8fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295870009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3295870009
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2999118748
Short name T801
Test name
Test status
Simulation time 6713236132 ps
CPU time 90.88 seconds
Started Dec 31 12:23:58 PM PST 23
Finished Dec 31 12:25:34 PM PST 23
Peak memory 198032 kb
Host smart-57a7ab19-a439-4076-a60c-bdf5cf230b21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999118748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2999118748
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.337962585
Short name T433
Test name
Test status
Simulation time 181730713228 ps
CPU time 2260.22 seconds
Started Dec 31 12:25:42 PM PST 23
Finished Dec 31 01:03:31 PM PST 23
Peak memory 198144 kb
Host smart-327b00cf-0e24-4160-a729-b49b22abb09e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=337962585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.337962585
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2103166167
Short name T149
Test name
Test status
Simulation time 60151711 ps
CPU time 1.09 seconds
Started Dec 31 12:26:28 PM PST 23
Finished Dec 31 12:26:30 PM PST 23
Peak memory 195908 kb
Host smart-0ca3ea22-e841-4b0e-bdc9-3382de30d392
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2103166167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2103166167
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2634679212
Short name T206
Test name
Test status
Simulation time 143225530 ps
CPU time 1.36 seconds
Started Dec 31 12:24:36 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 197512 kb
Host smart-9efa27fa-9505-4a81-b83c-80d7e33f4d33
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634679212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2634679212
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1184928131
Short name T198
Test name
Test status
Simulation time 69660337 ps
CPU time 0.81 seconds
Started Dec 31 12:26:31 PM PST 23
Finished Dec 31 12:26:34 PM PST 23
Peak memory 194888 kb
Host smart-b8c5467f-7e1d-43c9-99a2-400adf3a4c9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1184928131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1184928131
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4216684897
Short name T144
Test name
Test status
Simulation time 188971238 ps
CPU time 1.33 seconds
Started Dec 31 12:26:35 PM PST 23
Finished Dec 31 12:26:39 PM PST 23
Peak memory 196456 kb
Host smart-40e85a1b-c704-4a27-84d9-ba0eeb0d5220
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216684897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4216684897
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1991778605
Short name T196
Test name
Test status
Simulation time 254517809 ps
CPU time 1.19 seconds
Started Dec 31 12:24:27 PM PST 23
Finished Dec 31 12:24:30 PM PST 23
Peak memory 195416 kb
Host smart-a725cc4c-289e-4e5b-b7ec-ea7ee72c415c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1991778605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1991778605
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.226701476
Short name T177
Test name
Test status
Simulation time 50194855 ps
CPU time 1.18 seconds
Started Dec 31 12:24:05 PM PST 23
Finished Dec 31 12:24:12 PM PST 23
Peak memory 195196 kb
Host smart-5fd2c1dd-20db-4748-8b81-accd6a4ad961
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226701476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.226701476
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2679391872
Short name T184
Test name
Test status
Simulation time 457078258 ps
CPU time 1 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 196164 kb
Host smart-762863f5-0fa9-476d-b53d-d73af3758ba5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2679391872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2679391872
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2378287807
Short name T159
Test name
Test status
Simulation time 67969042 ps
CPU time 1.25 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 197604 kb
Host smart-f5cec90e-fce8-47bc-9293-16e5337d0dc4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378287807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2378287807
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1134722063
Short name T165
Test name
Test status
Simulation time 309318360 ps
CPU time 0.95 seconds
Started Dec 31 12:25:09 PM PST 23
Finished Dec 31 12:25:13 PM PST 23
Peak memory 195856 kb
Host smart-0449f0c0-2aac-424b-adfa-18423a3d68fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1134722063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1134722063
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3837571098
Short name T202
Test name
Test status
Simulation time 454386164 ps
CPU time 1.07 seconds
Started Dec 31 12:19:29 PM PST 23
Finished Dec 31 12:19:30 PM PST 23
Peak memory 195232 kb
Host smart-b2c0fb0a-7d4e-44f7-857b-7a7592bc9417
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837571098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3837571098
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.210495525
Short name T62
Test name
Test status
Simulation time 106598124 ps
CPU time 0.84 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:45 PM PST 23
Peak memory 195164 kb
Host smart-55e8d7f9-96f8-4448-92a7-9cda132ca72e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=210495525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.210495525
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2521328138
Short name T170
Test name
Test status
Simulation time 61386912 ps
CPU time 1.01 seconds
Started Dec 31 12:24:42 PM PST 23
Finished Dec 31 12:24:52 PM PST 23
Peak memory 195160 kb
Host smart-919bd8c8-d021-4aa3-a71e-e97562dc82b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521328138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2521328138
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.86772630
Short name T131
Test name
Test status
Simulation time 93138159 ps
CPU time 0.92 seconds
Started Dec 31 12:24:12 PM PST 23
Finished Dec 31 12:24:16 PM PST 23
Peak memory 194412 kb
Host smart-cd768737-e78b-4594-8f67-47aa68966661
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86772630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.86772630
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1883828264
Short name T209
Test name
Test status
Simulation time 50603517 ps
CPU time 1.29 seconds
Started Dec 31 12:24:18 PM PST 23
Finished Dec 31 12:24:22 PM PST 23
Peak memory 195052 kb
Host smart-5dd3d518-e633-473b-ba36-d32083ea8a6e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1883828264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1883828264
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2738152363
Short name T212
Test name
Test status
Simulation time 44882885 ps
CPU time 0.87 seconds
Started Dec 31 12:24:50 PM PST 23
Finished Dec 31 12:24:55 PM PST 23
Peak memory 195540 kb
Host smart-bb24ef21-88d2-446b-8ce7-6d5e113860cd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738152363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2738152363
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3276054532
Short name T155
Test name
Test status
Simulation time 207120057 ps
CPU time 1.05 seconds
Started Dec 31 12:24:14 PM PST 23
Finished Dec 31 12:24:18 PM PST 23
Peak memory 194592 kb
Host smart-e58d664f-3394-46f0-9de6-d7da921915ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3276054532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3276054532
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1106474479
Short name T63
Test name
Test status
Simulation time 50065922 ps
CPU time 1.47 seconds
Started Dec 31 12:20:17 PM PST 23
Finished Dec 31 12:20:19 PM PST 23
Peak memory 197464 kb
Host smart-0aee8349-049d-4abc-89f1-7aecf68e2a9f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106474479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1106474479
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1460789096
Short name T142
Test name
Test status
Simulation time 183178349 ps
CPU time 0.95 seconds
Started Dec 31 12:24:33 PM PST 23
Finished Dec 31 12:24:42 PM PST 23
Peak memory 196044 kb
Host smart-9d7faf6a-fd46-47a5-a0d7-41214ef493bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1460789096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1460789096
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.696122087
Short name T157
Test name
Test status
Simulation time 258698314 ps
CPU time 1.2 seconds
Started Dec 31 12:24:13 PM PST 23
Finished Dec 31 12:24:17 PM PST 23
Peak memory 197356 kb
Host smart-5a7682e2-2560-47f3-88b0-cfcd242ec765
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696122087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.696122087
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2519387582
Short name T185
Test name
Test status
Simulation time 118344097 ps
CPU time 1.13 seconds
Started Dec 31 12:19:49 PM PST 23
Finished Dec 31 12:19:54 PM PST 23
Peak memory 195148 kb
Host smart-8bdf1a52-ccaf-4ae0-aa84-0b434c56fc53
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2519387582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2519387582
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.423250538
Short name T189
Test name
Test status
Simulation time 268528470 ps
CPU time 1.15 seconds
Started Dec 31 12:24:37 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 195380 kb
Host smart-ff077351-e91b-484f-b5d5-864c12caf6cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423250538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.423250538
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.70916973
Short name T146
Test name
Test status
Simulation time 564420390 ps
CPU time 0.92 seconds
Started Dec 31 12:24:15 PM PST 23
Finished Dec 31 12:24:19 PM PST 23
Peak memory 196076 kb
Host smart-781296b7-2105-4452-9981-e3ab66f4b4bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=70916973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.70916973
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3666618404
Short name T60
Test name
Test status
Simulation time 27518611 ps
CPU time 0.94 seconds
Started Dec 31 12:24:18 PM PST 23
Finished Dec 31 12:24:22 PM PST 23
Peak memory 196128 kb
Host smart-05ae12e1-75cc-4552-b64f-083495798e9d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666618404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3666618404
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1945380010
Short name T211
Test name
Test status
Simulation time 184967386 ps
CPU time 1.24 seconds
Started Dec 31 12:24:36 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 196372 kb
Host smart-b404aac6-ffe4-4fd4-bc60-260c1e1beffd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1945380010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1945380010
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2584180271
Short name T186
Test name
Test status
Simulation time 899246746 ps
CPU time 1.42 seconds
Started Dec 31 12:24:36 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 196296 kb
Host smart-3e0fe0a8-a73a-4e9b-a7d4-c41a2da83211
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584180271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2584180271
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.246346240
Short name T169
Test name
Test status
Simulation time 188460686 ps
CPU time 1.49 seconds
Started Dec 31 12:24:14 PM PST 23
Finished Dec 31 12:24:19 PM PST 23
Peak memory 195228 kb
Host smart-40a17cb0-10c5-41c4-ac83-dca19c496702
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=246346240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.246346240
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.406065749
Short name T215
Test name
Test status
Simulation time 52025901 ps
CPU time 1.15 seconds
Started Dec 31 12:24:21 PM PST 23
Finished Dec 31 12:24:26 PM PST 23
Peak memory 196104 kb
Host smart-39ff9965-b60b-4840-af31-1b53c6c8a6dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406065749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.406065749
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1534141186
Short name T113
Test name
Test status
Simulation time 329333346 ps
CPU time 1.36 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 196308 kb
Host smart-fdf12fd6-4b01-4440-b25d-5b45d21b1be2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1534141186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1534141186
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2183681286
Short name T204
Test name
Test status
Simulation time 620288897 ps
CPU time 1.42 seconds
Started Dec 31 12:23:41 PM PST 23
Finished Dec 31 12:23:45 PM PST 23
Peak memory 196388 kb
Host smart-4d7bec4e-b1f0-4235-89e3-9c3b836d8f4f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183681286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2183681286
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4054428975
Short name T163
Test name
Test status
Simulation time 288669091 ps
CPU time 0.76 seconds
Started Dec 31 12:24:40 PM PST 23
Finished Dec 31 12:24:47 PM PST 23
Peak memory 194920 kb
Host smart-e7e159e3-a3c8-474a-8a08-81ffb27feb93
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4054428975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.4054428975
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.998234468
Short name T162
Test name
Test status
Simulation time 145502120 ps
CPU time 1.24 seconds
Started Dec 31 12:24:36 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 195992 kb
Host smart-2698e615-1810-459c-a1dd-3c8831934827
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998234468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.998234468
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.995851823
Short name T58
Test name
Test status
Simulation time 134981186 ps
CPU time 1.12 seconds
Started Dec 31 12:24:21 PM PST 23
Finished Dec 31 12:24:26 PM PST 23
Peak memory 193888 kb
Host smart-c17972a0-4a71-4c86-950e-5143b64818f9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=995851823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.995851823
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.255247317
Short name T168
Test name
Test status
Simulation time 49968308 ps
CPU time 1.35 seconds
Started Dec 31 12:24:12 PM PST 23
Finished Dec 31 12:24:17 PM PST 23
Peak memory 194972 kb
Host smart-473c820b-b087-40d8-ba7b-a0c6a749c619
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255247317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.255247317
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1475618227
Short name T130
Test name
Test status
Simulation time 63504058 ps
CPU time 1.26 seconds
Started Dec 31 12:24:36 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 196048 kb
Host smart-c4f94b59-bcaa-4431-b3ce-6a44ced317dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1475618227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1475618227
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1171135504
Short name T188
Test name
Test status
Simulation time 72786336 ps
CPU time 0.77 seconds
Started Dec 31 12:25:36 PM PST 23
Finished Dec 31 12:25:45 PM PST 23
Peak memory 194068 kb
Host smart-953bd995-90f3-4f90-af61-4b04f5778120
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171135504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1171135504
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.490958836
Short name T179
Test name
Test status
Simulation time 146181830 ps
CPU time 1.56 seconds
Started Dec 31 12:19:08 PM PST 23
Finished Dec 31 12:19:10 PM PST 23
Peak memory 197900 kb
Host smart-ee327f72-df87-43b1-8368-d56fb9283053
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=490958836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.490958836
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2439103293
Short name T193
Test name
Test status
Simulation time 209721162 ps
CPU time 1.05 seconds
Started Dec 31 12:25:51 PM PST 23
Finished Dec 31 12:25:59 PM PST 23
Peak memory 195884 kb
Host smart-31f1f18d-6290-4b1f-b206-090d44a7835d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439103293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2439103293
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3382445372
Short name T151
Test name
Test status
Simulation time 194851200 ps
CPU time 1.05 seconds
Started Dec 31 12:24:36 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 197060 kb
Host smart-17ef04a3-e522-425a-ba4b-1011215ac197
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3382445372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3382445372
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.404005508
Short name T133
Test name
Test status
Simulation time 41164026 ps
CPU time 1.05 seconds
Started Dec 31 12:26:05 PM PST 23
Finished Dec 31 12:26:11 PM PST 23
Peak memory 196220 kb
Host smart-fb2b0575-8e7b-4a4a-9385-7fb56e844ae0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404005508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.404005508
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3303865478
Short name T161
Test name
Test status
Simulation time 33689766 ps
CPU time 0.96 seconds
Started Dec 31 12:21:16 PM PST 23
Finished Dec 31 12:21:18 PM PST 23
Peak memory 196028 kb
Host smart-062e1a26-e650-48c2-8e86-5655ab896746
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3303865478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3303865478
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3796015196
Short name T44
Test name
Test status
Simulation time 131153545 ps
CPU time 1.21 seconds
Started Dec 31 12:22:40 PM PST 23
Finished Dec 31 12:22:42 PM PST 23
Peak memory 195436 kb
Host smart-52402b0e-c844-4c82-b7a1-8ed23d6c0f6f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796015196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3796015196
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.962579492
Short name T150
Test name
Test status
Simulation time 215962862 ps
CPU time 1.4 seconds
Started Dec 31 12:24:50 PM PST 23
Finished Dec 31 12:24:56 PM PST 23
Peak memory 195252 kb
Host smart-0d38945d-7c03-4f12-ab51-36a8d6165776
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=962579492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.962579492
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1088626567
Short name T61
Test name
Test status
Simulation time 434836823 ps
CPU time 1.21 seconds
Started Dec 31 12:26:41 PM PST 23
Finished Dec 31 12:26:44 PM PST 23
Peak memory 197552 kb
Host smart-41329aee-52bb-42e9-8648-ccdc2feaf034
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088626567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1088626567
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.425349107
Short name T153
Test name
Test status
Simulation time 139984036 ps
CPU time 0.81 seconds
Started Dec 31 12:28:10 PM PST 23
Finished Dec 31 12:28:14 PM PST 23
Peak memory 195784 kb
Host smart-41a59487-5e34-4bef-85f9-22812afbe7cf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=425349107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.425349107
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3101681926
Short name T135
Test name
Test status
Simulation time 28601024 ps
CPU time 0.71 seconds
Started Dec 31 12:23:09 PM PST 23
Finished Dec 31 12:23:11 PM PST 23
Peak memory 193976 kb
Host smart-1fb28784-8948-47e7-baf1-13306f30531b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101681926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3101681926
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.4244039615
Short name T191
Test name
Test status
Simulation time 65743283 ps
CPU time 1.27 seconds
Started Dec 31 12:18:09 PM PST 23
Finished Dec 31 12:18:11 PM PST 23
Peak memory 197996 kb
Host smart-c5d67405-5a15-4d42-99c8-b4414e39c247
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4244039615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.4244039615
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1628312455
Short name T175
Test name
Test status
Simulation time 45966917 ps
CPU time 1.04 seconds
Started Dec 31 12:24:46 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 194396 kb
Host smart-8ce94643-d395-4682-aac7-88752df9e715
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628312455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1628312455
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3446201700
Short name T136
Test name
Test status
Simulation time 45240076 ps
CPU time 0.76 seconds
Started Dec 31 12:21:41 PM PST 23
Finished Dec 31 12:21:42 PM PST 23
Peak memory 196048 kb
Host smart-7756351c-0696-4ed7-93d0-2f6cfc94e480
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3446201700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3446201700
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2980536591
Short name T199
Test name
Test status
Simulation time 189318804 ps
CPU time 1.08 seconds
Started Dec 31 12:22:37 PM PST 23
Finished Dec 31 12:22:39 PM PST 23
Peak memory 196556 kb
Host smart-990d7d89-1c85-4bcf-b359-78b62f6e5936
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980536591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2980536591
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.895409850
Short name T190
Test name
Test status
Simulation time 50220978 ps
CPU time 0.94 seconds
Started Dec 31 12:19:49 PM PST 23
Finished Dec 31 12:19:54 PM PST 23
Peak memory 195312 kb
Host smart-9b25f9b5-4bb6-4127-b1f6-e7d76a556aca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=895409850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.895409850
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1675252126
Short name T134
Test name
Test status
Simulation time 80088740 ps
CPU time 1.14 seconds
Started Dec 31 12:26:06 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 195436 kb
Host smart-a3d6a2eb-6879-4c1c-bb3e-413dc7c82c62
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675252126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1675252126
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.544124383
Short name T145
Test name
Test status
Simulation time 46961586 ps
CPU time 1.24 seconds
Started Dec 31 12:23:10 PM PST 23
Finished Dec 31 12:23:13 PM PST 23
Peak memory 196204 kb
Host smart-14fbe38d-029b-471b-b327-ec5b784bfded
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=544124383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.544124383
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1939566793
Short name T178
Test name
Test status
Simulation time 71088531 ps
CPU time 0.76 seconds
Started Dec 31 12:24:15 PM PST 23
Finished Dec 31 12:24:18 PM PST 23
Peak memory 194732 kb
Host smart-ab610bd1-f38a-401b-bc7d-85db8ed9611f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939566793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1939566793
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1660775704
Short name T173
Test name
Test status
Simulation time 112569339 ps
CPU time 1.13 seconds
Started Dec 31 12:24:14 PM PST 23
Finished Dec 31 12:24:18 PM PST 23
Peak memory 194452 kb
Host smart-03f8acff-d204-46e1-a948-14538fdff5e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1660775704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1660775704
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1946088021
Short name T210
Test name
Test status
Simulation time 58704984 ps
CPU time 0.95 seconds
Started Dec 31 12:24:15 PM PST 23
Finished Dec 31 12:24:18 PM PST 23
Peak memory 195872 kb
Host smart-cb4d91d9-4420-49fb-943d-a9c9414827fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946088021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1946088021
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1677183236
Short name T205
Test name
Test status
Simulation time 59549181 ps
CPU time 1.18 seconds
Started Dec 31 12:23:07 PM PST 23
Finished Dec 31 12:23:09 PM PST 23
Peak memory 195336 kb
Host smart-8090803c-32ee-4548-a0b0-42ecef44b56e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1677183236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1677183236
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.152141921
Short name T152
Test name
Test status
Simulation time 511269552 ps
CPU time 1.29 seconds
Started Dec 31 12:20:06 PM PST 23
Finished Dec 31 12:20:08 PM PST 23
Peak memory 197552 kb
Host smart-7d9be2ca-aaf9-495c-9ad6-65017e023da2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152141921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.152141921
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1409710414
Short name T181
Test name
Test status
Simulation time 104319083 ps
CPU time 0.85 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:03 PM PST 23
Peak memory 195764 kb
Host smart-4c2f8363-124d-462a-991a-193a1c434457
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1409710414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1409710414
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1774724685
Short name T167
Test name
Test status
Simulation time 142623928 ps
CPU time 0.87 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 196200 kb
Host smart-e3e6379e-1f2a-4eba-bcf2-76620ed9cca8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774724685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1774724685
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2431347342
Short name T182
Test name
Test status
Simulation time 490551777 ps
CPU time 1.08 seconds
Started Dec 31 12:24:16 PM PST 23
Finished Dec 31 12:24:20 PM PST 23
Peak memory 195728 kb
Host smart-5c1eddcd-f73d-48e1-b853-1d3029f6d104
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2431347342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2431347342
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4250913530
Short name T183
Test name
Test status
Simulation time 37691449 ps
CPU time 1.05 seconds
Started Dec 31 12:22:55 PM PST 23
Finished Dec 31 12:22:58 PM PST 23
Peak memory 197524 kb
Host smart-eafbaf26-a7fd-464a-83a8-d205ebfed843
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250913530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4250913530
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1258870024
Short name T154
Test name
Test status
Simulation time 98917347 ps
CPU time 1.12 seconds
Started Dec 31 12:25:16 PM PST 23
Finished Dec 31 12:25:20 PM PST 23
Peak memory 197484 kb
Host smart-d0551062-955d-4120-b1ab-88e7424119ac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1258870024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1258870024
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2038838157
Short name T201
Test name
Test status
Simulation time 29765925 ps
CPU time 0.85 seconds
Started Dec 31 12:24:20 PM PST 23
Finished Dec 31 12:24:24 PM PST 23
Peak memory 195708 kb
Host smart-87c3f46e-bcf7-49b4-bc13-436b7853cbaf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038838157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2038838157
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1557720802
Short name T148
Test name
Test status
Simulation time 268694187 ps
CPU time 1.38 seconds
Started Dec 31 12:18:07 PM PST 23
Finished Dec 31 12:18:09 PM PST 23
Peak memory 197872 kb
Host smart-2a01a0de-0b9b-4a7b-93aa-133cb3c7e689
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1557720802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1557720802
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.31743413
Short name T207
Test name
Test status
Simulation time 564257786 ps
CPU time 1.01 seconds
Started Dec 31 12:28:16 PM PST 23
Finished Dec 31 12:28:19 PM PST 23
Peak memory 196088 kb
Host smart-73e3d249-15eb-438c-bbe0-7f36df31dfa9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31743413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.31743413
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3302820366
Short name T200
Test name
Test status
Simulation time 113235878 ps
CPU time 0.98 seconds
Started Dec 31 12:22:54 PM PST 23
Finished Dec 31 12:22:56 PM PST 23
Peak memory 196008 kb
Host smart-21e95ae5-6a26-40b5-a486-db9d8ea495f3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3302820366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3302820366
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4282463723
Short name T129
Test name
Test status
Simulation time 110788401 ps
CPU time 1.33 seconds
Started Dec 31 12:22:54 PM PST 23
Finished Dec 31 12:22:56 PM PST 23
Peak memory 197520 kb
Host smart-8e214659-4563-4ecf-9483-4641b9373ddb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282463723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4282463723
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2914264010
Short name T160
Test name
Test status
Simulation time 176387093 ps
CPU time 1.14 seconds
Started Dec 31 12:24:46 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 195852 kb
Host smart-db06ef66-c79c-4724-819d-39ff0c70bee4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2914264010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2914264010
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4234782385
Short name T194
Test name
Test status
Simulation time 37625832 ps
CPU time 1.04 seconds
Started Dec 31 12:21:07 PM PST 23
Finished Dec 31 12:21:08 PM PST 23
Peak memory 195592 kb
Host smart-f3990f85-2194-477d-a765-d6c8c6655a25
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234782385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4234782385
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3848275432
Short name T59
Test name
Test status
Simulation time 223535196 ps
CPU time 1.26 seconds
Started Dec 31 12:18:44 PM PST 23
Finished Dec 31 12:18:46 PM PST 23
Peak memory 196020 kb
Host smart-f4832609-0bf8-4ad9-b862-fd1445694a1e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848275432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3848275432
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2559720313
Short name T213
Test name
Test status
Simulation time 49804454 ps
CPU time 1.2 seconds
Started Dec 31 12:26:20 PM PST 23
Finished Dec 31 12:26:22 PM PST 23
Peak memory 196424 kb
Host smart-abb3a6be-bd9b-4658-8b03-0c336bb53a35
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2559720313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2559720313
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.336761429
Short name T132
Test name
Test status
Simulation time 60971807 ps
CPU time 1.24 seconds
Started Dec 31 12:24:08 PM PST 23
Finished Dec 31 12:24:15 PM PST 23
Peak memory 196044 kb
Host smart-fec0a1ca-7e47-46f6-9776-8603477c7c01
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336761429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.336761429
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2084650033
Short name T64
Test name
Test status
Simulation time 68357488 ps
CPU time 0.85 seconds
Started Dec 31 12:24:07 PM PST 23
Finished Dec 31 12:24:14 PM PST 23
Peak memory 195136 kb
Host smart-0a680e1e-0fcb-4733-929a-bf935cd46309
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2084650033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2084650033
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2031346113
Short name T203
Test name
Test status
Simulation time 66902113 ps
CPU time 1.1 seconds
Started Dec 31 12:20:02 PM PST 23
Finished Dec 31 12:20:04 PM PST 23
Peak memory 197576 kb
Host smart-f354ab9e-801c-4c29-89eb-c4c2ec230266
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031346113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2031346113
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2810952062
Short name T141
Test name
Test status
Simulation time 314856873 ps
CPU time 1.29 seconds
Started Dec 31 12:25:12 PM PST 23
Finished Dec 31 12:25:22 PM PST 23
Peak memory 196072 kb
Host smart-43b958f7-5557-4c4b-ac5a-a11964d2b303
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2810952062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2810952062
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2923384092
Short name T176
Test name
Test status
Simulation time 152052128 ps
CPU time 0.97 seconds
Started Dec 31 12:18:10 PM PST 23
Finished Dec 31 12:18:12 PM PST 23
Peak memory 197848 kb
Host smart-6773035a-fe22-40ff-8b35-6db0c9764d7a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923384092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2923384092
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1963286930
Short name T112
Test name
Test status
Simulation time 539094020 ps
CPU time 1.26 seconds
Started Dec 31 12:22:55 PM PST 23
Finished Dec 31 12:22:58 PM PST 23
Peak memory 197324 kb
Host smart-656d76ea-a7eb-4f27-ae30-0ec8b289f788
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1963286930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1963286930
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3124857286
Short name T138
Test name
Test status
Simulation time 56273020 ps
CPU time 1.17 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 196532 kb
Host smart-334756e7-5f13-4af2-a6d2-9ec9ae5330e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124857286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3124857286
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2629283052
Short name T143
Test name
Test status
Simulation time 157533213 ps
CPU time 1.06 seconds
Started Dec 31 12:24:07 PM PST 23
Finished Dec 31 12:24:14 PM PST 23
Peak memory 195468 kb
Host smart-467bcf81-9cae-4dc0-b460-38a461c816b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2629283052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2629283052
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.609339519
Short name T180
Test name
Test status
Simulation time 55066556 ps
CPU time 1.06 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:25:50 PM PST 23
Peak memory 196072 kb
Host smart-08fc5eba-490b-472f-8040-00100b6882ae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609339519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.609339519
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.775185703
Short name T171
Test name
Test status
Simulation time 64988205 ps
CPU time 1.11 seconds
Started Dec 31 12:25:49 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 196820 kb
Host smart-79966161-4e22-4e31-9003-97ae72519f40
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=775185703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.775185703
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1243007938
Short name T139
Test name
Test status
Simulation time 48894410 ps
CPU time 1.21 seconds
Started Dec 31 12:27:00 PM PST 23
Finished Dec 31 12:27:03 PM PST 23
Peak memory 196476 kb
Host smart-a236fa0d-6ed6-4a50-801f-d343b08609e0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243007938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1243007938
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.984933774
Short name T197
Test name
Test status
Simulation time 65775931 ps
CPU time 1.13 seconds
Started Dec 31 12:27:00 PM PST 23
Finished Dec 31 12:27:03 PM PST 23
Peak memory 196204 kb
Host smart-32207f67-20db-440e-9027-675d56a3ba01
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=984933774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.984933774
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4084066742
Short name T214
Test name
Test status
Simulation time 400494249 ps
CPU time 0.96 seconds
Started Dec 31 12:23:24 PM PST 23
Finished Dec 31 12:23:26 PM PST 23
Peak memory 195244 kb
Host smart-53163233-9964-444d-b25c-b862a5980499
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084066742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4084066742
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1200445598
Short name T192
Test name
Test status
Simulation time 57059206 ps
CPU time 1.11 seconds
Started Dec 31 12:20:22 PM PST 23
Finished Dec 31 12:20:23 PM PST 23
Peak memory 195420 kb
Host smart-27e30179-28ac-475a-9f0e-2d9a4620126d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1200445598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1200445598
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.329444349
Short name T147
Test name
Test status
Simulation time 196104710 ps
CPU time 1.26 seconds
Started Dec 31 12:19:52 PM PST 23
Finished Dec 31 12:19:54 PM PST 23
Peak memory 196276 kb
Host smart-6a5c7c6f-10fd-489c-bc90-dd383a621117
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329444349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.329444349
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.389487984
Short name T158
Test name
Test status
Simulation time 116749267 ps
CPU time 1.1 seconds
Started Dec 31 12:27:09 PM PST 23
Finished Dec 31 12:27:12 PM PST 23
Peak memory 195932 kb
Host smart-ba669055-7836-4dac-b580-6ca6e2107741
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=389487984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.389487984
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3580967548
Short name T187
Test name
Test status
Simulation time 193401687 ps
CPU time 1.07 seconds
Started Dec 31 12:24:21 PM PST 23
Finished Dec 31 12:24:25 PM PST 23
Peak memory 196176 kb
Host smart-f13d0dec-28ae-4b92-919e-269283f97ce0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580967548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3580967548
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3554778493
Short name T137
Test name
Test status
Simulation time 118001248 ps
CPU time 1.16 seconds
Started Dec 31 12:19:06 PM PST 23
Finished Dec 31 12:19:08 PM PST 23
Peak memory 196536 kb
Host smart-e16a0aec-7658-4cea-9ee0-8e3d0fe56a9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3554778493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3554778493
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4201569122
Short name T172
Test name
Test status
Simulation time 41805998 ps
CPU time 0.97 seconds
Started Dec 31 12:24:27 PM PST 23
Finished Dec 31 12:24:30 PM PST 23
Peak memory 196016 kb
Host smart-d46e5767-c3ae-4dc5-8abe-c0f9820c88b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201569122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4201569122
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3731907570
Short name T140
Test name
Test status
Simulation time 114316425 ps
CPU time 1 seconds
Started Dec 31 12:24:46 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 195268 kb
Host smart-3e123ed3-9337-402c-a816-42ba7973fc01
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3731907570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3731907570
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4230599025
Short name T164
Test name
Test status
Simulation time 28843944 ps
CPU time 0.8 seconds
Started Dec 31 12:24:48 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 194724 kb
Host smart-b8bbec6e-efa1-4941-a914-223c5a3ac8c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230599025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4230599025
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2689187788
Short name T174
Test name
Test status
Simulation time 141541696 ps
CPU time 1.12 seconds
Started Dec 31 12:24:12 PM PST 23
Finished Dec 31 12:24:17 PM PST 23
Peak memory 194564 kb
Host smart-0f476425-2e85-415c-9fd2-11d462d821b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2689187788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2689187788
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2971998853
Short name T195
Test name
Test status
Simulation time 67153997 ps
CPU time 0.8 seconds
Started Dec 31 12:19:07 PM PST 23
Finished Dec 31 12:19:08 PM PST 23
Peak memory 195404 kb
Host smart-569bad78-c6ea-400f-a858-d66eb22e2732
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971998853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2971998853
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1137573597
Short name T208
Test name
Test status
Simulation time 21799454 ps
CPU time 0.67 seconds
Started Dec 31 12:24:48 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 192924 kb
Host smart-c1ff747e-a5f5-4bcc-b8c7-7606b7100f42
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1137573597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1137573597
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2940421286
Short name T166
Test name
Test status
Simulation time 34488425 ps
CPU time 0.94 seconds
Started Dec 31 12:24:47 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 194884 kb
Host smart-aeb7550a-7db6-4379-ba5e-d257bb9c404c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940421286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2940421286
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.416842456
Short name T156
Test name
Test status
Simulation time 81988510 ps
CPU time 1.15 seconds
Started Dec 31 12:24:48 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 195028 kb
Host smart-ffd33187-cbdf-456f-aea8-f63cc0fb20a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=416842456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.416842456
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.903063485
Short name T77
Test name
Test status
Simulation time 953755719 ps
CPU time 1.07 seconds
Started Dec 31 12:28:41 PM PST 23
Finished Dec 31 12:28:50 PM PST 23
Peak memory 196388 kb
Host smart-d9f515f5-b379-4c34-bc88-a7805e23924f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903063485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.903063485
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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