Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19824394	1			T28	16		T29	12		T1	14
all_values[1]	19824394	1			T28	16		T29	12		T1	14
all_values[2]	19824394	1			T28	16		T29	12		T1	14
all_values[3]	19824394	1			T28	16		T29	12		T1	14
all_values[4]	19824394	1			T28	16		T29	12		T1	14
all_values[5]	19824394	1			T28	16		T29	12		T1	14
all_values[6]	19824394	1			T28	16		T29	12		T1	14
all_values[7]	19824394	1			T28	16		T29	12		T1	14
all_values[8]	19824394	1			T28	16		T29	12		T1	14
all_values[9]	19824394	1			T28	16		T29	12		T1	14
all_values[10]	19824394	1			T28	16		T29	12		T1	14
all_values[11]	19824394	1			T28	16		T29	12		T1	14
all_values[12]	19824394	1			T28	16		T29	12		T1	14
all_values[13]	19824394	1			T28	16		T29	12		T1	14
all_values[14]	19824394	1			T28	16		T29	12		T1	14
all_values[15]	19824394	1			T28	16		T29	12		T1	14
all_values[16]	19824394	1			T28	16		T29	12		T1	14
all_values[17]	19824394	1			T28	16		T29	12		T1	14
all_values[18]	19824394	1			T28	16		T29	12		T1	14
all_values[19]	19824394	1			T28	16		T29	12		T1	14
all_values[20]	19824394	1			T28	16		T29	12		T1	14
all_values[21]	19824394	1			T28	16		T29	12		T1	14
all_values[22]	19824394	1			T28	16		T29	12		T1	14
all_values[23]	19824394	1			T28	16		T29	12		T1	14
all_values[24]	19824394	1			T28	16		T29	12		T1	14
all_values[25]	19824394	1			T28	16		T29	12		T1	14
all_values[26]	19824394	1			T28	16		T29	12		T1	14
all_values[27]	19824394	1			T28	16		T29	12		T1	14
all_values[28]	19824394	1			T28	16		T29	12		T1	14
all_values[29]	19824394	1			T28	16		T29	12		T1	14
all_values[30]	19824394	1			T28	16		T29	12		T1	14
all_values[31]	19824394	1			T28	16		T29	12		T1	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

351093523

1

T28

283

T29

238

T1

448

auto[1]

283287085

1

T28

229

T29

146

T11

52

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119592151

1

T28

144

T29

229

T1

448

auto[1]

514788457

1

T28

368

T29

155

T11

62

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2907816	1			T28	2		T29	5		T1	14
all_values[0]	auto[0]	auto[1]	8051630	1			T29	4		T11	1		T13	1
all_values[0]	auto[1]	auto[0]	820806	1			T29	1		T11	1		T14	3
all_values[0]	auto[1]	auto[1]	8044142	1			T28	14		T29	2		T14	11
all_values[1]	auto[0]	auto[0]	2921144	1			T28	6		T29	2		T1	14
all_values[1]	auto[0]	auto[1]	8048146	1			T28	10		T13	1		T14	3
all_values[1]	auto[1]	auto[0]	825869	1			T29	4		T14	7		T15	1
all_values[1]	auto[1]	auto[1]	8029235	1			T29	6		T11	2		T13	1
all_values[2]	auto[0]	auto[0]	2909702	1			T28	3		T29	3		T1	14
all_values[2]	auto[0]	auto[1]	8037113	1			T29	1		T13	1		T14	4
all_values[2]	auto[1]	auto[0]	829202	1			T29	6		T11	1		T14	9
all_values[2]	auto[1]	auto[1]	8048377	1			T28	13		T29	2		T13	1
all_values[3]	auto[0]	auto[0]	2919251	1			T28	2		T29	3		T1	14
all_values[3]	auto[0]	auto[1]	8088698	1			T28	4		T29	4		T11	1
all_values[3]	auto[1]	auto[0]	823428	1			T28	1		T29	1		T14	14
all_values[3]	auto[1]	auto[1]	7993017	1			T28	9		T29	4		T11	2
all_values[4]	auto[0]	auto[0]	2912415	1			T28	6		T29	5		T1	14
all_values[4]	auto[0]	auto[1]	8096783	1			T29	5		T13	1		T16	3
all_values[4]	auto[1]	auto[0]	820133	1			T28	1		T29	1		T11	3
all_values[4]	auto[1]	auto[1]	7995063	1			T28	9		T29	1		T13	1
all_values[5]	auto[0]	auto[0]	2919074	1			T28	2		T29	2		T1	14
all_values[5]	auto[0]	auto[1]	8060953	1			T28	4		T29	2		T13	1
all_values[5]	auto[1]	auto[0]	822638	1			T29	5		T11	3		T13	1
all_values[5]	auto[1]	auto[1]	8021729	1			T28	10		T29	3		T14	5
all_values[6]	auto[0]	auto[0]	2923466	1			T28	2		T29	3		T1	14
all_values[6]	auto[0]	auto[1]	8034468	1			T28	9		T29	4		T11	1
all_values[6]	auto[1]	auto[0]	824811	1			T28	1		T29	2		T14	13
all_values[6]	auto[1]	auto[1]	8041649	1			T28	4		T29	3		T14	3
all_values[7]	auto[0]	auto[0]	2911910	1			T28	2		T29	7		T1	14
all_values[7]	auto[0]	auto[1]	8082908	1			T28	9		T29	3		T13	1
all_values[7]	auto[1]	auto[0]	830074	1			T14	7		T15	1		T16	13
all_values[7]	auto[1]	auto[1]	7999502	1			T28	5		T29	2		T14	5
all_values[8]	auto[0]	auto[0]	2925505	1			T28	2		T29	3		T1	14
all_values[8]	auto[0]	auto[1]	8057229	1			T28	5		T29	6		T11	2
all_values[8]	auto[1]	auto[0]	819253	1			T29	2		T11	1		T14	9
all_values[8]	auto[1]	auto[1]	8022407	1			T28	9		T29	1		T13	1
all_values[9]	auto[0]	auto[0]	2909156	1			T28	11		T29	9		T1	14
all_values[9]	auto[0]	auto[1]	8031088	1			T28	1		T29	3		T14	6
all_values[9]	auto[1]	auto[0]	818030	1			T28	4		T11	1		T13	1
all_values[9]	auto[1]	auto[1]	8066120	1			T11	2		T14	6		T15	1
all_values[10]	auto[0]	auto[0]	2920988	1			T28	2		T29	3		T1	14
all_values[10]	auto[0]	auto[1]	8035463	1			T28	1		T29	4		T15	3
all_values[10]	auto[1]	auto[0]	820094	1			T28	12		T29	2		T11	1
all_values[10]	auto[1]	auto[1]	8047849	1			T28	1		T29	3		T11	2
all_values[11]	auto[0]	auto[0]	2916839	1			T28	6		T29	9		T1	14
all_values[11]	auto[0]	auto[1]	8065838	1			T29	1		T14	1		T15	2
all_values[11]	auto[1]	auto[0]	821745	1			T29	1		T11	1		T14	18
all_values[11]	auto[1]	auto[1]	8019972	1			T28	10		T29	1		T14	8
all_values[12]	auto[0]	auto[0]	2913062	1			T28	7		T29	6		T1	14
all_values[12]	auto[0]	auto[1]	8048523	1			T29	1		T11	2		T13	2
all_values[12]	auto[1]	auto[0]	829338	1			T28	9		T29	3		T11	1
all_values[12]	auto[1]	auto[1]	8033471	1			T29	2		T14	5		T15	1
all_values[13]	auto[0]	auto[0]	2916361	1			T28	2		T29	7		T1	14
all_values[13]	auto[0]	auto[1]	8035205	1			T28	4		T29	3		T11	3
all_values[13]	auto[1]	auto[0]	824870	1			T28	1		T29	1		T14	14
all_values[13]	auto[1]	auto[1]	8047958	1			T28	9		T29	1		T13	1
all_values[14]	auto[0]	auto[0]	2913058	1			T28	3		T29	5		T1	14
all_values[14]	auto[0]	auto[1]	8073172	1			T28	3		T29	5		T13	1
all_values[14]	auto[1]	auto[0]	828058	1			T28	1		T29	1		T14	15
all_values[14]	auto[1]	auto[1]	8010106	1			T28	9		T29	1		T11	3
all_values[15]	auto[0]	auto[0]	2910411	1			T28	6		T29	3		T1	14
all_values[15]	auto[0]	auto[1]	8045458	1			T28	10		T29	2		T11	3
all_values[15]	auto[1]	auto[0]	824800	1			T29	3		T14	2		T15	1
all_values[15]	auto[1]	auto[1]	8043725	1			T29	4		T14	4		T15	1
all_values[16]	auto[0]	auto[0]	2904617	1			T28	2		T29	2		T1	14
all_values[16]	auto[0]	auto[1]	8073084	1			T28	10		T11	2		T14	8
all_values[16]	auto[1]	auto[0]	819142	1			T28	1		T29	8		T14	4
all_values[16]	auto[1]	auto[1]	8027551	1			T28	3		T29	2		T11	1
all_values[17]	auto[0]	auto[0]	2915100	1			T28	2		T29	3		T1	14
all_values[17]	auto[0]	auto[1]	8063574	1			T28	5		T29	1		T13	1
all_values[17]	auto[1]	auto[0]	829784	1			T29	6		T14	10		T16	8
all_values[17]	auto[1]	auto[1]	8015936	1			T28	9		T29	2		T11	3
all_values[18]	auto[0]	auto[0]	2921639	1			T28	6		T29	5		T1	14
all_values[18]	auto[0]	auto[1]	8022449	1			T28	1		T29	4		T11	2
all_values[18]	auto[1]	auto[0]	816852	1			T29	1		T14	12		T16	16
all_values[18]	auto[1]	auto[1]	8063454	1			T28	9		T29	2		T11	1
all_values[19]	auto[0]	auto[0]	2926333	1			T28	5		T29	5		T1	14
all_values[19]	auto[0]	auto[1]	8048337	1			T28	11		T29	4		T11	3
all_values[19]	auto[1]	auto[0]	822121	1			T29	1		T13	1		T14	6
all_values[19]	auto[1]	auto[1]	8027603	1			T29	2		T14	9		T15	1
all_values[20]	auto[0]	auto[0]	2921015	1			T28	2		T29	7		T1	14
all_values[20]	auto[0]	auto[1]	8083255	1			T28	9		T11	2		T13	2
all_values[20]	auto[1]	auto[0]	824894	1			T29	5		T11	1		T14	6
all_values[20]	auto[1]	auto[1]	7995230	1			T28	5		T14	1		T15	2
all_values[21]	auto[0]	auto[0]	2915198	1			T28	2		T29	7		T1	14
all_values[21]	auto[0]	auto[1]	8055630	1			T28	13		T13	1		T14	2
all_values[21]	auto[1]	auto[0]	818064	1			T29	2		T14	6		T15	1
all_values[21]	auto[1]	auto[1]	8035502	1			T28	1		T29	3		T11	3
all_values[22]	auto[0]	auto[0]	2916307	1			T28	2		T29	4		T1	14
all_values[22]	auto[0]	auto[1]	8037045	1			T28	13		T29	3		T13	1
all_values[22]	auto[1]	auto[0]	814630	1			T29	2		T11	3		T14	8
all_values[22]	auto[1]	auto[1]	8056412	1			T28	1		T29	3		T14	13
all_values[23]	auto[0]	auto[0]	2912911	1			T28	2		T29	2		T1	14
all_values[23]	auto[0]	auto[1]	8092587	1			T28	10		T11	1		T14	11
all_values[23]	auto[1]	auto[0]	812002	1			T29	6		T14	3		T15	1
all_values[23]	auto[1]	auto[1]	8006894	1			T28	4		T29	4		T11	2
all_values[24]	auto[0]	auto[0]	2911639	1			T28	3		T29	9		T1	14
all_values[24]	auto[0]	auto[1]	8087802	1			T28	12		T29	3		T13	1
all_values[24]	auto[1]	auto[0]	814590	1			T11	3		T14	8		T15	1
all_values[24]	auto[1]	auto[1]	8010363	1			T28	1		T13	1		T14	3
all_values[25]	auto[0]	auto[0]	2917062	1			T28	6		T29	5		T1	14
all_values[25]	auto[0]	auto[1]	8035931	1			T28	9		T29	4		T11	2
all_values[25]	auto[1]	auto[0]	810557	1			T29	1		T11	1		T14	14
all_values[25]	auto[1]	auto[1]	8060844	1			T28	1		T29	2		T14	6
all_values[26]	auto[0]	auto[0]	2914560	1			T28	2		T29	4		T1	14
all_values[26]	auto[0]	auto[1]	8044240	1			T28	5		T29	3		T14	3
all_values[26]	auto[1]	auto[0]	821783	1			T29	3		T11	1		T14	12
all_values[26]	auto[1]	auto[1]	8043811	1			T28	9		T29	2		T11	2
all_values[27]	auto[0]	auto[0]	2910070	1			T28	2		T29	9		T1	14
all_values[27]	auto[0]	auto[1]	8068349	1			T28	1		T29	3		T11	3
all_values[27]	auto[1]	auto[0]	824830	1			T14	13		T16	8		T21	10
all_values[27]	auto[1]	auto[1]	8021145	1			T28	13		T14	1		T15	3
all_values[28]	auto[0]	auto[0]	2906619	1			T28	3		T29	3		T1	14
all_values[28]	auto[0]	auto[1]	8034791	1			T28	9		T29	4		T13	1
all_values[28]	auto[1]	auto[0]	833096	1			T29	1		T11	1		T14	9
all_values[28]	auto[1]	auto[1]	8049888	1			T28	4		T29	4		T11	2
all_values[29]	auto[0]	auto[0]	2912099	1			T28	2		T29	5		T1	14
all_values[29]	auto[0]	auto[1]	8067483	1			T29	2		T11	2		T13	1
all_values[29]	auto[1]	auto[0]	822202	1			T28	3		T29	1		T14	7
all_values[29]	auto[1]	auto[1]	8022610	1			T28	11		T29	4		T11	1
all_values[30]	auto[0]	auto[0]	2916527	1			T28	3		T29	2		T1	14
all_values[30]	auto[0]	auto[1]	8033164	1			T28	4		T29	2		T11	3
all_values[30]	auto[1]	auto[0]	817639	1			T29	2		T14	8		T15	1
all_values[30]	auto[1]	auto[1]	8057064	1			T28	9		T29	6		T14	9
all_values[31]	auto[0]	auto[0]	2918364	1			T28	2		T29	9		T1	14
all_values[31]	auto[0]	auto[1]	8062909	1			T28	1		T29	1		T13	1
all_values[31]	auto[1]	auto[0]	816598	1			T29	1		T13	1		T14	8
all_values[31]	auto[1]	auto[1]	8026523	1			T28	13		T29	1		T11	3