Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5897185	1			T28	18		T29	9		T1	16
all_pins[1]	5897185	1			T28	18		T29	9		T1	16
all_pins[2]	5897185	1			T28	18		T29	9		T1	16
all_pins[3]	5897185	1			T28	18		T29	9		T1	16
all_pins[4]	5897185	1			T28	18		T29	9		T1	16
all_pins[5]	5897185	1			T28	18		T29	9		T1	16
all_pins[6]	5897185	1			T28	18		T29	9		T1	16
all_pins[7]	5897185	1			T28	18		T29	9		T1	16
all_pins[8]	5897185	1			T28	18		T29	9		T1	16
all_pins[9]	5897185	1			T28	18		T29	9		T1	16
all_pins[10]	5897185	1			T28	18		T29	9		T1	16
all_pins[11]	5897185	1			T28	18		T29	9		T1	16
all_pins[12]	5897185	1			T28	18		T29	9		T1	16
all_pins[13]	5897185	1			T28	18		T29	9		T1	16
all_pins[14]	5897185	1			T28	18		T29	9		T1	16
all_pins[15]	5897185	1			T28	18		T29	9		T1	16
all_pins[16]	5897185	1			T28	18		T29	9		T1	16
all_pins[17]	5897185	1			T28	18		T29	9		T1	16
all_pins[18]	5897185	1			T28	18		T29	9		T1	16
all_pins[19]	5897185	1			T28	18		T29	9		T1	16
all_pins[20]	5897185	1			T28	18		T29	9		T1	16
all_pins[21]	5897185	1			T28	18		T29	9		T1	16
all_pins[22]	5897185	1			T28	18		T29	9		T1	16
all_pins[23]	5897185	1			T28	18		T29	9		T1	16
all_pins[24]	5897185	1			T28	18		T29	9		T1	16
all_pins[25]	5897185	1			T28	18		T29	9		T1	16
all_pins[26]	5897185	1			T28	18		T29	9		T1	16
all_pins[27]	5897185	1			T28	18		T29	9		T1	16
all_pins[28]	5897185	1			T28	18		T29	9		T1	16
all_pins[29]	5897185	1			T28	18		T29	9		T1	16
all_pins[30]	5897185	1			T28	18		T29	9		T1	16
all_pins[31]	5897185	1			T28	18		T29	9		T1	16

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	117035646	1			T28	383		T29	219		T1	390
values[0x1]	71674274	1			T28	193		T29	69		T1	122
transitions[0x0=>0x1]	42882196	1			T28	112		T29	47		T1	88
transitions[0x1=>0x0]	42882048	1			T28	112		T29	47		T1	88

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3658073	1			T28	9		T29	7		T1	16
all_pins[0]	values[0x1]	2239112	1			T28	9		T29	2		T14	11
all_pins[0]	transitions[0x0=>0x1]	1382998	1			T28	2		T29	2		T14	8
all_pins[0]	transitions[0x1=>0x0]	1380374	1			T28	2		T29	1		T11	3
all_pins[1]	values[0x0]	3652547	1			T28	16		T29	3		T1	13
all_pins[1]	values[0x1]	2244638	1			T28	2		T29	6		T1	3
all_pins[1]	transitions[0x0=>0x1]	1341613	1			T28	2		T29	4		T1	3
all_pins[1]	transitions[0x1=>0x0]	1336087	1			T28	9		T14	11		T16	5
all_pins[2]	values[0x0]	3655784	1			T28	7		T29	7		T1	14
all_pins[2]	values[0x1]	2241401	1			T28	11		T29	2		T1	2
all_pins[2]	transitions[0x0=>0x1]	1338037	1			T28	9		T11	4		T14	11
all_pins[2]	transitions[0x1=>0x0]	1341274	1			T29	4		T1	1		T11	1
all_pins[3]	values[0x0]	3660144	1			T28	10		T29	6		T1	13
all_pins[3]	values[0x1]	2237041	1			T28	8		T29	3		T1	3
all_pins[3]	transitions[0x0=>0x1]	1335812	1			T28	4		T29	3		T1	3
all_pins[3]	transitions[0x1=>0x0]	1340172	1			T28	7		T29	2		T1	2
all_pins[4]	values[0x0]	3660787	1			T28	13		T29	8		T1	12
all_pins[4]	values[0x1]	2236398	1			T28	5		T29	1		T1	4
all_pins[4]	transitions[0x0=>0x1]	1337346	1			T29	1		T1	4		T13	2
all_pins[4]	transitions[0x1=>0x0]	1337989	1			T28	3		T29	3		T1	3
all_pins[5]	values[0x0]	3656905	1			T28	11		T29	6		T1	12
all_pins[5]	values[0x1]	2240280	1			T28	7		T29	3		T1	4
all_pins[5]	transitions[0x0=>0x1]	1340768	1			T28	3		T29	3		T14	4
all_pins[5]	transitions[0x1=>0x0]	1336886	1			T28	1		T29	1		T13	2
all_pins[6]	values[0x0]	3656886	1			T28	5		T29	6		T1	15
all_pins[6]	values[0x1]	2240299	1			T28	13		T29	3		T1	1
all_pins[6]	transitions[0x0=>0x1]	1339728	1			T28	7		T29	2		T14	3
all_pins[6]	transitions[0x1=>0x0]	1339709	1			T28	1		T29	2		T1	3
all_pins[7]	values[0x0]	3659065	1			T28	7		T29	7		T1	16
all_pins[7]	values[0x1]	2238120	1			T28	11		T29	2		T14	4
all_pins[7]	transitions[0x0=>0x1]	1335714	1			T28	1		T14	3		T16	3
all_pins[7]	transitions[0x1=>0x0]	1337893	1			T28	3		T29	1		T1	1
all_pins[8]	values[0x0]	3657111	1			T28	16		T29	8		T1	7
all_pins[8]	values[0x1]	2240074	1			T28	2		T29	1		T1	9
all_pins[8]	transitions[0x0=>0x1]	1340308	1			T28	2		T29	1		T1	9
all_pins[8]	transitions[0x1=>0x0]	1338354	1			T28	11		T29	2		T14	4
all_pins[9]	values[0x0]	3658786	1			T28	16		T29	9		T1	9
all_pins[9]	values[0x1]	2238399	1			T28	2		T1	7		T11	3
all_pins[9]	transitions[0x0=>0x1]	1339962	1			T28	2		T1	1		T11	2
all_pins[9]	transitions[0x1=>0x0]	1341637	1			T28	2		T29	1		T1	3
all_pins[10]	values[0x0]	3655295	1			T28	13		T29	6		T1	16
all_pins[10]	values[0x1]	2241890	1			T28	5		T29	3		T11	3
all_pins[10]	transitions[0x0=>0x1]	1341583	1			T28	3		T29	3		T13	2
all_pins[10]	transitions[0x1=>0x0]	1338092	1			T1	7		T14	3		T15	2
all_pins[11]	values[0x0]	3659702	1			T28	12		T29	8		T1	9
all_pins[11]	values[0x1]	2237483	1			T28	6		T29	1		T1	7
all_pins[11]	transitions[0x0=>0x1]	1334842	1			T28	4		T1	7		T14	6
all_pins[11]	transitions[0x1=>0x0]	1339249	1			T28	3		T29	2		T11	3
all_pins[12]	values[0x0]	3661216	1			T28	16		T29	7		T1	13
all_pins[12]	values[0x1]	2235969	1			T28	2		T29	2		T1	3
all_pins[12]	transitions[0x0=>0x1]	1334883	1			T28	1		T29	1		T1	3
all_pins[12]	transitions[0x1=>0x0]	1336397	1			T28	5		T1	7		T14	6
all_pins[13]	values[0x0]	3658540	1			T28	13		T29	8		T1	12
all_pins[13]	values[0x1]	2238645	1			T28	5		T29	1		T1	4
all_pins[13]	transitions[0x0=>0x1]	1340127	1			T28	4		T1	4		T13	3
all_pins[13]	transitions[0x1=>0x0]	1337451	1			T28	1		T29	1		T1	3
all_pins[14]	values[0x0]	3657512	1			T28	13		T29	8		T1	9
all_pins[14]	values[0x1]	2239673	1			T28	5		T29	1		T1	7
all_pins[14]	transitions[0x0=>0x1]	1339489	1			T28	2		T1	7		T11	4
all_pins[14]	transitions[0x1=>0x0]	1338461	1			T28	2		T1	4		T13	3
all_pins[15]	values[0x0]	3652182	1			T28	15		T29	5		T1	12
all_pins[15]	values[0x1]	2245003	1			T28	3		T29	4		T1	4
all_pins[15]	transitions[0x0=>0x1]	1342159	1			T28	2		T29	3		T14	3
all_pins[15]	transitions[0x1=>0x0]	1336829	1			T28	4		T1	3		T11	4
all_pins[16]	values[0x0]	3656336	1			T28	14		T29	7		T1	11
all_pins[16]	values[0x1]	2240849	1			T28	4		T29	2		T1	5
all_pins[16]	transitions[0x0=>0x1]	1334990	1			T28	4		T29	1		T1	4
all_pins[16]	transitions[0x1=>0x0]	1339144	1			T28	3		T29	3		T1	3
all_pins[17]	values[0x0]	3655198	1			T28	14		T29	7		T1	13
all_pins[17]	values[0x1]	2241987	1			T28	4		T29	2		T1	3
all_pins[17]	transitions[0x0=>0x1]	1340614	1			T28	4		T29	1		T1	3
all_pins[17]	transitions[0x1=>0x0]	1339476	1			T28	4		T29	1		T1	5
all_pins[18]	values[0x0]	3656709	1			T28	12		T29	7		T1	11
all_pins[18]	values[0x1]	2240476	1			T28	6		T29	2		T1	5
all_pins[18]	transitions[0x0=>0x1]	1339224	1			T28	3		T1	5		T14	4
all_pins[18]	transitions[0x1=>0x0]	1340735	1			T28	1		T1	3		T11	2
all_pins[19]	values[0x0]	3656484	1			T28	17		T29	7		T1	12
all_pins[19]	values[0x1]	2240701	1			T28	1		T29	2		T1	4
all_pins[19]	transitions[0x0=>0x1]	1338791	1			T1	1		T13	1		T14	8
all_pins[19]	transitions[0x1=>0x0]	1338566	1			T28	5		T1	2		T11	4
all_pins[20]	values[0x0]	3661570	1			T28	6		T29	9		T1	11
all_pins[20]	values[0x1]	2235615	1			T28	12		T1	5		T11	1
all_pins[20]	transitions[0x0=>0x1]	1335624	1			T28	11		T1	2		T11	1
all_pins[20]	transitions[0x1=>0x0]	1340710	1			T29	2		T1	1		T14	9
all_pins[21]	values[0x0]	3659509	1			T28	15		T29	6		T1	12
all_pins[21]	values[0x1]	2237676	1			T28	3		T29	3		T1	4
all_pins[21]	transitions[0x0=>0x1]	1341349	1			T28	1		T29	3		T1	4
all_pins[21]	transitions[0x1=>0x0]	1339288	1			T28	10		T1	5		T13	1
all_pins[22]	values[0x0]	3656672	1			T28	14		T29	7		T1	14
all_pins[22]	values[0x1]	2240513	1			T28	4		T29	2		T1	2
all_pins[22]	transitions[0x0=>0x1]	1340349	1			T28	2		T29	2		T1	2
all_pins[22]	transitions[0x1=>0x0]	1337512	1			T28	1		T29	3		T1	4
all_pins[23]	values[0x0]	3656773	1			T28	8		T29	5		T1	8
all_pins[23]	values[0x1]	2240412	1			T28	10		T29	4		T1	8
all_pins[23]	transitions[0x0=>0x1]	1338595	1			T28	9		T29	3		T1	6
all_pins[23]	transitions[0x1=>0x0]	1338696	1			T28	3		T29	1		T14	10
all_pins[24]	values[0x0]	3656224	1			T28	14		T29	9		T1	8
all_pins[24]	values[0x1]	2240961	1			T28	4		T1	8		T13	1
all_pins[24]	transitions[0x0=>0x1]	1339004	1			T28	3		T1	4		T13	1
all_pins[24]	transitions[0x1=>0x0]	1338455	1			T28	9		T29	4		T1	4
all_pins[25]	values[0x0]	3657421	1			T28	15		T29	7		T1	12
all_pins[25]	values[0x1]	2239764	1			T28	3		T29	2		T1	4
all_pins[25]	transitions[0x0=>0x1]	1335900	1			T28	1		T29	2		T1	3
all_pins[25]	transitions[0x1=>0x0]	1337097	1			T28	2		T1	7		T13	1
all_pins[26]	values[0x0]	3659352	1			T28	15		T29	7		T1	14
all_pins[26]	values[0x1]	2237833	1			T28	3		T29	2		T1	2
all_pins[26]	transitions[0x0=>0x1]	1335222	1			T28	3		T29	1		T1	2
all_pins[26]	transitions[0x1=>0x0]	1337153	1			T28	3		T29	1		T1	4
all_pins[27]	values[0x0]	3651644	1			T28	8		T29	9		T1	16
all_pins[27]	values[0x1]	2245541	1			T28	10		T13	1		T14	1
all_pins[27]	transitions[0x0=>0x1]	1343827	1			T28	7		T13	1		T14	1
all_pins[27]	transitions[0x1=>0x0]	1336119	1			T29	2		T1	2		T11	6
all_pins[28]	values[0x0]	3657185	1			T28	8		T29	6		T1	11
all_pins[28]	values[0x1]	2240000	1			T28	10		T29	3		T1	5
all_pins[28]	transitions[0x0=>0x1]	1335971	1			T28	2		T29	3		T1	5
all_pins[28]	transitions[0x1=>0x0]	1341512	1			T28	2		T13	1		T14	1
all_pins[29]	values[0x0]	3656623	1			T28	11		T29	5		T1	13
all_pins[29]	values[0x1]	2240562	1			T28	7		T29	4		T1	3
all_pins[29]	transitions[0x0=>0x1]	1340188	1			T28	3		T29	4		T1	2
all_pins[29]	transitions[0x1=>0x0]	1339626	1			T28	6		T29	3		T1	4
all_pins[30]	values[0x0]	3656862	1			T28	11		T29	4		T1	10
all_pins[30]	values[0x1]	2240323	1			T28	7		T29	5		T1	6
all_pins[30]	transitions[0x0=>0x1]	1339017	1			T28	5		T29	3		T1	4
all_pins[30]	transitions[0x1=>0x0]	1339256	1			T28	5		T29	2		T1	1
all_pins[31]	values[0x0]	3660549	1			T28	9		T29	8		T1	16
all_pins[31]	values[0x1]	2236636	1			T28	9		T29	1		T11	4
all_pins[31]	transitions[0x0=>0x1]	1338162	1			T28	6		T29	1		T11	4
all_pins[31]	transitions[0x1=>0x0]	1341849	1			T28	4		T29	5		T1	6