Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19824394	1			T28	16		T29	12		T1	14
all_values[1]	19824394	1			T28	16		T29	12		T1	14
all_values[2]	19824394	1			T28	16		T29	12		T1	14
all_values[3]	19824394	1			T28	16		T29	12		T1	14
all_values[4]	19824394	1			T28	16		T29	12		T1	14
all_values[5]	19824394	1			T28	16		T29	12		T1	14
all_values[6]	19824394	1			T28	16		T29	12		T1	14
all_values[7]	19824394	1			T28	16		T29	12		T1	14
all_values[8]	19824394	1			T28	16		T29	12		T1	14
all_values[9]	19824394	1			T28	16		T29	12		T1	14
all_values[10]	19824394	1			T28	16		T29	12		T1	14
all_values[11]	19824394	1			T28	16		T29	12		T1	14
all_values[12]	19824394	1			T28	16		T29	12		T1	14
all_values[13]	19824394	1			T28	16		T29	12		T1	14
all_values[14]	19824394	1			T28	16		T29	12		T1	14
all_values[15]	19824394	1			T28	16		T29	12		T1	14
all_values[16]	19824394	1			T28	16		T29	12		T1	14
all_values[17]	19824394	1			T28	16		T29	12		T1	14
all_values[18]	19824394	1			T28	16		T29	12		T1	14
all_values[19]	19824394	1			T28	16		T29	12		T1	14
all_values[20]	19824394	1			T28	16		T29	12		T1	14
all_values[21]	19824394	1			T28	16		T29	12		T1	14
all_values[22]	19824394	1			T28	16		T29	12		T1	14
all_values[23]	19824394	1			T28	16		T29	12		T1	14
all_values[24]	19824394	1			T28	16		T29	12		T1	14
all_values[25]	19824394	1			T28	16		T29	12		T1	14
all_values[26]	19824394	1			T28	16		T29	12		T1	14
all_values[27]	19824394	1			T28	16		T29	12		T1	14
all_values[28]	19824394	1			T28	16		T29	12		T1	14
all_values[29]	19824394	1			T28	16		T29	12		T1	14
all_values[30]	19824394	1			T28	16		T29	12		T1	14
all_values[31]	19824394	1			T28	16		T29	12		T1	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

351093523

1

T28

283

T29

238

T1

448

auto[1]

283287085

1

T28

229

T29

146

T11

52

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119592151

1

T28

144

T29

229

T1

448

auto[1]

514788457

1

T28

368

T29

155

T11

62

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

626904081

1

T28

512

T29

331

T1

448

auto[1]

7476527

1

T29

53

T14

151

T16

137

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2907816	1			T28	2		T29	5		T1	14
all_values[0]	auto[0]	auto[0]	auto[1]	7934486	1			T29	3		T11	1		T13	1
all_values[0]	auto[0]	auto[1]	auto[0]	820806	1			T29	1		T11	1		T14	3
all_values[0]	auto[0]	auto[1]	auto[1]	7926975	1			T28	14		T29	1		T14	7
all_values[0]	auto[1]	auto[0]	auto[1]	117144	1			T29	1		T14	1		T16	3
all_values[0]	auto[1]	auto[1]	auto[1]	117167	1			T29	1		T14	4		T16	2
all_values[1]	auto[0]	auto[0]	auto[0]	2921144	1			T28	6		T29	2		T1	14
all_values[1]	auto[0]	auto[0]	auto[1]	7931638	1			T28	10		T13	1		T14	1
all_values[1]	auto[0]	auto[1]	auto[0]	825869	1			T29	4		T14	7		T15	1
all_values[1]	auto[0]	auto[1]	auto[1]	7912420	1			T29	5		T11	2		T13	1
all_values[1]	auto[1]	auto[0]	auto[1]	116508	1			T14	2		T16	1		T21	3
all_values[1]	auto[1]	auto[1]	auto[1]	116815	1			T29	1		T14	1		T16	3
all_values[2]	auto[0]	auto[0]	auto[0]	2909702	1			T28	3		T29	3		T1	14
all_values[2]	auto[0]	auto[0]	auto[1]	7919858	1			T29	1		T13	1		T14	3
all_values[2]	auto[0]	auto[1]	auto[0]	829202	1			T29	6		T11	1		T14	9
all_values[2]	auto[0]	auto[1]	auto[1]	7931650	1			T28	13		T13	1		T14	10
all_values[2]	auto[1]	auto[0]	auto[1]	117255	1			T14	1		T16	2		T21	2
all_values[2]	auto[1]	auto[1]	auto[1]	116727	1			T29	2		T14	3		T16	3
all_values[3]	auto[0]	auto[0]	auto[0]	2919251	1			T28	2		T29	3		T1	14
all_values[3]	auto[0]	auto[0]	auto[1]	7971414	1			T28	4		T29	3		T11	1
all_values[3]	auto[0]	auto[1]	auto[0]	823428	1			T28	1		T29	1		T14	14
all_values[3]	auto[0]	auto[1]	auto[1]	7877129	1			T28	9		T29	4		T11	2
all_values[3]	auto[1]	auto[0]	auto[1]	117284	1			T29	1		T14	1		T16	2
all_values[3]	auto[1]	auto[1]	auto[1]	115888	1			T14	5		T16	1		T21	3
all_values[4]	auto[0]	auto[0]	auto[0]	2912415	1			T28	6		T29	5		T1	14
all_values[4]	auto[0]	auto[0]	auto[1]	7979317	1			T29	2		T13	1		T16	1
all_values[4]	auto[0]	auto[1]	auto[0]	820133	1			T28	1		T29	1		T11	3
all_values[4]	auto[0]	auto[1]	auto[1]	7878649	1			T28	9		T29	1		T13	1
all_values[4]	auto[1]	auto[0]	auto[1]	117466	1			T29	3		T16	2		T21	1
all_values[4]	auto[1]	auto[1]	auto[1]	116414	1			T14	3		T16	2		T22	6
all_values[5]	auto[0]	auto[0]	auto[0]	2919074	1			T28	2		T29	2		T1	14
all_values[5]	auto[0]	auto[0]	auto[1]	7943713	1			T28	4		T29	2		T13	1
all_values[5]	auto[0]	auto[1]	auto[0]	822638	1			T29	5		T11	3		T13	1
all_values[5]	auto[0]	auto[1]	auto[1]	7905148	1			T28	10		T29	2		T14	3
all_values[5]	auto[1]	auto[0]	auto[1]	117240	1			T14	3		T16	4		T21	2
all_values[5]	auto[1]	auto[1]	auto[1]	116581	1			T29	1		T14	2		T16	3
all_values[6]	auto[0]	auto[0]	auto[0]	2923466	1			T28	2		T29	3		T1	14
all_values[6]	auto[0]	auto[0]	auto[1]	7917296	1			T28	9		T29	4		T11	1
all_values[6]	auto[0]	auto[1]	auto[0]	824811	1			T28	1		T29	2		T14	13
all_values[6]	auto[0]	auto[1]	auto[1]	7924885	1			T28	4		T29	2		T14	1
all_values[6]	auto[1]	auto[0]	auto[1]	117172	1			T14	3		T16	4		T21	3
all_values[6]	auto[1]	auto[1]	auto[1]	116764	1			T29	1		T14	2		T16	3
all_values[7]	auto[0]	auto[0]	auto[0]	2911910	1			T28	2		T29	7		T1	14
all_values[7]	auto[0]	auto[0]	auto[1]	7965420	1			T28	9		T29	2		T13	1
all_values[7]	auto[0]	auto[1]	auto[0]	830074	1			T14	7		T15	1		T16	13
all_values[7]	auto[0]	auto[1]	auto[1]	7883590	1			T28	5		T29	2		T14	1
all_values[7]	auto[1]	auto[0]	auto[1]	117488	1			T29	1		T14	2		T16	2
all_values[7]	auto[1]	auto[1]	auto[1]	115912	1			T14	4		T16	3		T21	3
all_values[8]	auto[0]	auto[0]	auto[0]	2925505	1			T28	2		T29	3		T1	14
all_values[8]	auto[0]	auto[0]	auto[1]	7939869	1			T28	5		T29	5		T11	2
all_values[8]	auto[0]	auto[1]	auto[0]	819253	1			T29	2		T11	1		T14	9
all_values[8]	auto[0]	auto[1]	auto[1]	7906168	1			T28	9		T13	1		T14	1
all_values[8]	auto[1]	auto[0]	auto[1]	117360	1			T29	1		T14	3		T16	3
all_values[8]	auto[1]	auto[1]	auto[1]	116239	1			T29	1		T14	2		T16	1
all_values[9]	auto[0]	auto[0]	auto[0]	2909156	1			T28	11		T29	9		T1	14
all_values[9]	auto[0]	auto[0]	auto[1]	7913236	1			T28	1		T29	1		T14	3
all_values[9]	auto[0]	auto[1]	auto[0]	818030	1			T28	4		T11	1		T13	1
all_values[9]	auto[0]	auto[1]	auto[1]	7949744	1			T11	2		T14	4		T15	1
all_values[9]	auto[1]	auto[0]	auto[1]	117852	1			T29	2		T14	3		T21	2
all_values[9]	auto[1]	auto[1]	auto[1]	116376	1			T14	2		T16	1		T21	1
all_values[10]	auto[0]	auto[0]	auto[0]	2920988	1			T28	2		T29	3		T1	14
all_values[10]	auto[0]	auto[0]	auto[1]	7917984	1			T28	1		T29	3		T15	3
all_values[10]	auto[0]	auto[1]	auto[0]	820094	1			T28	12		T29	2		T11	1
all_values[10]	auto[0]	auto[1]	auto[1]	7931670	1			T28	1		T29	2		T11	2
all_values[10]	auto[1]	auto[0]	auto[1]	117479	1			T29	1		T16	2		T22	1
all_values[10]	auto[1]	auto[1]	auto[1]	116179	1			T29	1		T14	5		T16	5
all_values[11]	auto[0]	auto[0]	auto[0]	2916839	1			T28	6		T29	9		T1	14
all_values[11]	auto[0]	auto[0]	auto[1]	7949175	1			T14	1		T15	2		T16	4
all_values[11]	auto[0]	auto[1]	auto[0]	821745	1			T29	1		T11	1		T14	18
all_values[11]	auto[0]	auto[1]	auto[1]	7903415	1			T28	10		T29	1		T14	7
all_values[11]	auto[1]	auto[0]	auto[1]	116663	1			T29	1		T16	1		T21	1
all_values[11]	auto[1]	auto[1]	auto[1]	116557	1			T14	1		T16	2		T21	1
all_values[12]	auto[0]	auto[0]	auto[0]	2913062	1			T28	7		T29	6		T1	14
all_values[12]	auto[0]	auto[0]	auto[1]	7931051	1			T11	2		T13	2		T14	1
all_values[12]	auto[0]	auto[1]	auto[0]	829338	1			T28	9		T29	3		T11	1
all_values[12]	auto[0]	auto[1]	auto[1]	7917463	1			T29	1		T14	1		T15	1
all_values[12]	auto[1]	auto[0]	auto[1]	117472	1			T29	1		T14	2		T16	2
all_values[12]	auto[1]	auto[1]	auto[1]	116008	1			T29	1		T14	4		T16	4
all_values[13]	auto[0]	auto[0]	auto[0]	2916361	1			T28	2		T29	7		T1	14
all_values[13]	auto[0]	auto[0]	auto[1]	7918365	1			T28	4		T11	3		T13	1
all_values[13]	auto[0]	auto[1]	auto[0]	824870	1			T28	1		T29	1		T14	14
all_values[13]	auto[0]	auto[1]	auto[1]	7930897	1			T28	9		T29	1		T13	1
all_values[13]	auto[1]	auto[0]	auto[1]	116840	1			T29	3		T14	2		T16	2
all_values[13]	auto[1]	auto[1]	auto[1]	117061	1			T14	3		T16	2		T22	4
all_values[14]	auto[0]	auto[0]	auto[0]	2913058	1			T28	3		T29	5		T1	14
all_values[14]	auto[0]	auto[0]	auto[1]	7956148	1			T28	3		T29	3		T13	1
all_values[14]	auto[0]	auto[1]	auto[0]	828058	1			T28	1		T29	1		T14	15
all_values[14]	auto[0]	auto[1]	auto[1]	7893526	1			T28	9		T29	1		T11	3
all_values[14]	auto[1]	auto[0]	auto[1]	117024	1			T29	2		T14	1		T21	1
all_values[14]	auto[1]	auto[1]	auto[1]	116580	1			T14	5		T16	2		T21	3
all_values[15]	auto[0]	auto[0]	auto[0]	2910411	1			T28	6		T29	3		T1	14
all_values[15]	auto[0]	auto[0]	auto[1]	7928381	1			T28	10		T29	1		T11	3
all_values[15]	auto[0]	auto[1]	auto[0]	824800	1			T29	3		T14	2		T15	1
all_values[15]	auto[0]	auto[1]	auto[1]	7927110	1			T29	4		T14	2		T15	1
all_values[15]	auto[1]	auto[0]	auto[1]	117077	1			T29	1		T14	4		T16	3
all_values[15]	auto[1]	auto[1]	auto[1]	116615	1			T14	2		T21	3		T22	3
all_values[16]	auto[0]	auto[0]	auto[0]	2904617	1			T28	2		T29	2		T1	14
all_values[16]	auto[0]	auto[0]	auto[1]	7955812	1			T28	10		T11	2		T14	5
all_values[16]	auto[0]	auto[1]	auto[0]	819142	1			T28	1		T29	8		T14	4
all_values[16]	auto[0]	auto[1]	auto[1]	7911216	1			T28	3		T29	1		T11	1
all_values[16]	auto[1]	auto[0]	auto[1]	117272	1			T14	3		T16	3		T21	2
all_values[16]	auto[1]	auto[1]	auto[1]	116335	1			T29	1		T14	2		T16	5
all_values[17]	auto[0]	auto[0]	auto[0]	2915100	1			T28	2		T29	3		T1	14
all_values[17]	auto[0]	auto[0]	auto[1]	7946730	1			T28	5		T29	1		T13	1
all_values[17]	auto[0]	auto[1]	auto[0]	829784	1			T29	6		T14	10		T16	8
all_values[17]	auto[0]	auto[1]	auto[1]	7899209	1			T28	9		T11	3		T14	3
all_values[17]	auto[1]	auto[0]	auto[1]	116844	1			T14	4		T21	3		T22	1
all_values[17]	auto[1]	auto[1]	auto[1]	116727	1			T29	2		T14	2		T16	4
all_values[18]	auto[0]	auto[0]	auto[0]	2921639	1			T28	6		T29	5		T1	14
all_values[18]	auto[0]	auto[0]	auto[1]	7905941	1			T28	1		T29	4		T11	2
all_values[18]	auto[0]	auto[1]	auto[0]	816852	1			T29	1		T14	12		T16	16
all_values[18]	auto[0]	auto[1]	auto[1]	7946874	1			T28	9		T11	1		T14	3
all_values[18]	auto[1]	auto[0]	auto[1]	116508	1			T14	1		T16	1		T22	1
all_values[18]	auto[1]	auto[1]	auto[1]	116580	1			T29	2		T14	3		T16	3
all_values[19]	auto[0]	auto[0]	auto[0]	2926333	1			T28	5		T29	5		T1	14
all_values[19]	auto[0]	auto[0]	auto[1]	7931107	1			T28	11		T29	3		T11	3
all_values[19]	auto[0]	auto[1]	auto[0]	822121	1			T29	1		T13	1		T14	6
all_values[19]	auto[0]	auto[1]	auto[1]	7911110	1			T29	1		T14	8		T15	1
all_values[19]	auto[1]	auto[0]	auto[1]	117230	1			T29	1		T14	3		T16	2
all_values[19]	auto[1]	auto[1]	auto[1]	116493	1			T29	1		T14	1		T16	4
all_values[20]	auto[0]	auto[0]	auto[0]	2921015	1			T28	2		T29	7		T1	14
all_values[20]	auto[0]	auto[0]	auto[1]	7966171	1			T28	9		T11	2		T13	2
all_values[20]	auto[0]	auto[1]	auto[0]	824894	1			T29	5		T11	1		T14	6
all_values[20]	auto[0]	auto[1]	auto[1]	7879333	1			T28	5		T15	2		T16	2
all_values[20]	auto[1]	auto[0]	auto[1]	117084	1			T14	5		T16	1		T108	2
all_values[20]	auto[1]	auto[1]	auto[1]	115897	1			T14	1		T21	3		T22	2
all_values[21]	auto[0]	auto[0]	auto[0]	2915198	1			T28	2		T29	7		T1	14
all_values[21]	auto[0]	auto[0]	auto[1]	7938711	1			T28	13		T13	1		T14	1
all_values[21]	auto[0]	auto[1]	auto[0]	818064	1			T29	2		T14	6		T15	1
all_values[21]	auto[0]	auto[1]	auto[1]	7919190	1			T28	1		T29	2		T11	3
all_values[21]	auto[1]	auto[0]	auto[1]	116919	1			T14	1		T16	2		T21	1
all_values[21]	auto[1]	auto[1]	auto[1]	116312	1			T29	1		T16	1		T21	2
all_values[22]	auto[0]	auto[0]	auto[0]	2916307	1			T28	2		T29	4		T1	14
all_values[22]	auto[0]	auto[0]	auto[1]	7919826	1			T28	13		T29	2		T13	1
all_values[22]	auto[0]	auto[1]	auto[0]	814630	1			T29	2		T11	3		T14	8
all_values[22]	auto[0]	auto[1]	auto[1]	7940164	1			T28	1		T29	2		T14	7
all_values[22]	auto[1]	auto[0]	auto[1]	117219	1			T29	1		T16	2		T21	2
all_values[22]	auto[1]	auto[1]	auto[1]	116248	1			T29	1		T14	6		T16	3
all_values[23]	auto[0]	auto[0]	auto[0]	2912911	1			T28	2		T29	2		T1	14
all_values[23]	auto[0]	auto[0]	auto[1]	7975192	1			T28	10		T11	1		T14	6
all_values[23]	auto[0]	auto[1]	auto[0]	812002	1			T29	6		T14	3		T15	1
all_values[23]	auto[0]	auto[1]	auto[1]	7890556	1			T28	4		T29	1		T11	2
all_values[23]	auto[1]	auto[0]	auto[1]	117395	1			T14	5		T16	4		T21	5
all_values[23]	auto[1]	auto[1]	auto[1]	116338	1			T29	3		T14	1		T22	6
all_values[24]	auto[0]	auto[0]	auto[0]	2911639	1			T28	3		T29	9		T1	14
all_values[24]	auto[0]	auto[0]	auto[1]	7969491	1			T28	12		T29	2		T13	1
all_values[24]	auto[0]	auto[1]	auto[0]	814590	1			T11	3		T14	8		T15	1
all_values[24]	auto[0]	auto[1]	auto[1]	7893943	1			T28	1		T13	1		T14	2
all_values[24]	auto[1]	auto[0]	auto[1]	118311	1			T29	1		T14	5		T16	4
all_values[24]	auto[1]	auto[1]	auto[1]	116420	1			T14	1		T16	2		T22	1
all_values[25]	auto[0]	auto[0]	auto[0]	2917062	1			T28	6		T29	5		T1	14
all_values[25]	auto[0]	auto[0]	auto[1]	7918739	1			T28	9		T29	4		T11	2
all_values[25]	auto[0]	auto[1]	auto[0]	810557	1			T29	1		T11	1		T14	14
all_values[25]	auto[0]	auto[1]	auto[1]	7944535	1			T28	1		T14	3		T15	1
all_values[25]	auto[1]	auto[0]	auto[1]	117192	1			T14	2		T16	2		T21	1
all_values[25]	auto[1]	auto[1]	auto[1]	116309	1			T29	2		T14	3		T16	2
all_values[26]	auto[0]	auto[0]	auto[0]	2914560	1			T28	2		T29	4		T1	14
all_values[26]	auto[0]	auto[0]	auto[1]	7927256	1			T28	5		T29	2		T14	2
all_values[26]	auto[0]	auto[1]	auto[0]	821783	1			T29	3		T11	1		T14	12
all_values[26]	auto[0]	auto[1]	auto[1]	7927266	1			T28	9		T29	1		T11	2
all_values[26]	auto[1]	auto[0]	auto[1]	116984	1			T29	1		T14	1		T16	2
all_values[26]	auto[1]	auto[1]	auto[1]	116545	1			T29	1		T14	4		T21	1
all_values[27]	auto[0]	auto[0]	auto[0]	2910070	1			T28	2		T29	9		T1	14
all_values[27]	auto[0]	auto[0]	auto[1]	7951646	1			T28	1		T29	2		T11	3
all_values[27]	auto[0]	auto[1]	auto[0]	824830	1			T14	13		T16	8		T21	10
all_values[27]	auto[0]	auto[1]	auto[1]	7904514	1			T28	13		T14	1		T15	3
all_values[27]	auto[1]	auto[0]	auto[1]	116703	1			T29	1		T14	4		T16	1
all_values[27]	auto[1]	auto[1]	auto[1]	116631	1			T16	2		T22	3		T108	1
all_values[28]	auto[0]	auto[0]	auto[0]	2906619	1			T28	3		T29	3		T1	14
all_values[28]	auto[0]	auto[0]	auto[1]	7917894	1			T28	9		T29	3		T13	1
all_values[28]	auto[0]	auto[1]	auto[0]	833096	1			T29	1		T11	1		T14	9
all_values[28]	auto[0]	auto[1]	auto[1]	7932886	1			T28	4		T29	4		T11	2
all_values[28]	auto[1]	auto[0]	auto[1]	116897	1			T29	1		T14	3		T16	3
all_values[28]	auto[1]	auto[1]	auto[1]	117002	1			T14	1		T16	3		T22	5
all_values[29]	auto[0]	auto[0]	auto[0]	2912099	1			T28	2		T29	5		T1	14
all_values[29]	auto[0]	auto[0]	auto[1]	7949889	1			T29	1		T11	2		T13	1
all_values[29]	auto[0]	auto[1]	auto[0]	822202	1			T28	3		T29	1		T14	7
all_values[29]	auto[0]	auto[1]	auto[1]	7906269	1			T28	11		T29	2		T11	1
all_values[29]	auto[1]	auto[0]	auto[1]	117594	1			T29	1		T14	4		T16	1
all_values[29]	auto[1]	auto[1]	auto[1]	116341	1			T29	2		T14	2		T16	2
all_values[30]	auto[0]	auto[0]	auto[0]	2916527	1			T28	3		T29	2		T1	14
all_values[30]	auto[0]	auto[0]	auto[1]	7916194	1			T28	4		T29	2		T11	3
all_values[30]	auto[0]	auto[1]	auto[0]	817639	1			T29	2		T14	8		T15	1
all_values[30]	auto[0]	auto[1]	auto[1]	7940488	1			T28	9		T29	4		T14	8
all_values[30]	auto[1]	auto[0]	auto[1]	116970	1			T14	2		T16	3		T21	4
all_values[30]	auto[1]	auto[1]	auto[1]	116576	1			T29	2		T14	1		T16	2
all_values[31]	auto[0]	auto[0]	auto[0]	2918364	1			T28	2		T29	9		T1	14
all_values[31]	auto[0]	auto[0]	auto[1]	7945695	1			T28	1		T13	1		T14	4
all_values[31]	auto[0]	auto[1]	auto[0]	816598	1			T29	1		T13	1		T14	8
all_values[31]	auto[0]	auto[1]	auto[1]	7910293	1			T28	13		T29	1		T11	3
all_values[31]	auto[1]	auto[0]	auto[1]	117214	1			T29	1		T14	3		T16	2
all_values[31]	auto[1]	auto[1]	auto[1]	116230	1			T14	1		T16	1		T21	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal