Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[1]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[2]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[3]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[4]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[5]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[6]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[7]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[8]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[9]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[10]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[11]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[12]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[13]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[14]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[15]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[16]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[17]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[18]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[19]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[20]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[21]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[22]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[23]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[24]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[25]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[26]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[27]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[28]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[29]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[30]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[31]	19563636	1			T28	16		T29	1		T1	14

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

377837535

1

T28

512

T29

32

T1

448

auto[1]

248198817

1

T42

6062

T43

5530

T44

19083

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

496061503

1

T28

512

T29

32

T1

448

auto[1]

129974849

1

T42

6721

T43

9945

T44

10796

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

457711189

1

T28

512

T29

32

T1

448

auto[1]

168325163

1

T42

6607

T43

10072

T44

10868

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	7158579	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	5104972	1			T42	81		T43	17		T44	301
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	2047187	1			T42	108		T43	168		T44	142
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2605488	1			T42	79		T43	159		T54	180
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	624660	1			T44	177		T57	34		T110	162
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	2022750	1			T42	132		T43	156		T44	138
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	7148974	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	5109569	1			T42	77		T43	16		T44	226
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	2045696	1			T42	84		T43	162		T44	160
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2608121	1			T42	103		T43	177		T54	228
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	623942	1			T44	164		T57	50		T110	120
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	2027334	1			T42	120		T43	158		T44	204
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	7147596	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	5118399	1			T42	86		T43	18		T44	263
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	2045558	1			T42	119		T43	126		T44	150
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2604327	1			T42	102		T43	177		T54	212
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	624805	1			T44	185		T57	44		T110	138
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	2022951	1			T42	94		T43	174		T44	162
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	7145283	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	5122268	1			T42	86		T43	14		T44	210
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	2041026	1			T42	95		T43	152		T44	161
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2605798	1			T42	118		T43	174		T54	202
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	624859	1			T44	168		T57	38		T110	140
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	2024402	1			T42	122		T43	145		T44	216
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	7148277	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	5108777	1			T42	90		T43	18		T44	232
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	2037137	1			T42	70		T43	116		T44	172
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2612973	1			T42	129		T43	190		T54	184
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	626443	1			T44	178		T57	56		T110	156
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	2030029	1			T42	106		T43	149		T44	173
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	7139641	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	5117735	1			T42	89		T43	15		T44	228
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	2045745	1			T42	120		T43	183		T44	170
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2615817	1			T42	90		T43	106		T54	151
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	622687	1			T44	197		T57	29		T110	113
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	2022011	1			T42	105		T43	154		T44	162
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	7156708	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	5099642	1			T42	90		T43	14		T44	263
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	2038041	1			T42	102		T43	147		T44	178
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2610535	1			T42	94		T43	186		T54	209
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	627064	1			T44	161		T57	29		T110	188
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	2031646	1			T42	114		T43	150		T44	170
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	7162974	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	5097910	1			T42	74		T43	15		T44	300
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	2045382	1			T42	102		T43	131		T44	166
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2603716	1			T42	110		T43	178		T54	150
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	626457	1			T44	173		T57	31		T110	142
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	2027197	1			T42	86		T43	198		T44	134
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	7150705	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	5107839	1			T42	91		T43	17		T44	253
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	2046059	1			T42	104		T43	125		T44	148
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2609554	1			T42	98		T43	164		T54	200
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	626345	1			T44	182		T57	32		T110	116
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	2023134	1			T42	89		T43	144		T44	185
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	7148600	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	5113800	1			T42	74		T43	17		T44	225
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	2046672	1			T42	116		T43	139		T44	170
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2604709	1			T42	80		T43	174		T54	221
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	624144	1			T44	172		T57	47		T110	146
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	2025711	1			T42	104		T43	162		T44	191
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	7162549	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	5098973	1			T42	70		T43	15		T44	269
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	2043979	1			T42	95		T43	166		T44	146
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2608045	1			T42	90		T43	140		T54	202
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	625361	1			T44	197		T57	44		T110	112
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	2024729	1			T42	138		T43	183		T44	154
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	7155512	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	5111694	1			T42	91		T43	17		T44	202
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	2051323	1			T42	112		T43	167		T44	202
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2605204	1			T42	107		T43	142		T54	170
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	624181	1			T44	118		T57	38		T110	161
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	2015722	1			T42	128		T43	142		T44	238
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	7148066	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	5113334	1			T42	79		T43	12		T44	284
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	2046382	1			T42	78		T43	136		T44	172
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2607790	1			T42	120		T43	175		T54	172
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	622655	1			T44	144		T57	35		T110	145
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	2025409	1			T42	99		T43	136		T44	164
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	7157697	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	5102106	1			T42	77		T43	17		T44	264
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	2037052	1			T42	115		T43	162		T44	128
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2612552	1			T42	74		T43	164		T54	190
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	625521	1			T44	196		T57	28		T110	136
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	2028708	1			T42	118		T43	179		T44	168
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	7152322	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	5101769	1			T42	82		T43	15		T44	273
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	2043558	1			T42	96		T43	136		T44	180
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2615488	1			T42	96		T43	159		T54	196
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	625852	1			T44	176		T57	39		T110	136
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	2024647	1			T42	120		T43	140		T44	136
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	7151074	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	5103557	1			T42	99		T43	12		T44	290
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	2045358	1			T42	110		T43	166		T44	163
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2609678	1			T42	118		T43	165		T54	225
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	625864	1			T44	162		T57	50		T110	148
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	2028105	1			T42	114		T43	134		T44	158
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	7155839	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	5107502	1			T42	85		T43	14		T44	267
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	2036999	1			T42	137		T43	161		T44	201
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2617078	1			T42	60		T43	144		T54	197
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	627442	1			T44	144		T57	44		T110	155
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	2018776	1			T42	100		T43	152		T44	152
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	7161710	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	5102112	1			T42	92		T43	14		T44	249
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	2035790	1			T42	94		T43	169		T44	174
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2617713	1			T42	125		T43	152		T54	208
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	625798	1			T44	153		T57	37		T110	132
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	2020513	1			T42	90		T43	156		T44	186
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	7162111	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	5104627	1			T42	83		T43	16		T44	264
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	2033663	1			T42	104		T43	143		T44	174
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2618478	1			T42	112		T43	142		T54	212
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	626344	1			T44	182		T57	36		T110	148
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	2018413	1			T42	100		T43	178		T44	150
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	7155085	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	5105950	1			T42	81		T43	18		T44	236
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	2036624	1			T42	103		T43	123		T44	188
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2616955	1			T42	106		T43	178		T54	150
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	627998	1			T44	143		T57	60		T110	167
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	2021024	1			T42	110		T43	146		T44	200
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	7153737	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	5104788	1			T42	69		T43	17		T44	260
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	2038220	1			T42	96		T43	168		T44	195
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2615779	1			T42	110		T43	155		T54	199
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	633394	1			T44	166		T57	36		T110	116
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	2017718	1			T42	117		T43	152		T44	138
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	7159320	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	5104097	1			T42	84		T43	18		T44	245
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	2034075	1			T42	84		T43	187		T44	130
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2620744	1			T42	99		T43	122		T54	166
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	628139	1			T44	201		T57	63		T110	156
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	2017261	1			T42	124		T43	122		T44	190
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	7152402	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	5124563	1			T42	80		T43	13		T44	251
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	2040085	1			T42	104		T43	156		T44	204
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2608104	1			T42	118		T43	150		T54	164
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	622206	1			T44	119		T57	38		T110	147
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	2016276	1			T42	105		T43	161		T44	192
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	7158569	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	5104093	1			T42	74		T43	15		T44	283
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	2034831	1			T42	90		T43	191		T44	133
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2620865	1			T42	121		T43	146		T54	218
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	626758	1			T44	196		T57	46		T110	156
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	2018520	1			T42	102		T43	106		T44	152
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	7156626	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	5102973	1			T42	82		T43	15		T44	241
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	2039390	1			T42	122		T43	154		T44	142
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2614036	1			T42	82		T43	144		T54	212
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	627061	1			T44	173		T57	46		T110	134
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	2023550	1			T42	98		T43	171		T44	206
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	7150747	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	5113423	1			T42	97		T43	15		T44	222
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	2034506	1			T42	82		T43	179		T44	177
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2619023	1			T42	105		T43	130		T54	186
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	630734	1			T44	192		T57	36		T110	128
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	2015203	1			T42	126		T43	162		T44	168
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	7161453	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	5107733	1			T42	88		T43	18		T44	279
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	2036609	1			T42	118		T43	155		T44	138
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2615188	1			T42	102		T43	150		T54	218
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	626574	1			T44	189		T57	44		T110	148
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	2016079	1			T42	102		T43	178		T44	166
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	7158106	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	5115712	1			T42	77		T43	13		T44	252
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	2042103	1			T42	126		T43	146		T44	172
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2612077	1			T42	88		T43	164		T54	222
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	625206	1			T44	158		T57	46		T110	136
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	2010432	1			T42	91		T43	147		T44	189
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	7160429	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	5110020	1			T42	86		T43	17		T44	275
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	2033910	1			T42	106		T43	126		T44	170
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2618746	1			T42	106		T43	156		T54	176
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	626607	1			T44	169		T57	42		T110	142
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	2013924	1			T42	94		T43	231		T44	146
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	7156515	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	5102087	1			T42	73		T43	17		T44	270
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	2035634	1			T42	94		T43	182		T44	178
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2620359	1			T42	80		T43	172		T54	208
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	628343	1			T44	165		T57	50		T110	143
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	2020698	1			T42	87		T43	135		T44	158
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	7150788	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	5119555	1			T42	78		T43	20		T44	278
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	2035768	1			T42	120		T43	145		T44	186
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2615069	1			T42	83		T43	152		T54	223
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	628795	1			T44	136		T57	21		T110	142
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	2013661	1			T42	80		T43	140		T44	163
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	7148767	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	5118219	1			T42	86		T43	18		T44	260
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	2040268	1			T42	104		T43	155		T44	178
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2616135	1			T42	91		T43	162		T54	162
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	626561	1			T44	184		T57	38		T110	151
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	2013686	1			T42	96		T43	182		T44	139

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal