Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[1]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[2]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[3]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[4]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[5]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[6]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[7]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[8]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[9]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[10]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[11]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[12]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[13]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[14]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[15]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[16]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[17]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[18]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[19]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[20]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[21]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[22]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[23]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[24]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[25]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[26]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[27]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[28]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[29]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[30]	19563636	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[31]	19563636	1			T28	16		T29	1		T1	14

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

377837535

1

T28

512

T29

32

T1

448

auto[1]

248198817

1

T42

6062

T43

5530

T44

19083

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

377831585

1

T28

395

T29

32

T1

364

auto[1]

248204767

1

T28

117

T1

84

T11

26

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	11451359	1			T28	9		T29	1		T1	11
bins_for_gpio_bits[0]	auto[0]	auto[1]	359727	1			T42	30		T43	39		T44	33
bins_for_gpio_bits[0]	auto[1]	auto[0]	359895	1			T28	7		T1	3		T11	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	7392655	1			T42	183		T43	134		T44	583
bins_for_gpio_bits[1]	auto[0]	auto[0]	11442914	1			T28	15		T29	1		T1	13
bins_for_gpio_bits[1]	auto[0]	auto[1]	359725	1			T42	25		T43	38		T44	36
bins_for_gpio_bits[1]	auto[1]	auto[0]	359877	1			T28	1		T1	1		T11	2
bins_for_gpio_bits[1]	auto[1]	auto[1]	7401120	1			T42	172		T43	136		T44	558
bins_for_gpio_bits[2]	auto[0]	auto[0]	11437427	1			T28	8		T29	1		T1	14
bins_for_gpio_bits[2]	auto[0]	auto[1]	359850	1			T42	29		T43	46		T44	41
bins_for_gpio_bits[2]	auto[1]	auto[0]	360054	1			T28	8		T11	1		T2	9
bins_for_gpio_bits[2]	auto[1]	auto[1]	7406305	1			T42	151		T43	146		T44	569
bins_for_gpio_bits[3]	auto[0]	auto[0]	11431871	1			T28	16		T29	1		T1	14
bins_for_gpio_bits[3]	auto[0]	auto[1]	360040	1			T42	32		T43	40		T44	44
bins_for_gpio_bits[3]	auto[1]	auto[0]	360236	1			T2	4		T18	1		T4	5
bins_for_gpio_bits[3]	auto[1]	auto[1]	7411489	1			T42	176		T43	119		T44	550
bins_for_gpio_bits[4]	auto[0]	auto[0]	11438674	1			T28	8		T29	1		T1	12
bins_for_gpio_bits[4]	auto[0]	auto[1]	359495	1			T42	28		T43	40		T44	42
bins_for_gpio_bits[4]	auto[1]	auto[0]	359713	1			T28	8		T1	2		T13	1
bins_for_gpio_bits[4]	auto[1]	auto[1]	7405754	1			T42	168		T43	127		T44	541
bins_for_gpio_bits[5]	auto[0]	auto[0]	11441204	1			T28	14		T29	1		T1	13
bins_for_gpio_bits[5]	auto[0]	auto[1]	359834	1			T42	27		T43	39		T44	46
bins_for_gpio_bits[5]	auto[1]	auto[0]	359999	1			T28	2		T1	1		T15	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	7402599	1			T42	167		T43	130		T44	541
bins_for_gpio_bits[6]	auto[0]	auto[0]	11444918	1			T28	16		T29	1		T1	11
bins_for_gpio_bits[6]	auto[0]	auto[1]	360167	1			T42	28		T43	37		T44	44
bins_for_gpio_bits[6]	auto[1]	auto[0]	360366	1			T1	3		T11	1		T13	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	7398185	1			T42	176		T43	127		T44	550
bins_for_gpio_bits[7]	auto[0]	auto[0]	11451156	1			T28	11		T29	1		T1	14
bins_for_gpio_bits[7]	auto[0]	auto[1]	360715	1			T42	25		T43	41		T44	41
bins_for_gpio_bits[7]	auto[1]	auto[0]	360916	1			T28	5		T15	1		T18	2
bins_for_gpio_bits[7]	auto[1]	auto[1]	7390849	1			T42	135		T43	172		T44	566
bins_for_gpio_bits[8]	auto[0]	auto[0]	11446798	1			T28	15		T29	1		T1	11
bins_for_gpio_bits[8]	auto[0]	auto[1]	359300	1			T42	20		T43	38		T44	43
bins_for_gpio_bits[8]	auto[1]	auto[0]	359520	1			T28	1		T1	3		T15	3
bins_for_gpio_bits[8]	auto[1]	auto[1]	7398018	1			T42	160		T43	123		T44	577
bins_for_gpio_bits[9]	auto[0]	auto[0]	11439144	1			T28	16		T29	1		T1	9
bins_for_gpio_bits[9]	auto[0]	auto[1]	360635	1			T42	26		T43	38		T44	38
bins_for_gpio_bits[9]	auto[1]	auto[0]	360837	1			T1	5		T15	1		T2	7
bins_for_gpio_bits[9]	auto[1]	auto[1]	7403020	1			T42	152		T43	141		T44	550
bins_for_gpio_bits[10]	auto[0]	auto[0]	11454761	1			T28	14		T29	1		T1	11
bins_for_gpio_bits[10]	auto[0]	auto[1]	359621	1			T42	30		T43	47		T44	43
bins_for_gpio_bits[10]	auto[1]	auto[0]	359812	1			T28	2		T1	3		T13	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	7389442	1			T42	178		T43	151		T44	577
bins_for_gpio_bits[11]	auto[0]	auto[0]	11452819	1			T28	16		T29	1		T1	9
bins_for_gpio_bits[11]	auto[0]	auto[1]	358986	1			T42	32		T43	41		T44	52
bins_for_gpio_bits[11]	auto[1]	auto[0]	359220	1			T1	5		T2	7		T18	2
bins_for_gpio_bits[11]	auto[1]	auto[1]	7392611	1			T42	187		T43	118		T44	506
bins_for_gpio_bits[12]	auto[0]	auto[0]	11441290	1			T28	8		T29	1		T1	6
bins_for_gpio_bits[12]	auto[0]	auto[1]	360766	1			T42	24		T43	39		T44	41
bins_for_gpio_bits[12]	auto[1]	auto[0]	360948	1			T28	8		T1	8		T13	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	7400632	1			T42	154		T43	109		T44	551
bins_for_gpio_bits[13]	auto[0]	auto[0]	11446860	1			T28	16		T29	1		T1	11
bins_for_gpio_bits[13]	auto[0]	auto[1]	360304	1			T42	28		T43	41		T44	34
bins_for_gpio_bits[13]	auto[1]	auto[0]	360441	1			T1	3		T2	4		T18	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	7396031	1			T42	167		T43	155		T44	594
bins_for_gpio_bits[14]	auto[0]	auto[0]	11451152	1			T28	13		T29	1		T1	14
bins_for_gpio_bits[14]	auto[0]	auto[1]	360027	1			T42	29		T43	39		T44	40
bins_for_gpio_bits[14]	auto[1]	auto[0]	360216	1			T28	3		T11	1		T13	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	7392241	1			T42	173		T43	116		T44	545
bins_for_gpio_bits[15]	auto[0]	auto[0]	11445755	1			T28	15		T29	1		T1	14
bins_for_gpio_bits[15]	auto[0]	auto[1]	360224	1			T42	29		T43	36		T44	49
bins_for_gpio_bits[15]	auto[1]	auto[0]	360355	1			T28	1		T11	1		T13	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	7397302	1			T42	184		T43	110		T44	561
bins_for_gpio_bits[16]	auto[0]	auto[0]	11449648	1			T28	11		T29	1		T1	14
bins_for_gpio_bits[16]	auto[0]	auto[1]	360055	1			T42	25		T43	34		T44	39
bins_for_gpio_bits[16]	auto[1]	auto[0]	360268	1			T28	5		T2	7		T4	3
bins_for_gpio_bits[16]	auto[1]	auto[1]	7393665	1			T42	160		T43	132		T44	524
bins_for_gpio_bits[17]	auto[0]	auto[0]	11454641	1			T28	12		T29	1		T1	12
bins_for_gpio_bits[17]	auto[0]	auto[1]	360366	1			T42	27		T43	39		T44	38
bins_for_gpio_bits[17]	auto[1]	auto[0]	360572	1			T28	4		T1	2		T11	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	7388057	1			T42	155		T43	131		T44	550
bins_for_gpio_bits[18]	auto[0]	auto[0]	11454147	1			T28	9		T29	1		T1	11
bins_for_gpio_bits[18]	auto[0]	auto[1]	359946	1			T42	30		T43	42		T44	42
bins_for_gpio_bits[18]	auto[1]	auto[0]	360105	1			T28	7		T1	3		T15	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	7389438	1			T42	153		T43	152		T44	554
bins_for_gpio_bits[19]	auto[0]	auto[0]	11448602	1			T28	10		T29	1		T1	8
bins_for_gpio_bits[19]	auto[0]	auto[1]	359885	1			T42	23		T43	37		T44	45
bins_for_gpio_bits[19]	auto[1]	auto[0]	360062	1			T28	6		T1	6		T13	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	7395087	1			T42	168		T43	127		T44	534
bins_for_gpio_bits[20]	auto[0]	auto[0]	11448208	1			T28	16		T29	1		T1	9
bins_for_gpio_bits[20]	auto[0]	auto[1]	359356	1			T42	31		T43	35		T44	36
bins_for_gpio_bits[20]	auto[1]	auto[0]	359528	1			T1	5		T15	1		T18	2
bins_for_gpio_bits[20]	auto[1]	auto[1]	7396544	1			T42	155		T43	134		T44	528
bins_for_gpio_bits[21]	auto[0]	auto[0]	11453415	1			T28	14		T29	1		T1	11
bins_for_gpio_bits[21]	auto[0]	auto[1]	360530	1			T42	24		T43	34		T44	37
bins_for_gpio_bits[21]	auto[1]	auto[0]	360724	1			T28	2		T1	3		T11	3
bins_for_gpio_bits[21]	auto[1]	auto[1]	7388967	1			T42	184		T43	106		T44	599
bins_for_gpio_bits[22]	auto[0]	auto[0]	11440214	1			T28	8		T29	1		T1	13
bins_for_gpio_bits[22]	auto[0]	auto[1]	360174	1			T42	27		T43	43		T44	51
bins_for_gpio_bits[22]	auto[1]	auto[0]	360377	1			T28	8		T1	1		T11	3
bins_for_gpio_bits[22]	auto[1]	auto[1]	7402871	1			T42	158		T43	131		T44	511
bins_for_gpio_bits[23]	auto[0]	auto[0]	11453423	1			T28	16		T29	1		T1	11
bins_for_gpio_bits[23]	auto[0]	auto[1]	360650	1			T42	27		T43	35		T44	39
bins_for_gpio_bits[23]	auto[1]	auto[0]	360842	1			T1	3		T11	2		T15	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	7388721	1			T42	149		T43	86		T44	592
bins_for_gpio_bits[24]	auto[0]	auto[0]	11449961	1			T28	11		T29	1		T1	11
bins_for_gpio_bits[24]	auto[0]	auto[1]	359924	1			T42	28		T43	44		T44	39
bins_for_gpio_bits[24]	auto[1]	auto[0]	360091	1			T28	5		T1	3		T11	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	7393660	1			T42	152		T43	142		T44	581
bins_for_gpio_bits[25]	auto[0]	auto[0]	11444246	1			T28	15		T29	1		T1	12
bins_for_gpio_bits[25]	auto[0]	auto[1]	359851	1			T42	27		T43	40		T44	39
bins_for_gpio_bits[25]	auto[1]	auto[0]	360030	1			T28	1		T1	2		T11	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	7399509	1			T42	196		T43	137		T44	543
bins_for_gpio_bits[26]	auto[0]	auto[0]	11452642	1			T28	8		T29	1		T1	9
bins_for_gpio_bits[26]	auto[0]	auto[1]	360434	1			T42	28		T43	46		T44	36
bins_for_gpio_bits[26]	auto[1]	auto[0]	360608	1			T28	8		T1	5		T11	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	7389952	1			T42	162		T43	150		T44	598
bins_for_gpio_bits[27]	auto[0]	auto[0]	11452326	1			T28	10		T29	1		T1	14
bins_for_gpio_bits[27]	auto[0]	auto[1]	359777	1			T42	19		T43	38		T44	48
bins_for_gpio_bits[27]	auto[1]	auto[0]	359960	1			T28	6		T11	2		T13	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	7391573	1			T42	149		T43	122		T44	551
bins_for_gpio_bits[28]	auto[0]	auto[0]	11452612	1			T28	16		T29	1		T1	12
bins_for_gpio_bits[28]	auto[0]	auto[1]	360320	1			T42	26		T43	44		T44	45
bins_for_gpio_bits[28]	auto[1]	auto[0]	360473	1			T1	2		T11	1		T2	13
bins_for_gpio_bits[28]	auto[1]	auto[1]	7390231	1			T42	154		T43	204		T44	545
bins_for_gpio_bits[29]	auto[0]	auto[0]	11451762	1			T28	9		T29	1		T1	6
bins_for_gpio_bits[29]	auto[0]	auto[1]	360546	1			T42	25		T43	39		T44	41
bins_for_gpio_bits[29]	auto[1]	auto[0]	360746	1			T28	7		T1	8		T11	3
bins_for_gpio_bits[29]	auto[1]	auto[1]	7390582	1			T42	135		T43	113		T44	552
bins_for_gpio_bits[30]	auto[0]	auto[0]	11442146	1			T28	12		T29	1		T1	13
bins_for_gpio_bits[30]	auto[0]	auto[1]	359293	1			T42	22		T43	40		T44	47
bins_for_gpio_bits[30]	auto[1]	auto[0]	359479	1			T28	4		T1	1		T2	13
bins_for_gpio_bits[30]	auto[1]	auto[1]	7402718	1			T42	136		T43	120		T44	530
bins_for_gpio_bits[31]	auto[0]	auto[0]	11445529	1			T28	8		T29	1		T1	11
bins_for_gpio_bits[31]	auto[0]	auto[1]	359438	1			T42	22		T43	42		T44	41
bins_for_gpio_bits[31]	auto[1]	auto[0]	359641	1			T28	8		T1	3		T11	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	7399028	1			T42	160		T43	158		T44	542