Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10959446 |
1 |
|
|
T28 |
2 |
|
T29 |
9 |
|
T1 |
14 |
| auto[1] |
8864948 |
1 |
|
|
T28 |
14 |
|
T29 |
3 |
|
T11 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18686260 |
1 |
|
|
T28 |
13 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1138134 |
1 |
|
|
T28 |
3 |
|
T11 |
1 |
|
T103 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10937457 |
1 |
|
|
T28 |
3 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8886937 |
1 |
|
|
T28 |
13 |
|
T11 |
3 |
|
T15 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3858318 |
1 |
|
|
T11 |
1 |
|
T15 |
2 |
|
T30 |
5 |
| auto[1] |
auto[0] |
auto[1] |
567158 |
1 |
|
|
T11 |
1 |
|
T103 |
1 |
|
T77 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3890485 |
1 |
|
|
T28 |
10 |
|
T11 |
1 |
|
T102 |
3 |
| auto[1] |
auto[1] |
auto[1] |
570976 |
1 |
|
|
T28 |
3 |
|
T82 |
2 |
|
T100 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10969290 |
1 |
|
|
T28 |
16 |
|
T29 |
2 |
|
T1 |
14 |
| auto[1] |
8855104 |
1 |
|
|
T29 |
10 |
|
T11 |
2 |
|
T13 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18698992 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1125402 |
1 |
|
|
T2 |
2 |
|
T103 |
1 |
|
T111 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11016624 |
1 |
|
|
T28 |
2 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8807770 |
1 |
|
|
T28 |
14 |
|
T13 |
2 |
|
T15 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3836620 |
1 |
|
|
T28 |
14 |
|
T13 |
1 |
|
T15 |
1 |
| auto[1] |
auto[0] |
auto[1] |
562065 |
1 |
|
|
T2 |
2 |
|
T111 |
1 |
|
T78 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3845748 |
1 |
|
|
T13 |
1 |
|
T30 |
2 |
|
T103 |
2 |
| auto[1] |
auto[1] |
auto[1] |
563337 |
1 |
|
|
T103 |
1 |
|
T77 |
1 |
|
T104 |
123 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10956451 |
1 |
|
|
T28 |
3 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8867943 |
1 |
|
|
T28 |
13 |
|
T29 |
5 |
|
T11 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18696682 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1127712 |
1 |
|
|
T2 |
3 |
|
T77 |
3 |
|
T100 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11011901 |
1 |
|
|
T28 |
14 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8812493 |
1 |
|
|
T28 |
2 |
|
T13 |
2 |
|
T15 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3822566 |
1 |
|
|
T28 |
1 |
|
T13 |
1 |
|
T15 |
1 |
| auto[1] |
auto[0] |
auto[1] |
560078 |
1 |
|
|
T2 |
3 |
|
T100 |
1 |
|
T112 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3862215 |
1 |
|
|
T28 |
1 |
|
T13 |
1 |
|
T102 |
2 |
| auto[1] |
auto[1] |
auto[1] |
567634 |
1 |
|
|
T77 |
3 |
|
T104 |
141 |
|
T53 |
1672 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10982677 |
1 |
|
|
T28 |
6 |
|
T29 |
10 |
|
T1 |
14 |
| auto[1] |
8841717 |
1 |
|
|
T28 |
10 |
|
T29 |
2 |
|
T11 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18687868 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1136526 |
1 |
|
|
T2 |
4 |
|
T103 |
1 |
|
T82 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10948552 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8875842 |
1 |
|
|
T28 |
1 |
|
T11 |
2 |
|
T15 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3889978 |
1 |
|
|
T11 |
2 |
|
T15 |
1 |
|
T2 |
6 |
| auto[1] |
auto[0] |
auto[1] |
572506 |
1 |
|
|
T2 |
3 |
|
T112 |
1 |
|
T45 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3849338 |
1 |
|
|
T28 |
1 |
|
T2 |
16 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[1] |
564020 |
1 |
|
|
T2 |
1 |
|
T103 |
1 |
|
T82 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10961585 |
1 |
|
|
T28 |
7 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8862809 |
1 |
|
|
T28 |
9 |
|
T29 |
5 |
|
T11 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18690746 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1133648 |
1 |
|
|
T111 |
1 |
|
T82 |
4 |
|
T113 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10969464 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8854930 |
1 |
|
|
T28 |
1 |
|
T13 |
1 |
|
T15 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3847364 |
1 |
|
|
T28 |
1 |
|
T13 |
1 |
|
T15 |
1 |
| auto[1] |
auto[0] |
auto[1] |
562811 |
1 |
|
|
T82 |
4 |
|
T113 |
1 |
|
T112 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3873918 |
1 |
|
|
T15 |
1 |
|
T30 |
2 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[1] |
570837 |
1 |
|
|
T111 |
1 |
|
T77 |
1 |
|
T104 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10951566 |
1 |
|
|
T28 |
6 |
|
T29 |
10 |
|
T1 |
14 |
| auto[1] |
8872828 |
1 |
|
|
T28 |
10 |
|
T29 |
2 |
|
T13 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18689927 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1134467 |
1 |
|
|
T82 |
4 |
|
T104 |
210 |
|
T105 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10953644 |
1 |
|
|
T28 |
3 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8870750 |
1 |
|
|
T28 |
13 |
|
T11 |
1 |
|
T13 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3861507 |
1 |
|
|
T28 |
4 |
|
T11 |
1 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
565673 |
1 |
|
|
T82 |
4 |
|
T104 |
139 |
|
T105 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3874776 |
1 |
|
|
T28 |
9 |
|
T13 |
1 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[1] |
568794 |
1 |
|
|
T104 |
71 |
|
T105 |
4 |
|
T53 |
1723 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10986230 |
1 |
|
|
T28 |
6 |
|
T29 |
10 |
|
T1 |
14 |
| auto[1] |
8838164 |
1 |
|
|
T28 |
10 |
|
T29 |
2 |
|
T11 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18696769 |
1 |
|
|
T28 |
13 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1127625 |
1 |
|
|
T28 |
3 |
|
T2 |
3 |
|
T103 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11001358 |
1 |
|
|
T28 |
3 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8823036 |
1 |
|
|
T28 |
13 |
|
T11 |
1 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3857903 |
1 |
|
|
T28 |
3 |
|
T13 |
1 |
|
T2 |
6 |
| auto[1] |
auto[0] |
auto[1] |
564661 |
1 |
|
|
T28 |
1 |
|
T2 |
3 |
|
T103 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3837508 |
1 |
|
|
T28 |
7 |
|
T11 |
1 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[1] |
562964 |
1 |
|
|
T28 |
2 |
|
T45 |
1 |
|
T104 |
87 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10955869 |
1 |
|
|
T28 |
16 |
|
T29 |
5 |
|
T1 |
14 |
| auto[1] |
8868525 |
1 |
|
|
T29 |
7 |
|
T14 |
6 |
|
T15 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18690909 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1133485 |
1 |
|
|
T11 |
1 |
|
T103 |
1 |
|
T104 |
184 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10979158 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8845236 |
1 |
|
|
T28 |
1 |
|
T11 |
3 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3840509 |
1 |
|
|
T28 |
1 |
|
T11 |
2 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
564276 |
1 |
|
|
T11 |
1 |
|
T104 |
123 |
|
T105 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3871242 |
1 |
|
|
T30 |
2 |
|
T103 |
3 |
|
T31 |
5 |
| auto[1] |
auto[1] |
auto[1] |
569209 |
1 |
|
|
T103 |
1 |
|
T104 |
61 |
|
T105 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10977701 |
1 |
|
|
T28 |
12 |
|
T29 |
2 |
|
T1 |
14 |
| auto[1] |
8846693 |
1 |
|
|
T28 |
4 |
|
T29 |
10 |
|
T11 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18688386 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1136008 |
1 |
|
|
T2 |
5 |
|
T112 |
1 |
|
T45 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10961820 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8862574 |
1 |
|
|
T28 |
1 |
|
T11 |
2 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3870980 |
1 |
|
|
T28 |
1 |
|
T11 |
2 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
570214 |
1 |
|
|
T2 |
5 |
|
T45 |
1 |
|
T104 |
99 |
| auto[1] |
auto[1] |
auto[0] |
3855586 |
1 |
|
|
T102 |
1 |
|
T30 |
1 |
|
T31 |
1 |
| auto[1] |
auto[1] |
auto[1] |
565794 |
1 |
|
|
T112 |
1 |
|
T104 |
136 |
|
T53 |
1858 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10978674 |
1 |
|
|
T28 |
7 |
|
T29 |
4 |
|
T1 |
14 |
| auto[1] |
8845720 |
1 |
|
|
T28 |
9 |
|
T29 |
8 |
|
T11 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18692130 |
1 |
|
|
T28 |
12 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1132264 |
1 |
|
|
T28 |
4 |
|
T2 |
2 |
|
T77 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10977574 |
1 |
|
|
T28 |
2 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8846820 |
1 |
|
|
T28 |
14 |
|
T11 |
3 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3869756 |
1 |
|
|
T28 |
4 |
|
T13 |
1 |
|
T2 |
24 |
| auto[1] |
auto[0] |
auto[1] |
567980 |
1 |
|
|
T28 |
1 |
|
T2 |
2 |
|
T77 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3844800 |
1 |
|
|
T28 |
6 |
|
T11 |
3 |
|
T102 |
3 |
| auto[1] |
auto[1] |
auto[1] |
564284 |
1 |
|
|
T28 |
3 |
|
T112 |
1 |
|
T104 |
63 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10944088 |
1 |
|
|
T28 |
7 |
|
T29 |
9 |
|
T1 |
14 |
| auto[1] |
8880306 |
1 |
|
|
T28 |
9 |
|
T29 |
3 |
|
T11 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18688733 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1135661 |
1 |
|
|
T82 |
1 |
|
T77 |
3 |
|
T104 |
172 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10962920 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8861474 |
1 |
|
|
T28 |
1 |
|
T13 |
2 |
|
T15 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3842102 |
1 |
|
|
T28 |
1 |
|
T13 |
2 |
|
T15 |
1 |
| auto[1] |
auto[0] |
auto[1] |
565100 |
1 |
|
|
T82 |
1 |
|
T77 |
3 |
|
T104 |
75 |
| auto[1] |
auto[1] |
auto[0] |
3883711 |
1 |
|
|
T15 |
1 |
|
T30 |
2 |
|
T31 |
6 |
| auto[1] |
auto[1] |
auto[1] |
570561 |
1 |
|
|
T104 |
97 |
|
T105 |
2 |
|
T53 |
2020 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10974670 |
1 |
|
|
T28 |
16 |
|
T29 |
9 |
|
T1 |
14 |
| auto[1] |
8849724 |
1 |
|
|
T29 |
3 |
|
T13 |
1 |
|
T14 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18686414 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1137980 |
1 |
|
|
T77 |
2 |
|
T45 |
1 |
|
T104 |
254 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10949335 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8875059 |
1 |
|
|
T28 |
1 |
|
T11 |
1 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3878969 |
1 |
|
|
T28 |
1 |
|
T11 |
1 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
569846 |
1 |
|
|
T77 |
2 |
|
T104 |
152 |
|
T105 |
5 |
| auto[1] |
auto[1] |
auto[0] |
3858110 |
1 |
|
|
T15 |
1 |
|
T30 |
3 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[1] |
568134 |
1 |
|
|
T45 |
1 |
|
T104 |
102 |
|
T53 |
1810 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10946815 |
1 |
|
|
T28 |
3 |
|
T29 |
4 |
|
T1 |
14 |
| auto[1] |
8877579 |
1 |
|
|
T28 |
13 |
|
T29 |
8 |
|
T11 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18698530 |
1 |
|
|
T28 |
13 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1125864 |
1 |
|
|
T28 |
3 |
|
T2 |
5 |
|
T104 |
256 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11014577 |
1 |
|
|
T28 |
3 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8809817 |
1 |
|
|
T28 |
13 |
|
T2 |
26 |
|
T102 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3845472 |
1 |
|
|
T2 |
21 |
|
T102 |
3 |
|
T30 |
4 |
| auto[1] |
auto[0] |
auto[1] |
563402 |
1 |
|
|
T2 |
5 |
|
T104 |
102 |
|
T105 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3838481 |
1 |
|
|
T28 |
10 |
|
T30 |
1 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[1] |
562462 |
1 |
|
|
T28 |
3 |
|
T104 |
154 |
|
T105 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11004270 |
1 |
|
|
T28 |
11 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8820124 |
1 |
|
|
T28 |
5 |
|
T29 |
5 |
|
T11 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18693462 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1130932 |
1 |
|
|
T103 |
1 |
|
T45 |
3 |
|
T104 |
217 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10988508 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8835886 |
1 |
|
|
T28 |
1 |
|
T11 |
2 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3869676 |
1 |
|
|
T28 |
1 |
|
T11 |
2 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
567714 |
1 |
|
|
T103 |
1 |
|
T104 |
84 |
|
T105 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3835278 |
1 |
|
|
T15 |
1 |
|
T102 |
1 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[1] |
563218 |
1 |
|
|
T45 |
3 |
|
T104 |
133 |
|
T105 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10970828 |
1 |
|
|
T28 |
15 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8853566 |
1 |
|
|
T28 |
1 |
|
T29 |
5 |
|
T11 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18697420 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1126974 |
1 |
|
|
T2 |
3 |
|
T82 |
4 |
|
T113 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11004672 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8819722 |
1 |
|
|
T11 |
3 |
|
T13 |
2 |
|
T15 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3842148 |
1 |
|
|
T13 |
2 |
|
T2 |
6 |
|
T30 |
3 |
| auto[1] |
auto[0] |
auto[1] |
562748 |
1 |
|
|
T2 |
3 |
|
T82 |
4 |
|
T104 |
106 |
| auto[1] |
auto[1] |
auto[0] |
3850600 |
1 |
|
|
T11 |
3 |
|
T15 |
1 |
|
T2 |
17 |
| auto[1] |
auto[1] |
auto[1] |
564226 |
1 |
|
|
T113 |
1 |
|
T104 |
114 |
|
T105 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10953352 |
1 |
|
|
T28 |
15 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8871042 |
1 |
|
|
T28 |
1 |
|
T29 |
5 |
|
T11 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18683238 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1141156 |
1 |
|
|
T2 |
4 |
|
T102 |
1 |
|
T103 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10930510 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8893884 |
1 |
|
|
T28 |
1 |
|
T13 |
2 |
|
T15 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3865128 |
1 |
|
|
T13 |
2 |
|
T2 |
6 |
|
T102 |
2 |
| auto[1] |
auto[0] |
auto[1] |
568352 |
1 |
|
|
T2 |
3 |
|
T102 |
1 |
|
T104 |
139 |
| auto[1] |
auto[1] |
auto[0] |
3887600 |
1 |
|
|
T28 |
1 |
|
T15 |
1 |
|
T2 |
16 |
| auto[1] |
auto[1] |
auto[1] |
572804 |
1 |
|
|
T2 |
1 |
|
T103 |
1 |
|
T82 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11005498 |
1 |
|
|
T28 |
12 |
|
T29 |
2 |
|
T1 |
14 |
| auto[1] |
8818896 |
1 |
|
|
T28 |
4 |
|
T29 |
10 |
|
T11 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18690103 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1134291 |
1 |
|
|
T2 |
4 |
|
T103 |
1 |
|
T112 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10971132 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8853262 |
1 |
|
|
T11 |
3 |
|
T13 |
1 |
|
T15 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3854956 |
1 |
|
|
T11 |
1 |
|
T13 |
1 |
|
T15 |
1 |
| auto[1] |
auto[0] |
auto[1] |
565073 |
1 |
|
|
T2 |
4 |
|
T104 |
72 |
|
T105 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3864015 |
1 |
|
|
T11 |
2 |
|
T30 |
2 |
|
T103 |
1 |
| auto[1] |
auto[1] |
auto[1] |
569218 |
1 |
|
|
T103 |
1 |
|
T112 |
1 |
|
T45 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10999441 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8824953 |
1 |
|
|
T28 |
1 |
|
T11 |
3 |
|
T13 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18690695 |
1 |
|
|
T28 |
11 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1133699 |
1 |
|
|
T28 |
5 |
|
T2 |
5 |
|
T103 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10954035 |
1 |
|
|
T28 |
3 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8870359 |
1 |
|
|
T28 |
13 |
|
T11 |
2 |
|
T13 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3896925 |
1 |
|
|
T28 |
7 |
|
T13 |
1 |
|
T15 |
1 |
| auto[1] |
auto[0] |
auto[1] |
570776 |
1 |
|
|
T28 |
5 |
|
T2 |
1 |
|
T103 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3839735 |
1 |
|
|
T28 |
1 |
|
T11 |
2 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
562923 |
1 |
|
|
T2 |
4 |
|
T45 |
1 |
|
T104 |
124 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10952993 |
1 |
|
|
T28 |
15 |
|
T29 |
9 |
|
T1 |
14 |
| auto[1] |
8871401 |
1 |
|
|
T28 |
1 |
|
T29 |
3 |
|
T11 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18689183 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1135211 |
1 |
|
|
T77 |
1 |
|
T104 |
225 |
|
T105 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10951445 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8872949 |
1 |
|
|
T28 |
1 |
|
T11 |
2 |
|
T13 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3861446 |
1 |
|
|
T11 |
2 |
|
T13 |
2 |
|
T2 |
17 |
| auto[1] |
auto[0] |
auto[1] |
565527 |
1 |
|
|
T104 |
114 |
|
T53 |
1860 |
|
T109 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3876292 |
1 |
|
|
T28 |
1 |
|
T15 |
1 |
|
T102 |
1 |
| auto[1] |
auto[1] |
auto[1] |
569684 |
1 |
|
|
T77 |
1 |
|
T104 |
111 |
|
T105 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10958800 |
1 |
|
|
T28 |
7 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8865594 |
1 |
|
|
T28 |
9 |
|
T29 |
5 |
|
T11 |
3 |