Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10957934 |
1 |
|
|
T28 |
11 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8866460 |
1 |
|
|
T28 |
5 |
|
T29 |
5 |
|
T14 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18695527 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1128867 |
1 |
|
|
T102 |
1 |
|
T77 |
2 |
|
T104 |
171 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11000072 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8824322 |
1 |
|
|
T28 |
1 |
|
T13 |
1 |
|
T15 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3854291 |
1 |
|
|
T13 |
1 |
|
T15 |
1 |
|
T102 |
2 |
| auto[1] |
auto[0] |
auto[1] |
565112 |
1 |
|
|
T102 |
1 |
|
T77 |
1 |
|
T104 |
90 |
| auto[1] |
auto[1] |
auto[0] |
3841164 |
1 |
|
|
T28 |
1 |
|
T30 |
1 |
|
T31 |
7 |
| auto[1] |
auto[1] |
auto[1] |
563755 |
1 |
|
|
T77 |
1 |
|
T104 |
81 |
|
T105 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |