Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10969290 |
1 |
|
|
T28 |
16 |
|
T29 |
2 |
|
T1 |
14 |
auto[1] |
8855104 |
1 |
|
|
T29 |
10 |
|
T11 |
2 |
|
T13 |
1 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16190330 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
auto[1] |
3634064 |
1 |
|
|
T11 |
2 |
|
T15 |
1 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10948374 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
auto[1] |
8876020 |
1 |
|
|
T11 |
2 |
|
T15 |
3 |
|
T2 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2627263 |
1 |
|
|
T15 |
1 |
|
T2 |
2 |
|
T4 |
11 |
auto[1] |
auto[0] |
auto[1] |
1822237 |
1 |
|
|
T2 |
1 |
|
T31 |
2 |
|
T111 |
2 |
auto[1] |
auto[1] |
auto[0] |
2614693 |
1 |
|
|
T15 |
1 |
|
T30 |
1 |
|
T31 |
7 |
auto[1] |
auto[1] |
auto[1] |
1811827 |
1 |
|
|
T11 |
2 |
|
T15 |
1 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |