Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18692670 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1131724 |
1 |
|
|
T102 |
1 |
|
T77 |
1 |
|
T100 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10987003 |
1 |
|
|
T28 |
14 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8837391 |
1 |
|
|
T28 |
2 |
|
T13 |
2 |
|
T15 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3844216 |
1 |
|
|
T28 |
1 |
|
T13 |
2 |
|
T2 |
9 |
| auto[1] |
auto[0] |
auto[1] |
563897 |
1 |
|
|
T104 |
136 |
|
T105 |
5 |
|
T53 |
2150 |
| auto[1] |
auto[1] |
auto[0] |
3861451 |
1 |
|
|
T28 |
1 |
|
T15 |
1 |
|
T102 |
1 |
| auto[1] |
auto[1] |
auto[1] |
567827 |
1 |
|
|
T102 |
1 |
|
T77 |
1 |
|
T100 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |