Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10970828 |
1 |
|
|
T28 |
15 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8853566 |
1 |
|
|
T28 |
1 |
|
T29 |
5 |
|
T11 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18689163 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1135231 |
1 |
|
|
T28 |
1 |
|
T30 |
2 |
|
T31 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10966168 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8858226 |
1 |
|
|
T28 |
1 |
|
T11 |
2 |
|
T13 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3870569 |
1 |
|
|
T13 |
2 |
|
T18 |
3 |
|
T102 |
3 |
| auto[1] |
auto[0] |
auto[1] |
568905 |
1 |
|
|
T30 |
1 |
|
T82 |
5 |
|
T6 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3852426 |
1 |
|
|
T11 |
2 |
|
T2 |
13 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[1] |
566326 |
1 |
|
|
T28 |
1 |
|
T30 |
1 |
|
T31 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10953352 |
1 |
|
|
T28 |
15 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8871042 |
1 |
|
|
T28 |
1 |
|
T29 |
5 |
|
T11 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18692641 |
1 |
|
|
T28 |
12 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1131753 |
1 |
|
|
T28 |
4 |
|
T13 |
1 |
|
T30 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10993700 |
1 |
|
|
T28 |
3 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8830694 |
1 |
|
|
T28 |
13 |
|
T13 |
1 |
|
T15 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3848489 |
1 |
|
|
T28 |
9 |
|
T15 |
1 |
|
T4 |
10 |
| auto[1] |
auto[0] |
auto[1] |
565544 |
1 |
|
|
T28 |
3 |
|
T13 |
1 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3850452 |
1 |
|
|
T30 |
1 |
|
T103 |
3 |
|
T31 |
1 |
| auto[1] |
auto[1] |
auto[1] |
566209 |
1 |
|
|
T28 |
1 |
|
T30 |
1 |
|
T31 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11005498 |
1 |
|
|
T28 |
12 |
|
T29 |
2 |
|
T1 |
14 |
| auto[1] |
8818896 |
1 |
|
|
T28 |
4 |
|
T29 |
10 |
|
T11 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18691218 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1133176 |
1 |
|
|
T30 |
1 |
|
T31 |
1 |
|
T6 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10973910 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8850484 |
1 |
|
|
T13 |
1 |
|
T30 |
6 |
|
T31 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3873939 |
1 |
|
|
T13 |
1 |
|
T30 |
3 |
|
T31 |
5 |
| auto[1] |
auto[0] |
auto[1] |
569450 |
1 |
|
|
T30 |
1 |
|
T6 |
2 |
|
T114 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3843369 |
1 |
|
|
T30 |
2 |
|
T31 |
3 |
|
T6 |
4 |
| auto[1] |
auto[1] |
auto[1] |
563726 |
1 |
|
|
T31 |
1 |
|
T6 |
3 |
|
T40 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10999441 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8824953 |
1 |
|
|
T28 |
1 |
|
T11 |
3 |
|
T13 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18684834 |
1 |
|
|
T28 |
11 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1139560 |
1 |
|
|
T28 |
5 |
|
T13 |
1 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10945644 |
1 |
|
|
T28 |
2 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8878750 |
1 |
|
|
T28 |
14 |
|
T11 |
1 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3870207 |
1 |
|
|
T28 |
8 |
|
T15 |
1 |
|
T102 |
2 |
| auto[1] |
auto[0] |
auto[1] |
569422 |
1 |
|
|
T28 |
5 |
|
T30 |
1 |
|
T31 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3868983 |
1 |
|
|
T28 |
1 |
|
T11 |
1 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[1] |
570138 |
1 |
|
|
T13 |
1 |
|
T2 |
2 |
|
T103 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10952993 |
1 |
|
|
T28 |
15 |
|
T29 |
9 |
|
T1 |
14 |
| auto[1] |
8871401 |
1 |
|
|
T28 |
1 |
|
T29 |
3 |
|
T11 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18689213 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1135181 |
1 |
|
|
T28 |
1 |
|
T11 |
1 |
|
T102 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10959767 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8864627 |
1 |
|
|
T28 |
1 |
|
T11 |
2 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3855978 |
1 |
|
|
T11 |
1 |
|
T13 |
1 |
|
T2 |
10 |
| auto[1] |
auto[0] |
auto[1] |
565067 |
1 |
|
|
T28 |
1 |
|
T11 |
1 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3873468 |
1 |
|
|
T102 |
1 |
|
T103 |
2 |
|
T31 |
1 |
| auto[1] |
auto[1] |
auto[1] |
570114 |
1 |
|
|
T102 |
1 |
|
T31 |
1 |
|
T6 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10958800 |
1 |
|
|
T28 |
7 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8865594 |
1 |
|
|
T28 |
9 |
|
T29 |
5 |
|
T11 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18691946 |
1 |
|
|
T28 |
12 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1132448 |
1 |
|
|
T28 |
4 |
|
T102 |
1 |
|
T30 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10989911 |
1 |
|
|
T28 |
4 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8834483 |
1 |
|
|
T28 |
12 |
|
T13 |
1 |
|
T15 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3846219 |
1 |
|
|
T28 |
2 |
|
T13 |
1 |
|
T4 |
10 |
| auto[1] |
auto[0] |
auto[1] |
563789 |
1 |
|
|
T28 |
2 |
|
T30 |
1 |
|
T31 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3855816 |
1 |
|
|
T28 |
6 |
|
T15 |
1 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[1] |
568659 |
1 |
|
|
T28 |
2 |
|
T102 |
1 |
|
T6 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10978419 |
1 |
|
|
T28 |
3 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8845975 |
1 |
|
|
T28 |
13 |
|
T14 |
14 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18686031 |
1 |
|
|
T28 |
13 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1138363 |
1 |
|
|
T28 |
3 |
|
T13 |
1 |
|
T15 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10933658 |
1 |
|
|
T28 |
2 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8890736 |
1 |
|
|
T28 |
14 |
|
T11 |
1 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3884603 |
1 |
|
|
T28 |
1 |
|
T11 |
1 |
|
T2 |
2 |
| auto[1] |
auto[0] |
auto[1] |
571274 |
1 |
|
|
T13 |
1 |
|
T2 |
1 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3867770 |
1 |
|
|
T28 |
10 |
|
T15 |
1 |
|
T18 |
2 |
| auto[1] |
auto[1] |
auto[1] |
567089 |
1 |
|
|
T28 |
3 |
|
T15 |
1 |
|
T18 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10941410 |
1 |
|
|
T28 |
12 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8882984 |
1 |
|
|
T28 |
4 |
|
T29 |
5 |
|
T11 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18694769 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1129625 |
1 |
|
|
T30 |
2 |
|
T31 |
2 |
|
T6 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10992620 |
1 |
|
|
T28 |
3 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8831774 |
1 |
|
|
T28 |
13 |
|
T15 |
1 |
|
T2 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3843044 |
1 |
|
|
T28 |
9 |
|
T2 |
3 |
|
T102 |
1 |
| auto[1] |
auto[0] |
auto[1] |
564427 |
1 |
|
|
T30 |
2 |
|
T31 |
1 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3859105 |
1 |
|
|
T28 |
4 |
|
T15 |
1 |
|
T31 |
2 |
| auto[1] |
auto[1] |
auto[1] |
565198 |
1 |
|
|
T31 |
1 |
|
T6 |
2 |
|
T113 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10979582 |
1 |
|
|
T28 |
2 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8844812 |
1 |
|
|
T28 |
14 |
|
T29 |
5 |
|
T11 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18696839 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1127555 |
1 |
|
|
T11 |
1 |
|
T13 |
1 |
|
T4 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10998718 |
1 |
|
|
T28 |
14 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8825676 |
1 |
|
|
T28 |
2 |
|
T11 |
3 |
|
T13 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3849348 |
1 |
|
|
T11 |
2 |
|
T2 |
3 |
|
T4 |
8 |
| auto[1] |
auto[0] |
auto[1] |
562681 |
1 |
|
|
T13 |
1 |
|
T4 |
2 |
|
T102 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3848773 |
1 |
|
|
T28 |
2 |
|
T13 |
1 |
|
T30 |
3 |
| auto[1] |
auto[1] |
auto[1] |
564874 |
1 |
|
|
T11 |
1 |
|
T31 |
2 |
|
T6 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11007949 |
1 |
|
|
T28 |
6 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8816445 |
1 |
|
|
T28 |
10 |
|
T29 |
5 |
|
T11 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18698921 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1125473 |
1 |
|
|
T18 |
1 |
|
T30 |
3 |
|
T31 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11025683 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8798711 |
1 |
|
|
T28 |
1 |
|
T11 |
1 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3855166 |
1 |
|
|
T11 |
1 |
|
T13 |
1 |
|
T2 |
10 |
| auto[1] |
auto[0] |
auto[1] |
565164 |
1 |
|
|
T30 |
3 |
|
T31 |
2 |
|
T111 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3818072 |
1 |
|
|
T28 |
1 |
|
T15 |
2 |
|
T18 |
2 |
| auto[1] |
auto[1] |
auto[1] |
560309 |
1 |
|
|
T18 |
1 |
|
T6 |
2 |
|
T19 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10949691 |
1 |
|
|
T28 |
7 |
|
T29 |
4 |
|
T1 |
14 |
| auto[1] |
8874703 |
1 |
|
|
T28 |
9 |
|
T29 |
8 |
|
T14 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18690065 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1134329 |
1 |
|
|
T31 |
1 |
|
T6 |
2 |
|
T77 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10968373 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8856021 |
1 |
|
|
T11 |
3 |
|
T13 |
1 |
|
T15 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3866264 |
1 |
|
|
T11 |
3 |
|
T13 |
1 |
|
T102 |
2 |
| auto[1] |
auto[0] |
auto[1] |
568085 |
1 |
|
|
T31 |
1 |
|
T6 |
1 |
|
T100 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3855428 |
1 |
|
|
T15 |
1 |
|
T30 |
1 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[1] |
566244 |
1 |
|
|
T6 |
1 |
|
T77 |
1 |
|
T10 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10981273 |
1 |
|
|
T28 |
3 |
|
T29 |
10 |
|
T1 |
14 |
| auto[1] |
8843121 |
1 |
|
|
T28 |
13 |
|
T29 |
2 |
|
T11 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18693078 |
1 |
|
|
T28 |
13 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1131316 |
1 |
|
|
T28 |
3 |
|
T11 |
1 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10991978 |
1 |
|
|
T28 |
2 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8832416 |
1 |
|
|
T28 |
14 |
|
T11 |
1 |
|
T13 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3849796 |
1 |
|
|
T28 |
1 |
|
T13 |
1 |
|
T15 |
1 |
| auto[1] |
auto[0] |
auto[1] |
565164 |
1 |
|
|
T2 |
1 |
|
T6 |
2 |
|
T114 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3851304 |
1 |
|
|
T28 |
10 |
|
T13 |
1 |
|
T31 |
1 |
| auto[1] |
auto[1] |
auto[1] |
566152 |
1 |
|
|
T28 |
3 |
|
T11 |
1 |
|
T31 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11009198 |
1 |
|
|
T28 |
6 |
|
T29 |
10 |
|
T1 |
14 |
| auto[1] |
8815196 |
1 |
|
|
T28 |
10 |
|
T29 |
2 |
|
T11 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18693658 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1130736 |
1 |
|
|
T13 |
1 |
|
T2 |
2 |
|
T18 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10993474 |
1 |
|
|
T28 |
14 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8830920 |
1 |
|
|
T28 |
2 |
|
T11 |
2 |
|
T13 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3879920 |
1 |
|
|
T4 |
7 |
|
T30 |
1 |
|
T103 |
2 |
| auto[1] |
auto[0] |
auto[1] |
569784 |
1 |
|
|
T13 |
1 |
|
T4 |
3 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3820264 |
1 |
|
|
T28 |
2 |
|
T11 |
2 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
560952 |
1 |
|
|
T2 |
2 |
|
T18 |
2 |
|
T31 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10980027 |
1 |
|
|
T28 |
6 |
|
T29 |
4 |
|
T1 |
14 |
| auto[1] |
8844367 |
1 |
|
|
T28 |
10 |
|
T29 |
8 |
|
T11 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18688390 |
1 |
|
|
T28 |
14 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1136004 |
1 |
|
|
T28 |
2 |
|
T15 |
1 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10955818 |
1 |
|
|
T28 |
14 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8868576 |
1 |
|
|
T28 |
2 |
|
T11 |
3 |
|
T13 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3870068 |
1 |
|
|
T13 |
1 |
|
T18 |
3 |
|
T4 |
10 |
| auto[1] |
auto[0] |
auto[1] |
569308 |
1 |
|
|
T102 |
1 |
|
T103 |
1 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3862504 |
1 |
|
|
T11 |
3 |
|
T13 |
1 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[1] |
566696 |
1 |
|
|
T28 |
2 |
|
T15 |
1 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10957934 |
1 |
|
|
T28 |
11 |
|
T29 |
7 |
|
T1 |
14 |
| auto[1] |
8866460 |
1 |
|
|
T28 |
5 |
|
T29 |
5 |
|
T14 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18683169 |
1 |
|
|
T28 |
16 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
1141225 |
1 |
|
|
T18 |
1 |
|
T4 |
2 |
|
T102 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10941016 |
1 |
|
|
T28 |
15 |
|
T29 |
12 |
|
T1 |
14 |
| auto[1] |
8883378 |
1 |
|
|
T28 |
1 |
|
T11 |
1 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3864454 |
1 |
|
|
T28 |
1 |
|
T11 |
1 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
569345 |
1 |
|
|
T18 |
1 |
|
T4 |
2 |
|
T102 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3877699 |
1 |
|
|
T15 |
1 |
|
T30 |
2 |
|
T31 |
5 |
| auto[1] |
auto[1] |
auto[1] |
571880 |
1 |
|
|
T31 |
1 |
|
T6 |
1 |
|
T106 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |