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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.06 99.10 100.00 99.80 99.68 100.00


Total test records in report: 950
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T777 /workspace/coverage/default/36.gpio_stress_all.1239955010 Jan 03 01:00:37 PM PST 24 Jan 03 01:04:50 PM PST 24 36789760335 ps
T778 /workspace/coverage/default/9.gpio_rand_intr_trigger.3529625204 Jan 03 12:59:37 PM PST 24 Jan 03 01:00:30 PM PST 24 77744373 ps
T779 /workspace/coverage/default/32.gpio_intr_rand_pgm.2146607728 Jan 03 01:00:35 PM PST 24 Jan 03 01:01:41 PM PST 24 27251182 ps
T780 /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.184652224 Jan 03 01:01:26 PM PST 24 Jan 03 01:02:41 PM PST 24 1344334051 ps
T781 /workspace/coverage/default/27.gpio_intr_rand_pgm.587493593 Jan 03 01:00:54 PM PST 24 Jan 03 01:01:58 PM PST 24 138137737 ps
T782 /workspace/coverage/default/48.gpio_smoke.3138352923 Jan 03 01:01:19 PM PST 24 Jan 03 01:02:26 PM PST 24 48367965 ps
T783 /workspace/coverage/default/45.gpio_stress_all.2286247707 Jan 03 01:00:54 PM PST 24 Jan 03 01:03:38 PM PST 24 14669923071 ps
T784 /workspace/coverage/default/37.gpio_smoke.1631376784 Jan 03 01:00:40 PM PST 24 Jan 03 01:01:45 PM PST 24 48827262 ps
T785 /workspace/coverage/default/3.gpio_full_random.3228031752 Jan 03 12:59:33 PM PST 24 Jan 03 01:00:26 PM PST 24 503026602 ps
T786 /workspace/coverage/default/2.gpio_stress_all.2610507068 Jan 03 12:59:21 PM PST 24 Jan 03 01:02:12 PM PST 24 4193533875 ps
T787 /workspace/coverage/default/28.gpio_smoke.4120681611 Jan 03 01:00:34 PM PST 24 Jan 03 01:01:41 PM PST 24 155005046 ps
T788 /workspace/coverage/default/46.gpio_random_dout_din.1301988894 Jan 03 01:00:56 PM PST 24 Jan 03 01:01:59 PM PST 24 115965231 ps
T789 /workspace/coverage/default/27.gpio_rand_intr_trigger.3434605449 Jan 03 01:00:57 PM PST 24 Jan 03 01:02:02 PM PST 24 125105922 ps
T790 /workspace/coverage/default/13.gpio_intr_rand_pgm.1349488519 Jan 03 12:59:43 PM PST 24 Jan 03 01:00:41 PM PST 24 135102936 ps
T791 /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1224750401 Jan 03 12:59:28 PM PST 24 Jan 03 01:00:23 PM PST 24 122953529 ps
T792 /workspace/coverage/default/43.gpio_filter_stress.2218720083 Jan 03 01:01:14 PM PST 24 Jan 03 01:02:36 PM PST 24 1296909901 ps
T793 /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.4087851466 Jan 03 01:00:57 PM PST 24 Jan 03 01:02:00 PM PST 24 53096021 ps
T794 /workspace/coverage/default/16.gpio_full_random.56714434 Jan 03 12:59:57 PM PST 24 Jan 03 01:00:59 PM PST 24 75290669 ps
T795 /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3177736493 Jan 03 01:00:53 PM PST 24 Jan 03 01:17:57 PM PST 24 83446730663 ps
T796 /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2494907875 Jan 03 01:00:16 PM PST 24 Jan 03 01:19:59 PM PST 24 67717625136 ps
T797 /workspace/coverage/default/2.gpio_rand_intr_trigger.935439150 Jan 03 12:59:23 PM PST 24 Jan 03 01:00:19 PM PST 24 163563719 ps
T798 /workspace/coverage/default/41.gpio_smoke.966725995 Jan 03 01:00:55 PM PST 24 Jan 03 01:01:58 PM PST 24 67921153 ps
T799 /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.965227870 Jan 03 12:59:53 PM PST 24 Jan 03 01:00:53 PM PST 24 126549990 ps
T800 /workspace/coverage/default/9.gpio_filter_stress.3195574520 Jan 03 12:59:35 PM PST 24 Jan 03 01:00:38 PM PST 24 1492703309 ps
T801 /workspace/coverage/default/6.gpio_alert_test.1836235489 Jan 03 12:59:39 PM PST 24 Jan 03 01:00:34 PM PST 24 74868073 ps
T802 /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.2735312280 Jan 03 01:00:50 PM PST 24 Jan 03 01:12:19 PM PST 24 351061188281 ps
T803 /workspace/coverage/default/3.gpio_stress_all.3908181897 Jan 03 12:59:33 PM PST 24 Jan 03 01:02:57 PM PST 24 13599804797 ps
T804 /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3802873746 Jan 03 01:01:10 PM PST 24 Jan 03 01:02:18 PM PST 24 61002969 ps
T805 /workspace/coverage/default/31.gpio_smoke.2633005907 Jan 03 01:00:57 PM PST 24 Jan 03 01:02:01 PM PST 24 70992243 ps
T806 /workspace/coverage/default/40.gpio_filter_stress.2901137964 Jan 03 01:00:59 PM PST 24 Jan 03 01:02:26 PM PST 24 1961769839 ps
T807 /workspace/coverage/default/12.gpio_random_dout_din.39547206 Jan 03 12:59:50 PM PST 24 Jan 03 01:00:51 PM PST 24 182328324 ps
T808 /workspace/coverage/default/0.gpio_alert_test.3621703215 Jan 03 12:59:04 PM PST 24 Jan 03 12:59:49 PM PST 24 14965977 ps
T809 /workspace/coverage/default/17.gpio_stress_all.1271521882 Jan 03 12:59:49 PM PST 24 Jan 03 01:03:49 PM PST 24 33035508256 ps
T810 /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4230937689 Jan 03 12:59:33 PM PST 24 Jan 03 01:00:27 PM PST 24 24336685 ps
T811 /workspace/coverage/default/22.gpio_intr_rand_pgm.3200148179 Jan 03 12:59:57 PM PST 24 Jan 03 01:00:59 PM PST 24 23711201 ps
T812 /workspace/coverage/default/22.gpio_rand_intr_trigger.74801503 Jan 03 01:00:01 PM PST 24 Jan 03 01:01:07 PM PST 24 478679043 ps
T813 /workspace/coverage/default/22.gpio_random_dout_din.428199172 Jan 03 01:00:00 PM PST 24 Jan 03 01:01:06 PM PST 24 858730823 ps
T814 /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3108749607 Jan 03 01:00:37 PM PST 24 Jan 03 01:01:45 PM PST 24 78401001 ps
T815 /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3445002117 Jan 03 12:59:26 PM PST 24 Jan 03 01:00:24 PM PST 24 365940625 ps
T816 /workspace/coverage/default/30.gpio_rand_intr_trigger.1515286749 Jan 03 01:00:33 PM PST 24 Jan 03 01:01:43 PM PST 24 728754942 ps
T817 /workspace/coverage/default/22.gpio_smoke.2651301596 Jan 03 01:00:48 PM PST 24 Jan 03 01:01:52 PM PST 24 133552214 ps
T818 /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1382875264 Jan 03 01:01:19 PM PST 24 Jan 03 01:02:27 PM PST 24 45404729 ps
T819 /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1899903848 Jan 03 12:59:15 PM PST 24 Jan 03 01:00:12 PM PST 24 1107013968 ps
T820 /workspace/coverage/default/25.gpio_smoke.3566017149 Jan 03 01:00:32 PM PST 24 Jan 03 01:01:40 PM PST 24 206091205 ps
T821 /workspace/coverage/default/2.gpio_filter_stress.1167069042 Jan 03 12:59:33 PM PST 24 Jan 03 01:00:32 PM PST 24 281213935 ps
T822 /workspace/coverage/default/0.gpio_intr_rand_pgm.2620798519 Jan 03 12:59:11 PM PST 24 Jan 03 01:00:06 PM PST 24 76350616 ps
T823 /workspace/coverage/default/33.gpio_smoke.3839636287 Jan 03 01:00:38 PM PST 24 Jan 03 01:01:44 PM PST 24 99569771 ps
T62 /workspace/coverage/default/4.gpio_sec_cm.884171984 Jan 03 12:59:42 PM PST 24 Jan 03 01:00:39 PM PST 24 112328995 ps
T824 /workspace/coverage/default/21.gpio_filter_stress.1874545732 Jan 03 01:00:25 PM PST 24 Jan 03 01:01:41 PM PST 24 607774911 ps
T825 /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.227030108 Jan 03 12:59:59 PM PST 24 Jan 03 01:17:32 PM PST 24 70136506921 ps
T826 /workspace/coverage/default/16.gpio_alert_test.964706395 Jan 03 01:01:19 PM PST 24 Jan 03 01:02:26 PM PST 24 16368631 ps
T827 /workspace/coverage/default/18.gpio_intr_rand_pgm.762206524 Jan 03 01:00:00 PM PST 24 Jan 03 01:01:05 PM PST 24 46839862 ps
T828 /workspace/coverage/default/25.gpio_intr_rand_pgm.27129358 Jan 03 01:00:34 PM PST 24 Jan 03 01:01:42 PM PST 24 114250467 ps
T829 /workspace/coverage/default/17.gpio_random_dout_din.1236128209 Jan 03 12:59:44 PM PST 24 Jan 03 01:00:42 PM PST 24 78288934 ps
T830 /workspace/coverage/default/1.gpio_smoke.2791527748 Jan 03 12:59:07 PM PST 24 Jan 03 12:59:55 PM PST 24 53234609 ps
T831 /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1577752990 Jan 03 01:00:33 PM PST 24 Jan 03 01:01:41 PM PST 24 83547973 ps
T832 /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3570939922 Jan 03 01:00:31 PM PST 24 Jan 03 01:01:42 PM PST 24 1654717967 ps
T833 /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.4196740032 Jan 03 01:00:32 PM PST 24 Jan 03 01:01:43 PM PST 24 309287328 ps
T834 /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1349616153 Jan 03 12:59:50 PM PST 24 Jan 03 01:00:52 PM PST 24 374470325 ps
T835 /workspace/coverage/default/34.gpio_smoke.1284374995 Jan 03 01:01:05 PM PST 24 Jan 03 01:02:12 PM PST 24 323624408 ps
T836 /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1073394052 Jan 03 01:01:16 PM PST 24 Jan 03 01:04:50 PM PST 24 9070453515 ps
T837 /workspace/coverage/default/41.gpio_rand_intr_trigger.375143814 Jan 03 01:01:18 PM PST 24 Jan 03 01:02:25 PM PST 24 172908374 ps
T838 /workspace/coverage/default/8.gpio_rand_intr_trigger.1359401980 Jan 03 12:59:31 PM PST 24 Jan 03 01:00:26 PM PST 24 109097096 ps
T839 /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1599825768 Jan 03 01:00:50 PM PST 24 Jan 03 01:01:55 PM PST 24 265777116 ps
T840 /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.4288936693 Jan 03 12:59:49 PM PST 24 Jan 03 01:00:51 PM PST 24 1624285937 ps
T841 /workspace/coverage/default/21.gpio_stress_all.3134162368 Jan 03 01:00:35 PM PST 24 Jan 03 01:03:24 PM PST 24 4354589586 ps
T842 /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.516854918 Jan 03 01:01:20 PM PST 24 Jan 03 01:02:28 PM PST 24 56133407 ps
T843 /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3808310651 Jan 03 12:59:43 PM PST 24 Jan 03 01:00:41 PM PST 24 163709248 ps
T844 /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1950686795 Jan 03 01:00:54 PM PST 24 Jan 03 01:01:57 PM PST 24 15933008 ps
T845 /workspace/coverage/default/19.gpio_rand_intr_trigger.3899617542 Jan 03 12:59:58 PM PST 24 Jan 03 01:01:02 PM PST 24 28416792 ps
T846 /workspace/coverage/default/34.gpio_filter_stress.1799414722 Jan 03 01:01:14 PM PST 24 Jan 03 01:02:31 PM PST 24 216416353 ps
T847 /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.868791092 Jan 03 01:00:06 PM PST 24 Jan 03 01:01:12 PM PST 24 52660245 ps
T848 /workspace/coverage/default/26.gpio_smoke.3668403410 Jan 03 01:00:55 PM PST 24 Jan 03 01:01:58 PM PST 24 63231995 ps
T849 /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2715768842 Jan 03 12:59:02 PM PST 24 Jan 03 12:59:45 PM PST 24 116712495 ps
T850 /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4265655792 Jan 03 01:01:13 PM PST 24 Jan 03 01:02:20 PM PST 24 134963690 ps
T851 /workspace/coverage/default/45.gpio_intr_rand_pgm.780591852 Jan 03 01:00:55 PM PST 24 Jan 03 01:01:58 PM PST 24 50411062 ps
T852 /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1246951865 Jan 03 12:59:00 PM PST 24 Jan 03 12:59:42 PM PST 24 57604242 ps
T853 /workspace/coverage/default/24.gpio_intr_rand_pgm.1194958394 Jan 03 01:00:37 PM PST 24 Jan 03 01:01:43 PM PST 24 35389778 ps
T854 /workspace/coverage/default/0.gpio_smoke.783475159 Jan 03 12:59:01 PM PST 24 Jan 03 12:59:44 PM PST 24 287164351 ps
T855 /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.778959825 Jan 03 01:00:51 PM PST 24 Jan 03 01:12:15 PM PST 24 146049597963 ps
T856 /workspace/coverage/default/19.gpio_filter_stress.3000961091 Jan 03 12:59:59 PM PST 24 Jan 03 01:01:09 PM PST 24 935609845 ps
T857 /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.243181084 Jan 03 01:00:52 PM PST 24 Jan 03 01:01:55 PM PST 24 88923688 ps
T858 /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1463716880 Jan 03 12:59:49 PM PST 24 Jan 03 01:00:48 PM PST 24 22714900 ps
T859 /workspace/coverage/default/25.gpio_rand_intr_trigger.3809198637 Jan 03 01:00:35 PM PST 24 Jan 03 01:01:44 PM PST 24 509207924 ps
T860 /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.859184232 Jan 03 12:59:38 PM PST 24 Jan 03 01:00:33 PM PST 24 56182367 ps
T861 /workspace/coverage/default/29.gpio_random_dout_din.1019483829 Jan 03 01:00:52 PM PST 24 Jan 03 01:01:55 PM PST 24 18249211 ps
T862 /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3553103969 Jan 03 01:00:32 PM PST 24 Jan 03 01:01:40 PM PST 24 147796148 ps
T863 /workspace/coverage/default/41.gpio_intr_rand_pgm.2893617604 Jan 03 01:01:15 PM PST 24 Jan 03 01:02:22 PM PST 24 242951579 ps
T864 /workspace/coverage/default/35.gpio_intr_rand_pgm.1527611547 Jan 03 01:00:31 PM PST 24 Jan 03 01:01:39 PM PST 24 690545425 ps
T865 /workspace/coverage/default/16.gpio_stress_all.2564129842 Jan 03 12:59:55 PM PST 24 Jan 03 01:02:25 PM PST 24 35032654244 ps
T866 /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.629405590 Jan 03 12:59:58 PM PST 24 Jan 03 01:01:01 PM PST 24 50528463 ps
T867 /workspace/coverage/default/36.gpio_intr_rand_pgm.4131064612 Jan 03 01:00:51 PM PST 24 Jan 03 01:01:55 PM PST 24 614957055 ps
T868 /workspace/coverage/default/40.gpio_alert_test.1743467401 Jan 03 01:00:59 PM PST 24 Jan 03 01:02:06 PM PST 24 43344726 ps
T869 /workspace/coverage/default/27.gpio_filter_stress.10961633 Jan 03 01:01:11 PM PST 24 Jan 03 01:02:36 PM PST 24 3926864050 ps
T870 /workspace/coverage/default/7.gpio_intr_rand_pgm.3484988227 Jan 03 12:59:34 PM PST 24 Jan 03 01:00:28 PM PST 24 75056180 ps
T871 /workspace/coverage/default/49.gpio_random_dout_din.929993856 Jan 03 01:00:55 PM PST 24 Jan 03 01:01:58 PM PST 24 46312716 ps
T872 /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1836735906 Jan 03 01:00:37 PM PST 24 Jan 03 01:05:24 PM PST 24 15926061179 ps
T873 /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.856561616 Jan 03 01:00:39 PM PST 24 Jan 03 01:01:44 PM PST 24 179244695 ps
T874 /workspace/coverage/default/46.gpio_stress_all.3822326185 Jan 03 01:01:01 PM PST 24 Jan 03 01:05:50 PM PST 24 15933568798 ps
T875 /workspace/coverage/default/44.gpio_stress_all.4175200002 Jan 03 01:01:16 PM PST 24 Jan 03 01:04:26 PM PST 24 9916282718 ps
T876 /workspace/coverage/default/29.gpio_filter_stress.755135955 Jan 03 01:00:44 PM PST 24 Jan 03 01:02:15 PM PST 24 780267676 ps
T877 /workspace/coverage/default/8.gpio_full_random.2280161575 Jan 03 12:59:26 PM PST 24 Jan 03 01:00:21 PM PST 24 361505219 ps
T878 /workspace/coverage/default/20.gpio_rand_intr_trigger.2919350090 Jan 03 01:00:14 PM PST 24 Jan 03 01:01:27 PM PST 24 476439997 ps
T879 /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1201610659 Jan 03 12:59:35 PM PST 24 Jan 03 01:00:30 PM PST 24 156111600 ps
T880 /workspace/coverage/default/0.gpio_full_random.2168618812 Jan 03 12:59:04 PM PST 24 Jan 03 12:59:49 PM PST 24 61307582 ps
T881 /workspace/coverage/cover_reg_top/9.gpio_intr_test.49713586 Jan 03 12:26:44 PM PST 24 Jan 03 12:26:46 PM PST 24 52750314 ps
T101 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1299303991 Jan 03 12:28:13 PM PST 24 Jan 03 12:28:21 PM PST 24 25896338 ps
T882 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1650855503 Jan 03 12:29:27 PM PST 24 Jan 03 12:29:59 PM PST 24 53649833 ps
T79 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3774197785 Jan 03 12:34:58 PM PST 24 Jan 03 12:36:34 PM PST 24 21610787 ps
T883 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2812212569 Jan 03 12:29:53 PM PST 24 Jan 03 12:30:35 PM PST 24 38272148 ps
T107 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1488455425 Jan 03 12:29:31 PM PST 24 Jan 03 12:30:05 PM PST 24 255821746 ps
T884 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.836965871 Jan 03 12:30:40 PM PST 24 Jan 03 12:31:45 PM PST 24 112869103 ps
T885 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2045445695 Jan 03 12:35:21 PM PST 24 Jan 03 12:36:56 PM PST 24 129334583 ps
T886 /workspace/coverage/cover_reg_top/47.gpio_intr_test.4069187271 Jan 03 12:28:41 PM PST 24 Jan 03 12:29:02 PM PST 24 31075615 ps
T887 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1750981164 Jan 03 12:28:19 PM PST 24 Jan 03 12:28:31 PM PST 24 52903732 ps
T35 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1838782794 Jan 03 12:30:08 PM PST 24 Jan 03 12:30:55 PM PST 24 63301078 ps
T888 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1088273098 Jan 03 12:29:10 PM PST 24 Jan 03 12:29:38 PM PST 24 36364101 ps
T80 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2564425702 Jan 03 12:29:51 PM PST 24 Jan 03 12:30:33 PM PST 24 14199876 ps
T889 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2102678536 Jan 03 12:26:29 PM PST 24 Jan 03 12:26:30 PM PST 24 15708726 ps
T890 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1433427825 Jan 03 12:30:25 PM PST 24 Jan 03 12:31:21 PM PST 24 17065410 ps
T891 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1532542058 Jan 03 12:29:57 PM PST 24 Jan 03 12:30:43 PM PST 24 4348500481 ps
T83 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1756112680 Jan 03 12:27:08 PM PST 24 Jan 03 12:27:10 PM PST 24 14595997 ps
T84 /workspace/coverage/cover_reg_top/29.gpio_intr_test.4046026060 Jan 03 12:29:30 PM PST 24 Jan 03 12:30:03 PM PST 24 19567474 ps
T85 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.60801265 Jan 03 12:30:26 PM PST 24 Jan 03 12:31:24 PM PST 24 17585940 ps
T86 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3862703848 Jan 03 12:29:07 PM PST 24 Jan 03 12:29:35 PM PST 24 40394464 ps
T87 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.844574079 Jan 03 12:30:11 PM PST 24 Jan 03 12:30:59 PM PST 24 35809111 ps
T892 /workspace/coverage/cover_reg_top/25.gpio_intr_test.533200680 Jan 03 12:28:51 PM PST 24 Jan 03 12:29:20 PM PST 24 30452908 ps
T37 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.760815955 Jan 03 12:32:16 PM PST 24 Jan 03 12:33:42 PM PST 24 72464615 ps
T88 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2881850080 Jan 03 12:32:21 PM PST 24 Jan 03 12:33:50 PM PST 24 53506195 ps
T93 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1181754139 Jan 03 12:26:46 PM PST 24 Jan 03 12:26:56 PM PST 24 52652899 ps
T94 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2575415165 Jan 03 12:29:49 PM PST 24 Jan 03 12:30:32 PM PST 24 38953871 ps
T36 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2558903738 Jan 03 12:30:18 PM PST 24 Jan 03 12:31:10 PM PST 24 170936954 ps
T95 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1674927660 Jan 03 12:29:16 PM PST 24 Jan 03 12:29:45 PM PST 24 348795353 ps
T96 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3526316684 Jan 03 12:28:13 PM PST 24 Jan 03 12:28:21 PM PST 24 16855198 ps
T97 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3795790402 Jan 03 12:39:29 PM PST 24 Jan 03 12:41:06 PM PST 24 15383775 ps
T92 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.755437620 Jan 03 12:28:59 PM PST 24 Jan 03 12:29:26 PM PST 24 20042070 ps
T98 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3215162836 Jan 03 12:29:18 PM PST 24 Jan 03 12:29:48 PM PST 24 189481885 ps
T99 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3744885105 Jan 03 12:31:33 PM PST 24 Jan 03 12:32:52 PM PST 24 29803414 ps
T893 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.337332534 Jan 03 12:35:40 PM PST 24 Jan 03 12:37:25 PM PST 24 41191405 ps
T894 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.426453900 Jan 03 12:29:34 PM PST 24 Jan 03 12:30:10 PM PST 24 84210821 ps
T895 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3270887937 Jan 03 12:28:22 PM PST 24 Jan 03 12:28:31 PM PST 24 262550239 ps
T896 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3296903853 Jan 03 12:23:47 PM PST 24 Jan 03 12:23:49 PM PST 24 17241150 ps
T897 /workspace/coverage/cover_reg_top/0.gpio_intr_test.514898465 Jan 03 12:29:40 PM PST 24 Jan 03 12:30:18 PM PST 24 16594273 ps
T898 /workspace/coverage/cover_reg_top/43.gpio_intr_test.2066498577 Jan 03 12:27:16 PM PST 24 Jan 03 12:27:20 PM PST 24 19229599 ps
T899 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2210558837 Jan 03 12:28:41 PM PST 24 Jan 03 12:29:02 PM PST 24 12957895 ps
T900 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1566525904 Jan 03 12:29:20 PM PST 24 Jan 03 12:29:51 PM PST 24 27393192 ps
T901 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3264095498 Jan 03 12:29:38 PM PST 24 Jan 03 12:30:16 PM PST 24 197785462 ps
T902 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3514448233 Jan 03 12:26:45 PM PST 24 Jan 03 12:26:54 PM PST 24 16825426 ps
T903 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2318635922 Jan 03 12:27:37 PM PST 24 Jan 03 12:27:42 PM PST 24 19241930 ps
T904 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1828350988 Jan 03 12:28:53 PM PST 24 Jan 03 12:29:21 PM PST 24 14645299 ps
T905 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2931002359 Jan 03 12:29:58 PM PST 24 Jan 03 12:30:42 PM PST 24 20833130 ps
T906 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1176861104 Jan 03 12:26:47 PM PST 24 Jan 03 12:26:56 PM PST 24 215343841 ps
T907 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.681667189 Jan 03 12:30:18 PM PST 24 Jan 03 12:31:10 PM PST 24 114711957 ps
T908 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3847309852 Jan 03 12:35:12 PM PST 24 Jan 03 12:36:35 PM PST 24 26307049 ps
T909 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1627285443 Jan 03 12:29:13 PM PST 24 Jan 03 12:29:42 PM PST 24 77157471 ps
T89 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.876270880 Jan 03 12:37:19 PM PST 24 Jan 03 12:38:44 PM PST 24 32630693 ps
T910 /workspace/coverage/cover_reg_top/48.gpio_intr_test.1929747253 Jan 03 12:28:40 PM PST 24 Jan 03 12:29:00 PM PST 24 46934215 ps
T911 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.709301169 Jan 03 12:29:03 PM PST 24 Jan 03 12:29:30 PM PST 24 49205294 ps
T912 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3697567611 Jan 03 12:30:51 PM PST 24 Jan 03 12:32:03 PM PST 24 120605423 ps
T913 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1968880654 Jan 03 12:29:08 PM PST 24 Jan 03 12:29:36 PM PST 24 124327316 ps
T914 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3297932180 Jan 03 12:29:43 PM PST 24 Jan 03 12:30:24 PM PST 24 42523203 ps
T915 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1009290881 Jan 03 12:26:34 PM PST 24 Jan 03 12:26:35 PM PST 24 48614110 ps
T41 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.289391313 Jan 03 12:30:00 PM PST 24 Jan 03 12:30:46 PM PST 24 79919173 ps
T916 /workspace/coverage/cover_reg_top/11.gpio_intr_test.4278278572 Jan 03 12:26:44 PM PST 24 Jan 03 12:26:46 PM PST 24 168512299 ps
T917 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2224182574 Jan 03 12:30:33 PM PST 24 Jan 03 12:31:35 PM PST 24 50863027 ps
T918 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2171631058 Jan 03 12:29:21 PM PST 24 Jan 03 12:29:51 PM PST 24 466882512 ps
T919 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2803032424 Jan 03 12:28:48 PM PST 24 Jan 03 12:29:18 PM PST 24 18466973 ps
T920 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3835812866 Jan 03 12:29:42 PM PST 24 Jan 03 12:30:21 PM PST 24 11612621 ps
T921 /workspace/coverage/cover_reg_top/44.gpio_intr_test.810672388 Jan 03 12:30:23 PM PST 24 Jan 03 12:31:19 PM PST 24 54326599 ps
T922 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2165589938 Jan 03 12:28:41 PM PST 24 Jan 03 12:29:01 PM PST 24 28292064 ps
T90 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.629647980 Jan 03 12:29:42 PM PST 24 Jan 03 12:30:23 PM PST 24 16449418 ps
T923 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4018344288 Jan 03 12:29:23 PM PST 24 Jan 03 12:29:56 PM PST 24 166282642 ps
T924 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3608907400 Jan 03 12:25:46 PM PST 24 Jan 03 12:25:48 PM PST 24 84067677 ps
T925 /workspace/coverage/cover_reg_top/46.gpio_intr_test.2204965105 Jan 03 12:29:57 PM PST 24 Jan 03 12:30:41 PM PST 24 12377038 ps
T926 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1621145709 Jan 03 12:28:45 PM PST 24 Jan 03 12:29:15 PM PST 24 22010312 ps
T927 /workspace/coverage/cover_reg_top/12.gpio_intr_test.2195474389 Jan 03 12:29:37 PM PST 24 Jan 03 12:30:14 PM PST 24 11297113 ps
T928 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4289590100 Jan 03 12:28:31 PM PST 24 Jan 03 12:28:45 PM PST 24 47442421 ps
T929 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2667918499 Jan 03 12:28:49 PM PST 24 Jan 03 12:29:19 PM PST 24 15318313 ps
T930 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.221649384 Jan 03 12:31:13 PM PST 24 Jan 03 12:32:19 PM PST 24 45883195 ps
T931 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1132801172 Jan 03 12:29:27 PM PST 24 Jan 03 12:29:59 PM PST 24 36798008 ps
T91 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3340732381 Jan 03 12:29:36 PM PST 24 Jan 03 12:30:13 PM PST 24 58873738 ps
T932 /workspace/coverage/cover_reg_top/6.gpio_intr_test.717564941 Jan 03 12:28:48 PM PST 24 Jan 03 12:29:18 PM PST 24 11923660 ps
T933 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3468270965 Jan 03 12:29:50 PM PST 24 Jan 03 12:30:32 PM PST 24 126117754 ps
T934 /workspace/coverage/cover_reg_top/34.gpio_intr_test.2503147468 Jan 03 12:29:04 PM PST 24 Jan 03 12:29:31 PM PST 24 34550536 ps
T935 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.59977828 Jan 03 12:39:12 PM PST 24 Jan 03 12:40:40 PM PST 24 48060915 ps
T936 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.539905398 Jan 03 12:26:47 PM PST 24 Jan 03 12:26:56 PM PST 24 125763055 ps
T937 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2800057356 Jan 03 12:32:23 PM PST 24 Jan 03 12:33:57 PM PST 24 10576098 ps
T938 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2696180103 Jan 03 12:29:30 PM PST 24 Jan 03 12:30:04 PM PST 24 22707945 ps
T939 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1666331118 Jan 03 12:29:15 PM PST 24 Jan 03 12:29:44 PM PST 24 22191137 ps
T940 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1380058536 Jan 03 12:28:41 PM PST 24 Jan 03 12:29:01 PM PST 24 14753895 ps
T941 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3876315238 Jan 03 12:26:29 PM PST 24 Jan 03 12:26:31 PM PST 24 39388209 ps
T942 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1592193590 Jan 03 12:27:51 PM PST 24 Jan 03 12:27:55 PM PST 24 35705608 ps
T943 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1842244604 Jan 03 12:29:28 PM PST 24 Jan 03 12:30:01 PM PST 24 64847078 ps
T944 /workspace/coverage/cover_reg_top/14.gpio_intr_test.2128969652 Jan 03 12:29:04 PM PST 24 Jan 03 12:29:31 PM PST 24 20398459 ps
T945 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.747290732 Jan 03 12:29:22 PM PST 24 Jan 03 12:29:54 PM PST 24 474855980 ps
T946 /workspace/coverage/cover_reg_top/8.gpio_intr_test.1302449165 Jan 03 12:35:03 PM PST 24 Jan 03 12:36:53 PM PST 24 10461451 ps
T947 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3410133076 Jan 03 12:35:22 PM PST 24 Jan 03 12:37:03 PM PST 24 35358426 ps
T948 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.253559464 Jan 03 12:29:47 PM PST 24 Jan 03 12:30:29 PM PST 24 149356342 ps
T949 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3399706543 Jan 03 12:29:16 PM PST 24 Jan 03 12:29:45 PM PST 24 19874426 ps
T950 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2953055529 Jan 03 12:29:02 PM PST 24 Jan 03 12:29:29 PM PST 24 175356039 ps

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.774674766
Short name T2
Test name
Test status
Simulation time 128392035 ps
CPU time 0.82 seconds
Started Jan 03 12:29:49 PM PST 24
Finished Jan 03 12:30:32 PM PST 24
Peak memory 197828 kb
Host smart-439eaeff-4ac4-46c5-b563-1c5af58ae19d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774674766 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.774674766
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1817737636
Short name T54
Test name
Test status
Simulation time 348950882 ps
CPU time 1.44 seconds
Started Jan 03 12:33:21 PM PST 24
Finished Jan 03 12:34:42 PM PST 24
Peak memory 197564 kb
Host smart-589ba55c-508b-4786-a832-162bd3da002a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1817737636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1817737636
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.4255789908
Short name T46
Test name
Test status
Simulation time 76156687 ps
CPU time 0.91 seconds
Started Jan 03 01:00:01 PM PST 24
Finished Jan 03 01:01:05 PM PST 24
Peak memory 196100 kb
Host smart-2da7c8c4-7059-4702-966b-6100c6afc3c4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255789908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.4255789908
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3822874754
Short name T53
Test name
Test status
Simulation time 47255875127 ps
CPU time 125.41 seconds
Started Jan 03 12:59:23 PM PST 24
Finished Jan 03 01:02:23 PM PST 24
Peak memory 198228 kb
Host smart-b6cafd77-a437-41da-b4b7-6092a5084bd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822874754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3822874754
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2916118073
Short name T31
Test name
Test status
Simulation time 116644150 ps
CPU time 1.37 seconds
Started Jan 03 12:28:57 PM PST 24
Finished Jan 03 12:29:24 PM PST 24
Peak memory 198244 kb
Host smart-06c4623c-abd4-455a-a889-11577889e65a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916118073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2916118073
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1393020997
Short name T14
Test name
Test status
Simulation time 27755585 ps
CPU time 0.62 seconds
Started Jan 03 12:39:39 PM PST 24
Finished Jan 03 12:41:03 PM PST 24
Peak memory 194144 kb
Host smart-ad3e708a-f2b8-4b07-8486-5d5822ed34b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393020997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1393020997
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1660430945
Short name T23
Test name
Test status
Simulation time 34044905 ps
CPU time 1.57 seconds
Started Jan 03 12:29:27 PM PST 24
Finished Jan 03 12:30:01 PM PST 24
Peak memory 197964 kb
Host smart-ae5375ac-08fa-4d0c-aa2a-92d05dedaa1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660430945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1660430945
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3302064030
Short name T38
Test name
Test status
Simulation time 40895503 ps
CPU time 0.61 seconds
Started Jan 03 12:30:05 PM PST 24
Finished Jan 03 12:30:50 PM PST 24
Peak memory 195632 kb
Host smart-50d32965-9cc7-4e44-a4dc-0ea3bb431665
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302064030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3302064030
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.951295189
Short name T61
Test name
Test status
Simulation time 323553406 ps
CPU time 0.93 seconds
Started Jan 03 12:59:07 PM PST 24
Finished Jan 03 12:59:56 PM PST 24
Peak memory 214700 kb
Host smart-b28bc401-e2b2-442c-ba3f-5e7c59b32521
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951295189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.951295189
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2881850080
Short name T88
Test name
Test status
Simulation time 53506195 ps
CPU time 0.64 seconds
Started Jan 03 12:32:21 PM PST 24
Finished Jan 03 12:33:50 PM PST 24
Peak memory 195168 kb
Host smart-0c90d5f4-d89f-48bb-81fe-d912cd41e63e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881850080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2881850080
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2749114018
Short name T6
Test name
Test status
Simulation time 600539847 ps
CPU time 1.44 seconds
Started Jan 03 12:28:53 PM PST 24
Finished Jan 03 12:29:22 PM PST 24
Peak memory 196732 kb
Host smart-ff95b1a1-2ef9-446a-9bc4-f13c54f21745
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749114018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2749114018
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3080387296
Short name T116
Test name
Test status
Simulation time 1237468426 ps
CPU time 2.96 seconds
Started Jan 03 12:59:01 PM PST 24
Finished Jan 03 12:59:46 PM PST 24
Peak memory 198240 kb
Host smart-4d294ab7-f79c-4340-a374-877e3604f8eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080387296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3080387296
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1636947728
Short name T333
Test name
Test status
Simulation time 67228237 ps
CPU time 0.56 seconds
Started Jan 03 12:59:06 PM PST 24
Finished Jan 03 12:59:53 PM PST 24
Peak memory 194272 kb
Host smart-0309e912-3285-4b65-bc94-3ae68f2849b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636947728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1636947728
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2438506740
Short name T110
Test name
Test status
Simulation time 79568992 ps
CPU time 1.21 seconds
Started Jan 03 12:32:45 PM PST 24
Finished Jan 03 12:34:49 PM PST 24
Peak memory 196284 kb
Host smart-4d6427de-002f-4955-ab93-da08d87870d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2438506740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2438506740
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1307532681
Short name T280
Test name
Test status
Simulation time 156682999899 ps
CPU time 866.63 seconds
Started Jan 03 12:59:49 PM PST 24
Finished Jan 03 01:15:14 PM PST 24
Peak memory 198300 kb
Host smart-7f264546-ed5d-469f-bcba-b5ed22ac8418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1307532681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1307532681
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2171631058
Short name T918
Test name
Test status
Simulation time 466882512 ps
CPU time 1.31 seconds
Started Jan 03 12:29:21 PM PST 24
Finished Jan 03 12:29:51 PM PST 24
Peak memory 197864 kb
Host smart-92b05ff8-e5a3-4149-a8f0-70d2ceede428
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171631058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2171631058
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3693952519
Short name T117
Test name
Test status
Simulation time 43456103 ps
CPU time 0.58 seconds
Started Jan 03 12:27:17 PM PST 24
Finished Jan 03 12:27:20 PM PST 24
Peak memory 193448 kb
Host smart-6954673f-8a7e-4e5a-82fe-ec265917f5c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693952519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3693952519
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/default/20.gpio_full_random.1108747373
Short name T45
Test name
Test status
Simulation time 45543940 ps
CPU time 0.84 seconds
Started Jan 03 01:00:22 PM PST 24
Finished Jan 03 01:01:32 PM PST 24
Peak memory 196040 kb
Host smart-a5e6e59f-5413-4d09-a73f-fc3e2d9f9bf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108747373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1108747373
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.629647980
Short name T90
Test name
Test status
Simulation time 16449418 ps
CPU time 0.63 seconds
Started Jan 03 12:29:42 PM PST 24
Finished Jan 03 12:30:23 PM PST 24
Peak memory 194780 kb
Host smart-3e91fcfd-c0c7-483f-8d33-d251defdeb58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629647980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.629647980
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1532542058
Short name T891
Test name
Test status
Simulation time 4348500481 ps
CPU time 2.47 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:30:43 PM PST 24
Peak memory 198192 kb
Host smart-a6e6fc78-859c-47cb-975a-790ad89f4754
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532542058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1532542058
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1674927660
Short name T95
Test name
Test status
Simulation time 348795353 ps
CPU time 0.68 seconds
Started Jan 03 12:29:16 PM PST 24
Finished Jan 03 12:29:45 PM PST 24
Peak memory 197724 kb
Host smart-89f7bf8e-e89a-4ab3-b3e7-140a18722474
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674927660 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1674927660
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3835812866
Short name T920
Test name
Test status
Simulation time 11612621 ps
CPU time 0.58 seconds
Started Jan 03 12:29:42 PM PST 24
Finished Jan 03 12:30:21 PM PST 24
Peak memory 194616 kb
Host smart-f2a1ee71-6dfd-410b-a68f-86afb7bedc26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835812866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3835812866
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.514898465
Short name T897
Test name
Test status
Simulation time 16594273 ps
CPU time 0.58 seconds
Started Jan 03 12:29:40 PM PST 24
Finished Jan 03 12:30:18 PM PST 24
Peak memory 193916 kb
Host smart-7c00c07d-4ed3-4367-aa0e-51b968b2d2b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514898465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.514898465
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3399706543
Short name T949
Test name
Test status
Simulation time 19874426 ps
CPU time 0.69 seconds
Started Jan 03 12:29:16 PM PST 24
Finished Jan 03 12:29:45 PM PST 24
Peak memory 194660 kb
Host smart-f04643e5-7796-4093-9b5e-327bdf2ffb77
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399706543 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3399706543
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3862703848
Short name T86
Test name
Test status
Simulation time 40394464 ps
CPU time 1.82 seconds
Started Jan 03 12:29:07 PM PST 24
Finished Jan 03 12:29:35 PM PST 24
Peak memory 198168 kb
Host smart-ff477b6b-3824-4c72-995a-20fbe6337d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862703848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3862703848
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1555684024
Short name T112
Test name
Test status
Simulation time 64962745 ps
CPU time 0.84 seconds
Started Jan 03 12:28:46 PM PST 24
Finished Jan 03 12:29:15 PM PST 24
Peak memory 197800 kb
Host smart-9d74417d-7a5c-42e2-bc00-388750b8cd39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555684024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1555684024
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1421387334
Short name T125
Test name
Test status
Simulation time 90021253 ps
CPU time 1.4 seconds
Started Jan 03 12:28:54 PM PST 24
Finished Jan 03 12:29:22 PM PST 24
Peak memory 198120 kb
Host smart-c807ea4a-24f2-4f52-a7bf-366ad5662b4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421387334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1421387334
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3675520947
Short name T5
Test name
Test status
Simulation time 20719449 ps
CPU time 0.6 seconds
Started Jan 03 12:30:26 PM PST 24
Finished Jan 03 12:31:24 PM PST 24
Peak memory 197048 kb
Host smart-983a2b28-813f-491c-a352-00de85799a0d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675520947 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3675520947
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1181754139
Short name T93
Test name
Test status
Simulation time 52652899 ps
CPU time 0.61 seconds
Started Jan 03 12:26:46 PM PST 24
Finished Jan 03 12:26:56 PM PST 24
Peak memory 195068 kb
Host smart-097211a3-4c41-4f47-961c-2afe736d5be0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181754139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1181754139
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3161898474
Short name T81
Test name
Test status
Simulation time 51495476 ps
CPU time 0.58 seconds
Started Jan 03 12:30:48 PM PST 24
Finished Jan 03 12:31:54 PM PST 24
Peak memory 193912 kb
Host smart-ddb5aaf7-91fb-4280-a0c3-a7f72e80e134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161898474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3161898474
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1299303991
Short name T101
Test name
Test status
Simulation time 25896338 ps
CPU time 0.82 seconds
Started Jan 03 12:28:13 PM PST 24
Finished Jan 03 12:28:21 PM PST 24
Peak memory 194652 kb
Host smart-5a547eba-41de-411f-b064-af7a652d0e29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299303991 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1299303991
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1750981164
Short name T887
Test name
Test status
Simulation time 52903732 ps
CPU time 2.38 seconds
Started Jan 03 12:28:19 PM PST 24
Finished Jan 03 12:28:31 PM PST 24
Peak memory 198256 kb
Host smart-b038b159-a77b-4676-ab26-161dc3031b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750981164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1750981164
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1488455425
Short name T107
Test name
Test status
Simulation time 255821746 ps
CPU time 1.09 seconds
Started Jan 03 12:29:31 PM PST 24
Finished Jan 03 12:30:05 PM PST 24
Peak memory 198176 kb
Host smart-8c24eaee-69db-4e68-b0f7-f43443f8ec2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488455425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1488455425
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.221649384
Short name T930
Test name
Test status
Simulation time 45883195 ps
CPU time 0.8 seconds
Started Jan 03 12:31:13 PM PST 24
Finished Jan 03 12:32:19 PM PST 24
Peak memory 198140 kb
Host smart-8df19e13-6ac6-492c-8cd1-0a1ac34a3b71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221649384 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.221649384
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1088273098
Short name T888
Test name
Test status
Simulation time 36364101 ps
CPU time 0.6 seconds
Started Jan 03 12:29:10 PM PST 24
Finished Jan 03 12:29:38 PM PST 24
Peak memory 194680 kb
Host smart-74d59aa2-19c9-4ddf-916f-272c39dc5461
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088273098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1088273098
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3297932180
Short name T914
Test name
Test status
Simulation time 42523203 ps
CPU time 0.55 seconds
Started Jan 03 12:29:43 PM PST 24
Finished Jan 03 12:30:24 PM PST 24
Peak memory 193872 kb
Host smart-04e3100f-37a9-4cf5-a25e-3f90f2a0d575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297932180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3297932180
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2575415165
Short name T94
Test name
Test status
Simulation time 38953871 ps
CPU time 0.65 seconds
Started Jan 03 12:29:49 PM PST 24
Finished Jan 03 12:30:32 PM PST 24
Peak memory 195308 kb
Host smart-eba9b2f7-b706-4103-9bf0-aea9b810daae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575415165 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2575415165
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3488825513
Short name T75
Test name
Test status
Simulation time 59069889 ps
CPU time 0.98 seconds
Started Jan 03 12:29:58 PM PST 24
Finished Jan 03 12:30:43 PM PST 24
Peak memory 198016 kb
Host smart-2b1e3a45-d7e6-4b04-9542-1b7fed43db50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488825513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3488825513
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1176861104
Short name T906
Test name
Test status
Simulation time 215343841 ps
CPU time 1.43 seconds
Started Jan 03 12:26:47 PM PST 24
Finished Jan 03 12:26:56 PM PST 24
Peak memory 198152 kb
Host smart-48f2f242-9485-4a6b-8445-decd2e71e19d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176861104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1176861104
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1829933265
Short name T11
Test name
Test status
Simulation time 15486988 ps
CPU time 0.59 seconds
Started Jan 03 12:29:11 PM PST 24
Finished Jan 03 12:29:39 PM PST 24
Peak memory 194788 kb
Host smart-46693182-418a-4f0c-bed9-b81f8e59ff14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829933265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1829933265
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.4278278572
Short name T916
Test name
Test status
Simulation time 168512299 ps
CPU time 0.6 seconds
Started Jan 03 12:26:44 PM PST 24
Finished Jan 03 12:26:46 PM PST 24
Peak memory 194664 kb
Host smart-97788075-aca5-4ade-beb7-ed38036a205a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278278572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.4278278572
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4053675570
Short name T82
Test name
Test status
Simulation time 20896444 ps
CPU time 0.65 seconds
Started Jan 03 12:31:43 PM PST 24
Finished Jan 03 12:33:09 PM PST 24
Peak memory 195072 kb
Host smart-87498af6-8064-440b-9a78-59a547fb9a94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053675570 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.4053675570
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.836965871
Short name T884
Test name
Test status
Simulation time 112869103 ps
CPU time 2.35 seconds
Started Jan 03 12:30:40 PM PST 24
Finished Jan 03 12:31:45 PM PST 24
Peak memory 198308 kb
Host smart-aab76a6f-6054-40fb-b1fc-7da42f06eed7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836965871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.836965871
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3697567611
Short name T912
Test name
Test status
Simulation time 120605423 ps
CPU time 1.27 seconds
Started Jan 03 12:30:51 PM PST 24
Finished Jan 03 12:32:03 PM PST 24
Peak memory 198000 kb
Host smart-575d5ec8-10e6-42a2-b5e7-cb1731e70c79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697567611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3697567611
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2224182574
Short name T917
Test name
Test status
Simulation time 50863027 ps
CPU time 0.87 seconds
Started Jan 03 12:30:33 PM PST 24
Finished Jan 03 12:31:35 PM PST 24
Peak memory 198004 kb
Host smart-a427ba9e-36a4-4493-a094-48a4cb716f6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224182574 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2224182574
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.549008490
Short name T10
Test name
Test status
Simulation time 39761037 ps
CPU time 0.58 seconds
Started Jan 03 12:29:01 PM PST 24
Finished Jan 03 12:29:29 PM PST 24
Peak memory 194780 kb
Host smart-2cd96f64-9bae-4840-aafb-a26f4c4c4711
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549008490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.549008490
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2195474389
Short name T927
Test name
Test status
Simulation time 11297113 ps
CPU time 0.56 seconds
Started Jan 03 12:29:37 PM PST 24
Finished Jan 03 12:30:14 PM PST 24
Peak memory 193896 kb
Host smart-4a65af0e-9b63-4ecd-b1ae-52c915a845ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195474389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2195474389
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3744885105
Short name T99
Test name
Test status
Simulation time 29803414 ps
CPU time 0.79 seconds
Started Jan 03 12:31:33 PM PST 24
Finished Jan 03 12:32:52 PM PST 24
Peak memory 196480 kb
Host smart-8ee6fe89-9931-43ac-84dd-4f8dfb863d6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744885105 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3744885105
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.337332534
Short name T893
Test name
Test status
Simulation time 41191405 ps
CPU time 1.05 seconds
Started Jan 03 12:35:40 PM PST 24
Finished Jan 03 12:37:25 PM PST 24
Peak memory 198308 kb
Host smart-82286268-fc41-4a5f-a2ff-c8b11befda25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337332534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.337332534
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.844574079
Short name T87
Test name
Test status
Simulation time 35809111 ps
CPU time 0.99 seconds
Started Jan 03 12:30:11 PM PST 24
Finished Jan 03 12:30:59 PM PST 24
Peak memory 196716 kb
Host smart-924b2b95-d40f-4ccd-8726-ff73d09cd93f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844574079 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.844574079
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.876270880
Short name T89
Test name
Test status
Simulation time 32630693 ps
CPU time 0.58 seconds
Started Jan 03 12:37:19 PM PST 24
Finished Jan 03 12:38:44 PM PST 24
Peak memory 195208 kb
Host smart-34110097-4a30-4eb9-a4e4-e1f6b0eba46d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876270880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.876270880
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2045445695
Short name T885
Test name
Test status
Simulation time 129334583 ps
CPU time 0.59 seconds
Started Jan 03 12:35:21 PM PST 24
Finished Jan 03 12:36:56 PM PST 24
Peak memory 194704 kb
Host smart-07cb1191-3233-4809-8780-48b8408057c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045445695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2045445695
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1566525904
Short name T900
Test name
Test status
Simulation time 27393192 ps
CPU time 0.71 seconds
Started Jan 03 12:29:20 PM PST 24
Finished Jan 03 12:29:51 PM PST 24
Peak memory 194880 kb
Host smart-2bf68cf8-6f4a-40f2-87f2-e278b741813d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566525904 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1566525904
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4018344288
Short name T923
Test name
Test status
Simulation time 166282642 ps
CPU time 2.47 seconds
Started Jan 03 12:29:23 PM PST 24
Finished Jan 03 12:29:56 PM PST 24
Peak memory 198040 kb
Host smart-cf141e47-4879-43a5-92ec-156e89af8506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018344288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.4018344288
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2576914828
Short name T40
Test name
Test status
Simulation time 142069359 ps
CPU time 1.1 seconds
Started Jan 03 12:28:51 PM PST 24
Finished Jan 03 12:29:21 PM PST 24
Peak memory 198364 kb
Host smart-af09fc0b-de93-485d-a7e0-9043f1e547f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576914828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2576914828
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1968880654
Short name T913
Test name
Test status
Simulation time 124327316 ps
CPU time 0.9 seconds
Started Jan 03 12:29:08 PM PST 24
Finished Jan 03 12:29:36 PM PST 24
Peak memory 198116 kb
Host smart-301063c3-8546-41c6-ad70-87de87d6dc7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968880654 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1968880654
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.59977828
Short name T935
Test name
Test status
Simulation time 48060915 ps
CPU time 0.56 seconds
Started Jan 03 12:39:12 PM PST 24
Finished Jan 03 12:40:40 PM PST 24
Peak memory 193488 kb
Host smart-fe4d6d19-39d3-41fd-9c22-31f1958e7415
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59977828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_
csr_rw.59977828
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2128969652
Short name T944
Test name
Test status
Simulation time 20398459 ps
CPU time 0.57 seconds
Started Jan 03 12:29:04 PM PST 24
Finished Jan 03 12:29:31 PM PST 24
Peak memory 193976 kb
Host smart-d8349e8e-39c7-44bc-bdba-6659f0a02298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128969652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2128969652
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2402213468
Short name T77
Test name
Test status
Simulation time 41635718 ps
CPU time 0.79 seconds
Started Jan 03 12:29:30 PM PST 24
Finished Jan 03 12:30:05 PM PST 24
Peak memory 196592 kb
Host smart-11e5d900-bb93-43bc-add0-fdbbb131e570
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402213468 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2402213468
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3608907400
Short name T924
Test name
Test status
Simulation time 84067677 ps
CPU time 1.94 seconds
Started Jan 03 12:25:46 PM PST 24
Finished Jan 03 12:25:48 PM PST 24
Peak memory 198500 kb
Host smart-b22a56bc-a612-4139-8bf9-e3eb75bdb779
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608907400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3608907400
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.760815955
Short name T37
Test name
Test status
Simulation time 72464615 ps
CPU time 1.03 seconds
Started Jan 03 12:32:16 PM PST 24
Finished Jan 03 12:33:42 PM PST 24
Peak memory 197816 kb
Host smart-9ba53457-44ca-4589-8547-42e09f19c525
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760815955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.760815955
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2128678108
Short name T7
Test name
Test status
Simulation time 26526122 ps
CPU time 0.81 seconds
Started Jan 03 12:24:44 PM PST 24
Finished Jan 03 12:24:46 PM PST 24
Peak memory 198092 kb
Host smart-a93f13d4-0c0b-49cf-845f-fef011378127
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128678108 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2128678108
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1433427825
Short name T890
Test name
Test status
Simulation time 17065410 ps
CPU time 0.59 seconds
Started Jan 03 12:30:25 PM PST 24
Finished Jan 03 12:31:21 PM PST 24
Peak memory 194536 kb
Host smart-932295d0-9a8c-425f-a989-718b16cae424
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433427825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1433427825
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2595480406
Short name T29
Test name
Test status
Simulation time 177500273 ps
CPU time 0.57 seconds
Started Jan 03 12:24:44 PM PST 24
Finished Jan 03 12:24:46 PM PST 24
Peak memory 193896 kb
Host smart-023561b1-b130-4166-9878-1f8b58baaf0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595480406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2595480406
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.4060346093
Short name T4
Test name
Test status
Simulation time 28511277 ps
CPU time 0.77 seconds
Started Jan 03 12:29:28 PM PST 24
Finished Jan 03 12:30:02 PM PST 24
Peak memory 196692 kb
Host smart-c4075f56-4a34-461f-ba14-70bc05a57c31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060346093 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.4060346093
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.747290732
Short name T945
Test name
Test status
Simulation time 474855980 ps
CPU time 1.31 seconds
Started Jan 03 12:29:22 PM PST 24
Finished Jan 03 12:29:54 PM PST 24
Peak memory 196924 kb
Host smart-2c4abc27-3888-48ac-86cd-cc3742df116e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747290732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.747290732
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1842244604
Short name T943
Test name
Test status
Simulation time 64847078 ps
CPU time 0.83 seconds
Started Jan 03 12:29:28 PM PST 24
Finished Jan 03 12:30:01 PM PST 24
Peak memory 197824 kb
Host smart-be9a7dfc-bf44-4d95-a7a9-c0d93c2d048d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842244604 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1842244604
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.158323467
Short name T128
Test name
Test status
Simulation time 46699607 ps
CPU time 0.58 seconds
Started Jan 03 12:27:37 PM PST 24
Finished Jan 03 12:27:41 PM PST 24
Peak memory 193404 kb
Host smart-6e30177d-36d2-4980-a53d-60caedc70be2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158323467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.158323467
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1132801172
Short name T931
Test name
Test status
Simulation time 36798008 ps
CPU time 0.56 seconds
Started Jan 03 12:29:27 PM PST 24
Finished Jan 03 12:29:59 PM PST 24
Peak memory 193660 kb
Host smart-746c8246-ba99-43da-bb7f-de53c5d9c73e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132801172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1132801172
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2318635922
Short name T903
Test name
Test status
Simulation time 19241930 ps
CPU time 0.73 seconds
Started Jan 03 12:27:37 PM PST 24
Finished Jan 03 12:27:42 PM PST 24
Peak memory 196280 kb
Host smart-092b3713-a6e3-40c7-9c0c-f4b5d09d8a3c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318635922 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2318635922
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1650855503
Short name T882
Test name
Test status
Simulation time 53649833 ps
CPU time 0.87 seconds
Started Jan 03 12:29:27 PM PST 24
Finished Jan 03 12:29:59 PM PST 24
Peak memory 197776 kb
Host smart-b262b649-7011-49b9-a911-3af0a7bce549
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650855503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1650855503
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2953055529
Short name T950
Test name
Test status
Simulation time 175356039 ps
CPU time 1.07 seconds
Started Jan 03 12:29:02 PM PST 24
Finished Jan 03 12:29:29 PM PST 24
Peak memory 197996 kb
Host smart-2b6aa673-b2dd-41bf-9408-8bc9aad9b12c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953055529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2953055529
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3876315238
Short name T941
Test name
Test status
Simulation time 39388209 ps
CPU time 0.59 seconds
Started Jan 03 12:26:29 PM PST 24
Finished Jan 03 12:26:31 PM PST 24
Peak memory 196480 kb
Host smart-2c2a9ad7-661d-43fe-a5e6-d7cdfc639ee2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876315238 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3876315238
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1666331118
Short name T939
Test name
Test status
Simulation time 22191137 ps
CPU time 0.58 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:29:44 PM PST 24
Peak memory 195120 kb
Host smart-904ef9e7-8a46-4ce7-b3f3-567a42a37348
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666331118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1666331118
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3296903853
Short name T896
Test name
Test status
Simulation time 17241150 ps
CPU time 0.58 seconds
Started Jan 03 12:23:47 PM PST 24
Finished Jan 03 12:23:49 PM PST 24
Peak memory 194604 kb
Host smart-e99edbba-7bba-4ef6-87a5-654886722774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296903853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3296903853
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2878207136
Short name T100
Test name
Test status
Simulation time 46663208 ps
CPU time 0.75 seconds
Started Jan 03 12:30:07 PM PST 24
Finished Jan 03 12:30:54 PM PST 24
Peak memory 195696 kb
Host smart-1ad28ac4-ffca-4896-b756-d20f233e5969
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878207136 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2878207136
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3224133748
Short name T74
Test name
Test status
Simulation time 50113093 ps
CPU time 1.32 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:29:45 PM PST 24
Peak memory 197936 kb
Host smart-2224fb0c-7dc9-47b9-a6ef-fd6f5b0ad760
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224133748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3224133748
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1838782794
Short name T35
Test name
Test status
Simulation time 63301078 ps
CPU time 1.02 seconds
Started Jan 03 12:30:08 PM PST 24
Finished Jan 03 12:30:55 PM PST 24
Peak memory 197928 kb
Host smart-4f622eec-5003-44c3-af48-c89a63d68ce5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838782794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1838782794
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2102678536
Short name T889
Test name
Test status
Simulation time 15708726 ps
CPU time 0.6 seconds
Started Jan 03 12:26:29 PM PST 24
Finished Jan 03 12:26:30 PM PST 24
Peak memory 196548 kb
Host smart-ed2b3ea5-2122-4d0a-8de5-5e50473a9e2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102678536 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2102678536
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.357002338
Short name T78
Test name
Test status
Simulation time 34690574 ps
CPU time 0.57 seconds
Started Jan 03 12:29:14 PM PST 24
Finished Jan 03 12:29:42 PM PST 24
Peak memory 195204 kb
Host smart-9021b2a4-13eb-4181-8e84-dac49fabb92e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357002338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.357002338
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2564425702
Short name T80
Test name
Test status
Simulation time 14199876 ps
CPU time 0.62 seconds
Started Jan 03 12:29:51 PM PST 24
Finished Jan 03 12:30:33 PM PST 24
Peak memory 194820 kb
Host smart-4b49e69d-ab63-4423-a5f5-75ca15859951
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564425702 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2564425702
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.253559464
Short name T948
Test name
Test status
Simulation time 149356342 ps
CPU time 2.02 seconds
Started Jan 03 12:29:47 PM PST 24
Finished Jan 03 12:30:29 PM PST 24
Peak memory 198016 kb
Host smart-505fb4e0-de0d-4a01-a2aa-ad103538d1e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253559464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.253559464
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.681667189
Short name T907
Test name
Test status
Simulation time 114711957 ps
CPU time 0.79 seconds
Started Jan 03 12:30:18 PM PST 24
Finished Jan 03 12:31:10 PM PST 24
Peak memory 197676 kb
Host smart-50e0cc7c-128a-4c1a-82ac-88f18efd792e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681667189 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.681667189
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1592193590
Short name T942
Test name
Test status
Simulation time 35705608 ps
CPU time 0.58 seconds
Started Jan 03 12:27:51 PM PST 24
Finished Jan 03 12:27:55 PM PST 24
Peak memory 193908 kb
Host smart-c169508d-6215-4044-8865-78fb52479ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592193590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1592193590
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3410133076
Short name T947
Test name
Test status
Simulation time 35358426 ps
CPU time 0.58 seconds
Started Jan 03 12:35:22 PM PST 24
Finished Jan 03 12:37:03 PM PST 24
Peak memory 194740 kb
Host smart-8bb4c956-7cd2-4e98-966d-c07007d860d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410133076 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3410133076
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.744404485
Short name T8
Test name
Test status
Simulation time 1901230465 ps
CPU time 2.74 seconds
Started Jan 03 12:30:17 PM PST 24
Finished Jan 03 12:31:11 PM PST 24
Peak memory 197628 kb
Host smart-9e2736b0-3020-4759-9d6c-177963e880ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744404485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.744404485
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2558903738
Short name T36
Test name
Test status
Simulation time 170936954 ps
CPU time 1.35 seconds
Started Jan 03 12:30:18 PM PST 24
Finished Jan 03 12:31:10 PM PST 24
Peak memory 197800 kb
Host smart-eb8b58c9-c9a3-4ba9-9463-b882e6122267
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558903738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2558903738
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1360806377
Short name T111
Test name
Test status
Simulation time 20687177 ps
CPU time 0.73 seconds
Started Jan 03 12:29:17 PM PST 24
Finished Jan 03 12:29:45 PM PST 24
Peak memory 196468 kb
Host smart-e5f5a302-5550-4f54-a560-dd17eaab3d2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360806377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1360806377
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4061284706
Short name T24
Test name
Test status
Simulation time 57054255 ps
CPU time 2.1 seconds
Started Jan 03 12:29:01 PM PST 24
Finished Jan 03 12:29:29 PM PST 24
Peak memory 197260 kb
Host smart-3795132b-cd45-446f-8f33-e0ab906b1afb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061284706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.4061284706
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3081334833
Short name T20
Test name
Test status
Simulation time 15482333 ps
CPU time 0.58 seconds
Started Jan 03 12:29:25 PM PST 24
Finished Jan 03 12:29:56 PM PST 24
Peak memory 194280 kb
Host smart-8cea2db4-a81e-421a-afdc-c073ff0900dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081334833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3081334833
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1648824282
Short name T15
Test name
Test status
Simulation time 246056036 ps
CPU time 0.96 seconds
Started Jan 03 12:29:23 PM PST 24
Finished Jan 03 12:29:55 PM PST 24
Peak memory 197860 kb
Host smart-cf555966-46c1-4ffe-b575-9e090ad27e88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648824282 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1648824282
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3795790402
Short name T97
Test name
Test status
Simulation time 15383775 ps
CPU time 0.61 seconds
Started Jan 03 12:39:29 PM PST 24
Finished Jan 03 12:41:06 PM PST 24
Peak memory 194752 kb
Host smart-8a739fcd-8578-4869-b9ae-c351752ba3d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795790402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3795790402
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.899329790
Short name T108
Test name
Test status
Simulation time 69861543 ps
CPU time 0.56 seconds
Started Jan 03 12:29:17 PM PST 24
Finished Jan 03 12:29:46 PM PST 24
Peak memory 193820 kb
Host smart-cbf374f4-a792-40ba-8939-9924220543d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899329790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.899329790
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2803032424
Short name T919
Test name
Test status
Simulation time 18466973 ps
CPU time 0.61 seconds
Started Jan 03 12:28:48 PM PST 24
Finished Jan 03 12:29:18 PM PST 24
Peak memory 194684 kb
Host smart-34646238-b0dd-4069-a9e3-5f99f4ce5fd2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803032424 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2803032424
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.426453900
Short name T894
Test name
Test status
Simulation time 84210821 ps
CPU time 1.15 seconds
Started Jan 03 12:29:34 PM PST 24
Finished Jan 03 12:30:10 PM PST 24
Peak memory 198280 kb
Host smart-1d97318e-d7ff-4fcd-addb-f7fa2fb6232c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426453900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.426453900
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1621145709
Short name T926
Test name
Test status
Simulation time 22010312 ps
CPU time 0.56 seconds
Started Jan 03 12:28:45 PM PST 24
Finished Jan 03 12:29:15 PM PST 24
Peak memory 194036 kb
Host smart-cffde3ae-8235-40ca-8599-e1ee93766cc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621145709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1621145709
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2667918499
Short name T929
Test name
Test status
Simulation time 15318313 ps
CPU time 0.57 seconds
Started Jan 03 12:28:49 PM PST 24
Finished Jan 03 12:29:19 PM PST 24
Peak memory 194528 kb
Host smart-00f4e119-f1b7-4081-86eb-0dd339d56775
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667918499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2667918499
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1939589728
Short name T26
Test name
Test status
Simulation time 53917667 ps
CPU time 0.59 seconds
Started Jan 03 12:30:18 PM PST 24
Finished Jan 03 12:31:10 PM PST 24
Peak memory 193516 kb
Host smart-c8360acc-931a-4027-b3f3-7ce9c3b217f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939589728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1939589728
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3712662862
Short name T126
Test name
Test status
Simulation time 43470578 ps
CPU time 0.54 seconds
Started Jan 03 12:36:02 PM PST 24
Finished Jan 03 12:37:35 PM PST 24
Peak memory 194588 kb
Host smart-f597f52a-897a-45f0-bedb-3d49de35fe6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712662862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3712662862
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.533200680
Short name T892
Test name
Test status
Simulation time 30452908 ps
CPU time 0.6 seconds
Started Jan 03 12:28:51 PM PST 24
Finished Jan 03 12:29:20 PM PST 24
Peak memory 194732 kb
Host smart-54d360d6-bc11-428d-9922-5de226653d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533200680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.533200680
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2099345623
Short name T21
Test name
Test status
Simulation time 43067110 ps
CPU time 0.58 seconds
Started Jan 03 12:36:03 PM PST 24
Finished Jan 03 12:37:51 PM PST 24
Peak memory 194740 kb
Host smart-a982bb75-3113-4747-8dcf-a9132b37680b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099345623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2099345623
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2725038679
Short name T124
Test name
Test status
Simulation time 48429849 ps
CPU time 0.6 seconds
Started Jan 03 12:29:59 PM PST 24
Finished Jan 03 12:30:44 PM PST 24
Peak memory 193936 kb
Host smart-89d64524-6467-4769-9c67-c2c9ba0214bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725038679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2725038679
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.4046026060
Short name T84
Test name
Test status
Simulation time 19567474 ps
CPU time 0.61 seconds
Started Jan 03 12:29:30 PM PST 24
Finished Jan 03 12:30:03 PM PST 24
Peak memory 193928 kb
Host smart-22d323f3-4d3a-4f64-9994-c287cdd19786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046026060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.4046026060
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1756112680
Short name T83
Test name
Test status
Simulation time 14595997 ps
CPU time 0.65 seconds
Started Jan 03 12:27:08 PM PST 24
Finished Jan 03 12:27:10 PM PST 24
Peak memory 194372 kb
Host smart-1e86ff04-2322-427c-9575-29c0c6f31cfc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756112680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1756112680
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3779769372
Short name T119
Test name
Test status
Simulation time 82220478 ps
CPU time 2.83 seconds
Started Jan 03 12:31:34 PM PST 24
Finished Jan 03 12:32:54 PM PST 24
Peak memory 196912 kb
Host smart-6fdf4341-9b76-424e-8883-fcd9de39af8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779769372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3779769372
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3340732381
Short name T91
Test name
Test status
Simulation time 58873738 ps
CPU time 0.63 seconds
Started Jan 03 12:29:36 PM PST 24
Finished Jan 03 12:30:13 PM PST 24
Peak memory 194656 kb
Host smart-e60fcb61-0b64-4460-83e1-c1c2d7bf2deb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340732381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3340732381
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4289590100
Short name T928
Test name
Test status
Simulation time 47442421 ps
CPU time 0.65 seconds
Started Jan 03 12:28:31 PM PST 24
Finished Jan 03 12:28:45 PM PST 24
Peak memory 197076 kb
Host smart-c3d72bd5-c808-4548-bd35-cb55f7ac7a26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289590100 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.4289590100
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.610038665
Short name T102
Test name
Test status
Simulation time 14553475 ps
CPU time 0.58 seconds
Started Jan 03 12:28:56 PM PST 24
Finished Jan 03 12:29:23 PM PST 24
Peak memory 195336 kb
Host smart-fc8f53e0-c03f-41e7-ba25-503e4aff6d01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610038665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.610038665
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2800057356
Short name T937
Test name
Test status
Simulation time 10576098 ps
CPU time 0.55 seconds
Started Jan 03 12:32:23 PM PST 24
Finished Jan 03 12:33:57 PM PST 24
Peak memory 193700 kb
Host smart-0c3f40d4-7eb7-4676-bdd1-7c262cfb489a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800057356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2800057356
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2971327485
Short name T18
Test name
Test status
Simulation time 40907138 ps
CPU time 0.6 seconds
Started Jan 03 12:29:23 PM PST 24
Finished Jan 03 12:29:54 PM PST 24
Peak memory 195016 kb
Host smart-a0d2fb37-6ce4-404a-ac3a-59da3da84fc8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971327485 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2971327485
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1950623081
Short name T3
Test name
Test status
Simulation time 744592141 ps
CPU time 1.15 seconds
Started Jan 03 12:29:40 PM PST 24
Finished Jan 03 12:30:19 PM PST 24
Peak memory 198336 kb
Host smart-4f65be5a-eff8-4d2c-8143-016658961447
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950623081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1950623081
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1009290881
Short name T915
Test name
Test status
Simulation time 48614110 ps
CPU time 0.9 seconds
Started Jan 03 12:26:34 PM PST 24
Finished Jan 03 12:26:35 PM PST 24
Peak memory 198064 kb
Host smart-ffdb899d-e579-4ab7-aa09-3c5bf08a5c78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009290881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1009290881
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3847309852
Short name T908
Test name
Test status
Simulation time 26307049 ps
CPU time 0.54 seconds
Started Jan 03 12:35:12 PM PST 24
Finished Jan 03 12:36:35 PM PST 24
Peak memory 193596 kb
Host smart-4bc7ba21-ca3c-4424-a2d6-339d8b0b7e61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847309852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3847309852
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1156560314
Short name T122
Test name
Test status
Simulation time 11485808 ps
CPU time 0.59 seconds
Started Jan 03 12:29:55 PM PST 24
Finished Jan 03 12:30:38 PM PST 24
Peak memory 193880 kb
Host smart-23cecf6a-282c-4043-b8ee-867d1f5756aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156560314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1156560314
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2503147468
Short name T934
Test name
Test status
Simulation time 34550536 ps
CPU time 0.59 seconds
Started Jan 03 12:29:04 PM PST 24
Finished Jan 03 12:29:31 PM PST 24
Peak memory 194468 kb
Host smart-a3646763-8593-4ba2-bf74-4a59076229ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503147468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2503147468
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.530542601
Short name T118
Test name
Test status
Simulation time 39081826 ps
CPU time 0.59 seconds
Started Jan 03 12:30:14 PM PST 24
Finished Jan 03 12:31:03 PM PST 24
Peak memory 194248 kb
Host smart-bc63685f-21a4-417d-9d20-5c078ff0f6e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530542601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.530542601
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.166159656
Short name T27
Test name
Test status
Simulation time 62069891 ps
CPU time 0.63 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:30:41 PM PST 24
Peak memory 192420 kb
Host smart-d904bcab-9768-409f-815a-ce3476f5c40e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166159656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.166159656
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1190462164
Short name T120
Test name
Test status
Simulation time 12373830 ps
CPU time 0.59 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:30:41 PM PST 24
Peak memory 193768 kb
Host smart-32a4a8bf-79d3-439a-b508-7b53c42a8e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190462164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1190462164
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3339906482
Short name T123
Test name
Test status
Simulation time 15180752 ps
CPU time 0.59 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:02 PM PST 24
Peak memory 193616 kb
Host smart-194f1cd7-916d-4d9d-8685-ed3ee88a7095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339906482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3339906482
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.527509182
Short name T113
Test name
Test status
Simulation time 88771007 ps
CPU time 0.76 seconds
Started Jan 03 12:28:46 PM PST 24
Finished Jan 03 12:29:15 PM PST 24
Peak memory 196376 kb
Host smart-fd21a136-c65b-43a6-b71c-0872703d0bad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527509182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.527509182
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2168260535
Short name T76
Test name
Test status
Simulation time 36609899 ps
CPU time 1.44 seconds
Started Jan 03 12:27:09 PM PST 24
Finished Jan 03 12:27:13 PM PST 24
Peak memory 198164 kb
Host smart-7d07edb1-6358-4ea4-8961-2ee1a791e77c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168260535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2168260535
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3313246461
Short name T1
Test name
Test status
Simulation time 21411831 ps
CPU time 0.65 seconds
Started Jan 03 12:29:17 PM PST 24
Finished Jan 03 12:29:46 PM PST 24
Peak memory 195400 kb
Host smart-63f4c032-3612-4a2e-9199-9b9a3ec9195e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313246461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3313246461
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1627285443
Short name T909
Test name
Test status
Simulation time 77157471 ps
CPU time 1.1 seconds
Started Jan 03 12:29:13 PM PST 24
Finished Jan 03 12:29:42 PM PST 24
Peak memory 198296 kb
Host smart-a4c2b929-db09-4eb5-aaf0-1a5a3d07e170
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627285443 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1627285443
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3323241671
Short name T103
Test name
Test status
Simulation time 11850024 ps
CPU time 0.62 seconds
Started Jan 03 12:28:26 PM PST 24
Finished Jan 03 12:28:37 PM PST 24
Peak memory 194916 kb
Host smart-0407941b-797f-444a-8ced-389557bf6634
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323241671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3323241671
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2033147926
Short name T127
Test name
Test status
Simulation time 17878538 ps
CPU time 0.66 seconds
Started Jan 03 12:26:24 PM PST 24
Finished Jan 03 12:26:25 PM PST 24
Peak memory 194840 kb
Host smart-5e907851-ac2e-42fb-af65-ba41d58ebb11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033147926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2033147926
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1828350988
Short name T904
Test name
Test status
Simulation time 14645299 ps
CPU time 0.58 seconds
Started Jan 03 12:28:53 PM PST 24
Finished Jan 03 12:29:21 PM PST 24
Peak memory 194808 kb
Host smart-7c0e9477-fdef-4089-8c57-cddb4c16b9fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828350988 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1828350988
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3264095498
Short name T901
Test name
Test status
Simulation time 197785462 ps
CPU time 1.21 seconds
Started Jan 03 12:29:38 PM PST 24
Finished Jan 03 12:30:16 PM PST 24
Peak memory 197708 kb
Host smart-d5d19185-8b92-401c-8d7d-39d956d566b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264095498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3264095498
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3270887937
Short name T895
Test name
Test status
Simulation time 262550239 ps
CPU time 1.08 seconds
Started Jan 03 12:28:22 PM PST 24
Finished Jan 03 12:28:31 PM PST 24
Peak memory 198128 kb
Host smart-874c961b-6d27-4205-b8b6-7edb95cc4e86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270887937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3270887937
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2931002359
Short name T905
Test name
Test status
Simulation time 20833130 ps
CPU time 0.57 seconds
Started Jan 03 12:29:58 PM PST 24
Finished Jan 03 12:30:42 PM PST 24
Peak memory 194120 kb
Host smart-09c53f98-0a9b-4066-b451-203e8508a340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931002359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2931002359
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3366943597
Short name T25
Test name
Test status
Simulation time 15100666 ps
CPU time 0.67 seconds
Started Jan 03 12:27:16 PM PST 24
Finished Jan 03 12:27:20 PM PST 24
Peak memory 191960 kb
Host smart-0ac1e51f-5f17-4552-9c85-69aa5119066d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366943597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3366943597
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3526316684
Short name T96
Test name
Test status
Simulation time 16855198 ps
CPU time 0.6 seconds
Started Jan 03 12:28:13 PM PST 24
Finished Jan 03 12:28:21 PM PST 24
Peak memory 192868 kb
Host smart-462b7fa9-e916-4680-9cb1-57cba114ba39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526316684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3526316684
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2066498577
Short name T898
Test name
Test status
Simulation time 19229599 ps
CPU time 0.65 seconds
Started Jan 03 12:27:16 PM PST 24
Finished Jan 03 12:27:20 PM PST 24
Peak memory 192356 kb
Host smart-8420fda8-3591-4ceb-a7c1-91a8db0ae816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066498577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2066498577
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.810672388
Short name T921
Test name
Test status
Simulation time 54326599 ps
CPU time 0.56 seconds
Started Jan 03 12:30:23 PM PST 24
Finished Jan 03 12:31:19 PM PST 24
Peak memory 193688 kb
Host smart-c0091604-bd6b-4601-944a-6c59fc986b29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810672388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.810672388
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1380058536
Short name T940
Test name
Test status
Simulation time 14753895 ps
CPU time 0.57 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:01 PM PST 24
Peak memory 194416 kb
Host smart-f0dcd1e3-6ff2-402d-bd3c-8314ccdd3c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380058536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1380058536
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2204965105
Short name T925
Test name
Test status
Simulation time 12377038 ps
CPU time 0.61 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:30:41 PM PST 24
Peak memory 192556 kb
Host smart-8274759b-7a21-42ee-b4e5-e1a7ebfb502d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204965105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2204965105
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.4069187271
Short name T886
Test name
Test status
Simulation time 31075615 ps
CPU time 0.56 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:02 PM PST 24
Peak memory 194272 kb
Host smart-d6d0fda7-63ac-4963-b02f-47dd856f6453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069187271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.4069187271
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1929747253
Short name T910
Test name
Test status
Simulation time 46934215 ps
CPU time 0.58 seconds
Started Jan 03 12:28:40 PM PST 24
Finished Jan 03 12:29:00 PM PST 24
Peak memory 193840 kb
Host smart-ff024123-db6e-44ef-b53c-d160190f9acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929747253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1929747253
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2210558837
Short name T899
Test name
Test status
Simulation time 12957895 ps
CPU time 0.61 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:02 PM PST 24
Peak memory 193892 kb
Host smart-f3c994df-a858-47ec-bf1a-18c4143de54d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210558837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2210558837
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3454679609
Short name T121
Test name
Test status
Simulation time 40474995 ps
CPU time 0.67 seconds
Started Jan 03 12:29:04 PM PST 24
Finished Jan 03 12:29:31 PM PST 24
Peak memory 197368 kb
Host smart-802f2780-73a5-4677-a89e-5951459a61c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454679609 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3454679609
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.681983655
Short name T9
Test name
Test status
Simulation time 24712545 ps
CPU time 0.56 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:30:41 PM PST 24
Peak memory 193488 kb
Host smart-b224ee27-b987-4638-aae6-6971becb288d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681983655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.681983655
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.69886397
Short name T22
Test name
Test status
Simulation time 50622891 ps
CPU time 0.59 seconds
Started Jan 03 12:26:45 PM PST 24
Finished Jan 03 12:26:54 PM PST 24
Peak memory 194140 kb
Host smart-dd17203d-969e-454d-a50b-4fb3d4f3c514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69886397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.69886397
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3778542919
Short name T28
Test name
Test status
Simulation time 33750719 ps
CPU time 0.77 seconds
Started Jan 03 12:29:48 PM PST 24
Finished Jan 03 12:30:30 PM PST 24
Peak memory 196160 kb
Host smart-7cece5b3-4d10-49df-94e7-842ec9e29c8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778542919 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3778542919
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3969817331
Short name T39
Test name
Test status
Simulation time 44829855 ps
CPU time 1.92 seconds
Started Jan 03 12:26:52 PM PST 24
Finished Jan 03 12:26:57 PM PST 24
Peak memory 198288 kb
Host smart-bce627c4-3865-4760-a3f7-9ce7e1c91cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969817331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3969817331
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.131839705
Short name T30
Test name
Test status
Simulation time 68235019 ps
CPU time 1.06 seconds
Started Jan 03 12:28:22 PM PST 24
Finished Jan 03 12:28:31 PM PST 24
Peak memory 198120 kb
Host smart-ec017c7d-4efd-4168-9a1e-a3c8316fd23c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131839705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.131839705
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.539905398
Short name T936
Test name
Test status
Simulation time 125763055 ps
CPU time 0.94 seconds
Started Jan 03 12:26:47 PM PST 24
Finished Jan 03 12:26:56 PM PST 24
Peak memory 198052 kb
Host smart-1405de16-059c-407b-a5fb-60f9826918e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539905398 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.539905398
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2165589938
Short name T922
Test name
Test status
Simulation time 28292064 ps
CPU time 0.57 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:01 PM PST 24
Peak memory 194364 kb
Host smart-7de67cb9-11cc-452e-9f30-b4c99fa6ac78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165589938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2165589938
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.717564941
Short name T932
Test name
Test status
Simulation time 11923660 ps
CPU time 0.59 seconds
Started Jan 03 12:28:48 PM PST 24
Finished Jan 03 12:29:18 PM PST 24
Peak memory 193896 kb
Host smart-45fd01c4-00cd-43d0-9dd4-0d6345cacfc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717564941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.717564941
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.709301169
Short name T911
Test name
Test status
Simulation time 49205294 ps
CPU time 1.21 seconds
Started Jan 03 12:29:03 PM PST 24
Finished Jan 03 12:29:30 PM PST 24
Peak memory 197472 kb
Host smart-9ec57b06-b6ea-4e7d-a83f-be83793db5a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709301169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.709301169
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3468270965
Short name T933
Test name
Test status
Simulation time 126117754 ps
CPU time 1.04 seconds
Started Jan 03 12:29:50 PM PST 24
Finished Jan 03 12:30:32 PM PST 24
Peak memory 198284 kb
Host smart-529daca1-64fa-46c7-b242-84d74ac4be0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468270965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3468270965
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1348178249
Short name T13
Test name
Test status
Simulation time 410693902 ps
CPU time 0.81 seconds
Started Jan 03 12:28:47 PM PST 24
Finished Jan 03 12:29:17 PM PST 24
Peak memory 198108 kb
Host smart-41cadc87-fe7a-45db-a97a-ca1b7bb7af97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348178249 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1348178249
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.755437620
Short name T92
Test name
Test status
Simulation time 20042070 ps
CPU time 0.6 seconds
Started Jan 03 12:28:59 PM PST 24
Finished Jan 03 12:29:26 PM PST 24
Peak memory 195204 kb
Host smart-ee567b4c-e4f0-49c9-9e8b-191e7d9c0796
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755437620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.755437620
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1129203996
Short name T16
Test name
Test status
Simulation time 53065359 ps
CPU time 0.6 seconds
Started Jan 03 12:26:53 PM PST 24
Finished Jan 03 12:26:59 PM PST 24
Peak memory 194028 kb
Host smart-04300c2a-fe7a-404a-99b5-904b0ce9e5b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129203996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1129203996
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2696180103
Short name T938
Test name
Test status
Simulation time 22707945 ps
CPU time 0.65 seconds
Started Jan 03 12:29:30 PM PST 24
Finished Jan 03 12:30:04 PM PST 24
Peak memory 195892 kb
Host smart-6f43555d-c589-4f55-9a89-973a2e77fa6d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696180103 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2696180103
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3580978836
Short name T12
Test name
Test status
Simulation time 35504219 ps
CPU time 1.66 seconds
Started Jan 03 12:35:35 PM PST 24
Finished Jan 03 12:37:10 PM PST 24
Peak memory 198008 kb
Host smart-39f5d5e8-b8b9-47f1-816a-cd2d11922466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580978836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3580978836
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.289391313
Short name T41
Test name
Test status
Simulation time 79919173 ps
CPU time 1.09 seconds
Started Jan 03 12:30:00 PM PST 24
Finished Jan 03 12:30:46 PM PST 24
Peak memory 198200 kb
Host smart-e5ad1d9c-9a49-4bee-a5f7-931cfcc63bbb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289391313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.289391313
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3733833935
Short name T19
Test name
Test status
Simulation time 160772198 ps
CPU time 1.07 seconds
Started Jan 03 12:35:54 PM PST 24
Finished Jan 03 12:37:52 PM PST 24
Peak memory 198080 kb
Host smart-87a6c647-b755-46c7-ba64-b9a29a6eb880
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733833935 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3733833935
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2812212569
Short name T883
Test name
Test status
Simulation time 38272148 ps
CPU time 0.55 seconds
Started Jan 03 12:29:53 PM PST 24
Finished Jan 03 12:30:35 PM PST 24
Peak memory 193388 kb
Host smart-004e590d-8272-4bee-8ee2-f132dc1bed88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812212569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2812212569
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1302449165
Short name T946
Test name
Test status
Simulation time 10461451 ps
CPU time 0.55 seconds
Started Jan 03 12:35:03 PM PST 24
Finished Jan 03 12:36:53 PM PST 24
Peak memory 193576 kb
Host smart-5d1acf49-cd56-479b-8819-262ea26482b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302449165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1302449165
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3215162836
Short name T98
Test name
Test status
Simulation time 189481885 ps
CPU time 2.91 seconds
Started Jan 03 12:29:18 PM PST 24
Finished Jan 03 12:29:48 PM PST 24
Peak memory 197952 kb
Host smart-b8dd78de-ac33-432a-b63b-f430a7475350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215162836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3215162836
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2622221705
Short name T106
Test name
Test status
Simulation time 256607299 ps
CPU time 1.04 seconds
Started Jan 03 12:29:27 PM PST 24
Finished Jan 03 12:29:59 PM PST 24
Peak memory 198104 kb
Host smart-c6403226-ebed-4aaa-a45c-c8ea152febb2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622221705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2622221705
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3514448233
Short name T902
Test name
Test status
Simulation time 16825426 ps
CPU time 0.76 seconds
Started Jan 03 12:26:45 PM PST 24
Finished Jan 03 12:26:54 PM PST 24
Peak memory 198052 kb
Host smart-9ed37b63-3e01-4e72-a2df-22ab593c42bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514448233 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3514448233
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3774197785
Short name T79
Test name
Test status
Simulation time 21610787 ps
CPU time 0.58 seconds
Started Jan 03 12:34:58 PM PST 24
Finished Jan 03 12:36:34 PM PST 24
Peak memory 195108 kb
Host smart-0874428d-747a-4f4b-bc4d-7d2619db6779
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774197785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3774197785
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.49713586
Short name T881
Test name
Test status
Simulation time 52750314 ps
CPU time 0.59 seconds
Started Jan 03 12:26:44 PM PST 24
Finished Jan 03 12:26:46 PM PST 24
Peak memory 193880 kb
Host smart-30009c06-29ac-4ab6-bcb8-82810aba882f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49713586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.49713586
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.60801265
Short name T85
Test name
Test status
Simulation time 17585940 ps
CPU time 0.6 seconds
Started Jan 03 12:30:26 PM PST 24
Finished Jan 03 12:31:24 PM PST 24
Peak memory 195512 kb
Host smart-d0af6f1d-6695-40a5-9ec0-15ca0e9007fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60801265 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.gpio_same_csr_outstanding.60801265
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.43591010
Short name T17
Test name
Test status
Simulation time 338906953 ps
CPU time 1.18 seconds
Started Jan 03 12:30:51 PM PST 24
Finished Jan 03 12:31:58 PM PST 24
Peak memory 197832 kb
Host smart-b91e3524-c25d-43a9-a355-8035e613d9c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43591010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.43591010
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3764281286
Short name T114
Test name
Test status
Simulation time 78912190 ps
CPU time 0.9 seconds
Started Jan 03 12:29:58 PM PST 24
Finished Jan 03 12:30:43 PM PST 24
Peak memory 196700 kb
Host smart-8fb36f0d-52e9-4f23-9ed4-407597d6e91a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764281286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3764281286
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3621703215
Short name T808
Test name
Test status
Simulation time 14965977 ps
CPU time 0.54 seconds
Started Jan 03 12:59:04 PM PST 24
Finished Jan 03 12:59:49 PM PST 24
Peak memory 194744 kb
Host smart-e55c6622-a4ca-4a41-baa1-47e74d7745b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621703215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3621703215
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3495518155
Short name T605
Test name
Test status
Simulation time 722941506 ps
CPU time 0.9 seconds
Started Jan 03 12:58:58 PM PST 24
Finished Jan 03 12:59:39 PM PST 24
Peak memory 196396 kb
Host smart-de055cc0-9507-4f67-bf61-0aa5ded00a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495518155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3495518155
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1628024333
Short name T691
Test name
Test status
Simulation time 353479214 ps
CPU time 9.47 seconds
Started Jan 03 12:59:09 PM PST 24
Finished Jan 03 01:00:09 PM PST 24
Peak memory 197020 kb
Host smart-c1bb40e7-9a0a-4689-8f1f-46819fdb2b6f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628024333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1628024333
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2168618812
Short name T880
Test name
Test status
Simulation time 61307582 ps
CPU time 0.89 seconds
Started Jan 03 12:59:04 PM PST 24
Finished Jan 03 12:59:49 PM PST 24
Peak memory 197812 kb
Host smart-60605e1d-0550-42e3-a733-baa4925a8b99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168618812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2168618812
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2620798519
Short name T822
Test name
Test status
Simulation time 76350616 ps
CPU time 1.11 seconds
Started Jan 03 12:59:11 PM PST 24
Finished Jan 03 01:00:06 PM PST 24
Peak memory 196056 kb
Host smart-2e600f8b-355c-4f2f-bc22-f96e691e9cdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620798519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2620798519
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1961468070
Short name T277
Test name
Test status
Simulation time 301520675 ps
CPU time 3.23 seconds
Started Jan 03 12:59:05 PM PST 24
Finished Jan 03 12:59:52 PM PST 24
Peak memory 197092 kb
Host smart-d6273dbc-9845-4fb2-b7a3-4c410415f032
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961468070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1961468070
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3127738595
Short name T645
Test name
Test status
Simulation time 115842440 ps
CPU time 1.21 seconds
Started Jan 03 12:59:05 PM PST 24
Finished Jan 03 12:59:51 PM PST 24
Peak memory 198136 kb
Host smart-d7d1174d-5e7d-4d8d-98ee-8f81cbe30617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127738595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3127738595
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3014532268
Short name T574
Test name
Test status
Simulation time 42755925 ps
CPU time 0.99 seconds
Started Jan 03 12:59:10 PM PST 24
Finished Jan 03 01:00:04 PM PST 24
Peak memory 195964 kb
Host smart-09149077-3c50-423c-8c1d-2a54d7642b9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014532268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3014532268
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1899903848
Short name T819
Test name
Test status
Simulation time 1107013968 ps
CPU time 3.72 seconds
Started Jan 03 12:59:15 PM PST 24
Finished Jan 03 01:00:12 PM PST 24
Peak memory 197952 kb
Host smart-9693d966-644e-44dc-99c6-38016701eb08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899903848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1899903848
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.783475159
Short name T854
Test name
Test status
Simulation time 287164351 ps
CPU time 1.11 seconds
Started Jan 03 12:59:01 PM PST 24
Finished Jan 03 12:59:44 PM PST 24
Peak memory 195524 kb
Host smart-1a613323-4f64-4c7c-b5b4-6e1b55446e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783475159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.783475159
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.117776452
Short name T67
Test name
Test status
Simulation time 405793075 ps
CPU time 1.19 seconds
Started Jan 03 12:59:10 PM PST 24
Finished Jan 03 01:00:05 PM PST 24
Peak memory 195824 kb
Host smart-59676cea-7deb-4cf3-992c-556b79efeb8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117776452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.117776452
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2423138521
Short name T546
Test name
Test status
Simulation time 3625289477 ps
CPU time 93.98 seconds
Started Jan 03 12:59:10 PM PST 24
Finished Jan 03 01:01:37 PM PST 24
Peak memory 198180 kb
Host smart-0b8f78b4-a1b7-4ca0-a522-c98f09bd5f2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423138521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2423138521
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.734994105
Short name T514
Test name
Test status
Simulation time 795882608457 ps
CPU time 1563.71 seconds
Started Jan 03 12:59:09 PM PST 24
Finished Jan 03 01:26:04 PM PST 24
Peak memory 198392 kb
Host smart-a822fbea-ebf3-45e0-9b74-9a57f99dded6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=734994105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.734994105
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1246951865
Short name T852
Test name
Test status
Simulation time 57604242 ps
CPU time 0.77 seconds
Started Jan 03 12:59:00 PM PST 24
Finished Jan 03 12:59:42 PM PST 24
Peak memory 195424 kb
Host smart-382bd533-5f02-41a4-abf9-6a739fde393a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246951865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1246951865
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1125649752
Short name T584
Test name
Test status
Simulation time 607431843 ps
CPU time 8.93 seconds
Started Jan 03 12:59:00 PM PST 24
Finished Jan 03 12:59:50 PM PST 24
Peak memory 197000 kb
Host smart-e64f78f4-88e3-480e-8003-7a953d0dec4e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125649752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1125649752
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2311678050
Short name T761
Test name
Test status
Simulation time 90143598 ps
CPU time 0.66 seconds
Started Jan 03 12:59:07 PM PST 24
Finished Jan 03 12:59:56 PM PST 24
Peak memory 194760 kb
Host smart-6ef40f96-2cf1-4cec-ad82-a17c39602db8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311678050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2311678050
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1450213859
Short name T738
Test name
Test status
Simulation time 70551448 ps
CPU time 0.78 seconds
Started Jan 03 12:59:09 PM PST 24
Finished Jan 03 01:00:00 PM PST 24
Peak memory 195448 kb
Host smart-3c969c9e-4a82-466a-a882-9bf05b8f9edc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450213859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1450213859
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.946724021
Short name T572
Test name
Test status
Simulation time 60663324 ps
CPU time 0.83 seconds
Started Jan 03 12:59:05 PM PST 24
Finished Jan 03 12:59:50 PM PST 24
Peak memory 196168 kb
Host smart-e10c39bc-998b-4552-b5cb-e04fce34db84
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946724021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.946724021
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1138817152
Short name T362
Test name
Test status
Simulation time 696976775 ps
CPU time 2.26 seconds
Started Jan 03 12:59:05 PM PST 24
Finished Jan 03 12:59:52 PM PST 24
Peak memory 197084 kb
Host smart-bfa5d848-047c-4c07-ab71-28946983d252
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138817152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1138817152
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2831268876
Short name T760
Test name
Test status
Simulation time 23765267 ps
CPU time 0.83 seconds
Started Jan 03 12:59:06 PM PST 24
Finished Jan 03 12:59:54 PM PST 24
Peak memory 196632 kb
Host smart-49c55fc5-2567-4e17-ac2e-0f15c71ee710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831268876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2831268876
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3951977983
Short name T475
Test name
Test status
Simulation time 180557231 ps
CPU time 1.07 seconds
Started Jan 03 12:59:00 PM PST 24
Finished Jan 03 12:59:42 PM PST 24
Peak memory 196092 kb
Host smart-6e9b7531-fd95-4203-aa98-5e6673617a05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951977983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3951977983
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.423932839
Short name T570
Test name
Test status
Simulation time 187212527 ps
CPU time 1.73 seconds
Started Jan 03 12:59:05 PM PST 24
Finished Jan 03 12:59:51 PM PST 24
Peak memory 197788 kb
Host smart-e84e3147-b61f-41bf-b9d9-0327b22d992c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423932839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.423932839
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1303991990
Short name T32
Test name
Test status
Simulation time 194209191 ps
CPU time 0.76 seconds
Started Jan 03 12:59:04 PM PST 24
Finished Jan 03 12:59:49 PM PST 24
Peak memory 213432 kb
Host smart-c27295c0-ccdf-47a2-bb44-098f8fa70468
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303991990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1303991990
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2791527748
Short name T830
Test name
Test status
Simulation time 53234609 ps
CPU time 0.89 seconds
Started Jan 03 12:59:07 PM PST 24
Finished Jan 03 12:59:55 PM PST 24
Peak memory 195488 kb
Host smart-69aa7915-14d9-4fff-ad3d-85b6ccf61b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791527748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2791527748
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2715768842
Short name T849
Test name
Test status
Simulation time 116712495 ps
CPU time 1.03 seconds
Started Jan 03 12:59:02 PM PST 24
Finished Jan 03 12:59:45 PM PST 24
Peak memory 195672 kb
Host smart-80ff81b4-37dc-4492-880c-2f385a1195d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715768842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2715768842
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1966834949
Short name T432
Test name
Test status
Simulation time 25960830714 ps
CPU time 176.71 seconds
Started Jan 03 12:59:11 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 198300 kb
Host smart-9cbbc725-d4b5-41f8-abab-47bac5ab80f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966834949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1966834949
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.1109357806
Short name T444
Test name
Test status
Simulation time 339148487897 ps
CPU time 1053.38 seconds
Started Jan 03 12:58:57 PM PST 24
Finished Jan 03 01:17:10 PM PST 24
Peak memory 198316 kb
Host smart-0792633b-1040-45e9-a9f1-feab82540eb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1109357806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.1109357806
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2096366148
Short name T643
Test name
Test status
Simulation time 14094515 ps
CPU time 0.56 seconds
Started Jan 03 12:59:34 PM PST 24
Finished Jan 03 01:00:27 PM PST 24
Peak memory 194084 kb
Host smart-8f7198ed-3184-49ac-b7d7-b684643f3869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096366148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2096366148
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3396084645
Short name T664
Test name
Test status
Simulation time 49336810 ps
CPU time 0.82 seconds
Started Jan 03 12:59:40 PM PST 24
Finished Jan 03 01:00:35 PM PST 24
Peak memory 195468 kb
Host smart-e6104a1d-e099-4b8b-b6b1-790ee3f2ca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396084645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3396084645
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2052284266
Short name T327
Test name
Test status
Simulation time 519592541 ps
CPU time 18.21 seconds
Started Jan 03 12:59:45 PM PST 24
Finished Jan 03 01:01:02 PM PST 24
Peak memory 196904 kb
Host smart-064fe381-0d2f-49b4-ba5b-cec4feee8ae3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052284266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2052284266
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2325304416
Short name T641
Test name
Test status
Simulation time 231419362 ps
CPU time 0.72 seconds
Started Jan 03 12:59:36 PM PST 24
Finished Jan 03 01:00:29 PM PST 24
Peak memory 195360 kb
Host smart-5cbed963-84ff-41ce-b4b8-09f122f10be3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325304416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2325304416
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.560659449
Short name T740
Test name
Test status
Simulation time 67098183 ps
CPU time 1.04 seconds
Started Jan 03 12:59:37 PM PST 24
Finished Jan 03 01:00:31 PM PST 24
Peak memory 195728 kb
Host smart-58907f14-64a6-498a-8f1f-a69202199bcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560659449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.560659449
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1006633979
Short name T646
Test name
Test status
Simulation time 390305117 ps
CPU time 1.64 seconds
Started Jan 03 12:59:39 PM PST 24
Finished Jan 03 01:00:33 PM PST 24
Peak memory 198304 kb
Host smart-afd5812f-bd10-421b-b885-0098ec0fe8fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006633979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1006633979
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.593672664
Short name T667
Test name
Test status
Simulation time 180603211 ps
CPU time 1.18 seconds
Started Jan 03 12:59:50 PM PST 24
Finished Jan 03 01:00:51 PM PST 24
Peak memory 196456 kb
Host smart-f11fdee4-5a0e-421a-9064-8feb30ad2a49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593672664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
593672664
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.919167877
Short name T736
Test name
Test status
Simulation time 23791975 ps
CPU time 0.9 seconds
Started Jan 03 12:59:44 PM PST 24
Finished Jan 03 01:00:41 PM PST 24
Peak memory 196128 kb
Host smart-c433008e-ffec-4de1-bf3b-fe19035daab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919167877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.919167877
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1463716880
Short name T858
Test name
Test status
Simulation time 22714900 ps
CPU time 0.65 seconds
Started Jan 03 12:59:49 PM PST 24
Finished Jan 03 01:00:48 PM PST 24
Peak memory 194260 kb
Host smart-ed94c727-ff69-409c-a644-d1fda5002048
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463716880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1463716880
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.601110266
Short name T611
Test name
Test status
Simulation time 348661347 ps
CPU time 5.42 seconds
Started Jan 03 12:59:35 PM PST 24
Finished Jan 03 01:00:32 PM PST 24
Peak memory 198116 kb
Host smart-dc5117c5-122c-466f-a42c-dc0b067dc49e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601110266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.601110266
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1729154193
Short name T236
Test name
Test status
Simulation time 52079818 ps
CPU time 1.01 seconds
Started Jan 03 12:59:30 PM PST 24
Finished Jan 03 01:00:24 PM PST 24
Peak memory 195692 kb
Host smart-81be7002-1f03-41bc-8472-6acfb094e9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729154193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1729154193
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1001357790
Short name T206
Test name
Test status
Simulation time 187732799 ps
CPU time 1.06 seconds
Started Jan 03 12:59:44 PM PST 24
Finished Jan 03 01:00:42 PM PST 24
Peak memory 195904 kb
Host smart-4c005771-29f8-4ac9-9a9c-d5d4a60dff25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001357790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1001357790
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2873762613
Short name T464
Test name
Test status
Simulation time 18485336945 ps
CPU time 117.81 seconds
Started Jan 03 12:59:40 PM PST 24
Finished Jan 03 01:02:32 PM PST 24
Peak memory 198080 kb
Host smart-50c77794-fbb9-471f-a756-bc97f415f62f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873762613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2873762613
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3294678939
Short name T712
Test name
Test status
Simulation time 66380202931 ps
CPU time 938.46 seconds
Started Jan 03 12:59:41 PM PST 24
Finished Jan 03 01:16:16 PM PST 24
Peak memory 198388 kb
Host smart-0528c2a6-ef6f-45f4-b885-6f1c6545caed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3294678939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3294678939
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3956901364
Short name T616
Test name
Test status
Simulation time 33322976 ps
CPU time 0.57 seconds
Started Jan 03 12:59:45 PM PST 24
Finished Jan 03 01:00:43 PM PST 24
Peak memory 194268 kb
Host smart-e5725b97-77cc-45ba-9011-d5b0e423138e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956901364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3956901364
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3448512488
Short name T515
Test name
Test status
Simulation time 52146564 ps
CPU time 0.87 seconds
Started Jan 03 12:59:38 PM PST 24
Finished Jan 03 01:00:31 PM PST 24
Peak memory 196244 kb
Host smart-f7bd6d7c-48b4-46ad-9b85-0a9c914e07df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448512488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3448512488
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1577470537
Short name T708
Test name
Test status
Simulation time 274772639 ps
CPU time 7.97 seconds
Started Jan 03 12:59:52 PM PST 24
Finished Jan 03 01:00:59 PM PST 24
Peak memory 198028 kb
Host smart-df6674f7-8368-4c50-8eb8-a1ee8eb0d775
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577470537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1577470537
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2285614171
Short name T421
Test name
Test status
Simulation time 44763883 ps
CPU time 0.79 seconds
Started Jan 03 12:59:37 PM PST 24
Finished Jan 03 01:00:30 PM PST 24
Peak memory 196572 kb
Host smart-4ac91de8-7724-40a0-b59c-bf04973f5243
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285614171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2285614171
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3208589949
Short name T264
Test name
Test status
Simulation time 19965542 ps
CPU time 0.71 seconds
Started Jan 03 12:59:46 PM PST 24
Finished Jan 03 01:00:44 PM PST 24
Peak memory 195376 kb
Host smart-af553250-66b8-4fd2-9e1c-8a88e69bf138
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208589949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3208589949
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.859184232
Short name T860
Test name
Test status
Simulation time 56182367 ps
CPU time 2.1 seconds
Started Jan 03 12:59:38 PM PST 24
Finished Jan 03 01:00:33 PM PST 24
Peak memory 198056 kb
Host smart-81a5bdbc-455d-4011-9a53-a11e55f6ed41
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859184232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.859184232
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2635138439
Short name T618
Test name
Test status
Simulation time 474204359 ps
CPU time 2.7 seconds
Started Jan 03 12:59:38 PM PST 24
Finished Jan 03 01:00:33 PM PST 24
Peak memory 197040 kb
Host smart-c23908f8-05d4-48af-8f93-fedd190125f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635138439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2635138439
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1896101380
Short name T553
Test name
Test status
Simulation time 252335935 ps
CPU time 1.18 seconds
Started Jan 03 12:59:51 PM PST 24
Finished Jan 03 01:00:51 PM PST 24
Peak memory 197216 kb
Host smart-f53b4125-bb4a-4cbb-a0b6-22b0494b4d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896101380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1896101380
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.500950615
Short name T258
Test name
Test status
Simulation time 279391289 ps
CPU time 1.13 seconds
Started Jan 03 12:59:36 PM PST 24
Finished Jan 03 01:00:29 PM PST 24
Peak memory 197180 kb
Host smart-cbc0a9fb-0085-4cd4-8010-9e637cb231c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500950615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.500950615
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3735505011
Short name T235
Test name
Test status
Simulation time 116411548 ps
CPU time 2.16 seconds
Started Jan 03 12:59:43 PM PST 24
Finished Jan 03 01:00:42 PM PST 24
Peak memory 197992 kb
Host smart-b9ae6a3a-a6d2-4dc1-8ab1-a6604f686f3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735505011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3735505011
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1904284111
Short name T651
Test name
Test status
Simulation time 59820681 ps
CPU time 0.83 seconds
Started Jan 03 12:59:55 PM PST 24
Finished Jan 03 01:00:57 PM PST 24
Peak memory 195928 kb
Host smart-aae31fe4-a9d8-4356-81d3-0729990af9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904284111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1904284111
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3747861874
Short name T296
Test name
Test status
Simulation time 831769257 ps
CPU time 1.01 seconds
Started Jan 03 12:59:48 PM PST 24
Finished Jan 03 01:00:48 PM PST 24
Peak memory 195820 kb
Host smart-69ee4b1a-c96e-4ccd-8d66-60c23f9c95a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747861874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3747861874
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3496217645
Short name T330
Test name
Test status
Simulation time 17370326714 ps
CPU time 102.5 seconds
Started Jan 03 12:59:43 PM PST 24
Finished Jan 03 01:02:22 PM PST 24
Peak memory 198196 kb
Host smart-ed845c3f-34f9-4463-81c4-b06a2d89e9d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496217645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3496217645
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.1251580275
Short name T742
Test name
Test status
Simulation time 36110367987 ps
CPU time 281.17 seconds
Started Jan 03 12:59:36 PM PST 24
Finished Jan 03 01:05:10 PM PST 24
Peak memory 198344 kb
Host smart-660f0699-1e66-4201-a521-8da61c0116b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1251580275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.1251580275
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2807081217
Short name T659
Test name
Test status
Simulation time 17889274 ps
CPU time 0.54 seconds
Started Jan 03 12:59:38 PM PST 24
Finished Jan 03 01:00:31 PM PST 24
Peak memory 193428 kb
Host smart-c220196b-a438-45eb-8553-66b5d2969bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807081217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2807081217
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.856484538
Short name T284
Test name
Test status
Simulation time 18845159 ps
CPU time 0.73 seconds
Started Jan 03 12:59:54 PM PST 24
Finished Jan 03 01:00:54 PM PST 24
Peak memory 195372 kb
Host smart-de499e09-d9d3-4202-8dd7-de96d4eb5df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856484538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.856484538
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3755136387
Short name T278
Test name
Test status
Simulation time 988978191 ps
CPU time 13.34 seconds
Started Jan 03 12:59:47 PM PST 24
Finished Jan 03 01:00:59 PM PST 24
Peak memory 195748 kb
Host smart-4b3fcd2c-d114-42d4-9ab9-596ea15ee2e6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755136387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3755136387
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3043989331
Short name T445
Test name
Test status
Simulation time 76516230 ps
CPU time 0.99 seconds
Started Jan 03 12:59:45 PM PST 24
Finished Jan 03 01:00:43 PM PST 24
Peak memory 196616 kb
Host smart-9cf07a31-37f6-4fef-bce8-0f63d4a0eafc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043989331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3043989331
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1754872346
Short name T352
Test name
Test status
Simulation time 143831334 ps
CPU time 1.31 seconds
Started Jan 03 12:59:41 PM PST 24
Finished Jan 03 01:00:36 PM PST 24
Peak memory 197232 kb
Host smart-b276ffe0-9ab6-452b-a36e-7c2a2c258211
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754872346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1754872346
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3208447128
Short name T578
Test name
Test status
Simulation time 28536930 ps
CPU time 1.12 seconds
Started Jan 03 12:59:54 PM PST 24
Finished Jan 03 01:00:55 PM PST 24
Peak memory 197304 kb
Host smart-70ea458d-9997-445a-8af1-8703098c489f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208447128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3208447128
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1670352313
Short name T490
Test name
Test status
Simulation time 1062004363 ps
CPU time 2.81 seconds
Started Jan 03 12:59:53 PM PST 24
Finished Jan 03 01:00:55 PM PST 24
Peak memory 197248 kb
Host smart-9ec6f361-5a8e-4932-9224-a9e52080b1b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670352313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1670352313
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.39547206
Short name T807
Test name
Test status
Simulation time 182328324 ps
CPU time 1.21 seconds
Started Jan 03 12:59:50 PM PST 24
Finished Jan 03 01:00:51 PM PST 24
Peak memory 197108 kb
Host smart-249374a0-7616-4acc-82cc-3bd1a192e3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39547206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.39547206
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1015962468
Short name T488
Test name
Test status
Simulation time 25133400 ps
CPU time 1.02 seconds
Started Jan 03 12:59:53 PM PST 24
Finished Jan 03 01:00:54 PM PST 24
Peak memory 196136 kb
Host smart-1515a879-668f-4358-9315-0f59df3a0716
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015962468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1015962468
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3073212036
Short name T318
Test name
Test status
Simulation time 1088226021 ps
CPU time 5.21 seconds
Started Jan 03 12:59:43 PM PST 24
Finished Jan 03 01:00:45 PM PST 24
Peak memory 198056 kb
Host smart-ded7b393-8292-484c-9f8a-8ac0638dd614
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073212036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3073212036
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.262126918
Short name T254
Test name
Test status
Simulation time 70892660 ps
CPU time 1.1 seconds
Started Jan 03 12:59:46 PM PST 24
Finished Jan 03 01:00:45 PM PST 24
Peak memory 195860 kb
Host smart-770ddaa8-9c51-4881-a1b1-e0f4069c91b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262126918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.262126918
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3795527694
Short name T229
Test name
Test status
Simulation time 45938733 ps
CPU time 1.19 seconds
Started Jan 03 12:59:37 PM PST 24
Finished Jan 03 01:00:31 PM PST 24
Peak memory 195692 kb
Host smart-90e7b3a7-9511-45c5-b59b-59d4a4ff823e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795527694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3795527694
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3204876598
Short name T642
Test name
Test status
Simulation time 7853903450 ps
CPU time 200.39 seconds
Started Jan 03 12:59:40 PM PST 24
Finished Jan 03 01:03:55 PM PST 24
Peak memory 198244 kb
Host smart-e2efcdc4-7869-4724-8454-7813fb0a96d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204876598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3204876598
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.4184288994
Short name T334
Test name
Test status
Simulation time 24203273 ps
CPU time 0.55 seconds
Started Jan 03 12:59:41 PM PST 24
Finished Jan 03 01:00:37 PM PST 24
Peak memory 194044 kb
Host smart-378349f6-e759-4f93-a5e3-63de73b87d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184288994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.4184288994
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2510520140
Short name T383
Test name
Test status
Simulation time 25345168 ps
CPU time 0.73 seconds
Started Jan 03 12:59:42 PM PST 24
Finished Jan 03 01:00:39 PM PST 24
Peak memory 194048 kb
Host smart-4db64c03-88bd-43dc-af22-b65b1c409ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510520140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2510520140
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2960834717
Short name T234
Test name
Test status
Simulation time 225489743 ps
CPU time 8.72 seconds
Started Jan 03 12:59:44 PM PST 24
Finished Jan 03 01:00:49 PM PST 24
Peak memory 196420 kb
Host smart-20641cbc-a074-446d-be40-e9d73065a316
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960834717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2960834717
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2584730677
Short name T393
Test name
Test status
Simulation time 44708752 ps
CPU time 0.72 seconds
Started Jan 03 12:59:50 PM PST 24
Finished Jan 03 01:00:50 PM PST 24
Peak memory 195888 kb
Host smart-26ca6dff-f054-41ea-b46a-4c950097aa6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584730677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2584730677
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1349488519
Short name T790
Test name
Test status
Simulation time 135102936 ps
CPU time 1.07 seconds
Started Jan 03 12:59:43 PM PST 24
Finished Jan 03 01:00:41 PM PST 24
Peak memory 195956 kb
Host smart-748d5d55-fb37-4ebd-b749-bbad868e7870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349488519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1349488519
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.115354125
Short name T566
Test name
Test status
Simulation time 74235843 ps
CPU time 2.85 seconds
Started Jan 03 12:59:40 PM PST 24
Finished Jan 03 01:00:38 PM PST 24
Peak memory 198228 kb
Host smart-344ed3d6-b57a-4d93-9028-223c51c958aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115354125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.115354125
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.60806154
Short name T497
Test name
Test status
Simulation time 132475386 ps
CPU time 2.71 seconds
Started Jan 03 12:59:52 PM PST 24
Finished Jan 03 01:00:54 PM PST 24
Peak memory 195972 kb
Host smart-5987319e-0d63-4e76-968d-9dbefcc6f3d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60806154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.60806154
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2526643437
Short name T366
Test name
Test status
Simulation time 425822391 ps
CPU time 1.17 seconds
Started Jan 03 12:59:57 PM PST 24
Finished Jan 03 01:00:59 PM PST 24
Peak memory 196500 kb
Host smart-ba28fb9f-6c6d-42c9-ae95-7a52d9a15c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526643437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2526643437
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.4268065391
Short name T307
Test name
Test status
Simulation time 83021936 ps
CPU time 0.83 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:01:05 PM PST 24
Peak memory 195996 kb
Host smart-c1233d7e-f545-4aa6-8eed-16135d9e8be8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268065391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.4268065391
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.621508620
Short name T281
Test name
Test status
Simulation time 516353674 ps
CPU time 5.48 seconds
Started Jan 03 12:59:39 PM PST 24
Finished Jan 03 01:00:38 PM PST 24
Peak memory 198136 kb
Host smart-11f99657-e1cd-4ace-803e-1a705d58f2b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621508620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.621508620
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3671257264
Short name T635
Test name
Test status
Simulation time 35962317 ps
CPU time 1 seconds
Started Jan 03 12:59:48 PM PST 24
Finished Jan 03 01:00:48 PM PST 24
Peak memory 196620 kb
Host smart-78fe900d-deb0-43b7-9895-4853a9feec2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671257264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3671257264
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1280389952
Short name T478
Test name
Test status
Simulation time 117426567 ps
CPU time 0.74 seconds
Started Jan 03 12:59:39 PM PST 24
Finished Jan 03 01:00:34 PM PST 24
Peak memory 196080 kb
Host smart-1830a9c7-2286-4179-9f57-59447d32ed26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280389952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1280389952
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2096673828
Short name T386
Test name
Test status
Simulation time 12655247780 ps
CPU time 146.75 seconds
Started Jan 03 12:59:40 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 198164 kb
Host smart-a3d322fd-7e25-4362-b4ca-a1f7f59c62aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096673828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2096673828
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.562831988
Short name T591
Test name
Test status
Simulation time 249591998344 ps
CPU time 780.74 seconds
Started Jan 03 12:59:41 PM PST 24
Finished Jan 03 01:13:38 PM PST 24
Peak memory 198216 kb
Host smart-275d3579-09d6-41df-b10c-4afbe67e385d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=562831988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.562831988
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3803397324
Short name T723
Test name
Test status
Simulation time 35769157 ps
CPU time 0.54 seconds
Started Jan 03 12:59:48 PM PST 24
Finished Jan 03 01:00:47 PM PST 24
Peak memory 193992 kb
Host smart-a56c5d82-077c-4714-983b-b9f6ec7b665c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803397324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3803397324
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.965227870
Short name T799
Test name
Test status
Simulation time 126549990 ps
CPU time 0.7 seconds
Started Jan 03 12:59:53 PM PST 24
Finished Jan 03 01:00:53 PM PST 24
Peak memory 194180 kb
Host smart-f3f216c3-7f9e-4fc9-b3e1-8c4e8a5f9477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965227870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.965227870
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3377440045
Short name T384
Test name
Test status
Simulation time 1398585830 ps
CPU time 9.38 seconds
Started Jan 03 12:59:41 PM PST 24
Finished Jan 03 01:00:45 PM PST 24
Peak memory 197020 kb
Host smart-ffe9d73a-eb30-478c-a4bc-57e03fcff499
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377440045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3377440045
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.431826021
Short name T538
Test name
Test status
Simulation time 67201033 ps
CPU time 0.92 seconds
Started Jan 03 12:59:51 PM PST 24
Finished Jan 03 01:00:51 PM PST 24
Peak memory 197244 kb
Host smart-57e37dd9-9950-4be1-8b91-e7ad71677344
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431826021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.431826021
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2398988448
Short name T219
Test name
Test status
Simulation time 877642679 ps
CPU time 1.23 seconds
Started Jan 03 01:00:01 PM PST 24
Finished Jan 03 01:01:06 PM PST 24
Peak memory 197120 kb
Host smart-f59fd658-86ed-4575-b7e1-fbfb3cd1710b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398988448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2398988448
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1349616153
Short name T834
Test name
Test status
Simulation time 374470325 ps
CPU time 3.53 seconds
Started Jan 03 12:59:50 PM PST 24
Finished Jan 03 01:00:52 PM PST 24
Peak memory 198192 kb
Host smart-8a5dcdba-0bdc-499b-bf68-aa89dca1d7ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349616153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1349616153
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1765317104
Short name T319
Test name
Test status
Simulation time 58007510 ps
CPU time 1.79 seconds
Started Jan 03 12:59:56 PM PST 24
Finished Jan 03 01:00:59 PM PST 24
Peak memory 196368 kb
Host smart-b1e786a0-3bdc-4221-b402-76a866771efc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765317104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1765317104
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1375900223
Short name T401
Test name
Test status
Simulation time 57140112 ps
CPU time 1.22 seconds
Started Jan 03 12:59:41 PM PST 24
Finished Jan 03 01:00:39 PM PST 24
Peak memory 197148 kb
Host smart-60d45d4a-1e98-4a55-a44b-c5018dc29e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375900223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1375900223
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1350864140
Short name T52
Test name
Test status
Simulation time 33941188 ps
CPU time 1.08 seconds
Started Jan 03 12:59:41 PM PST 24
Finished Jan 03 01:00:36 PM PST 24
Peak memory 195880 kb
Host smart-78163f90-fa8a-43c3-90d0-a882e5c8aab7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350864140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1350864140
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2982025931
Short name T391
Test name
Test status
Simulation time 62139648 ps
CPU time 2.77 seconds
Started Jan 03 12:59:55 PM PST 24
Finished Jan 03 01:00:57 PM PST 24
Peak memory 198116 kb
Host smart-ee9940aa-cf73-459e-a5cb-57e47302f63d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982025931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2982025931
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2428877094
Short name T503
Test name
Test status
Simulation time 173386887 ps
CPU time 1.26 seconds
Started Jan 03 12:59:54 PM PST 24
Finished Jan 03 01:00:54 PM PST 24
Peak memory 197952 kb
Host smart-da658963-a4e4-4f33-955a-7d18e11d0f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428877094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2428877094
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1308300720
Short name T343
Test name
Test status
Simulation time 405292732 ps
CPU time 1.08 seconds
Started Jan 03 12:59:55 PM PST 24
Finished Jan 03 01:00:55 PM PST 24
Peak memory 195588 kb
Host smart-7a3b16a2-2065-4ac4-b8c7-cc2ec8e02eef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308300720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1308300720
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3617495676
Short name T453
Test name
Test status
Simulation time 6830842982 ps
CPU time 163.79 seconds
Started Jan 03 12:59:48 PM PST 24
Finished Jan 03 01:03:30 PM PST 24
Peak memory 198164 kb
Host smart-ac75657c-4e98-4ae3-9828-e1065e14712b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617495676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3617495676
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3261445988
Short name T72
Test name
Test status
Simulation time 53277090380 ps
CPU time 636.88 seconds
Started Jan 03 01:00:02 PM PST 24
Finished Jan 03 01:11:43 PM PST 24
Peak memory 198416 kb
Host smart-1b900128-35ff-40f1-ba1d-4b1a04496220
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3261445988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3261445988
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.438780240
Short name T415
Test name
Test status
Simulation time 12906619 ps
CPU time 0.57 seconds
Started Jan 03 12:59:45 PM PST 24
Finished Jan 03 01:00:43 PM PST 24
Peak memory 194080 kb
Host smart-e14902c6-fe3c-493c-8ccd-d51bfb1bddc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438780240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.438780240
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3884266369
Short name T627
Test name
Test status
Simulation time 16926655 ps
CPU time 0.61 seconds
Started Jan 03 01:00:05 PM PST 24
Finished Jan 03 01:01:11 PM PST 24
Peak memory 193904 kb
Host smart-ec341331-06b4-4d5b-8372-b3af053e2e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884266369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3884266369
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.4063846863
Short name T648
Test name
Test status
Simulation time 302628017 ps
CPU time 15.48 seconds
Started Jan 03 12:59:42 PM PST 24
Finished Jan 03 01:00:54 PM PST 24
Peak memory 195576 kb
Host smart-8269e8de-22bf-4c02-a865-00b0ddd249ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063846863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.4063846863
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.321252470
Short name T711
Test name
Test status
Simulation time 116275227 ps
CPU time 0.93 seconds
Started Jan 03 01:00:03 PM PST 24
Finished Jan 03 01:01:08 PM PST 24
Peak memory 196744 kb
Host smart-907c7bbd-0dc1-47b0-82a7-7db081ebd69e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321252470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.321252470
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3851994185
Short name T508
Test name
Test status
Simulation time 22567491 ps
CPU time 0.74 seconds
Started Jan 03 12:59:59 PM PST 24
Finished Jan 03 01:01:02 PM PST 24
Peak memory 196212 kb
Host smart-0b34fccc-dfca-45c0-8177-13b62183715a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851994185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3851994185
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1762910183
Short name T528
Test name
Test status
Simulation time 59362300 ps
CPU time 1.2 seconds
Started Jan 03 01:00:05 PM PST 24
Finished Jan 03 01:01:11 PM PST 24
Peak memory 198280 kb
Host smart-0f783714-c394-40ad-b314-6b4c5229c732
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762910183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1762910183
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1290712353
Short name T459
Test name
Test status
Simulation time 81228075 ps
CPU time 1.67 seconds
Started Jan 03 12:59:43 PM PST 24
Finished Jan 03 01:00:41 PM PST 24
Peak memory 195920 kb
Host smart-66b1a04c-e4e8-4da5-a55a-05ba04192761
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290712353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1290712353
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1423940302
Short name T438
Test name
Test status
Simulation time 20720898 ps
CPU time 0.71 seconds
Started Jan 03 01:00:03 PM PST 24
Finished Jan 03 01:01:08 PM PST 24
Peak memory 195396 kb
Host smart-4abcb5d4-b27b-4e8d-a9a9-6f75c4d04436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423940302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1423940302
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.4279091953
Short name T593
Test name
Test status
Simulation time 103023998 ps
CPU time 1.1 seconds
Started Jan 03 01:00:05 PM PST 24
Finished Jan 03 01:01:11 PM PST 24
Peak memory 196284 kb
Host smart-3266af0a-a08a-491d-8edb-fd8fc8da1683
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279091953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.4279091953
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1184460469
Short name T292
Test name
Test status
Simulation time 657235442 ps
CPU time 3.88 seconds
Started Jan 03 01:00:05 PM PST 24
Finished Jan 03 01:01:14 PM PST 24
Peak memory 197304 kb
Host smart-e66200c4-8d04-4e0e-8f06-836bf63db915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184460469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1184460469
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2355742332
Short name T769
Test name
Test status
Simulation time 385070033 ps
CPU time 1.5 seconds
Started Jan 03 12:59:42 PM PST 24
Finished Jan 03 01:00:39 PM PST 24
Peak memory 196932 kb
Host smart-20c16ed2-c781-4f1f-88d8-6d3b35ee7d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355742332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2355742332
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3794047979
Short name T290
Test name
Test status
Simulation time 103647290 ps
CPU time 0.97 seconds
Started Jan 03 12:59:41 PM PST 24
Finished Jan 03 01:00:39 PM PST 24
Peak memory 195808 kb
Host smart-c18b0079-29e8-419d-98e0-f457b6de98c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794047979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3794047979
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1704025764
Short name T394
Test name
Test status
Simulation time 7505358391 ps
CPU time 77.35 seconds
Started Jan 03 12:59:48 PM PST 24
Finished Jan 03 01:02:04 PM PST 24
Peak memory 198172 kb
Host smart-7635d401-2a2a-432b-9a1b-4482aedabfad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704025764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1704025764
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.1982138726
Short name T441
Test name
Test status
Simulation time 210071171366 ps
CPU time 1603.33 seconds
Started Jan 03 01:01:20 PM PST 24
Finished Jan 03 01:29:10 PM PST 24
Peak memory 197748 kb
Host smart-e26212f5-3ba6-44f0-af35-718d5a213258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1982138726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.1982138726
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.964706395
Short name T826
Test name
Test status
Simulation time 16368631 ps
CPU time 0.54 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:26 PM PST 24
Peak memory 194124 kb
Host smart-cd366f4a-88e6-4e97-8912-08ff53f7425e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964706395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.964706395
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2823255454
Short name T403
Test name
Test status
Simulation time 97267745 ps
CPU time 0.72 seconds
Started Jan 03 12:59:52 PM PST 24
Finished Jan 03 01:00:53 PM PST 24
Peak memory 195288 kb
Host smart-dbb8a26c-dbe2-4170-a03f-8d33c5e7bf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823255454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2823255454
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2903397198
Short name T523
Test name
Test status
Simulation time 366931116 ps
CPU time 19.22 seconds
Started Jan 03 12:59:44 PM PST 24
Finished Jan 03 01:01:01 PM PST 24
Peak memory 197032 kb
Host smart-99270b4b-d2d8-4ea2-a09e-8a0f7de6c191
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903397198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2903397198
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.56714434
Short name T794
Test name
Test status
Simulation time 75290669 ps
CPU time 1.09 seconds
Started Jan 03 12:59:57 PM PST 24
Finished Jan 03 01:00:59 PM PST 24
Peak memory 197992 kb
Host smart-d21e3439-000c-41fe-aeff-3d78dc7065b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56714434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.56714434
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.136618975
Short name T773
Test name
Test status
Simulation time 110163082 ps
CPU time 0.7 seconds
Started Jan 03 12:59:43 PM PST 24
Finished Jan 03 01:00:40 PM PST 24
Peak memory 195220 kb
Host smart-55c85bce-60d2-47ee-b14f-7b0e17023f93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136618975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.136618975
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1943098618
Short name T729
Test name
Test status
Simulation time 154218432 ps
CPU time 2.97 seconds
Started Jan 03 12:59:43 PM PST 24
Finished Jan 03 01:00:42 PM PST 24
Peak memory 198280 kb
Host smart-3e10497f-1e66-4077-be49-56bb7e14964a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943098618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1943098618
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2388112241
Short name T661
Test name
Test status
Simulation time 296615085 ps
CPU time 2.35 seconds
Started Jan 03 12:59:49 PM PST 24
Finished Jan 03 01:00:50 PM PST 24
Peak memory 197276 kb
Host smart-3e12c38f-9947-4592-abd7-48fd28c8e2a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388112241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2388112241
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.399985466
Short name T274
Test name
Test status
Simulation time 33644254 ps
CPU time 1.14 seconds
Started Jan 03 12:59:56 PM PST 24
Finished Jan 03 01:00:58 PM PST 24
Peak memory 195944 kb
Host smart-3fb98a7d-ce35-432f-8150-de5b418bfb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399985466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.399985466
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1823412224
Short name T314
Test name
Test status
Simulation time 53090600 ps
CPU time 0.83 seconds
Started Jan 03 12:59:45 PM PST 24
Finished Jan 03 01:00:43 PM PST 24
Peak memory 196516 kb
Host smart-87447bdd-e4cd-4a8a-9317-776d541eb5e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823412224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1823412224
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2623241082
Short name T218
Test name
Test status
Simulation time 248277902 ps
CPU time 2.49 seconds
Started Jan 03 12:59:46 PM PST 24
Finished Jan 03 01:00:46 PM PST 24
Peak memory 198012 kb
Host smart-cc939efd-4941-4967-a598-b80686be9edd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623241082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2623241082
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1787114266
Short name T575
Test name
Test status
Simulation time 101252944 ps
CPU time 1.02 seconds
Started Jan 03 01:00:04 PM PST 24
Finished Jan 03 01:01:10 PM PST 24
Peak memory 196516 kb
Host smart-f2b20ffc-1eaa-45fb-8239-43e5f1f10ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787114266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1787114266
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1789821675
Short name T466
Test name
Test status
Simulation time 282813719 ps
CPU time 1.36 seconds
Started Jan 03 12:59:55 PM PST 24
Finished Jan 03 01:00:57 PM PST 24
Peak memory 196328 kb
Host smart-b477ae2a-b246-47da-b871-d7204386e66e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789821675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1789821675
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2564129842
Short name T865
Test name
Test status
Simulation time 35032654244 ps
CPU time 90.07 seconds
Started Jan 03 12:59:55 PM PST 24
Finished Jan 03 01:02:25 PM PST 24
Peak memory 198168 kb
Host smart-19288c15-be1a-4093-96ef-f5ddd4358484
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564129842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2564129842
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2510411959
Short name T698
Test name
Test status
Simulation time 234047658855 ps
CPU time 749.81 seconds
Started Jan 03 01:01:00 PM PST 24
Finished Jan 03 01:14:35 PM PST 24
Peak memory 197348 kb
Host smart-31c2b368-0ef4-4cc9-aa77-450fa5e36053
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2510411959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2510411959
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.594763232
Short name T656
Test name
Test status
Simulation time 39346839 ps
CPU time 0.56 seconds
Started Jan 03 12:59:52 PM PST 24
Finished Jan 03 01:00:52 PM PST 24
Peak memory 194004 kb
Host smart-1ba6e410-130f-4baa-b9dc-02b8fc8565bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594763232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.594763232
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.319580833
Short name T579
Test name
Test status
Simulation time 45351001 ps
CPU time 0.81 seconds
Started Jan 03 12:59:51 PM PST 24
Finished Jan 03 01:00:52 PM PST 24
Peak memory 196432 kb
Host smart-7cddcd11-3770-4e31-843a-4a87156549ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319580833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.319580833
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.4187362935
Short name T454
Test name
Test status
Simulation time 597509207 ps
CPU time 10.07 seconds
Started Jan 03 12:59:49 PM PST 24
Finished Jan 03 01:00:58 PM PST 24
Peak memory 197044 kb
Host smart-10c209c7-59db-4703-afc5-554407f3cc0d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187362935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.4187362935
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.4246999362
Short name T419
Test name
Test status
Simulation time 481880296 ps
CPU time 0.85 seconds
Started Jan 03 12:59:49 PM PST 24
Finished Jan 03 01:00:49 PM PST 24
Peak memory 197056 kb
Host smart-36d7d2b3-7155-49fc-93b1-cf0557d1c99e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246999362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.4246999362
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1559664718
Short name T477
Test name
Test status
Simulation time 158917045 ps
CPU time 1.29 seconds
Started Jan 03 12:59:47 PM PST 24
Finished Jan 03 01:00:46 PM PST 24
Peak memory 198052 kb
Host smart-55c100d9-dcbd-411c-8753-5c89d0fdfbcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559664718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1559664718
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3366865467
Short name T547
Test name
Test status
Simulation time 669823093 ps
CPU time 3.51 seconds
Started Jan 03 12:59:56 PM PST 24
Finished Jan 03 01:01:01 PM PST 24
Peak memory 198220 kb
Host smart-2aaaea50-c9af-44a2-81c3-19e03c8bed7c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366865467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3366865467
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.4032268206
Short name T322
Test name
Test status
Simulation time 111927945 ps
CPU time 3.25 seconds
Started Jan 03 12:59:48 PM PST 24
Finished Jan 03 01:00:50 PM PST 24
Peak memory 197144 kb
Host smart-82196245-6585-456c-8f99-1f7c854e557c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032268206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.4032268206
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1236128209
Short name T829
Test name
Test status
Simulation time 78288934 ps
CPU time 0.86 seconds
Started Jan 03 12:59:44 PM PST 24
Finished Jan 03 01:00:42 PM PST 24
Peak memory 195884 kb
Host smart-9b85a601-84c3-47cd-ab9b-0ea107775857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236128209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1236128209
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1382875264
Short name T818
Test name
Test status
Simulation time 45404729 ps
CPU time 0.88 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:27 PM PST 24
Peak memory 195468 kb
Host smart-a793f3b3-c12a-43ed-9707-4f3bd37d5aaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382875264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1382875264
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1275529934
Short name T299
Test name
Test status
Simulation time 158170481 ps
CPU time 4.54 seconds
Started Jan 03 12:59:58 PM PST 24
Finished Jan 03 01:01:05 PM PST 24
Peak memory 198028 kb
Host smart-f222046e-4b73-47d0-9462-063ff410d55b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275529934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1275529934
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1361781960
Short name T286
Test name
Test status
Simulation time 24946868 ps
CPU time 0.78 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:01:04 PM PST 24
Peak memory 196120 kb
Host smart-aef751b3-5a3a-45a6-b44e-efc7ef8fcdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361781960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1361781960
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3808310651
Short name T843
Test name
Test status
Simulation time 163709248 ps
CPU time 1.37 seconds
Started Jan 03 12:59:43 PM PST 24
Finished Jan 03 01:00:41 PM PST 24
Peak memory 196512 kb
Host smart-dd2fdc69-8991-4adb-9c80-cf105eee8f20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808310651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3808310651
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1271521882
Short name T809
Test name
Test status
Simulation time 33035508256 ps
CPU time 181 seconds
Started Jan 03 12:59:49 PM PST 24
Finished Jan 03 01:03:49 PM PST 24
Peak memory 198260 kb
Host smart-82d30ba7-b4e7-46c5-beb9-b60a2f1a80fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271521882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1271521882
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.2763813857
Short name T63
Test name
Test status
Simulation time 366914624534 ps
CPU time 1202.88 seconds
Started Jan 03 12:59:51 PM PST 24
Finished Jan 03 01:20:53 PM PST 24
Peak memory 198344 kb
Host smart-a578395f-e555-473d-92d9-fa65648d7fbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2763813857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.2763813857
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1831862068
Short name T644
Test name
Test status
Simulation time 20127780 ps
CPU time 0.56 seconds
Started Jan 03 01:00:05 PM PST 24
Finished Jan 03 01:01:10 PM PST 24
Peak memory 193976 kb
Host smart-1f1bc567-c3c2-4f3f-aef0-0dfa849aa216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831862068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1831862068
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.410217873
Short name T207
Test name
Test status
Simulation time 23902488 ps
CPU time 0.76 seconds
Started Jan 03 12:59:59 PM PST 24
Finished Jan 03 01:01:02 PM PST 24
Peak memory 195248 kb
Host smart-c00d6929-5afa-441b-ac4b-3debf072f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410217873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.410217873
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2086422714
Short name T554
Test name
Test status
Simulation time 1199496951 ps
CPU time 12.69 seconds
Started Jan 03 12:59:58 PM PST 24
Finished Jan 03 01:01:12 PM PST 24
Peak memory 196924 kb
Host smart-8dc04474-40fd-4ddd-a30f-a5ad942fbd9a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086422714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2086422714
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1322595030
Short name T750
Test name
Test status
Simulation time 296590533 ps
CPU time 0.92 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:01:04 PM PST 24
Peak memory 197912 kb
Host smart-2f18b611-5dc8-4ffb-9aef-81af7118f26e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322595030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1322595030
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.762206524
Short name T827
Test name
Test status
Simulation time 46839862 ps
CPU time 0.93 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:01:05 PM PST 24
Peak memory 196548 kb
Host smart-46037fa4-22c6-4e95-a2d2-9c26ba2c7be3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762206524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.762206524
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1094173238
Short name T768
Test name
Test status
Simulation time 120137965 ps
CPU time 2.37 seconds
Started Jan 03 01:00:02 PM PST 24
Finished Jan 03 01:01:07 PM PST 24
Peak memory 198200 kb
Host smart-7f4ca8ae-6a68-4fd2-8770-ec9158645c56
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094173238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1094173238
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.541116043
Short name T249
Test name
Test status
Simulation time 355862358 ps
CPU time 2.79 seconds
Started Jan 03 01:00:04 PM PST 24
Finished Jan 03 01:01:12 PM PST 24
Peak memory 196584 kb
Host smart-313782af-a4fa-4f62-9570-c125d464503b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541116043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
541116043
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2597176747
Short name T69
Test name
Test status
Simulation time 23410167 ps
CPU time 0.73 seconds
Started Jan 03 12:59:55 PM PST 24
Finished Jan 03 01:00:57 PM PST 24
Peak memory 196264 kb
Host smart-96b9c67f-d4e1-4135-864d-9c5b36906551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597176747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2597176747
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1266416695
Short name T501
Test name
Test status
Simulation time 26651388 ps
CPU time 1 seconds
Started Jan 03 12:59:51 PM PST 24
Finished Jan 03 01:00:51 PM PST 24
Peak memory 196880 kb
Host smart-6c67c85b-9739-4952-96b6-c8b9360c6256
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266416695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1266416695
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1270272113
Short name T537
Test name
Test status
Simulation time 169419996 ps
CPU time 2.2 seconds
Started Jan 03 12:59:58 PM PST 24
Finished Jan 03 01:01:03 PM PST 24
Peak memory 197988 kb
Host smart-8b0cf8a4-4c43-4f1b-b91c-904c7d531110
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270272113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1270272113
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2223712326
Short name T709
Test name
Test status
Simulation time 48649916 ps
CPU time 1.04 seconds
Started Jan 03 12:59:41 PM PST 24
Finished Jan 03 01:00:39 PM PST 24
Peak memory 196336 kb
Host smart-31af4501-7fc1-4418-9c57-e3718e075fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223712326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2223712326
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.629405590
Short name T866
Test name
Test status
Simulation time 50528463 ps
CPU time 1.11 seconds
Started Jan 03 12:59:58 PM PST 24
Finished Jan 03 01:01:01 PM PST 24
Peak memory 196632 kb
Host smart-1075b3cc-14d6-48b4-91c2-71959937bbaf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629405590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.629405590
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3424963010
Short name T346
Test name
Test status
Simulation time 20288114062 ps
CPU time 141.22 seconds
Started Jan 03 01:00:02 PM PST 24
Finished Jan 03 01:03:27 PM PST 24
Peak memory 198232 kb
Host smart-5d63c932-49b5-4854-88d7-0284e8648a63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424963010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3424963010
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.718952861
Short name T744
Test name
Test status
Simulation time 96780779108 ps
CPU time 1179.23 seconds
Started Jan 03 01:00:03 PM PST 24
Finished Jan 03 01:20:47 PM PST 24
Peak memory 198348 kb
Host smart-f02232fd-e05f-4206-8645-365b1072415d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=718952861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.718952861
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2755521338
Short name T474
Test name
Test status
Simulation time 19272619 ps
CPU time 0.53 seconds
Started Jan 03 01:00:03 PM PST 24
Finished Jan 03 01:01:08 PM PST 24
Peak memory 193552 kb
Host smart-d1738820-35a6-4df1-b902-1290e6ea3ed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755521338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2755521338
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2015172607
Short name T771
Test name
Test status
Simulation time 106262454 ps
CPU time 0.72 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:01:05 PM PST 24
Peak memory 195212 kb
Host smart-ba7d32f1-78c0-483f-b0f8-d1ea80a62e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015172607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2015172607
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3000961091
Short name T856
Test name
Test status
Simulation time 935609845 ps
CPU time 6.77 seconds
Started Jan 03 12:59:59 PM PST 24
Finished Jan 03 01:01:09 PM PST 24
Peak memory 196900 kb
Host smart-65f60a10-8913-4a4d-b8d3-434deab98972
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000961091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3000961091
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2685878620
Short name T549
Test name
Test status
Simulation time 343218747 ps
CPU time 0.8 seconds
Started Jan 03 01:00:01 PM PST 24
Finished Jan 03 01:01:05 PM PST 24
Peak memory 195792 kb
Host smart-29049cb8-d8d0-4590-9b5f-1d4a45272b87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685878620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2685878620
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2670336184
Short name T636
Test name
Test status
Simulation time 971761505 ps
CPU time 1.31 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:01:05 PM PST 24
Peak memory 198132 kb
Host smart-ac744103-fb2b-46b1-bdcf-6a42441d908c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670336184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2670336184
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3899617542
Short name T845
Test name
Test status
Simulation time 28416792 ps
CPU time 0.99 seconds
Started Jan 03 12:59:58 PM PST 24
Finished Jan 03 01:01:02 PM PST 24
Peak memory 195384 kb
Host smart-b263a0a0-1d4b-4e3c-b1a0-df38d2c37ec7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899617542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3899617542
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3869098046
Short name T283
Test name
Test status
Simulation time 92183481 ps
CPU time 1 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:01:05 PM PST 24
Peak memory 196824 kb
Host smart-1e3f8f57-6a64-4c10-9426-a947b9b9add1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869098046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3869098046
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3676912184
Short name T388
Test name
Test status
Simulation time 33437849 ps
CPU time 0.91 seconds
Started Jan 03 12:59:58 PM PST 24
Finished Jan 03 01:01:01 PM PST 24
Peak memory 196728 kb
Host smart-70132151-75d5-4320-be02-d0a053abab3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676912184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3676912184
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.4097748476
Short name T534
Test name
Test status
Simulation time 76144074 ps
CPU time 3.52 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:01:07 PM PST 24
Peak memory 198108 kb
Host smart-56cabebc-8a5c-44a1-9467-3c6581fe5a81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097748476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.4097748476
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1467724056
Short name T251
Test name
Test status
Simulation time 160284232 ps
CPU time 0.95 seconds
Started Jan 03 01:00:02 PM PST 24
Finished Jan 03 01:01:06 PM PST 24
Peak memory 195764 kb
Host smart-7cc713d6-9f6d-49db-84d6-140486011e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467724056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1467724056
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4169507901
Short name T680
Test name
Test status
Simulation time 69324415 ps
CPU time 1.17 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:01:05 PM PST 24
Peak memory 195860 kb
Host smart-562cfad0-c29f-4777-ae2d-d569ea2ffca0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169507901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4169507901
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.973255104
Short name T351
Test name
Test status
Simulation time 18933429656 ps
CPU time 79.6 seconds
Started Jan 03 12:59:59 PM PST 24
Finished Jan 03 01:02:22 PM PST 24
Peak memory 198140 kb
Host smart-975a0730-d889-4f61-95d9-109f7fdb1794
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973255104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.973255104
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1287792522
Short name T360
Test name
Test status
Simulation time 73637175370 ps
CPU time 192.22 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:04:15 PM PST 24
Peak memory 198364 kb
Host smart-fa2932a1-0b08-4368-98c3-c9c2c4c76381
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1287792522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1287792522
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1554994220
Short name T308
Test name
Test status
Simulation time 13569428 ps
CPU time 0.61 seconds
Started Jan 03 12:59:31 PM PST 24
Finished Jan 03 01:00:24 PM PST 24
Peak memory 194280 kb
Host smart-42cb9611-a04d-4585-83bf-86b0d4e0fbf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554994220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1554994220
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.47670960
Short name T252
Test name
Test status
Simulation time 161400937 ps
CPU time 0.77 seconds
Started Jan 03 12:59:35 PM PST 24
Finished Jan 03 01:00:28 PM PST 24
Peak memory 195992 kb
Host smart-9d659a2d-8b9b-4f99-a9d1-926226c64d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47670960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.47670960
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1167069042
Short name T821
Test name
Test status
Simulation time 281213935 ps
CPU time 5.68 seconds
Started Jan 03 12:59:33 PM PST 24
Finished Jan 03 01:00:32 PM PST 24
Peak memory 195592 kb
Host smart-8218c984-b5de-40c0-95ab-f814fe75ebf8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167069042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1167069042
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.181201954
Short name T743
Test name
Test status
Simulation time 23767145 ps
CPU time 0.64 seconds
Started Jan 03 12:59:21 PM PST 24
Finished Jan 03 01:00:16 PM PST 24
Peak memory 194492 kb
Host smart-c42df638-ad2f-40de-b710-3a0296fe17b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181201954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.181201954
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1795241790
Short name T704
Test name
Test status
Simulation time 59817726 ps
CPU time 1.07 seconds
Started Jan 03 12:59:24 PM PST 24
Finished Jan 03 01:00:20 PM PST 24
Peak memory 197016 kb
Host smart-43fa5df3-6bec-4313-9dc1-08834d4dab4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795241790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1795241790
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1969327753
Short name T262
Test name
Test status
Simulation time 43052151 ps
CPU time 1.72 seconds
Started Jan 03 12:59:28 PM PST 24
Finished Jan 03 01:00:23 PM PST 24
Peak memory 196820 kb
Host smart-d621efab-9d08-4756-bdfe-4ec308750749
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969327753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1969327753
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.935439150
Short name T797
Test name
Test status
Simulation time 163563719 ps
CPU time 1 seconds
Started Jan 03 12:59:23 PM PST 24
Finished Jan 03 01:00:19 PM PST 24
Peak memory 195436 kb
Host smart-5afe6c2f-2e5b-4c75-a32e-bb6142af2668
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935439150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.935439150
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2751058469
Short name T295
Test name
Test status
Simulation time 386043634 ps
CPU time 1.06 seconds
Started Jan 03 12:59:29 PM PST 24
Finished Jan 03 01:00:23 PM PST 24
Peak memory 196048 kb
Host smart-83f698a3-1d2d-49e8-9a24-5af3c6f4d60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751058469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2751058469
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2139224657
Short name T375
Test name
Test status
Simulation time 119049618 ps
CPU time 1.06 seconds
Started Jan 03 12:59:27 PM PST 24
Finished Jan 03 01:00:22 PM PST 24
Peak memory 196916 kb
Host smart-de7fbdc3-2a06-4093-b7a0-faa18afaa27a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139224657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2139224657
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3445002117
Short name T815
Test name
Test status
Simulation time 365940625 ps
CPU time 4.36 seconds
Started Jan 03 12:59:26 PM PST 24
Finished Jan 03 01:00:24 PM PST 24
Peak memory 198028 kb
Host smart-4d37e867-2a1f-4b32-90ff-6ba8b780145b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445002117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3445002117
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3439003059
Short name T33
Test name
Test status
Simulation time 86498241 ps
CPU time 0.95 seconds
Started Jan 03 12:59:24 PM PST 24
Finished Jan 03 01:00:20 PM PST 24
Peak memory 214692 kb
Host smart-127f5dfd-7204-40ab-a7ee-5a0c8bcee37f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439003059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3439003059
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.4084435941
Short name T68
Test name
Test status
Simulation time 30273873 ps
CPU time 0.9 seconds
Started Jan 03 12:58:53 PM PST 24
Finished Jan 03 12:59:27 PM PST 24
Peak memory 195896 kb
Host smart-9132f3cb-5254-4fee-99a1-427b72a491d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084435941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.4084435941
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.602503027
Short name T329
Test name
Test status
Simulation time 118611937 ps
CPU time 1 seconds
Started Jan 03 12:59:23 PM PST 24
Finished Jan 03 01:00:19 PM PST 24
Peak memory 195848 kb
Host smart-a0639258-07b8-4a64-a2ac-538869c1824c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602503027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.602503027
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2610507068
Short name T786
Test name
Test status
Simulation time 4193533875 ps
CPU time 117.12 seconds
Started Jan 03 12:59:21 PM PST 24
Finished Jan 03 01:02:12 PM PST 24
Peak memory 198144 kb
Host smart-9b70f670-43b0-4424-9695-d29d24464079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610507068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2610507068
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.2163776343
Short name T418
Test name
Test status
Simulation time 211525975058 ps
CPU time 897.46 seconds
Started Jan 03 12:59:21 PM PST 24
Finished Jan 03 01:15:12 PM PST 24
Peak memory 198408 kb
Host smart-cb425152-6175-4252-bc62-7dc0138dc3b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2163776343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.2163776343
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1661804566
Short name T51
Test name
Test status
Simulation time 43139499 ps
CPU time 0.57 seconds
Started Jan 03 01:00:23 PM PST 24
Finished Jan 03 01:01:35 PM PST 24
Peak memory 194092 kb
Host smart-f8e4a2c4-d284-4114-b83f-e30fb6d3c6a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661804566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1661804566
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2295852632
Short name T317
Test name
Test status
Simulation time 133692905 ps
CPU time 0.76 seconds
Started Jan 03 01:00:15 PM PST 24
Finished Jan 03 01:01:25 PM PST 24
Peak memory 195432 kb
Host smart-2ac3c7c6-4d04-4e5e-94b2-54524c144ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295852632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2295852632
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2808724655
Short name T469
Test name
Test status
Simulation time 178222905 ps
CPU time 5.08 seconds
Started Jan 03 01:00:18 PM PST 24
Finished Jan 03 01:01:33 PM PST 24
Peak memory 195928 kb
Host smart-8bd02c1c-b76e-42f9-b1ef-cddb7eacda4d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808724655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2808724655
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2581205822
Short name T268
Test name
Test status
Simulation time 35761851 ps
CPU time 0.98 seconds
Started Jan 03 01:00:09 PM PST 24
Finished Jan 03 01:01:16 PM PST 24
Peak memory 196812 kb
Host smart-a05a64f5-9e02-4786-b092-803909e508f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581205822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2581205822
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3977366341
Short name T425
Test name
Test status
Simulation time 187312464 ps
CPU time 2.09 seconds
Started Jan 03 01:00:16 PM PST 24
Finished Jan 03 01:01:28 PM PST 24
Peak memory 198036 kb
Host smart-ec9989be-f284-415f-b521-1331ea5d425a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977366341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3977366341
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2919350090
Short name T878
Test name
Test status
Simulation time 476439997 ps
CPU time 1.44 seconds
Started Jan 03 01:00:14 PM PST 24
Finished Jan 03 01:01:27 PM PST 24
Peak memory 195900 kb
Host smart-8b878ad3-da72-427b-9347-99d3d04c9fac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919350090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2919350090
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1786133700
Short name T772
Test name
Test status
Simulation time 55602695 ps
CPU time 1 seconds
Started Jan 03 01:00:06 PM PST 24
Finished Jan 03 01:01:12 PM PST 24
Peak memory 195812 kb
Host smart-42575313-d204-4baa-971b-8dd130b8f602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786133700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1786133700
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1111758707
Short name T695
Test name
Test status
Simulation time 31726327 ps
CPU time 0.63 seconds
Started Jan 03 01:00:10 PM PST 24
Finished Jan 03 01:01:18 PM PST 24
Peak memory 194260 kb
Host smart-25e48a38-ebe3-4a7a-8252-a5433b967aca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111758707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1111758707
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2150821404
Short name T389
Test name
Test status
Simulation time 1819444708 ps
CPU time 5.53 seconds
Started Jan 03 01:00:18 PM PST 24
Finished Jan 03 01:01:32 PM PST 24
Peak memory 198016 kb
Host smart-0b42e97b-f5cf-4d74-9caa-cbe64aabebdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150821404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2150821404
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2187684716
Short name T486
Test name
Test status
Simulation time 23719699 ps
CPU time 0.71 seconds
Started Jan 03 01:00:14 PM PST 24
Finished Jan 03 01:01:25 PM PST 24
Peak memory 194124 kb
Host smart-545f8c17-007c-4ff8-a0e8-ae7b765b0a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187684716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2187684716
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1025587860
Short name T525
Test name
Test status
Simulation time 33548081 ps
CPU time 0.77 seconds
Started Jan 03 01:00:02 PM PST 24
Finished Jan 03 01:01:06 PM PST 24
Peak memory 195380 kb
Host smart-d1808406-b37b-435c-8f7c-0d69c3112c29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025587860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1025587860
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2325967808
Short name T573
Test name
Test status
Simulation time 15153844539 ps
CPU time 182.32 seconds
Started Jan 03 01:00:10 PM PST 24
Finished Jan 03 01:04:19 PM PST 24
Peak memory 198268 kb
Host smart-ae513626-5017-4ac7-9392-0a0ede8fc1cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325967808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2325967808
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2494907875
Short name T796
Test name
Test status
Simulation time 67717625136 ps
CPU time 1112.37 seconds
Started Jan 03 01:00:16 PM PST 24
Finished Jan 03 01:19:59 PM PST 24
Peak memory 198384 kb
Host smart-ff8965c9-5bac-44e4-a500-133f9815b46e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2494907875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2494907875
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1946369349
Short name T647
Test name
Test status
Simulation time 15256170 ps
CPU time 0.58 seconds
Started Jan 03 01:00:08 PM PST 24
Finished Jan 03 01:01:14 PM PST 24
Peak memory 194028 kb
Host smart-fa83abed-015f-4df1-a3bc-1faa63804bcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946369349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1946369349
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.101481402
Short name T473
Test name
Test status
Simulation time 21338886 ps
CPU time 0.77 seconds
Started Jan 03 01:00:24 PM PST 24
Finished Jan 03 01:01:35 PM PST 24
Peak memory 196168 kb
Host smart-0c98788e-332e-42f0-9580-2bc3ab6cad7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101481402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.101481402
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1874545732
Short name T824
Test name
Test status
Simulation time 607774911 ps
CPU time 6.73 seconds
Started Jan 03 01:00:25 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 197036 kb
Host smart-4452aa8e-974c-4986-b028-3451076694a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874545732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1874545732
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3955089447
Short name T757
Test name
Test status
Simulation time 361621664 ps
CPU time 0.7 seconds
Started Jan 03 01:00:26 PM PST 24
Finished Jan 03 01:01:37 PM PST 24
Peak memory 194664 kb
Host smart-efe175b9-cc82-4461-812d-ee49dee9cb0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955089447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3955089447
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1301647540
Short name T657
Test name
Test status
Simulation time 73911479 ps
CPU time 1.24 seconds
Started Jan 03 01:00:14 PM PST 24
Finished Jan 03 01:01:25 PM PST 24
Peak memory 196900 kb
Host smart-7018ff30-4d43-438f-a119-49ffd7aa4f81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301647540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1301647540
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3207741065
Short name T762
Test name
Test status
Simulation time 75516286 ps
CPU time 2.77 seconds
Started Jan 03 01:00:21 PM PST 24
Finished Jan 03 01:01:34 PM PST 24
Peak memory 198072 kb
Host smart-c17c2b1c-59cc-4b43-93d6-f46284f7510a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207741065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3207741065
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.71376224
Short name T606
Test name
Test status
Simulation time 295650118 ps
CPU time 2.27 seconds
Started Jan 03 01:00:23 PM PST 24
Finished Jan 03 01:01:36 PM PST 24
Peak memory 197344 kb
Host smart-5cf62a3f-28dc-4e1e-a1c9-ee0b31417e3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71376224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.71376224
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.547268758
Short name T580
Test name
Test status
Simulation time 234282756 ps
CPU time 0.97 seconds
Started Jan 03 01:00:21 PM PST 24
Finished Jan 03 01:01:32 PM PST 24
Peak memory 196768 kb
Host smart-6da5409f-286d-4c48-a382-2a2b64731e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547268758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.547268758
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3850956447
Short name T221
Test name
Test status
Simulation time 131814923 ps
CPU time 1.24 seconds
Started Jan 03 01:00:19 PM PST 24
Finished Jan 03 01:01:29 PM PST 24
Peak memory 197048 kb
Host smart-5a3062e5-aa72-4ffe-99c4-b39a63f8dfed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850956447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3850956447
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3570939922
Short name T832
Test name
Test status
Simulation time 1654717967 ps
CPU time 4.5 seconds
Started Jan 03 01:00:31 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 198056 kb
Host smart-d4cbeb44-d2f5-4628-b171-80eeae15ea0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570939922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3570939922
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1895129381
Short name T676
Test name
Test status
Simulation time 152547034 ps
CPU time 1.41 seconds
Started Jan 03 01:00:23 PM PST 24
Finished Jan 03 01:01:33 PM PST 24
Peak memory 196892 kb
Host smart-85640c57-165f-459a-9bbc-398b17f37ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895129381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1895129381
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.4250928574
Short name T400
Test name
Test status
Simulation time 162316743 ps
CPU time 0.89 seconds
Started Jan 03 01:00:22 PM PST 24
Finished Jan 03 01:01:33 PM PST 24
Peak memory 196536 kb
Host smart-61af5e41-de0d-49cc-b169-54ddb485e447
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250928574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.4250928574
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3134162368
Short name T841
Test name
Test status
Simulation time 4354589586 ps
CPU time 103.24 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:03:24 PM PST 24
Peak memory 198204 kb
Host smart-f6f46d20-bbf0-4344-9dd2-07cfb267b369
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134162368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3134162368
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.227030108
Short name T825
Test name
Test status
Simulation time 70136506921 ps
CPU time 990.26 seconds
Started Jan 03 12:59:59 PM PST 24
Finished Jan 03 01:17:32 PM PST 24
Peak memory 198416 kb
Host smart-94a215f2-a6d8-4c90-ad2b-9d46fdab0c47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=227030108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.227030108
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.384140710
Short name T623
Test name
Test status
Simulation time 14122971 ps
CPU time 0.56 seconds
Started Jan 03 12:59:59 PM PST 24
Finished Jan 03 01:01:02 PM PST 24
Peak memory 194048 kb
Host smart-9e33ad6c-ee6c-498f-a45e-b2f72af32699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384140710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.384140710
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.4105069721
Short name T332
Test name
Test status
Simulation time 20376175 ps
CPU time 0.66 seconds
Started Jan 03 01:00:04 PM PST 24
Finished Jan 03 01:01:08 PM PST 24
Peak memory 194148 kb
Host smart-1c991dee-76da-4cf8-81fb-1324f1ac1db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105069721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.4105069721
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2292575774
Short name T239
Test name
Test status
Simulation time 467581961 ps
CPU time 12.76 seconds
Started Jan 03 12:59:58 PM PST 24
Finished Jan 03 01:01:14 PM PST 24
Peak memory 196368 kb
Host smart-955efdd4-3e0d-49f7-9e73-27774428533b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292575774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2292575774
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.164368450
Short name T543
Test name
Test status
Simulation time 1705868000 ps
CPU time 1 seconds
Started Jan 03 01:00:04 PM PST 24
Finished Jan 03 01:01:08 PM PST 24
Peak memory 197968 kb
Host smart-c7ff5e04-2ff2-4c46-a76c-3b599bdc2abc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164368450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.164368450
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3200148179
Short name T811
Test name
Test status
Simulation time 23711201 ps
CPU time 0.78 seconds
Started Jan 03 12:59:57 PM PST 24
Finished Jan 03 01:00:59 PM PST 24
Peak memory 195568 kb
Host smart-d936d5bb-038c-4ec1-991a-7539907a0c61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200148179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3200148179
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.868791092
Short name T847
Test name
Test status
Simulation time 52660245 ps
CPU time 1.69 seconds
Started Jan 03 01:00:06 PM PST 24
Finished Jan 03 01:01:12 PM PST 24
Peak memory 197192 kb
Host smart-b8e47317-a9d9-4d8b-8cf2-ef859bf5d14a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868791092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.868791092
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.74801503
Short name T812
Test name
Test status
Simulation time 478679043 ps
CPU time 2.76 seconds
Started Jan 03 01:00:01 PM PST 24
Finished Jan 03 01:01:07 PM PST 24
Peak memory 195848 kb
Host smart-c7284c34-83c1-4e55-a57a-b81a3d7c2123
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74801503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.74801503
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.428199172
Short name T813
Test name
Test status
Simulation time 858730823 ps
CPU time 1.16 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:01:06 PM PST 24
Peak memory 196856 kb
Host smart-d3309610-565f-40a9-b3b7-85a427de9366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428199172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.428199172
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.431690104
Short name T776
Test name
Test status
Simulation time 50007700 ps
CPU time 0.69 seconds
Started Jan 03 01:00:03 PM PST 24
Finished Jan 03 01:01:07 PM PST 24
Peak memory 194212 kb
Host smart-cd4c494e-6c61-48c3-a035-9ff5a96e3655
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431690104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.431690104
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.739302811
Short name T472
Test name
Test status
Simulation time 3651793830 ps
CPU time 4.76 seconds
Started Jan 03 01:00:04 PM PST 24
Finished Jan 03 01:01:12 PM PST 24
Peak memory 198176 kb
Host smart-be50df42-4da3-42e0-9129-5c303ace8572
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739302811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.739302811
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2651301596
Short name T817
Test name
Test status
Simulation time 133552214 ps
CPU time 1.19 seconds
Started Jan 03 01:00:48 PM PST 24
Finished Jan 03 01:01:52 PM PST 24
Peak memory 197004 kb
Host smart-b73cdb59-d592-4924-9585-c0607c9785f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651301596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2651301596
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3410506327
Short name T399
Test name
Test status
Simulation time 193369988 ps
CPU time 1.41 seconds
Started Jan 03 01:00:01 PM PST 24
Finished Jan 03 01:01:06 PM PST 24
Peak memory 196876 kb
Host smart-9612985d-f594-4bd3-a698-607133cafd06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410506327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3410506327
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2551687742
Short name T722
Test name
Test status
Simulation time 12588503829 ps
CPU time 106.63 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:02:49 PM PST 24
Peak memory 198256 kb
Host smart-d7b7b7c8-6717-4f98-934c-1df89b4abe6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551687742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2551687742
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3502979130
Short name T562
Test name
Test status
Simulation time 77762233225 ps
CPU time 577.76 seconds
Started Jan 03 01:00:01 PM PST 24
Finished Jan 03 01:10:42 PM PST 24
Peak memory 206496 kb
Host smart-46b23873-0830-430d-a3c5-56803a7b334a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3502979130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3502979130
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1864004758
Short name T387
Test name
Test status
Simulation time 42288256 ps
CPU time 0.6 seconds
Started Jan 03 01:00:17 PM PST 24
Finished Jan 03 01:01:27 PM PST 24
Peak memory 193988 kb
Host smart-5af26c8e-24dd-4d15-a23d-e1ce36775e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864004758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1864004758
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2271198982
Short name T298
Test name
Test status
Simulation time 139988102 ps
CPU time 0.82 seconds
Started Jan 03 01:00:04 PM PST 24
Finished Jan 03 01:01:08 PM PST 24
Peak memory 196192 kb
Host smart-ce4b9bbd-d4fd-4fc2-8a67-03476f0dddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271198982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2271198982
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2107394045
Short name T436
Test name
Test status
Simulation time 832969448 ps
CPU time 6.13 seconds
Started Jan 03 01:00:03 PM PST 24
Finished Jan 03 01:01:13 PM PST 24
Peak memory 196948 kb
Host smart-3e1fdc63-bf1e-4e82-bcd2-8c94a85e05d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107394045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2107394045
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.263453269
Short name T47
Test name
Test status
Simulation time 158415795 ps
CPU time 0.64 seconds
Started Jan 03 01:00:17 PM PST 24
Finished Jan 03 01:01:27 PM PST 24
Peak memory 195364 kb
Host smart-c54e6448-b209-4bb5-93e9-6655cbb81de2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263453269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.263453269
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3178341028
Short name T105
Test name
Test status
Simulation time 104622213 ps
CPU time 0.97 seconds
Started Jan 03 01:00:01 PM PST 24
Finished Jan 03 01:01:06 PM PST 24
Peak memory 196888 kb
Host smart-3f84cb69-84ea-403e-b27b-628a5b184b90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178341028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3178341028
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3288732464
Short name T510
Test name
Test status
Simulation time 82741993 ps
CPU time 3.05 seconds
Started Jan 03 01:00:16 PM PST 24
Finished Jan 03 01:01:30 PM PST 24
Peak memory 196392 kb
Host smart-6c2b97f2-8ad1-47d3-add0-b325e2b3fa01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288732464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3288732464
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3864243932
Short name T696
Test name
Test status
Simulation time 248381785 ps
CPU time 2.34 seconds
Started Jan 03 01:00:01 PM PST 24
Finished Jan 03 01:01:07 PM PST 24
Peak memory 195900 kb
Host smart-38adb4a5-0756-46f9-936d-e2067cc74946
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864243932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3864243932
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3425767312
Short name T376
Test name
Test status
Simulation time 29703404 ps
CPU time 0.65 seconds
Started Jan 03 01:00:00 PM PST 24
Finished Jan 03 01:01:04 PM PST 24
Peak memory 194344 kb
Host smart-62fa60cc-0a20-46cc-b06b-7abe576e37e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425767312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3425767312
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3450226071
Short name T447
Test name
Test status
Simulation time 126596194 ps
CPU time 1.16 seconds
Started Jan 03 01:00:10 PM PST 24
Finished Jan 03 01:01:19 PM PST 24
Peak memory 197220 kb
Host smart-a9346362-c396-45af-a8d8-c3a78d033828
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450226071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3450226071
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3275974708
Short name T368
Test name
Test status
Simulation time 122928913 ps
CPU time 1.9 seconds
Started Jan 03 01:00:06 PM PST 24
Finished Jan 03 01:01:12 PM PST 24
Peak memory 197920 kb
Host smart-e0d0fac3-9acb-4626-9b28-8c526a8b9d37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275974708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3275974708
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2771369875
Short name T315
Test name
Test status
Simulation time 29868757 ps
CPU time 0.92 seconds
Started Jan 03 12:59:57 PM PST 24
Finished Jan 03 01:00:59 PM PST 24
Peak memory 196472 kb
Host smart-77285c0e-48dc-4dd4-86ed-6fd4b02c9f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771369875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2771369875
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1225179427
Short name T446
Test name
Test status
Simulation time 84303223 ps
CPU time 1.19 seconds
Started Jan 03 01:00:02 PM PST 24
Finished Jan 03 01:01:06 PM PST 24
Peak memory 196888 kb
Host smart-aec0c663-f2a2-4669-bfc0-3b553acebc43
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225179427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1225179427
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.4182587276
Short name T747
Test name
Test status
Simulation time 20529235598 ps
CPU time 110.49 seconds
Started Jan 03 01:00:17 PM PST 24
Finished Jan 03 01:03:17 PM PST 24
Peak memory 198128 kb
Host smart-5960d7cf-d607-4e23-9cde-d52c5584fb39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182587276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.4182587276
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2067936299
Short name T302
Test name
Test status
Simulation time 1612765899011 ps
CPU time 1221.91 seconds
Started Jan 03 01:00:05 PM PST 24
Finished Jan 03 01:21:31 PM PST 24
Peak memory 198388 kb
Host smart-c0ecd64a-81c0-4b0a-abc7-60b8d8921374
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2067936299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2067936299
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3810858798
Short name T70
Test name
Test status
Simulation time 28354112 ps
CPU time 0.56 seconds
Started Jan 03 01:00:22 PM PST 24
Finished Jan 03 01:01:32 PM PST 24
Peak memory 194096 kb
Host smart-35360271-ba5c-41e7-9566-d428e7f880c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810858798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3810858798
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3458211353
Short name T450
Test name
Test status
Simulation time 21639396 ps
CPU time 0.65 seconds
Started Jan 03 01:00:17 PM PST 24
Finished Jan 03 01:01:27 PM PST 24
Peak memory 194012 kb
Host smart-71cd6c79-a285-40b0-b4f3-96b7374d7d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458211353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3458211353
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3724154638
Short name T357
Test name
Test status
Simulation time 1400783570 ps
CPU time 18.37 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 196304 kb
Host smart-5bec9658-d26d-4022-acc5-cdf5de25fa90
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724154638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3724154638
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2006714839
Short name T567
Test name
Test status
Simulation time 145446981 ps
CPU time 0.99 seconds
Started Jan 03 01:00:18 PM PST 24
Finished Jan 03 01:01:29 PM PST 24
Peak memory 196596 kb
Host smart-b32f5bfd-d4ed-41a7-a7a7-a9de792f3da1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006714839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2006714839
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1194958394
Short name T853
Test name
Test status
Simulation time 35389778 ps
CPU time 0.69 seconds
Started Jan 03 01:00:37 PM PST 24
Finished Jan 03 01:01:43 PM PST 24
Peak memory 194392 kb
Host smart-fa4d247f-6277-4928-bc63-cb4592558828
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194958394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1194958394
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2549978998
Short name T48
Test name
Test status
Simulation time 304462653 ps
CPU time 3.03 seconds
Started Jan 03 01:00:17 PM PST 24
Finished Jan 03 01:01:30 PM PST 24
Peak memory 198276 kb
Host smart-49e488e7-f02c-4821-831c-acfae90b94ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549978998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2549978998
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.75295236
Short name T256
Test name
Test status
Simulation time 189381328 ps
CPU time 1.21 seconds
Started Jan 03 01:00:21 PM PST 24
Finished Jan 03 01:01:32 PM PST 24
Peak memory 197360 kb
Host smart-ccc3940b-ba7d-4e72-834a-eb08ba71b97f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75295236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.75295236
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.989192208
Short name T331
Test name
Test status
Simulation time 166733384 ps
CPU time 1.08 seconds
Started Jan 03 01:00:18 PM PST 24
Finished Jan 03 01:01:28 PM PST 24
Peak memory 196000 kb
Host smart-20b944d1-bcb0-4320-9cf8-597694c802a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989192208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.989192208
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.4196740032
Short name T833
Test name
Test status
Simulation time 309287328 ps
CPU time 1.22 seconds
Started Jan 03 01:00:32 PM PST 24
Finished Jan 03 01:01:43 PM PST 24
Peak memory 197212 kb
Host smart-b6c5e2eb-bb46-4ccd-b4d2-8fec60fc224f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196740032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.4196740032
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3553103969
Short name T862
Test name
Test status
Simulation time 147796148 ps
CPU time 1.18 seconds
Started Jan 03 01:00:32 PM PST 24
Finished Jan 03 01:01:40 PM PST 24
Peak memory 197944 kb
Host smart-aaad02b7-b76d-4a80-bd3a-2b3cbf247e4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553103969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3553103969
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.172448808
Short name T536
Test name
Test status
Simulation time 74000961 ps
CPU time 0.87 seconds
Started Jan 03 01:00:16 PM PST 24
Finished Jan 03 01:01:27 PM PST 24
Peak memory 195556 kb
Host smart-b4231633-7f22-4c1d-aa2c-8e8bdbd95b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172448808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.172448808
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3200207847
Short name T714
Test name
Test status
Simulation time 125680702 ps
CPU time 1.01 seconds
Started Jan 03 01:00:18 PM PST 24
Finished Jan 03 01:01:28 PM PST 24
Peak memory 195792 kb
Host smart-77b290ee-96d0-4ab1-80b3-c83385bb1c53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200207847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3200207847
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2810206056
Short name T639
Test name
Test status
Simulation time 27909784703 ps
CPU time 161.86 seconds
Started Jan 03 01:00:22 PM PST 24
Finished Jan 03 01:04:13 PM PST 24
Peak memory 198252 kb
Host smart-3342ae44-9fba-41d3-8be9-0a124b4b35cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810206056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2810206056
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3885566341
Short name T679
Test name
Test status
Simulation time 70168723421 ps
CPU time 1556.49 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:27:37 PM PST 24
Peak memory 198352 kb
Host smart-f85cce19-5e0a-492d-9690-75bb62cab8df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3885566341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3885566341
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1091808851
Short name T569
Test name
Test status
Simulation time 45121060 ps
CPU time 0.61 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:01:56 PM PST 24
Peak memory 194036 kb
Host smart-cf222cb3-264e-4e01-82f1-4dc1b174a46f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091808851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1091808851
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2406805952
Short name T668
Test name
Test status
Simulation time 17120846 ps
CPU time 0.65 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 194128 kb
Host smart-1271c13c-4556-4c23-b911-6fdadf89b0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406805952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2406805952
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2129916169
Short name T493
Test name
Test status
Simulation time 226506593 ps
CPU time 11.2 seconds
Started Jan 03 01:00:39 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 196380 kb
Host smart-6f362504-29b3-4077-a9d0-32f5c9538262
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129916169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2129916169
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.4228074616
Short name T227
Test name
Test status
Simulation time 196728537 ps
CPU time 0.84 seconds
Started Jan 03 01:00:36 PM PST 24
Finished Jan 03 01:01:43 PM PST 24
Peak memory 196908 kb
Host smart-48a81afb-480c-4788-af6c-6a11f04ea1ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228074616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.4228074616
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.27129358
Short name T828
Test name
Test status
Simulation time 114250467 ps
CPU time 1.51 seconds
Started Jan 03 01:00:34 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 197044 kb
Host smart-b0ab2e18-9194-47b5-8b45-34beb185c99a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27129358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.27129358
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.904493736
Short name T774
Test name
Test status
Simulation time 403658245 ps
CPU time 2.69 seconds
Started Jan 03 01:00:49 PM PST 24
Finished Jan 03 01:01:54 PM PST 24
Peak memory 198152 kb
Host smart-4b36811e-de0c-412b-a991-4bb0e409eeb2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904493736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.904493736
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3809198637
Short name T859
Test name
Test status
Simulation time 509207924 ps
CPU time 2.96 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 196984 kb
Host smart-2a50e0fa-9bf4-4513-86d7-8d0d5a662d7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809198637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3809198637
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3738836611
Short name T273
Test name
Test status
Simulation time 120376018 ps
CPU time 0.98 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 196108 kb
Host smart-8e601944-b797-4332-a723-9d98ec6b8cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738836611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3738836611
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3169646725
Short name T468
Test name
Test status
Simulation time 45067509 ps
CPU time 0.89 seconds
Started Jan 03 01:00:38 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 195860 kb
Host smart-29c64f10-3b58-417c-ba8d-cba940e83c75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169646725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3169646725
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1689757145
Short name T677
Test name
Test status
Simulation time 104305630 ps
CPU time 4.49 seconds
Started Jan 03 01:00:51 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 197996 kb
Host smart-4bc830f3-87cd-44dd-a3c2-8966dbfdf835
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689757145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1689757145
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3566017149
Short name T820
Test name
Test status
Simulation time 206091205 ps
CPU time 1.27 seconds
Started Jan 03 01:00:32 PM PST 24
Finished Jan 03 01:01:40 PM PST 24
Peak memory 196812 kb
Host smart-0a1b93c8-6378-4dcf-b451-f2e6a28f3a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566017149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3566017149
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3781970904
Short name T253
Test name
Test status
Simulation time 48978475 ps
CPU time 1.05 seconds
Started Jan 03 01:00:31 PM PST 24
Finished Jan 03 01:01:39 PM PST 24
Peak memory 196592 kb
Host smart-868d933f-be33-41d1-875b-375874582182
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781970904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3781970904
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2186013058
Short name T527
Test name
Test status
Simulation time 100242764002 ps
CPU time 192.67 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:04:53 PM PST 24
Peak memory 198172 kb
Host smart-a45c9e35-218d-4b41-9ce9-b6b3f7391910
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186013058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2186013058
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.2735312280
Short name T802
Test name
Test status
Simulation time 351061188281 ps
CPU time 626.48 seconds
Started Jan 03 01:00:50 PM PST 24
Finished Jan 03 01:12:19 PM PST 24
Peak memory 198368 kb
Host smart-f83576ac-be9b-40e9-830f-a34a02f67f51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2735312280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.2735312280
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3401854050
Short name T614
Test name
Test status
Simulation time 35193409 ps
CPU time 0.56 seconds
Started Jan 03 01:01:14 PM PST 24
Finished Jan 03 01:02:21 PM PST 24
Peak memory 194968 kb
Host smart-f1b3f0c6-da37-4bdd-9458-a099ba706989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401854050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3401854050
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.469148907
Short name T213
Test name
Test status
Simulation time 107559359 ps
CPU time 0.64 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:01:56 PM PST 24
Peak memory 194732 kb
Host smart-bac33a31-7290-4596-aa78-4d8a7002d38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469148907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.469148907
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2247489500
Short name T245
Test name
Test status
Simulation time 1495334575 ps
CPU time 18.65 seconds
Started Jan 03 01:00:50 PM PST 24
Finished Jan 03 01:02:11 PM PST 24
Peak memory 196968 kb
Host smart-fac3ebbb-a8e0-4201-871b-598beb0d83ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247489500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2247489500
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3708498162
Short name T733
Test name
Test status
Simulation time 92780518 ps
CPU time 0.86 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 196900 kb
Host smart-4b0268cc-8a67-4ed0-a560-5b4c4ab1721b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708498162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3708498162
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3947174904
Short name T297
Test name
Test status
Simulation time 53785324 ps
CPU time 0.66 seconds
Started Jan 03 01:00:40 PM PST 24
Finished Jan 03 01:01:45 PM PST 24
Peak memory 194960 kb
Host smart-9acea721-2707-4bb8-8aff-ace34c6543cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947174904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3947174904
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2412479403
Short name T531
Test name
Test status
Simulation time 316149595 ps
CPU time 3.68 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 198116 kb
Host smart-ee6b04e7-2d79-4129-a434-837745d8d4c7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412479403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2412479403
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.4030748110
Short name T694
Test name
Test status
Simulation time 81742127 ps
CPU time 1.81 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 196136 kb
Host smart-d4ad230f-cdf9-4363-8748-065a059d7503
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030748110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.4030748110
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1515788308
Short name T347
Test name
Test status
Simulation time 55944111 ps
CPU time 0.8 seconds
Started Jan 03 01:00:40 PM PST 24
Finished Jan 03 01:01:46 PM PST 24
Peak memory 195492 kb
Host smart-ea4a5155-ff33-40e4-bd99-1767d2390531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515788308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1515788308
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2747741415
Short name T434
Test name
Test status
Simulation time 179780904 ps
CPU time 0.84 seconds
Started Jan 03 01:00:39 PM PST 24
Finished Jan 03 01:01:45 PM PST 24
Peak memory 196688 kb
Host smart-06251e4f-f261-424d-819d-7b953b20135f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747741415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2747741415
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1850082208
Short name T492
Test name
Test status
Simulation time 695214513 ps
CPU time 4.08 seconds
Started Jan 03 01:00:40 PM PST 24
Finished Jan 03 01:01:48 PM PST 24
Peak memory 197928 kb
Host smart-ec29222c-1d6d-4cfb-b3f2-c08537462912
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850082208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1850082208
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3668403410
Short name T848
Test name
Test status
Simulation time 63231995 ps
CPU time 1.2 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 196484 kb
Host smart-76e2793f-7427-4e63-961d-5cfa1ea75e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668403410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3668403410
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1351757537
Short name T631
Test name
Test status
Simulation time 64339540 ps
CPU time 0.97 seconds
Started Jan 03 01:00:39 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 195512 kb
Host smart-0b16c641-d25a-4a8d-a2b5-2d1fa9334af5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351757537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1351757537
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2105976979
Short name T301
Test name
Test status
Simulation time 28693234430 ps
CPU time 175.33 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:04:49 PM PST 24
Peak memory 198204 kb
Host smart-b1645049-8a95-4ae2-b023-31b5372b2309
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105976979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2105976979
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3664392637
Short name T496
Test name
Test status
Simulation time 79484344928 ps
CPU time 343.93 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:07:38 PM PST 24
Peak memory 198368 kb
Host smart-75b4488d-8146-4fc9-bec4-fd884696ec80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3664392637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3664392637
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.690826120
Short name T548
Test name
Test status
Simulation time 28302455 ps
CPU time 0.56 seconds
Started Jan 03 01:00:34 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 194688 kb
Host smart-76b714a0-f8f0-4414-bae4-eb94b3e4f2f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690826120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.690826120
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.442096025
Short name T753
Test name
Test status
Simulation time 72437281 ps
CPU time 0.87 seconds
Started Jan 03 01:00:56 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 195916 kb
Host smart-18da85f7-3ce5-487a-b94b-65c48a264714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442096025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.442096025
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.10961633
Short name T869
Test name
Test status
Simulation time 3926864050 ps
CPU time 19.37 seconds
Started Jan 03 01:01:11 PM PST 24
Finished Jan 03 01:02:36 PM PST 24
Peak memory 197204 kb
Host smart-214dc5a9-c115-46de-ae5a-9424e296eb22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10961633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stress
.10961633
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2658117022
Short name T465
Test name
Test status
Simulation time 327194051 ps
CPU time 1.05 seconds
Started Jan 03 01:00:34 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 198128 kb
Host smart-2e75bbb7-39ec-4880-9370-7e2cc9d94e43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658117022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2658117022
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.587493593
Short name T781
Test name
Test status
Simulation time 138137737 ps
CPU time 1.25 seconds
Started Jan 03 01:00:54 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 195880 kb
Host smart-d5b6f7e7-957d-4417-a4bf-30da159bace7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587493593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.587493593
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3535843002
Short name T751
Test name
Test status
Simulation time 356156887 ps
CPU time 3.45 seconds
Started Jan 03 01:01:01 PM PST 24
Finished Jan 03 01:02:09 PM PST 24
Peak memory 198168 kb
Host smart-9347a0aa-b89e-46ef-b130-c47d90b9d449
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535843002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3535843002
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3434605449
Short name T789
Test name
Test status
Simulation time 125105922 ps
CPU time 2.61 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:02 PM PST 24
Peak memory 197340 kb
Host smart-a3bcff06-1e02-4957-b511-7bb57c09142d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434605449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3434605449
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2363644902
Short name T443
Test name
Test status
Simulation time 77189181 ps
CPU time 1 seconds
Started Jan 03 01:00:56 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 196120 kb
Host smart-df53f367-013b-454d-978c-429bf3f3bbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363644902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2363644902
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2119042497
Short name T224
Test name
Test status
Simulation time 54398967 ps
CPU time 1.14 seconds
Started Jan 03 01:00:56 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 198068 kb
Host smart-8a33f836-a952-4be7-8695-46e65f440898
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119042497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2119042497
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3024164002
Short name T323
Test name
Test status
Simulation time 426826740 ps
CPU time 5.8 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:02:03 PM PST 24
Peak memory 198068 kb
Host smart-6b1fd9e0-0d01-4231-94bc-096c5776c8a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024164002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3024164002
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3801069073
Short name T248
Test name
Test status
Simulation time 171769188 ps
CPU time 1.23 seconds
Started Jan 03 01:01:01 PM PST 24
Finished Jan 03 01:02:06 PM PST 24
Peak memory 195120 kb
Host smart-ed2aa224-33d9-474e-88cd-66e8e8b5f0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801069073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3801069073
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4265655792
Short name T850
Test name
Test status
Simulation time 134963690 ps
CPU time 0.99 seconds
Started Jan 03 01:01:13 PM PST 24
Finished Jan 03 01:02:20 PM PST 24
Peak memory 195692 kb
Host smart-bd1b2e33-3d7b-4798-b696-43a695aa6fcb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265655792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4265655792
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2914017819
Short name T673
Test name
Test status
Simulation time 12646189160 ps
CPU time 89.05 seconds
Started Jan 03 01:00:37 PM PST 24
Finished Jan 03 01:03:12 PM PST 24
Peak memory 198228 kb
Host smart-43ca3619-7b14-4cec-9206-e19381fac58e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914017819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2914017819
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1836735906
Short name T872
Test name
Test status
Simulation time 15926061179 ps
CPU time 221.36 seconds
Started Jan 03 01:00:37 PM PST 24
Finished Jan 03 01:05:24 PM PST 24
Peak memory 198372 kb
Host smart-2941d273-8944-4a96-ae4c-cc545d73a277
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1836735906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1836735906
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3350331717
Short name T402
Test name
Test status
Simulation time 29657001 ps
CPU time 0.56 seconds
Started Jan 03 01:00:23 PM PST 24
Finished Jan 03 01:01:33 PM PST 24
Peak memory 194104 kb
Host smart-2ede4f01-7cdc-4f4c-95fa-7a30ffd07faa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350331717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3350331717
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.4254995224
Short name T625
Test name
Test status
Simulation time 21357319 ps
CPU time 0.67 seconds
Started Jan 03 01:00:37 PM PST 24
Finished Jan 03 01:01:43 PM PST 24
Peak memory 194156 kb
Host smart-213b8af6-7883-4e5b-83bc-4b2744fdc885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254995224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.4254995224
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1852439627
Short name T545
Test name
Test status
Simulation time 714841758 ps
CPU time 19.65 seconds
Started Jan 03 01:00:32 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 196596 kb
Host smart-5e0361b4-9d10-4d4e-866d-ceda169337f7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852439627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1852439627
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1069910354
Short name T482
Test name
Test status
Simulation time 81654906 ps
CPU time 0.6 seconds
Started Jan 03 01:00:39 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 194404 kb
Host smart-2a0e4923-c398-45a5-bd05-5d6b31d5ddbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069910354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1069910354
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1704592518
Short name T705
Test name
Test status
Simulation time 37475338 ps
CPU time 1.03 seconds
Started Jan 03 01:00:18 PM PST 24
Finished Jan 03 01:01:29 PM PST 24
Peak memory 195872 kb
Host smart-cffd9fdf-c2e6-4bf3-a058-202385f4037c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704592518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1704592518
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3331235347
Short name T775
Test name
Test status
Simulation time 420886423 ps
CPU time 1.66 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 198220 kb
Host smart-2ac1a5a3-eab8-4ac3-9bb5-f2c659456a4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331235347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3331235347
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2401376536
Short name T423
Test name
Test status
Simulation time 117536540 ps
CPU time 3.22 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 195848 kb
Host smart-96fc0d48-84cf-4c6f-b01a-57e869f47952
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401376536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2401376536
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2404717686
Short name T509
Test name
Test status
Simulation time 131069654 ps
CPU time 0.99 seconds
Started Jan 03 01:00:22 PM PST 24
Finished Jan 03 01:01:32 PM PST 24
Peak memory 195824 kb
Host smart-480ba0ba-a591-4c18-9a4f-e1fef7662260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404717686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2404717686
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2970061790
Short name T215
Test name
Test status
Simulation time 108361593 ps
CPU time 1.09 seconds
Started Jan 03 01:00:25 PM PST 24
Finished Jan 03 01:01:35 PM PST 24
Peak memory 196104 kb
Host smart-6ed62c99-7d24-4158-ad44-895968b8aa1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970061790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2970061790
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1628302344
Short name T564
Test name
Test status
Simulation time 533042606 ps
CPU time 1.93 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 198088 kb
Host smart-656e94ec-c4d5-464b-b671-1bbd774f8dfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628302344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1628302344
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.4120681611
Short name T787
Test name
Test status
Simulation time 155005046 ps
CPU time 1.13 seconds
Started Jan 03 01:00:34 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 196296 kb
Host smart-dda5c1ed-e6b9-4b48-b435-4eeb72ff0aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120681611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.4120681611
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.281292712
Short name T624
Test name
Test status
Simulation time 47488353 ps
CPU time 1 seconds
Started Jan 03 01:00:25 PM PST 24
Finished Jan 03 01:01:34 PM PST 24
Peak memory 195660 kb
Host smart-dfa23300-de94-42db-9902-4132c7b71dac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281292712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.281292712
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3073070971
Short name T463
Test name
Test status
Simulation time 13958983948 ps
CPU time 137.76 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:03:58 PM PST 24
Peak memory 198156 kb
Host smart-cd5af549-9d26-462f-9656-b5c99fae9150
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073070971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3073070971
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.1452548315
Short name T354
Test name
Test status
Simulation time 397147057495 ps
CPU time 1186.58 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:21:27 PM PST 24
Peak memory 206508 kb
Host smart-32475639-8905-4e81-8598-b6ece4af851e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1452548315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.1452548315
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1435374081
Short name T632
Test name
Test status
Simulation time 32389180 ps
CPU time 0.56 seconds
Started Jan 03 01:00:39 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 194376 kb
Host smart-03c2bc83-a8b9-408b-ad2c-c490c3fbcbfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435374081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1435374081
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1666990296
Short name T433
Test name
Test status
Simulation time 68663662 ps
CPU time 0.63 seconds
Started Jan 03 01:00:22 PM PST 24
Finished Jan 03 01:01:31 PM PST 24
Peak memory 194084 kb
Host smart-cd655d4b-e931-4989-bddf-17480f9ab5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666990296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1666990296
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.755135955
Short name T876
Test name
Test status
Simulation time 780267676 ps
CPU time 27.14 seconds
Started Jan 03 01:00:44 PM PST 24
Finished Jan 03 01:02:15 PM PST 24
Peak memory 197020 kb
Host smart-f2e7d9b8-3587-425e-b260-e5433ee73c73
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755135955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.755135955
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3511039228
Short name T617
Test name
Test status
Simulation time 745345280 ps
CPU time 0.97 seconds
Started Jan 03 01:00:24 PM PST 24
Finished Jan 03 01:01:35 PM PST 24
Peak memory 196532 kb
Host smart-5a60a2d8-6a4b-479e-9427-a879334a52b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511039228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3511039228
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2721368384
Short name T341
Test name
Test status
Simulation time 100789424 ps
CPU time 1.28 seconds
Started Jan 03 01:00:34 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 197124 kb
Host smart-87ba40ed-f5ca-40c7-8f90-63c434958467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721368384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2721368384
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.461317458
Short name T608
Test name
Test status
Simulation time 579121194 ps
CPU time 3.15 seconds
Started Jan 03 01:00:22 PM PST 24
Finished Jan 03 01:01:35 PM PST 24
Peak memory 198124 kb
Host smart-c633ea06-6fa8-4423-b992-08522dfa4716
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461317458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.461317458
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3475057452
Short name T104
Test name
Test status
Simulation time 1404827178 ps
CPU time 2.7 seconds
Started Jan 03 01:00:39 PM PST 24
Finished Jan 03 01:01:46 PM PST 24
Peak memory 197376 kb
Host smart-b28f4a8b-3bcb-4ec7-8b1d-72c26e2be33f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475057452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3475057452
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1019483829
Short name T861
Test name
Test status
Simulation time 18249211 ps
CPU time 0.65 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 194416 kb
Host smart-bf16edcb-d5a5-4d55-adde-988769d40af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019483829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1019483829
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1342298011
Short name T408
Test name
Test status
Simulation time 34003175 ps
CPU time 0.65 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 194936 kb
Host smart-9163c468-0378-4421-9262-1cd6014eed21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342298011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1342298011
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1308478825
Short name T763
Test name
Test status
Simulation time 1741379321 ps
CPU time 4.97 seconds
Started Jan 03 01:00:50 PM PST 24
Finished Jan 03 01:01:57 PM PST 24
Peak memory 198128 kb
Host smart-cab2699f-1627-4f63-94b1-08fb4d30c0bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308478825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1308478825
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2252885209
Short name T710
Test name
Test status
Simulation time 116908808 ps
CPU time 1.02 seconds
Started Jan 03 01:00:51 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 195612 kb
Host smart-c3aca376-fd27-4c4d-968d-30ea8d8698b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252885209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2252885209
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.186840916
Short name T669
Test name
Test status
Simulation time 149857944 ps
CPU time 0.89 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 195900 kb
Host smart-1aec0ae8-8a8d-4c31-9363-6c43882764c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186840916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.186840916
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2307034976
Short name T649
Test name
Test status
Simulation time 28459565639 ps
CPU time 184.41 seconds
Started Jan 03 01:00:24 PM PST 24
Finished Jan 03 01:04:38 PM PST 24
Peak memory 198136 kb
Host smart-a8f00fa3-de72-41f6-8986-057f507398cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307034976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2307034976
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.3181898172
Short name T361
Test name
Test status
Simulation time 139056423021 ps
CPU time 1950.79 seconds
Started Jan 03 01:00:24 PM PST 24
Finished Jan 03 01:34:04 PM PST 24
Peak memory 198312 kb
Host smart-732f9b26-b57e-420b-b617-7cf554b5e251
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3181898172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.3181898172
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.772829093
Short name T630
Test name
Test status
Simulation time 12397942 ps
CPU time 0.57 seconds
Started Jan 03 12:59:28 PM PST 24
Finished Jan 03 01:00:22 PM PST 24
Peak memory 194004 kb
Host smart-2280a306-831b-4758-bc6a-2e5fcd26f255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772829093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.772829093
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3416510804
Short name T370
Test name
Test status
Simulation time 39447582 ps
CPU time 0.75 seconds
Started Jan 03 12:59:32 PM PST 24
Finished Jan 03 01:00:26 PM PST 24
Peak memory 196184 kb
Host smart-3cc85629-628b-4cc0-84fc-e7c0781dbaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416510804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3416510804
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1751353605
Short name T599
Test name
Test status
Simulation time 729734549 ps
CPU time 10 seconds
Started Jan 03 12:59:44 PM PST 24
Finished Jan 03 01:00:51 PM PST 24
Peak memory 196984 kb
Host smart-2917a320-dc8e-4aa0-ab94-ef9622e26d6b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751353605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1751353605
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3228031752
Short name T785
Test name
Test status
Simulation time 503026602 ps
CPU time 0.86 seconds
Started Jan 03 12:59:33 PM PST 24
Finished Jan 03 01:00:26 PM PST 24
Peak memory 196792 kb
Host smart-a64e4697-2b8c-4f20-ad35-3a384773aacb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228031752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3228031752
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.494900241
Short name T214
Test name
Test status
Simulation time 277281924 ps
CPU time 1.25 seconds
Started Jan 03 12:59:28 PM PST 24
Finished Jan 03 01:00:23 PM PST 24
Peak memory 197320 kb
Host smart-6e90a0b7-b962-4a5f-8594-c3fad5ca6967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494900241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.494900241
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2055496008
Short name T485
Test name
Test status
Simulation time 474197950 ps
CPU time 3.03 seconds
Started Jan 03 12:59:39 PM PST 24
Finished Jan 03 01:00:36 PM PST 24
Peak memory 196420 kb
Host smart-f48f93b8-c463-48b2-a6b0-c9c9444adf98
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055496008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2055496008
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3070034930
Short name T595
Test name
Test status
Simulation time 30998331 ps
CPU time 0.88 seconds
Started Jan 03 12:59:46 PM PST 24
Finished Jan 03 01:00:45 PM PST 24
Peak memory 195428 kb
Host smart-889d7057-d229-4a8b-88f4-32084f457bb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070034930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3070034930
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3892052184
Short name T544
Test name
Test status
Simulation time 21875097 ps
CPU time 0.71 seconds
Started Jan 03 12:59:52 PM PST 24
Finished Jan 03 01:00:52 PM PST 24
Peak memory 195388 kb
Host smart-8935b34e-fea6-4711-a562-8ed8a16b0afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892052184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3892052184
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1224750401
Short name T791
Test name
Test status
Simulation time 122953529 ps
CPU time 1.2 seconds
Started Jan 03 12:59:28 PM PST 24
Finished Jan 03 01:00:23 PM PST 24
Peak memory 195932 kb
Host smart-f29ec47b-d779-42eb-9071-a15fa61315b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224750401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1224750401
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1201610659
Short name T879
Test name
Test status
Simulation time 156111600 ps
CPU time 2.76 seconds
Started Jan 03 12:59:35 PM PST 24
Finished Jan 03 01:00:30 PM PST 24
Peak memory 197964 kb
Host smart-514c7d67-480d-4aa6-8842-ced3820a18e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201610659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1201610659
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.64513587
Short name T34
Test name
Test status
Simulation time 188823546 ps
CPU time 0.92 seconds
Started Jan 03 12:59:32 PM PST 24
Finished Jan 03 01:00:25 PM PST 24
Peak memory 214680 kb
Host smart-383cb8a2-f93a-474b-ad06-26ef34b27e9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64513587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.64513587
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1323348045
Short name T237
Test name
Test status
Simulation time 44299972 ps
CPU time 1.27 seconds
Started Jan 03 12:59:28 PM PST 24
Finished Jan 03 01:00:23 PM PST 24
Peak memory 196564 kb
Host smart-f70dba65-c339-4107-91d8-6bd1c6f9e5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323348045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1323348045
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3856377159
Short name T565
Test name
Test status
Simulation time 30369330 ps
CPU time 0.86 seconds
Started Jan 03 12:59:25 PM PST 24
Finished Jan 03 01:00:20 PM PST 24
Peak memory 196200 kb
Host smart-ace96b23-f485-440b-a628-05653b1ee38f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856377159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3856377159
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3908181897
Short name T803
Test name
Test status
Simulation time 13599804797 ps
CPU time 150.59 seconds
Started Jan 03 12:59:33 PM PST 24
Finished Jan 03 01:02:57 PM PST 24
Peak memory 198236 kb
Host smart-e1a1f6ec-ca3f-41df-9d66-380f48040b3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908181897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3908181897
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.319038548
Short name T310
Test name
Test status
Simulation time 30353715508 ps
CPU time 431.97 seconds
Started Jan 03 12:59:27 PM PST 24
Finished Jan 03 01:07:33 PM PST 24
Peak memory 198264 kb
Host smart-1b4e1d40-3221-4f1f-9a12-d4be432db75f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=319038548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.319038548
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1344827524
Short name T49
Test name
Test status
Simulation time 21974324 ps
CPU time 0.55 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:40 PM PST 24
Peak memory 193980 kb
Host smart-f39d13da-815b-4df2-870b-9904413c83d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344827524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1344827524
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1705729598
Short name T320
Test name
Test status
Simulation time 57997034 ps
CPU time 0.76 seconds
Started Jan 03 01:00:19 PM PST 24
Finished Jan 03 01:01:29 PM PST 24
Peak memory 195968 kb
Host smart-6d8ad0cd-bd6c-4946-ac6a-7ea7b03996f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705729598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1705729598
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2203680052
Short name T65
Test name
Test status
Simulation time 1462557597 ps
CPU time 22 seconds
Started Jan 03 01:00:30 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 198136 kb
Host smart-0187bed1-b33b-4317-9d41-145a58f3f857
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203680052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2203680052
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.895176952
Short name T226
Test name
Test status
Simulation time 85912215 ps
CPU time 0.67 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 195460 kb
Host smart-8d783621-fadc-4ba5-b429-880655e92a22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895176952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.895176952
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3999034522
Short name T271
Test name
Test status
Simulation time 53175990 ps
CPU time 1.38 seconds
Started Jan 03 01:00:39 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 196528 kb
Host smart-a9dfd58c-c005-45b8-883d-5776ff9005ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999034522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3999034522
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.361552673
Short name T480
Test name
Test status
Simulation time 21300684 ps
CPU time 1.04 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:02 PM PST 24
Peak memory 196956 kb
Host smart-ed057af7-88fc-4c8a-8f05-a2d6e4764774
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361552673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.361552673
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1515286749
Short name T816
Test name
Test status
Simulation time 728754942 ps
CPU time 2.99 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:43 PM PST 24
Peak memory 197024 kb
Host smart-605504fe-3979-413e-92e9-6182b09eaf87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515286749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1515286749
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2740439689
Short name T440
Test name
Test status
Simulation time 30812386 ps
CPU time 1.05 seconds
Started Jan 03 01:00:54 PM PST 24
Finished Jan 03 01:01:57 PM PST 24
Peak memory 195916 kb
Host smart-8087ec38-dac3-4bb9-a012-1a414cea4554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740439689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2740439689
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3701077120
Short name T240
Test name
Test status
Simulation time 82012598 ps
CPU time 0.89 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:01:57 PM PST 24
Peak memory 195936 kb
Host smart-02690804-6961-4775-bba4-e6deeb0dea0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701077120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3701077120
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1556470982
Short name T716
Test name
Test status
Simulation time 962439054 ps
CPU time 4.4 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 198084 kb
Host smart-79b928e8-4ca6-463f-972b-0e3190003610
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556470982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1556470982
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.773675576
Short name T442
Test name
Test status
Simulation time 56277238 ps
CPU time 1.45 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 197904 kb
Host smart-f7bf40f7-f32f-4143-8df3-e4309eb5f20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773675576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.773675576
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1577752990
Short name T831
Test name
Test status
Simulation time 83547973 ps
CPU time 1.26 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 195908 kb
Host smart-2f7198d2-8224-4d40-aeda-7e1ce63168bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577752990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1577752990
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2619742487
Short name T259
Test name
Test status
Simulation time 22730783597 ps
CPU time 157.48 seconds
Started Jan 03 01:00:51 PM PST 24
Finished Jan 03 01:04:31 PM PST 24
Peak memory 198256 kb
Host smart-5c420a72-04bc-48e3-a1b3-5956193992a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619742487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2619742487
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.3099832639
Short name T697
Test name
Test status
Simulation time 298226716055 ps
CPU time 874.17 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:16:30 PM PST 24
Peak memory 198304 kb
Host smart-576c5014-bd72-4143-83f2-3fd6ad832d63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3099832639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.3099832639
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2845002914
Short name T613
Test name
Test status
Simulation time 14339715 ps
CPU time 0.58 seconds
Started Jan 03 01:00:36 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 193976 kb
Host smart-fa6e3837-7493-4cc2-bcc3-c8e36460bd22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845002914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2845002914
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2998576851
Short name T746
Test name
Test status
Simulation time 144632910 ps
CPU time 0.88 seconds
Started Jan 03 01:00:59 PM PST 24
Finished Jan 03 01:02:06 PM PST 24
Peak memory 196448 kb
Host smart-6b21daf8-8922-44be-b71a-aaf70c1bd861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998576851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2998576851
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3263535581
Short name T724
Test name
Test status
Simulation time 3054786022 ps
CPU time 26.59 seconds
Started Jan 03 01:00:48 PM PST 24
Finished Jan 03 01:02:18 PM PST 24
Peak memory 196996 kb
Host smart-81ec0d66-95a5-4c4e-99c3-0d7d7405f1b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263535581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3263535581
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2786766175
Short name T629
Test name
Test status
Simulation time 39892490 ps
CPU time 0.72 seconds
Started Jan 03 01:00:36 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 194708 kb
Host smart-97f4f4fc-0cdc-4ceb-aaf8-341843467974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786766175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2786766175
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1425717635
Short name T689
Test name
Test status
Simulation time 197861827 ps
CPU time 0.9 seconds
Started Jan 03 01:00:51 PM PST 24
Finished Jan 03 01:01:54 PM PST 24
Peak memory 195360 kb
Host smart-25e85f4e-22f1-45b8-8472-ea77306efa47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425717635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1425717635
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.4002166988
Short name T427
Test name
Test status
Simulation time 82246564 ps
CPU time 2.91 seconds
Started Jan 03 01:00:50 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 196540 kb
Host smart-3685e1c8-c01e-4fa5-af28-f03cc6caab46
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002166988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.4002166988
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2957102251
Short name T306
Test name
Test status
Simulation time 471589196 ps
CPU time 3.05 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:57 PM PST 24
Peak memory 196832 kb
Host smart-11b5cbbb-ff9c-4605-8dbf-01c7448cf92a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957102251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2957102251
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.161090483
Short name T414
Test name
Test status
Simulation time 17779587 ps
CPU time 0.71 seconds
Started Jan 03 01:00:59 PM PST 24
Finished Jan 03 01:02:06 PM PST 24
Peak memory 193956 kb
Host smart-570e445b-b0c6-4493-a3c1-b9328b43f1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161090483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.161090483
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3599041931
Short name T499
Test name
Test status
Simulation time 183073489 ps
CPU time 1.02 seconds
Started Jan 03 01:00:49 PM PST 24
Finished Jan 03 01:01:53 PM PST 24
Peak memory 196572 kb
Host smart-e4d37f2a-014c-4ce0-a712-eb07a570e763
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599041931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3599041931
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.537009497
Short name T460
Test name
Test status
Simulation time 35953555 ps
CPU time 1.7 seconds
Started Jan 03 01:00:34 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 198016 kb
Host smart-ae96194d-41e8-40e7-8c4a-ed1accb031ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537009497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.537009497
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2633005907
Short name T805
Test name
Test status
Simulation time 70992243 ps
CPU time 1.14 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:01 PM PST 24
Peak memory 195788 kb
Host smart-550fbc48-b46e-428e-b651-7ca3193950d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633005907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2633005907
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1920405477
Short name T424
Test name
Test status
Simulation time 58321143 ps
CPU time 1.17 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 195920 kb
Host smart-3a8d6077-956c-4ba6-92ea-11cbe53d983d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920405477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1920405477
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2437860792
Short name T530
Test name
Test status
Simulation time 6325023812 ps
CPU time 166.85 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:04:27 PM PST 24
Peak memory 198232 kb
Host smart-9add4011-7f22-4387-9ae4-aff39650a77a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437860792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2437860792
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2909401106
Short name T462
Test name
Test status
Simulation time 93528325369 ps
CPU time 876.93 seconds
Started Jan 03 01:00:37 PM PST 24
Finished Jan 03 01:16:19 PM PST 24
Peak memory 198360 kb
Host smart-bd4248f4-7001-49bf-9b33-fcc70029a29c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2909401106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2909401106
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1508101688
Short name T312
Test name
Test status
Simulation time 18176445 ps
CPU time 0.55 seconds
Started Jan 03 01:00:40 PM PST 24
Finished Jan 03 01:01:45 PM PST 24
Peak memory 194004 kb
Host smart-13bddc17-03ad-4124-a1f8-974147fea891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508101688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1508101688
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3691622016
Short name T621
Test name
Test status
Simulation time 323436405 ps
CPU time 0.7 seconds
Started Jan 03 01:00:37 PM PST 24
Finished Jan 03 01:01:43 PM PST 24
Peak memory 195352 kb
Host smart-df426c1d-9b21-4b5b-b5a1-1fc5ab5daf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691622016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3691622016
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.363274243
Short name T339
Test name
Test status
Simulation time 310315222 ps
CPU time 14.7 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 195564 kb
Host smart-00ce36a8-3e2e-4b76-b9ee-9323d74b295b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363274243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.363274243
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.4001078076
Short name T685
Test name
Test status
Simulation time 62207719 ps
CPU time 0.72 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:57 PM PST 24
Peak memory 194836 kb
Host smart-31192a90-98aa-45d5-9137-2dc823669cda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001078076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.4001078076
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2146607728
Short name T779
Test name
Test status
Simulation time 27251182 ps
CPU time 0.85 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 196672 kb
Host smart-08f0d3d8-d200-4af9-9cf3-f3d63e0fa68e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146607728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2146607728
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3162603286
Short name T448
Test name
Test status
Simulation time 237090138 ps
CPU time 2.55 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:57 PM PST 24
Peak memory 198148 kb
Host smart-0a989900-6b7b-42b8-934f-fa0854480796
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162603286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3162603286
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.4010457373
Short name T502
Test name
Test status
Simulation time 134187128 ps
CPU time 0.91 seconds
Started Jan 03 01:00:36 PM PST 24
Finished Jan 03 01:01:43 PM PST 24
Peak memory 195508 kb
Host smart-8a07a5eb-2eb9-4da8-9724-6805e316f278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010457373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.4010457373
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1061388910
Short name T598
Test name
Test status
Simulation time 95310054 ps
CPU time 1.01 seconds
Started Jan 03 01:00:32 PM PST 24
Finished Jan 03 01:01:39 PM PST 24
Peak memory 196868 kb
Host smart-fdd0b2f0-b8e6-415f-896b-f988870dc090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061388910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1061388910
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2927288880
Short name T435
Test name
Test status
Simulation time 127058685 ps
CPU time 1.01 seconds
Started Jan 03 01:00:35 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 196840 kb
Host smart-0671f764-589b-4a7f-80dc-a65e85440a58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927288880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2927288880
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1944601263
Short name T305
Test name
Test status
Simulation time 320622657 ps
CPU time 4.13 seconds
Started Jan 03 01:00:37 PM PST 24
Finished Jan 03 01:01:46 PM PST 24
Peak memory 197948 kb
Host smart-6e7ca52a-fc38-49c3-b61d-60168a3f3122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944601263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1944601263
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1393731345
Short name T516
Test name
Test status
Simulation time 192966770 ps
CPU time 1.03 seconds
Started Jan 03 01:00:37 PM PST 24
Finished Jan 03 01:01:52 PM PST 24
Peak memory 196532 kb
Host smart-d229c4b9-a6bd-4ef2-9de4-f6ae987a4bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393731345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1393731345
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3183351042
Short name T243
Test name
Test status
Simulation time 50325925 ps
CPU time 1.02 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 195788 kb
Host smart-57f8dac9-0aba-4adf-881b-b9a3d74fd3fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183351042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3183351042
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.693423932
Short name T212
Test name
Test status
Simulation time 11663629953 ps
CPU time 70.35 seconds
Started Jan 03 01:00:49 PM PST 24
Finished Jan 03 01:03:02 PM PST 24
Peak memory 198260 kb
Host smart-92bbfd5c-1ff9-4593-a42e-a88785ebb7f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693423932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.693423932
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.778959825
Short name T855
Test name
Test status
Simulation time 146049597963 ps
CPU time 621.34 seconds
Started Jan 03 01:00:51 PM PST 24
Finished Jan 03 01:12:15 PM PST 24
Peak memory 198388 kb
Host smart-9b013549-05df-4a69-9728-bd8e2c478bad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=778959825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.778959825
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.615202113
Short name T426
Test name
Test status
Simulation time 13698556 ps
CPU time 0.56 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:22 PM PST 24
Peak memory 194032 kb
Host smart-a8b98af9-fa62-4833-8ad4-6bf86af89c97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615202113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.615202113
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2059446140
Short name T542
Test name
Test status
Simulation time 55892000 ps
CPU time 0.66 seconds
Started Jan 03 01:00:54 PM PST 24
Finished Jan 03 01:01:57 PM PST 24
Peak memory 194840 kb
Host smart-44bb0abe-a1d2-433e-bc15-972f250367f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059446140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2059446140
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1763294360
Short name T693
Test name
Test status
Simulation time 3365403282 ps
CPU time 24.29 seconds
Started Jan 03 01:00:49 PM PST 24
Finished Jan 03 01:02:16 PM PST 24
Peak memory 198132 kb
Host smart-11e35454-8f50-4650-9290-62144e08d117
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763294360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1763294360
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2921302418
Short name T452
Test name
Test status
Simulation time 134320776 ps
CPU time 0.8 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 196016 kb
Host smart-c1e4a9b6-da32-437b-8b51-32c3c883ec28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921302418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2921302418
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1420364884
Short name T660
Test name
Test status
Simulation time 93703636 ps
CPU time 1.18 seconds
Started Jan 03 01:00:50 PM PST 24
Finished Jan 03 01:01:53 PM PST 24
Peak memory 196156 kb
Host smart-9696d072-7aa2-421f-bcb3-5cbbcfa2f67d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420364884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1420364884
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1074936872
Short name T279
Test name
Test status
Simulation time 388666387 ps
CPU time 1.91 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:01 PM PST 24
Peak memory 198104 kb
Host smart-d28cff31-6769-4f65-a022-899529466c4b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074936872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1074936872
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1464539485
Short name T349
Test name
Test status
Simulation time 439719149 ps
CPU time 2.39 seconds
Started Jan 03 01:00:49 PM PST 24
Finished Jan 03 01:01:54 PM PST 24
Peak memory 196604 kb
Host smart-1f47020c-1772-4817-9763-aaaeaae4ae2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464539485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1464539485
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3121524534
Short name T316
Test name
Test status
Simulation time 60363416 ps
CPU time 1.17 seconds
Started Jan 03 01:00:49 PM PST 24
Finished Jan 03 01:01:53 PM PST 24
Peak memory 198128 kb
Host smart-ed595840-2ec9-4484-b12d-b85ef7075bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121524534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3121524534
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4244082761
Short name T577
Test name
Test status
Simulation time 154121604 ps
CPU time 0.96 seconds
Started Jan 03 01:00:50 PM PST 24
Finished Jan 03 01:01:53 PM PST 24
Peak memory 196552 kb
Host smart-8ac09ff7-1bd4-45ae-9ba7-30487ca91894
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244082761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4244082761
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3619303509
Short name T654
Test name
Test status
Simulation time 632668310 ps
CPU time 5.01 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:04 PM PST 24
Peak memory 198132 kb
Host smart-a93bf545-9fac-4adb-9519-8ad0c2226862
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619303509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3619303509
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3839636287
Short name T823
Test name
Test status
Simulation time 99569771 ps
CPU time 1.38 seconds
Started Jan 03 01:00:38 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 196788 kb
Host smart-4feec2ca-8504-4bdc-933b-64cbe8b7a576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839636287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3839636287
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.128403648
Short name T749
Test name
Test status
Simulation time 77091506 ps
CPU time 1.34 seconds
Started Jan 03 01:00:39 PM PST 24
Finished Jan 03 01:01:45 PM PST 24
Peak memory 195532 kb
Host smart-abb0d50f-42eb-4ec2-85af-0deae7c308d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128403648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.128403648
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3068832577
Short name T699
Test name
Test status
Simulation time 41722733797 ps
CPU time 124.76 seconds
Started Jan 03 01:01:07 PM PST 24
Finished Jan 03 01:04:19 PM PST 24
Peak memory 198236 kb
Host smart-b776b7bc-3457-4083-8711-cae2678ad4a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068832577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3068832577
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.438835829
Short name T700
Test name
Test status
Simulation time 20092233685 ps
CPU time 258.95 seconds
Started Jan 03 01:00:56 PM PST 24
Finished Jan 03 01:06:18 PM PST 24
Peak memory 198400 kb
Host smart-d422327b-a717-4d96-8de3-123de791c343
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=438835829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.438835829
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3085484075
Short name T416
Test name
Test status
Simulation time 15467757 ps
CPU time 0.57 seconds
Started Jan 03 01:01:24 PM PST 24
Finished Jan 03 01:02:32 PM PST 24
Peak memory 193996 kb
Host smart-30d48a88-61c3-4fb0-9c4e-9c930f9a15ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085484075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3085484075
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1258258805
Short name T715
Test name
Test status
Simulation time 27347611 ps
CPU time 0.7 seconds
Started Jan 03 01:01:03 PM PST 24
Finished Jan 03 01:02:08 PM PST 24
Peak memory 195908 kb
Host smart-77100cf8-335c-4b42-8927-8efca3f6a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258258805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1258258805
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1799414722
Short name T846
Test name
Test status
Simulation time 216416353 ps
CPU time 10.44 seconds
Started Jan 03 01:01:14 PM PST 24
Finished Jan 03 01:02:31 PM PST 24
Peak memory 196852 kb
Host smart-896849fd-d8fb-4ea0-9862-86c82e3cf9fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799414722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1799414722
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1507675266
Short name T293
Test name
Test status
Simulation time 154584497 ps
CPU time 1.03 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:26 PM PST 24
Peak memory 197964 kb
Host smart-9a5ea4dc-5937-412a-adb2-3cfdb085a591
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507675266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1507675266
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1976080742
Short name T420
Test name
Test status
Simulation time 389016435 ps
CPU time 1.35 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:02 PM PST 24
Peak memory 197112 kb
Host smart-661e3697-46d2-4b24-a11e-152cd17c8091
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976080742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1976080742
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2338645759
Short name T663
Test name
Test status
Simulation time 498604794 ps
CPU time 3 seconds
Started Jan 03 01:00:54 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 198176 kb
Host smart-0426486a-3b3f-4033-946c-ec091e6ac28a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338645759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2338645759
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1235816279
Short name T555
Test name
Test status
Simulation time 90144172 ps
CPU time 2.32 seconds
Started Jan 03 01:01:13 PM PST 24
Finished Jan 03 01:02:21 PM PST 24
Peak memory 197216 kb
Host smart-2cf4983f-67d8-435d-a8c6-5d1d02e0d806
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235816279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1235816279
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2447474504
Short name T707
Test name
Test status
Simulation time 54246753 ps
CPU time 1.2 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:56 PM PST 24
Peak memory 195896 kb
Host smart-444d8b0c-fed9-4e9e-927c-d5d929e5eed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447474504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2447474504
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1325786168
Short name T600
Test name
Test status
Simulation time 342527522 ps
CPU time 1.01 seconds
Started Jan 03 01:01:11 PM PST 24
Finished Jan 03 01:02:17 PM PST 24
Peak memory 195996 kb
Host smart-4021adb8-3bd7-4de8-b378-dc8e09559bd7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325786168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1325786168
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.4210942935
Short name T407
Test name
Test status
Simulation time 535743471 ps
CPU time 6.16 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:02:30 PM PST 24
Peak memory 198044 kb
Host smart-9049b4a0-efa6-4636-a105-9df529d8d999
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210942935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.4210942935
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1284374995
Short name T835
Test name
Test status
Simulation time 323624408 ps
CPU time 1.19 seconds
Started Jan 03 01:01:05 PM PST 24
Finished Jan 03 01:02:12 PM PST 24
Peak memory 196760 kb
Host smart-e895f1db-d50d-41d6-8b83-8356eeaacdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284374995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1284374995
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3802873746
Short name T804
Test name
Test status
Simulation time 61002969 ps
CPU time 1.38 seconds
Started Jan 03 01:01:10 PM PST 24
Finished Jan 03 01:02:18 PM PST 24
Peak memory 196900 kb
Host smart-29f1ce0b-b757-4a3b-947a-8e7b4d91c712
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802873746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3802873746
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3572235899
Short name T66
Test name
Test status
Simulation time 9030408775 ps
CPU time 62.1 seconds
Started Jan 03 01:01:22 PM PST 24
Finished Jan 03 01:03:33 PM PST 24
Peak memory 198360 kb
Host smart-0e19f965-bcd6-4402-a652-4c7ee89f3d97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572235899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3572235899
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.4050109043
Short name T682
Test name
Test status
Simulation time 670455309077 ps
CPU time 989.7 seconds
Started Jan 03 01:01:12 PM PST 24
Finished Jan 03 01:18:53 PM PST 24
Peak memory 198420 kb
Host smart-c69c7d77-b387-44fd-bf29-cbc6377b5d17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4050109043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.4050109043
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1707052629
Short name T365
Test name
Test status
Simulation time 14208902 ps
CPU time 0.57 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 194204 kb
Host smart-570f121d-c0a8-4cd4-bec9-414ff8efde19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707052629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1707052629
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.243181084
Short name T857
Test name
Test status
Simulation time 88923688 ps
CPU time 0.69 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 194788 kb
Host smart-fa668edf-b1c6-4fd9-9fe9-e1b9028f10aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243181084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.243181084
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.173944627
Short name T413
Test name
Test status
Simulation time 324126897 ps
CPU time 15.82 seconds
Started Jan 03 01:00:50 PM PST 24
Finished Jan 03 01:02:10 PM PST 24
Peak memory 197096 kb
Host smart-c92aca3c-a27b-4965-b302-7e9218e99040
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173944627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.173944627
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3855314439
Short name T494
Test name
Test status
Simulation time 28911383 ps
CPU time 0.61 seconds
Started Jan 03 01:00:32 PM PST 24
Finished Jan 03 01:01:39 PM PST 24
Peak memory 194352 kb
Host smart-afe6725d-38d8-4aa4-96fa-4696fc637c01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855314439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3855314439
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1527611547
Short name T864
Test name
Test status
Simulation time 690545425 ps
CPU time 1.18 seconds
Started Jan 03 01:00:31 PM PST 24
Finished Jan 03 01:01:39 PM PST 24
Peak memory 196160 kb
Host smart-60c2ccf1-16c2-4f9b-be43-88ea1d88b579
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527611547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1527611547
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3108749607
Short name T814
Test name
Test status
Simulation time 78401001 ps
CPU time 2.95 seconds
Started Jan 03 01:00:37 PM PST 24
Finished Jan 03 01:01:45 PM PST 24
Peak memory 198208 kb
Host smart-7db8edb9-0f32-4cd6-8754-34a5b48c4e1d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108749607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3108749607
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1830519409
Short name T717
Test name
Test status
Simulation time 96804880 ps
CPU time 2.14 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 198128 kb
Host smart-44830686-f89d-4cfd-b5ae-1ea55bde5c70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830519409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1830519409
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3604344402
Short name T263
Test name
Test status
Simulation time 36014876 ps
CPU time 0.73 seconds
Started Jan 03 01:00:36 PM PST 24
Finished Jan 03 01:01:43 PM PST 24
Peak memory 196076 kb
Host smart-546b8a46-5c1f-432b-935f-5d68e9504e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604344402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3604344402
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2402828325
Short name T291
Test name
Test status
Simulation time 42247077 ps
CPU time 0.92 seconds
Started Jan 03 01:00:32 PM PST 24
Finished Jan 03 01:01:39 PM PST 24
Peak memory 196700 kb
Host smart-a6910253-aa85-46e4-9da3-dd9d7c002de3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402828325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2402828325
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.4230812161
Short name T404
Test name
Test status
Simulation time 264704785 ps
CPU time 2.89 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:43 PM PST 24
Peak memory 198008 kb
Host smart-47b6912c-9e45-4e9c-b4f2-80970294137b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230812161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.4230812161
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1965218853
Short name T690
Test name
Test status
Simulation time 108511589 ps
CPU time 0.98 seconds
Started Jan 03 01:01:12 PM PST 24
Finished Jan 03 01:02:28 PM PST 24
Peak memory 195788 kb
Host smart-ccccf563-eaeb-408c-b463-5b1f3242be36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965218853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1965218853
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.672357506
Short name T287
Test name
Test status
Simulation time 177994591 ps
CPU time 1.36 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:27 PM PST 24
Peak memory 196652 kb
Host smart-d78af49e-87c2-42f6-8e62-4a29cd28d2b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672357506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.672357506
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2159654273
Short name T587
Test name
Test status
Simulation time 13456597413 ps
CPU time 50.2 seconds
Started Jan 03 01:00:38 PM PST 24
Finished Jan 03 01:02:33 PM PST 24
Peak memory 198204 kb
Host smart-2188e8e4-474f-4028-b023-5814bb092586
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159654273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2159654273
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3177736493
Short name T795
Test name
Test status
Simulation time 83446730663 ps
CPU time 962.48 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:17:57 PM PST 24
Peak memory 198372 kb
Host smart-b9802a77-a40f-487f-9e57-cf63a153e280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3177736493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3177736493
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3440751250
Short name T731
Test name
Test status
Simulation time 12959312 ps
CPU time 0.58 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:01:56 PM PST 24
Peak memory 194032 kb
Host smart-47b583dc-9979-4d13-82f0-013f2b6ef5fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440751250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3440751250
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2322519840
Short name T398
Test name
Test status
Simulation time 138732745 ps
CPU time 0.89 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 196672 kb
Host smart-4626927e-a0a3-4f38-bf3c-3c476fd6df42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322519840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2322519840
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3193502812
Short name T231
Test name
Test status
Simulation time 1741740138 ps
CPU time 16.27 seconds
Started Jan 03 01:00:38 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 195676 kb
Host smart-cd6cbca5-aea0-4507-bf89-10513d206ffc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193502812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3193502812
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2054200744
Short name T650
Test name
Test status
Simulation time 142893312 ps
CPU time 0.94 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:01:56 PM PST 24
Peak memory 196704 kb
Host smart-6f163518-e77a-4377-9fb5-759e85ba2999
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054200744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2054200744
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.4131064612
Short name T867
Test name
Test status
Simulation time 614957055 ps
CPU time 1.1 seconds
Started Jan 03 01:00:51 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 196204 kb
Host smart-e7d8a9d0-6709-4ab9-822f-0bfe18c5cb65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131064612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.4131064612
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.708586057
Short name T576
Test name
Test status
Simulation time 92360061 ps
CPU time 3.89 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 198260 kb
Host smart-50cf4ad7-e4a3-4718-9ea3-afbec6f56585
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708586057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.708586057
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2391544330
Short name T765
Test name
Test status
Simulation time 93638608 ps
CPU time 2.03 seconds
Started Jan 03 01:00:36 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 197368 kb
Host smart-5cebbc47-cc1a-4c3a-b0ff-4132704dc7d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391544330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2391544330
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1950896956
Short name T672
Test name
Test status
Simulation time 217578126 ps
CPU time 0.89 seconds
Started Jan 03 01:00:36 PM PST 24
Finished Jan 03 01:01:43 PM PST 24
Peak memory 196072 kb
Host smart-02da6c76-d199-4383-a507-8522568fc999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950896956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1950896956
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.368876587
Short name T285
Test name
Test status
Simulation time 52123236 ps
CPU time 1 seconds
Started Jan 03 01:00:36 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 196032 kb
Host smart-e65dd294-2968-4473-8c70-3b5908da8c19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368876587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.368876587
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.563524456
Short name T328
Test name
Test status
Simulation time 289469114 ps
CPU time 3.17 seconds
Started Jan 03 01:00:37 PM PST 24
Finished Jan 03 01:01:46 PM PST 24
Peak memory 198104 kb
Host smart-9f49d07d-323f-4bb1-b1cb-1fa5e9c04f9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563524456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.563524456
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1046050795
Short name T563
Test name
Test status
Simulation time 248516384 ps
CPU time 1.1 seconds
Started Jan 03 01:00:33 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 196372 kb
Host smart-2976c8a4-2fbb-46ae-94c7-e6e12dcdae06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046050795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1046050795
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1599825768
Short name T839
Test name
Test status
Simulation time 265777116 ps
CPU time 1.21 seconds
Started Jan 03 01:00:50 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 198036 kb
Host smart-816c6087-c6ca-4a27-8deb-14892100fb7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599825768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1599825768
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1239955010
Short name T777
Test name
Test status
Simulation time 36789760335 ps
CPU time 187.61 seconds
Started Jan 03 01:00:37 PM PST 24
Finished Jan 03 01:04:50 PM PST 24
Peak memory 198212 kb
Host smart-7d3b0951-2339-4667-99d4-fd3b4cc06839
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239955010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1239955010
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1028732497
Short name T73
Test name
Test status
Simulation time 25040888875 ps
CPU time 723.32 seconds
Started Jan 03 01:00:36 PM PST 24
Finished Jan 03 01:13:44 PM PST 24
Peak memory 198300 kb
Host smart-633f408c-c487-4074-902e-c72bc5d77c3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1028732497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1028732497
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.4229991572
Short name T50
Test name
Test status
Simulation time 17575481 ps
CPU time 0.55 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 194040 kb
Host smart-c565a73d-a060-4b31-945e-16af8004d910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229991572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.4229991572
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.856561616
Short name T873
Test name
Test status
Simulation time 179244695 ps
CPU time 0.65 seconds
Started Jan 03 01:00:39 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 194012 kb
Host smart-7932fe95-b2c8-47ac-a286-a7064ab8da9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856561616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.856561616
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.908732135
Short name T518
Test name
Test status
Simulation time 546202536 ps
CPU time 12.99 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:02:10 PM PST 24
Peak memory 198124 kb
Host smart-6f653526-4435-41b2-9e63-ac167b053db5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908732135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.908732135
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3922291593
Short name T381
Test name
Test status
Simulation time 395442214 ps
CPU time 1.05 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:01:56 PM PST 24
Peak memory 196660 kb
Host smart-a845241e-32fa-4f52-8539-f8c9471c9903
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922291593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3922291593
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1782987504
Short name T337
Test name
Test status
Simulation time 43186371 ps
CPU time 0.83 seconds
Started Jan 03 01:00:56 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 195348 kb
Host smart-6b923167-ea40-4ad8-9ac2-e4d940fe1df6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782987504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1782987504
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.479279495
Short name T422
Test name
Test status
Simulation time 19272551 ps
CPU time 0.89 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 196968 kb
Host smart-15abb0e0-0d92-463e-86e0-a8e135097ef2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479279495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.479279495
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2252754856
Short name T604
Test name
Test status
Simulation time 69776716 ps
CPU time 1.68 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 196564 kb
Host smart-39414fae-9afa-4b1e-a525-585c8206cfea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252754856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2252754856
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.739967538
Short name T355
Test name
Test status
Simulation time 26812739 ps
CPU time 0.94 seconds
Started Jan 03 01:00:49 PM PST 24
Finished Jan 03 01:01:52 PM PST 24
Peak memory 195832 kb
Host smart-66c0ef72-3471-4ca6-84a8-cc5926c03455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739967538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.739967538
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2539556456
Short name T367
Test name
Test status
Simulation time 208475972 ps
CPU time 1.08 seconds
Started Jan 03 01:00:39 PM PST 24
Finished Jan 03 01:01:45 PM PST 24
Peak memory 196572 kb
Host smart-10700ae7-2c36-4dc9-ab49-bc7fc5888b9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539556456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2539556456
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2516711279
Short name T397
Test name
Test status
Simulation time 249573370 ps
CPU time 2.86 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:03 PM PST 24
Peak memory 198036 kb
Host smart-b908798c-1707-46ba-91a3-cc3be90e84ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516711279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2516711279
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1631376784
Short name T784
Test name
Test status
Simulation time 48827262 ps
CPU time 0.83 seconds
Started Jan 03 01:00:40 PM PST 24
Finished Jan 03 01:01:45 PM PST 24
Peak memory 195240 kb
Host smart-f0d7502d-f46a-4538-bba5-6d1d06e552b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631376784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1631376784
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.61935878
Short name T507
Test name
Test status
Simulation time 143943601 ps
CPU time 1.12 seconds
Started Jan 03 01:00:36 PM PST 24
Finished Jan 03 01:01:42 PM PST 24
Peak memory 196408 kb
Host smart-33516e32-4ef4-4948-802d-027f0c6a207d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61935878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.61935878
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1134967299
Short name T288
Test name
Test status
Simulation time 7906798905 ps
CPU time 101.16 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:03:37 PM PST 24
Peak memory 198160 kb
Host smart-17f95753-8a99-49e0-98b3-969af342dfee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134967299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1134967299
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.4023229494
Short name T626
Test name
Test status
Simulation time 32730044078 ps
CPU time 274.8 seconds
Started Jan 03 01:00:40 PM PST 24
Finished Jan 03 01:06:20 PM PST 24
Peak memory 198256 kb
Host smart-32a37b95-4d26-4a4d-a3bf-34ad37c89aa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4023229494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.4023229494
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.991352970
Short name T324
Test name
Test status
Simulation time 24197978 ps
CPU time 0.55 seconds
Started Jan 03 01:01:02 PM PST 24
Finished Jan 03 01:02:07 PM PST 24
Peak memory 194064 kb
Host smart-bdd70b39-cafd-46d7-9934-124564ca98ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991352970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.991352970
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.460672216
Short name T633
Test name
Test status
Simulation time 41859090 ps
CPU time 0.69 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 195184 kb
Host smart-352b3055-6e91-4518-9fe8-5316769efe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460672216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.460672216
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1405712209
Short name T412
Test name
Test status
Simulation time 3483698542 ps
CPU time 23.93 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:02:21 PM PST 24
Peak memory 196936 kb
Host smart-446288b6-de63-459e-a748-cd3efc9e54b2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405712209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1405712209
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.97323533
Short name T655
Test name
Test status
Simulation time 273152756 ps
CPU time 0.91 seconds
Started Jan 03 01:01:11 PM PST 24
Finished Jan 03 01:02:17 PM PST 24
Peak memory 197152 kb
Host smart-98455de0-7577-48de-aa42-fc6fd409e0fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97323533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.97323533
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.187216074
Short name T210
Test name
Test status
Simulation time 20213151 ps
CPU time 0.73 seconds
Started Jan 03 01:01:10 PM PST 24
Finished Jan 03 01:02:17 PM PST 24
Peak memory 195608 kb
Host smart-0666c89f-eb7f-4151-b721-35899bb3026a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187216074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.187216074
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.521701387
Short name T582
Test name
Test status
Simulation time 62785024 ps
CPU time 2.45 seconds
Started Jan 03 01:01:14 PM PST 24
Finished Jan 03 01:02:23 PM PST 24
Peak memory 198128 kb
Host smart-96fc2d4a-1c51-449a-88e2-96b6155d5431
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521701387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.521701387
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3476577959
Short name T303
Test name
Test status
Simulation time 74582351 ps
CPU time 2.11 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:03 PM PST 24
Peak memory 197232 kb
Host smart-0171c53a-e0c8-4533-8faa-fdf846dce616
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476577959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3476577959
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1631955864
Short name T439
Test name
Test status
Simulation time 151561770 ps
CPU time 0.9 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:01 PM PST 24
Peak memory 196188 kb
Host smart-90525570-2349-4f35-b397-434045ef6b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631955864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1631955864
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2075918829
Short name T652
Test name
Test status
Simulation time 102290078 ps
CPU time 0.74 seconds
Started Jan 03 01:01:09 PM PST 24
Finished Jan 03 01:02:16 PM PST 24
Peak memory 195480 kb
Host smart-1146f5f0-a67d-47fc-aef1-7b2c82f9318e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075918829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2075918829
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3993761700
Short name T529
Test name
Test status
Simulation time 655850948 ps
CPU time 5.35 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 197980 kb
Host smart-1dfc41af-220f-47b5-9896-fc38f45c77c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993761700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3993761700
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3659492898
Short name T359
Test name
Test status
Simulation time 57547414 ps
CPU time 1.03 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 197336 kb
Host smart-eec6074a-391a-4b8a-961d-db1a8fc5eefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659492898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3659492898
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2040293300
Short name T506
Test name
Test status
Simulation time 96595148 ps
CPU time 1.28 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:01:57 PM PST 24
Peak memory 195836 kb
Host smart-668f36c3-d049-4e37-8920-c3af38525d6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040293300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2040293300
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.231217739
Short name T247
Test name
Test status
Simulation time 24359007712 ps
CPU time 86.8 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:03:21 PM PST 24
Peak memory 198208 kb
Host smart-17a96b52-b2e8-493a-bdcb-848e584432e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231217739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.231217739
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.2700068937
Short name T369
Test name
Test status
Simulation time 133274382908 ps
CPU time 1877.09 seconds
Started Jan 03 01:00:58 PM PST 24
Finished Jan 03 01:33:27 PM PST 24
Peak memory 198404 kb
Host smart-2f7c06c1-bf4f-49db-8c6d-9cb23208ef81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2700068937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.2700068937
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3828874351
Short name T720
Test name
Test status
Simulation time 34271072 ps
CPU time 0.58 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 194172 kb
Host smart-8d799910-a513-4048-b56d-61e1bb3d6536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828874351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3828874351
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1950686795
Short name T844
Test name
Test status
Simulation time 15933008 ps
CPU time 0.6 seconds
Started Jan 03 01:00:54 PM PST 24
Finished Jan 03 01:01:57 PM PST 24
Peak memory 194688 kb
Host smart-da57566f-e0e1-4102-b2d2-d903d311639e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950686795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1950686795
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.504194941
Short name T233
Test name
Test status
Simulation time 313170773 ps
CPU time 4.62 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 195660 kb
Host smart-4058dbe1-d8ac-4200-95c7-39cff04198cd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504194941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.504194941
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1067102786
Short name T216
Test name
Test status
Simulation time 206615721 ps
CPU time 0.79 seconds
Started Jan 03 01:00:41 PM PST 24
Finished Jan 03 01:01:46 PM PST 24
Peak memory 195900 kb
Host smart-35540b3b-67a3-4241-8f4b-df71630e9692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067102786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1067102786
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3178407465
Short name T223
Test name
Test status
Simulation time 177014981 ps
CPU time 1.17 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 195892 kb
Host smart-7bbfcd8e-4b1d-4916-a706-1820456731b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178407465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3178407465
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1267790331
Short name T500
Test name
Test status
Simulation time 91491005 ps
CPU time 1.11 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 196976 kb
Host smart-eeb30fb3-63be-4340-9389-6bcbbd73f62e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267790331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1267790331
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.422551477
Short name T739
Test name
Test status
Simulation time 136951745 ps
CPU time 0.98 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 195524 kb
Host smart-48dbae2f-7ca9-46b7-ab30-931b2c7bff92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422551477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
422551477
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.110105136
Short name T730
Test name
Test status
Simulation time 45370491 ps
CPU time 1 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:23 PM PST 24
Peak memory 196016 kb
Host smart-94ba5a0b-bece-4597-8726-4f825f653f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110105136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.110105136
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1902729072
Short name T552
Test name
Test status
Simulation time 87838061 ps
CPU time 0.82 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:02:08 PM PST 24
Peak memory 197116 kb
Host smart-c92ad836-b353-4221-9f6e-c675fd290850
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902729072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1902729072
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.696761369
Short name T688
Test name
Test status
Simulation time 177783542 ps
CPU time 2.08 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:01:57 PM PST 24
Peak memory 198044 kb
Host smart-da0ad95d-dcc4-4a1a-aaa4-9d9e13281b3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696761369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.696761369
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1468089391
Short name T430
Test name
Test status
Simulation time 151353596 ps
CPU time 0.89 seconds
Started Jan 03 01:01:11 PM PST 24
Finished Jan 03 01:02:17 PM PST 24
Peak memory 195976 kb
Host smart-6d6348cd-888a-4874-88d6-52fd1aaafc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468089391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1468089391
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1937944368
Short name T456
Test name
Test status
Simulation time 103351174 ps
CPU time 0.84 seconds
Started Jan 03 01:00:51 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 195440 kb
Host smart-0611d2d2-ba1c-4bc3-aeae-eae37525e35e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937944368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1937944368
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.86333241
Short name T241
Test name
Test status
Simulation time 33151653848 ps
CPU time 108.44 seconds
Started Jan 03 01:00:39 PM PST 24
Finished Jan 03 01:03:31 PM PST 24
Peak memory 198236 kb
Host smart-3d1f8cb0-ad15-4aae-a162-4aa79cd41c52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86333241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gp
io_stress_all.86333241
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2516571386
Short name T294
Test name
Test status
Simulation time 424544599194 ps
CPU time 793.18 seconds
Started Jan 03 01:00:48 PM PST 24
Finished Jan 03 01:15:04 PM PST 24
Peak memory 206548 kb
Host smart-27d18501-dc0a-4a4f-a9cb-66ffa0795994
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2516571386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2516571386
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2420393920
Short name T590
Test name
Test status
Simulation time 142181385 ps
CPU time 0.56 seconds
Started Jan 03 12:59:42 PM PST 24
Finished Jan 03 01:00:39 PM PST 24
Peak memory 194300 kb
Host smart-0cd20d63-80c3-4054-8617-8ae087771b44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420393920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2420393920
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1613250463
Short name T222
Test name
Test status
Simulation time 68390954 ps
CPU time 0.79 seconds
Started Jan 03 12:59:53 PM PST 24
Finished Jan 03 01:00:53 PM PST 24
Peak memory 195948 kb
Host smart-005f9976-fb0c-4e67-bce6-87001c6bb332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613250463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1613250463
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2821995469
Short name T429
Test name
Test status
Simulation time 5462776189 ps
CPU time 18.2 seconds
Started Jan 03 12:59:50 PM PST 24
Finished Jan 03 01:01:07 PM PST 24
Peak memory 196976 kb
Host smart-55dcc653-96c3-49c0-ad9c-f43cb5f44696
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821995469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2821995469
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2897822868
Short name T766
Test name
Test status
Simulation time 245282802 ps
CPU time 0.9 seconds
Started Jan 03 12:59:33 PM PST 24
Finished Jan 03 01:00:26 PM PST 24
Peak memory 197900 kb
Host smart-4c146bb8-a96d-4163-b691-9e5e8d2f640b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897822868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2897822868
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.649753439
Short name T658
Test name
Test status
Simulation time 129986502 ps
CPU time 1.02 seconds
Started Jan 03 12:59:46 PM PST 24
Finished Jan 03 01:00:45 PM PST 24
Peak memory 196852 kb
Host smart-83486126-8563-48a0-be5e-c95155fb691d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649753439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.649753439
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3273420995
Short name T371
Test name
Test status
Simulation time 30378416 ps
CPU time 1.23 seconds
Started Jan 03 12:59:48 PM PST 24
Finished Jan 03 01:00:48 PM PST 24
Peak memory 196940 kb
Host smart-f6166cdc-1f32-45c7-bd3c-99e8b44743bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273420995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3273420995
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.194730907
Short name T225
Test name
Test status
Simulation time 144984291 ps
CPU time 0.83 seconds
Started Jan 03 12:59:35 PM PST 24
Finished Jan 03 01:00:28 PM PST 24
Peak memory 195120 kb
Host smart-02fb57e7-7e3e-4d3a-9119-b853b189d699
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194730907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.194730907
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1179489169
Short name T345
Test name
Test status
Simulation time 598788739 ps
CPU time 0.93 seconds
Started Jan 03 12:59:35 PM PST 24
Finished Jan 03 01:00:28 PM PST 24
Peak memory 196792 kb
Host smart-68ff60fb-b124-44a5-a8b7-eb9aad3840ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179489169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1179489169
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1643911420
Short name T356
Test name
Test status
Simulation time 54344919 ps
CPU time 0.99 seconds
Started Jan 03 12:59:34 PM PST 24
Finished Jan 03 01:00:27 PM PST 24
Peak memory 196072 kb
Host smart-a0dab63b-80bb-4b94-af45-90d577a92190
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643911420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1643911420
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1940867573
Short name T348
Test name
Test status
Simulation time 1928506662 ps
CPU time 6.18 seconds
Started Jan 03 12:59:49 PM PST 24
Finished Jan 03 01:00:54 PM PST 24
Peak memory 198100 kb
Host smart-c810489b-a770-4281-808f-ca135c355763
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940867573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1940867573
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.884171984
Short name T62
Test name
Test status
Simulation time 112328995 ps
CPU time 0.77 seconds
Started Jan 03 12:59:42 PM PST 24
Finished Jan 03 01:00:39 PM PST 24
Peak memory 213564 kb
Host smart-777b9a81-8bb7-4edd-95d9-2211501bf9da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884171984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.884171984
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.745202308
Short name T512
Test name
Test status
Simulation time 121958401 ps
CPU time 0.99 seconds
Started Jan 03 12:59:39 PM PST 24
Finished Jan 03 01:00:34 PM PST 24
Peak memory 196460 kb
Host smart-f45070d3-12e8-4ea1-82ec-5a11dd1b574d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745202308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.745202308
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1019930841
Short name T535
Test name
Test status
Simulation time 154998111 ps
CPU time 1.02 seconds
Started Jan 03 12:59:41 PM PST 24
Finished Jan 03 01:00:36 PM PST 24
Peak memory 195788 kb
Host smart-c70d2794-653a-4f97-90da-4f98d3e95bb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019930841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1019930841
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.823652817
Short name T336
Test name
Test status
Simulation time 9234649553 ps
CPU time 61.09 seconds
Started Jan 03 12:59:36 PM PST 24
Finished Jan 03 01:01:29 PM PST 24
Peak memory 198264 kb
Host smart-a3ea6369-77dc-4758-87f4-224917632375
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823652817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.823652817
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1455454013
Short name T703
Test name
Test status
Simulation time 16311044987 ps
CPU time 350.72 seconds
Started Jan 03 12:59:37 PM PST 24
Finished Jan 03 01:06:20 PM PST 24
Peak memory 198356 kb
Host smart-b9dced6d-819e-43a5-9728-1c9a17e1cf83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1455454013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1455454013
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1743467401
Short name T868
Test name
Test status
Simulation time 43344726 ps
CPU time 0.55 seconds
Started Jan 03 01:00:59 PM PST 24
Finished Jan 03 01:02:06 PM PST 24
Peak memory 194064 kb
Host smart-1cbbbb42-f871-4a7a-8817-c4f34acaada8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743467401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1743467401
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1515532672
Short name T275
Test name
Test status
Simulation time 720694207 ps
CPU time 0.93 seconds
Started Jan 03 01:01:09 PM PST 24
Finished Jan 03 01:02:16 PM PST 24
Peak memory 197208 kb
Host smart-4250c468-d2d4-431a-bad5-201b28e094fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515532672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1515532672
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2901137964
Short name T806
Test name
Test status
Simulation time 1961769839 ps
CPU time 20.61 seconds
Started Jan 03 01:00:59 PM PST 24
Finished Jan 03 01:02:26 PM PST 24
Peak memory 195620 kb
Host smart-f28cf8f5-da30-435c-ac8b-4dd9f2198359
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901137964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2901137964
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1432713735
Short name T602
Test name
Test status
Simulation time 74975128 ps
CPU time 0.64 seconds
Started Jan 03 01:01:03 PM PST 24
Finished Jan 03 01:02:09 PM PST 24
Peak memory 195272 kb
Host smart-33f86891-cc76-4fc1-a610-0348ea273023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432713735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1432713735
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.4211646229
Short name T246
Test name
Test status
Simulation time 47878967 ps
CPU time 1.21 seconds
Started Jan 03 01:01:10 PM PST 24
Finished Jan 03 01:02:18 PM PST 24
Peak memory 196680 kb
Host smart-b60f3790-0788-4f4a-9ab5-7ac0d87768d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211646229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.4211646229
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2470364808
Short name T392
Test name
Test status
Simulation time 769016910 ps
CPU time 3.1 seconds
Started Jan 03 01:00:58 PM PST 24
Finished Jan 03 01:02:04 PM PST 24
Peak memory 198272 kb
Host smart-6c9f1d88-ffef-44a4-b7c3-329fd71fb6ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470364808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2470364808
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.705282033
Short name T540
Test name
Test status
Simulation time 175485930 ps
CPU time 3.13 seconds
Started Jan 03 01:01:09 PM PST 24
Finished Jan 03 01:02:19 PM PST 24
Peak memory 195976 kb
Host smart-82667321-d47c-40d6-90f7-69f7134a45e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705282033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
705282033
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.779005104
Short name T217
Test name
Test status
Simulation time 25593833 ps
CPU time 0.89 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 196632 kb
Host smart-c02b7982-85ff-4439-a2f8-fa02bba38182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779005104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.779005104
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.336240775
Short name T671
Test name
Test status
Simulation time 101064715 ps
CPU time 1.05 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 196064 kb
Host smart-a39cfa44-c185-4170-b6ef-db3da2d3c6ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336240775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.336240775
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2495570690
Short name T458
Test name
Test status
Simulation time 254868538 ps
CPU time 2.23 seconds
Started Jan 03 01:01:22 PM PST 24
Finished Jan 03 01:02:31 PM PST 24
Peak memory 198040 kb
Host smart-974722a3-4e13-4861-80f3-6044e27ef06a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495570690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2495570690
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2751923930
Short name T267
Test name
Test status
Simulation time 61205307 ps
CPU time 0.97 seconds
Started Jan 03 01:00:51 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 196440 kb
Host smart-cef2539c-90a0-4c70-ab07-e7fcbb135806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751923930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2751923930
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3121304707
Short name T504
Test name
Test status
Simulation time 47421599 ps
CPU time 0.83 seconds
Started Jan 03 01:00:54 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 196148 kb
Host smart-55e1ecde-567f-4b31-84e9-7d9b8f9e77e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121304707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3121304707
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2837797760
Short name T674
Test name
Test status
Simulation time 30880155658 ps
CPU time 186.89 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:05:08 PM PST 24
Peak memory 198268 kb
Host smart-55bae311-2193-4207-bddf-bbf0177e6707
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837797760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2837797760
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.785300670
Short name T71
Test name
Test status
Simulation time 9334626547 ps
CPU time 149.07 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:04:53 PM PST 24
Peak memory 198364 kb
Host smart-1fe2baab-3c61-46d1-b473-3e7eacc92786
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=785300670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.785300670
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1089142417
Short name T431
Test name
Test status
Simulation time 12698719 ps
CPU time 0.56 seconds
Started Jan 03 01:01:00 PM PST 24
Finished Jan 03 01:02:06 PM PST 24
Peak memory 194060 kb
Host smart-cf35af32-0332-4c64-b377-a0673c29f530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089142417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1089142417
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3069746159
Short name T622
Test name
Test status
Simulation time 143793689 ps
CPU time 0.84 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:23 PM PST 24
Peak memory 195332 kb
Host smart-3ddd6db8-b5a2-4847-b089-4ae3d32e3a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069746159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3069746159
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1105217317
Short name T583
Test name
Test status
Simulation time 344834539 ps
CPU time 8.92 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:35 PM PST 24
Peak memory 197052 kb
Host smart-78b2cfc5-7a1b-4c38-aed6-686015f63fcc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105217317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1105217317
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2251034367
Short name T208
Test name
Test status
Simulation time 23708709 ps
CPU time 0.64 seconds
Started Jan 03 01:00:54 PM PST 24
Finished Jan 03 01:01:57 PM PST 24
Peak memory 195224 kb
Host smart-f8c409ca-59e2-4bbb-a134-97e96cc51326
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251034367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2251034367
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2893617604
Short name T863
Test name
Test status
Simulation time 242951579 ps
CPU time 1.03 seconds
Started Jan 03 01:01:15 PM PST 24
Finished Jan 03 01:02:22 PM PST 24
Peak memory 196124 kb
Host smart-6ed3d3c1-346e-4fd4-997f-345663929894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893617604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2893617604
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1775572833
Short name T260
Test name
Test status
Simulation time 100136144 ps
CPU time 3.56 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:02:28 PM PST 24
Peak memory 198276 kb
Host smart-a7d2405d-ddd1-47e7-9bb8-2e42c8f51454
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775572833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1775572833
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.375143814
Short name T837
Test name
Test status
Simulation time 172908374 ps
CPU time 1.15 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:25 PM PST 24
Peak memory 196208 kb
Host smart-9ec4d3c7-8168-4f59-8ea6-62040c27955e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375143814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
375143814
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.613416034
Short name T230
Test name
Test status
Simulation time 24541334 ps
CPU time 0.88 seconds
Started Jan 03 01:01:12 PM PST 24
Finished Jan 03 01:02:18 PM PST 24
Peak memory 196164 kb
Host smart-9cf1d270-2149-4e0c-b117-43bb3a966d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613416034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.613416034
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2719600723
Short name T619
Test name
Test status
Simulation time 24277099 ps
CPU time 0.88 seconds
Started Jan 03 01:01:11 PM PST 24
Finished Jan 03 01:02:17 PM PST 24
Peak memory 196136 kb
Host smart-f31748c7-f29f-43fe-a682-5d7dc5262e0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719600723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2719600723
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2941152202
Short name T609
Test name
Test status
Simulation time 333958022 ps
CPU time 3.99 seconds
Started Jan 03 01:01:22 PM PST 24
Finished Jan 03 01:02:33 PM PST 24
Peak memory 197192 kb
Host smart-694b5b9a-a005-41ca-9c94-cc6f6bd24c64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941152202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2941152202
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.966725995
Short name T798
Test name
Test status
Simulation time 67921153 ps
CPU time 1.23 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 195944 kb
Host smart-07d9e5c5-ce08-4ed9-ba07-276aa77b5b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966725995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.966725995
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.4191873223
Short name T556
Test name
Test status
Simulation time 120238663 ps
CPU time 0.93 seconds
Started Jan 03 01:01:11 PM PST 24
Finished Jan 03 01:02:18 PM PST 24
Peak memory 196616 kb
Host smart-d54bf470-d3f6-46a3-9fc7-61a37895e67c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191873223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.4191873223
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3978265085
Short name T533
Test name
Test status
Simulation time 6734827630 ps
CPU time 155.02 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:04:32 PM PST 24
Peak memory 198032 kb
Host smart-296eae68-2bfa-466c-9a1a-cf1a03905c24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978265085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3978265085
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.1105046372
Short name T266
Test name
Test status
Simulation time 248292390053 ps
CPU time 666.2 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:13:02 PM PST 24
Peak memory 198336 kb
Host smart-8cba307e-6062-4d86-9a1a-82a9524f1b94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1105046372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.1105046372
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2866697302
Short name T520
Test name
Test status
Simulation time 122451182 ps
CPU time 0.55 seconds
Started Jan 03 01:00:56 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 194768 kb
Host smart-4ea32680-ebf4-4cc1-848a-732b21467f3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866697302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2866697302
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2863670132
Short name T519
Test name
Test status
Simulation time 51250540 ps
CPU time 0.68 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:01 PM PST 24
Peak memory 194220 kb
Host smart-19e7d0fd-21ce-44d6-825e-c6de7f516fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863670132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2863670132
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.4126297411
Short name T255
Test name
Test status
Simulation time 610163258 ps
CPU time 5.18 seconds
Started Jan 03 01:00:49 PM PST 24
Finished Jan 03 01:01:57 PM PST 24
Peak memory 197004 kb
Host smart-d37c788c-801c-42cc-850f-64cf669981ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126297411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.4126297411
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1795094346
Short name T597
Test name
Test status
Simulation time 33916654 ps
CPU time 0.71 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 194788 kb
Host smart-d47facba-cab9-46c9-ba87-c11697b1cf2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795094346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1795094346
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3301014288
Short name T732
Test name
Test status
Simulation time 250159475 ps
CPU time 1.15 seconds
Started Jan 03 01:00:47 PM PST 24
Finished Jan 03 01:01:51 PM PST 24
Peak memory 196856 kb
Host smart-cbe16080-88c1-4be2-8012-4ddf250a107c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301014288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3301014288
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.164001066
Short name T358
Test name
Test status
Simulation time 62257373 ps
CPU time 2.29 seconds
Started Jan 03 01:00:56 PM PST 24
Finished Jan 03 01:02:01 PM PST 24
Peak memory 197284 kb
Host smart-75b50eed-2e4e-4a82-896e-991cf14f3d33
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164001066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.164001066
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1877652240
Short name T353
Test name
Test status
Simulation time 562480503 ps
CPU time 2.78 seconds
Started Jan 03 01:00:48 PM PST 24
Finished Jan 03 01:01:54 PM PST 24
Peak memory 198148 kb
Host smart-609a3410-5734-4a74-8c5f-f22e2214544a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877652240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1877652240
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.273340964
Short name T521
Test name
Test status
Simulation time 47449423 ps
CPU time 0.96 seconds
Started Jan 03 01:00:47 PM PST 24
Finished Jan 03 01:01:52 PM PST 24
Peak memory 196720 kb
Host smart-41c0faf8-fcbe-492b-8ef1-108cdbdda82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273340964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.273340964
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1721438790
Short name T681
Test name
Test status
Simulation time 22866821 ps
CPU time 0.95 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:01 PM PST 24
Peak memory 195840 kb
Host smart-a551bc80-0889-414f-a320-0b7151c2f2c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721438790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1721438790
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3326869456
Short name T571
Test name
Test status
Simulation time 68277967 ps
CPU time 1.23 seconds
Started Jan 03 01:00:52 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 198104 kb
Host smart-e23e79ac-5577-48e7-854c-81e46b761de7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326869456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3326869456
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2604880327
Short name T228
Test name
Test status
Simulation time 141323148 ps
CPU time 1.23 seconds
Started Jan 03 01:00:59 PM PST 24
Finished Jan 03 01:02:06 PM PST 24
Peak memory 195928 kb
Host smart-25691831-83dd-474f-bba6-9e0d4d5f27fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604880327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2604880327
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2210501555
Short name T326
Test name
Test status
Simulation time 108537382 ps
CPU time 1.13 seconds
Started Jan 03 01:00:50 PM PST 24
Finished Jan 03 01:01:53 PM PST 24
Peak memory 196676 kb
Host smart-788e49f8-4c03-4372-bbc6-81885e3b4e58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210501555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2210501555
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3824610966
Short name T470
Test name
Test status
Simulation time 45252707994 ps
CPU time 235.64 seconds
Started Jan 03 01:01:01 PM PST 24
Finished Jan 03 01:06:01 PM PST 24
Peak memory 197036 kb
Host smart-22966fa7-5ee0-4ed0-af6f-af9d715b217d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824610966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3824610966
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.4104934201
Short name T634
Test name
Test status
Simulation time 213031125113 ps
CPU time 1041.61 seconds
Started Jan 03 01:00:56 PM PST 24
Finished Jan 03 01:19:19 PM PST 24
Peak memory 198276 kb
Host smart-7f494a5d-078e-48de-9ed2-4afb324f684a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4104934201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.4104934201
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.752172047
Short name T686
Test name
Test status
Simulation time 13920993 ps
CPU time 0.55 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:22 PM PST 24
Peak memory 194708 kb
Host smart-7b1b2dac-97de-49a2-a8bb-185b33cc9870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752172047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.752172047
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1494452736
Short name T313
Test name
Test status
Simulation time 23581202 ps
CPU time 0.6 seconds
Started Jan 03 01:01:05 PM PST 24
Finished Jan 03 01:02:12 PM PST 24
Peak memory 193956 kb
Host smart-f03e7dd0-cd78-448a-8407-46abb2b1be68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494452736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1494452736
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2218720083
Short name T792
Test name
Test status
Simulation time 1296909901 ps
CPU time 16.31 seconds
Started Jan 03 01:01:14 PM PST 24
Finished Jan 03 01:02:36 PM PST 24
Peak memory 198104 kb
Host smart-1d8a0074-d84e-4cef-97f5-ab4d6ee8208a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218720083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2218720083
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.4210617633
Short name T232
Test name
Test status
Simulation time 67807109 ps
CPU time 0.88 seconds
Started Jan 03 01:01:13 PM PST 24
Finished Jan 03 01:02:20 PM PST 24
Peak memory 197204 kb
Host smart-4e739892-129b-4c25-91af-0ed70d4433ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210617633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.4210617633
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1633612709
Short name T471
Test name
Test status
Simulation time 94092518 ps
CPU time 1.37 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:01 PM PST 24
Peak memory 198176 kb
Host smart-c14610fc-3d8d-4202-a198-8bcae8b60dbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633612709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1633612709
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3000241099
Short name T382
Test name
Test status
Simulation time 727281467 ps
CPU time 3.69 seconds
Started Jan 03 01:01:01 PM PST 24
Finished Jan 03 01:02:11 PM PST 24
Peak memory 198224 kb
Host smart-f65f5774-8941-4152-b60d-1e4a27166cbf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000241099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3000241099
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3756612882
Short name T340
Test name
Test status
Simulation time 990387234 ps
CPU time 2.81 seconds
Started Jan 03 01:01:12 PM PST 24
Finished Jan 03 01:02:20 PM PST 24
Peak memory 197380 kb
Host smart-fcb9ef6b-3331-400d-8897-5e4c69e210f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756612882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3756612882
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1435789541
Short name T727
Test name
Test status
Simulation time 247166337 ps
CPU time 1.02 seconds
Started Jan 03 01:00:59 PM PST 24
Finished Jan 03 01:02:06 PM PST 24
Peak memory 196548 kb
Host smart-a1f4d11a-e6da-4876-9309-101fd5d39210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435789541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1435789541
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.4017568702
Short name T489
Test name
Test status
Simulation time 58620157 ps
CPU time 0.71 seconds
Started Jan 03 01:01:15 PM PST 24
Finished Jan 03 01:02:24 PM PST 24
Peak memory 196228 kb
Host smart-3ede5cdb-80fc-404e-b3e2-a4cc90ca3abc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017568702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.4017568702
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.267527597
Short name T701
Test name
Test status
Simulation time 225237939 ps
CPU time 1.58 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:28 PM PST 24
Peak memory 197996 kb
Host smart-c7426de9-8e22-4b19-b96c-68e990a4df7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267527597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.267527597
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.672463272
Short name T406
Test name
Test status
Simulation time 33144606 ps
CPU time 1.04 seconds
Started Jan 03 01:01:10 PM PST 24
Finished Jan 03 01:02:17 PM PST 24
Peak memory 196000 kb
Host smart-43271586-0251-4b0d-94ee-93aa0c42bca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672463272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.672463272
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.4254911940
Short name T770
Test name
Test status
Simulation time 97132355 ps
CPU time 0.72 seconds
Started Jan 03 01:00:56 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 195108 kb
Host smart-1625c170-dfa1-4c94-891e-7e2a5f90740a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254911940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.4254911940
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.844070098
Short name T335
Test name
Test status
Simulation time 12857141678 ps
CPU time 170.63 seconds
Started Jan 03 01:01:14 PM PST 24
Finished Jan 03 01:05:11 PM PST 24
Peak memory 198204 kb
Host smart-dcdde5c1-97c7-4a45-9d6f-55a8b94eeb0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844070098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.844070098
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.535630399
Short name T767
Test name
Test status
Simulation time 675097065734 ps
CPU time 1781.29 seconds
Started Jan 03 01:00:58 PM PST 24
Finished Jan 03 01:31:43 PM PST 24
Peak memory 198292 kb
Host smart-7db0167e-6a96-487a-b7a6-f474e6328c80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=535630399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.535630399
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.835065176
Short name T428
Test name
Test status
Simulation time 47041034 ps
CPU time 0.54 seconds
Started Jan 03 01:01:28 PM PST 24
Finished Jan 03 01:02:38 PM PST 24
Peak memory 194676 kb
Host smart-2bbac0e1-197f-4f83-9070-5fe2b0e9b0b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835065176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.835065176
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.4199659950
Short name T758
Test name
Test status
Simulation time 362980805 ps
CPU time 0.75 seconds
Started Jan 03 01:01:23 PM PST 24
Finished Jan 03 01:02:32 PM PST 24
Peak memory 195372 kb
Host smart-d098318b-9048-4dcd-a61a-4a19ef7584fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199659950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.4199659950
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2907928217
Short name T250
Test name
Test status
Simulation time 486938070 ps
CPU time 12.7 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:37 PM PST 24
Peak memory 196352 kb
Host smart-6fa5fbe3-a443-4e73-ae08-5aaa63551945
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907928217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2907928217
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1675423231
Short name T409
Test name
Test status
Simulation time 135641686 ps
CPU time 0.9 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:02:25 PM PST 24
Peak memory 197356 kb
Host smart-14a54899-2a8d-4a37-aecc-e8b4f8f3a6ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675423231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1675423231
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2118491933
Short name T289
Test name
Test status
Simulation time 96382821 ps
CPU time 1.26 seconds
Started Jan 03 01:01:21 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 196776 kb
Host smart-f46cb4ac-ed05-4673-9c1f-f0a1400719f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118491933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2118491933
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1628308577
Short name T265
Test name
Test status
Simulation time 92967979 ps
CPU time 3.38 seconds
Started Jan 03 01:01:11 PM PST 24
Finished Jan 03 01:02:21 PM PST 24
Peak memory 198148 kb
Host smart-5d14db52-7998-414d-bc03-fc798274e0de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628308577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1628308577
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3590884795
Short name T755
Test name
Test status
Simulation time 113668642 ps
CPU time 1.8 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 198192 kb
Host smart-c0faf72f-1319-4f38-920d-419e7dd58748
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590884795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3590884795
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3677398372
Short name T638
Test name
Test status
Simulation time 86148590 ps
CPU time 0.95 seconds
Started Jan 03 01:01:14 PM PST 24
Finished Jan 03 01:02:21 PM PST 24
Peak memory 196596 kb
Host smart-9dea0796-240c-445f-96ad-e1621ea8e732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677398372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3677398372
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.161974767
Short name T378
Test name
Test status
Simulation time 35531229 ps
CPU time 1.21 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:24 PM PST 24
Peak memory 197032 kb
Host smart-285ea15d-2e83-4d2b-9a2b-3af7b2f6411a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161974767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.161974767
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.4214763805
Short name T524
Test name
Test status
Simulation time 1338148851 ps
CPU time 5.58 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:30 PM PST 24
Peak memory 198048 kb
Host smart-358bb900-fa1a-4110-b7ea-159eaf80fe07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214763805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.4214763805
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1565517853
Short name T484
Test name
Test status
Simulation time 131788470 ps
CPU time 1.05 seconds
Started Jan 03 01:01:15 PM PST 24
Finished Jan 03 01:02:22 PM PST 24
Peak memory 196392 kb
Host smart-cbbaaaee-b905-4de2-99a7-15eaf95bb6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565517853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1565517853
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3553990667
Short name T380
Test name
Test status
Simulation time 67152677 ps
CPU time 1.12 seconds
Started Jan 03 01:01:22 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 195688 kb
Host smart-b0998e13-e15f-4297-83b7-8220b4cfc23b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553990667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3553990667
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.4175200002
Short name T875
Test name
Test status
Simulation time 9916282718 ps
CPU time 123.95 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:04:26 PM PST 24
Peak memory 198260 kb
Host smart-c0d79e46-d59d-43fb-92b0-c09958edb36a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175200002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.4175200002
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3172013857
Short name T377
Test name
Test status
Simulation time 37866544800 ps
CPU time 317.35 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:07:41 PM PST 24
Peak memory 198428 kb
Host smart-c76bfdea-f5d8-49bf-941b-3f41a121c38c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3172013857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3172013857
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1913047622
Short name T304
Test name
Test status
Simulation time 43307239 ps
CPU time 0.56 seconds
Started Jan 03 01:00:50 PM PST 24
Finished Jan 03 01:01:53 PM PST 24
Peak memory 194184 kb
Host smart-e859f5c9-a14d-43a4-a2e0-0c8b3b6cfffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913047622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1913047622
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.4243622876
Short name T539
Test name
Test status
Simulation time 32961362 ps
CPU time 0.63 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:01:56 PM PST 24
Peak memory 194684 kb
Host smart-583e0201-f63a-46c5-93af-4a4aa5261c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243622876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.4243622876
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.901731501
Short name T350
Test name
Test status
Simulation time 765037987 ps
CPU time 25.23 seconds
Started Jan 03 01:00:48 PM PST 24
Finished Jan 03 01:02:16 PM PST 24
Peak memory 198092 kb
Host smart-5076cf50-bc00-4eca-8c8e-03542ef5f56a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901731501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.901731501
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2583298080
Short name T551
Test name
Test status
Simulation time 349965234 ps
CPU time 0.98 seconds
Started Jan 03 01:00:53 PM PST 24
Finished Jan 03 01:02:05 PM PST 24
Peak memory 196528 kb
Host smart-a3564922-5c00-41c3-bb4e-a89f4ab94771
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583298080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2583298080
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.780591852
Short name T851
Test name
Test status
Simulation time 50411062 ps
CPU time 1.32 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 198148 kb
Host smart-63c96a79-91a0-430c-b43f-bdb3929500a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780591852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.780591852
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.449459464
Short name T257
Test name
Test status
Simulation time 94558960 ps
CPU time 3.5 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:03 PM PST 24
Peak memory 198112 kb
Host smart-c359a174-177b-497e-8464-fd2e28acfc5b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449459464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.449459464
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3214328144
Short name T522
Test name
Test status
Simulation time 301853429 ps
CPU time 2.9 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 198184 kb
Host smart-9d2f20c2-775d-4ce1-9df5-3391ded3e045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214328144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3214328144
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.4178735430
Short name T437
Test name
Test status
Simulation time 205453146 ps
CPU time 1.1 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:02:35 PM PST 24
Peak memory 195832 kb
Host smart-6a225309-d68e-42ad-87c3-49f56b0b6898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178735430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.4178735430
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.646598231
Short name T481
Test name
Test status
Simulation time 34503234 ps
CPU time 0.84 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:25 PM PST 24
Peak memory 196528 kb
Host smart-2df40987-e398-4340-a89f-10fec7b5a73e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646598231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.646598231
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.4237589495
Short name T662
Test name
Test status
Simulation time 566406847 ps
CPU time 2.09 seconds
Started Jan 03 01:00:51 PM PST 24
Finished Jan 03 01:01:55 PM PST 24
Peak memory 197976 kb
Host smart-c748b647-13d9-456c-9b85-75aae47af9de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237589495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.4237589495
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.234260173
Short name T282
Test name
Test status
Simulation time 342833601 ps
CPU time 1.12 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:02:35 PM PST 24
Peak memory 195760 kb
Host smart-8e8642d3-4d0f-4688-b5ba-1e9e4d192e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234260173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.234260173
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3758042085
Short name T455
Test name
Test status
Simulation time 65070299 ps
CPU time 1.12 seconds
Started Jan 03 01:01:22 PM PST 24
Finished Jan 03 01:02:30 PM PST 24
Peak memory 195584 kb
Host smart-a701ab54-3d0f-40af-b57a-e81b001f7e01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758042085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3758042085
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2286247707
Short name T783
Test name
Test status
Simulation time 14669923071 ps
CPU time 102.28 seconds
Started Jan 03 01:00:54 PM PST 24
Finished Jan 03 01:03:38 PM PST 24
Peak memory 198124 kb
Host smart-1f2953a9-4b4d-4207-8e63-3cb315d9ed6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286247707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2286247707
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2559972439
Short name T754
Test name
Test status
Simulation time 316911713374 ps
CPU time 1380.65 seconds
Started Jan 03 01:01:01 PM PST 24
Finished Jan 03 01:25:06 PM PST 24
Peak memory 198260 kb
Host smart-ae334f35-6663-4b13-afd9-b0c0c2e1f41e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2559972439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2559972439
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1536919740
Short name T385
Test name
Test status
Simulation time 13351534 ps
CPU time 0.55 seconds
Started Jan 03 01:01:14 PM PST 24
Finished Jan 03 01:02:20 PM PST 24
Peak memory 194200 kb
Host smart-51224806-45d5-4dc3-945a-bde14e20b51f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536919740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1536919740
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1528045893
Short name T726
Test name
Test status
Simulation time 30826706 ps
CPU time 0.84 seconds
Started Jan 03 01:01:07 PM PST 24
Finished Jan 03 01:02:15 PM PST 24
Peak memory 196592 kb
Host smart-a139260c-f551-4a41-beb5-11e595576778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528045893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1528045893
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.4141191601
Short name T675
Test name
Test status
Simulation time 2975126505 ps
CPU time 22.89 seconds
Started Jan 03 01:00:58 PM PST 24
Finished Jan 03 01:02:24 PM PST 24
Peak memory 196664 kb
Host smart-4bb4724a-20cd-461a-8338-6432ba8752fd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141191601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.4141191601
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.540420387
Short name T272
Test name
Test status
Simulation time 417069248 ps
CPU time 0.95 seconds
Started Jan 03 01:01:14 PM PST 24
Finished Jan 03 01:02:21 PM PST 24
Peak memory 196980 kb
Host smart-a9b59883-fea0-41cf-a1ac-53659dc82bb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540420387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.540420387
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3727713777
Short name T372
Test name
Test status
Simulation time 68194929 ps
CPU time 0.74 seconds
Started Jan 03 01:00:58 PM PST 24
Finished Jan 03 01:02:02 PM PST 24
Peak memory 195560 kb
Host smart-83d264af-f75d-412a-9d84-c1df28262829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727713777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3727713777
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3140737186
Short name T115
Test name
Test status
Simulation time 353066369 ps
CPU time 3.16 seconds
Started Jan 03 01:01:11 PM PST 24
Finished Jan 03 01:02:20 PM PST 24
Peak memory 198036 kb
Host smart-73dc05a6-a38b-46d6-af3a-a325639ac339
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140737186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3140737186
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.180359009
Short name T557
Test name
Test status
Simulation time 153664257 ps
CPU time 2.76 seconds
Started Jan 03 01:01:11 PM PST 24
Finished Jan 03 01:02:19 PM PST 24
Peak memory 197300 kb
Host smart-1f589937-d92d-4d8a-ae51-ad20e00eead9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180359009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
180359009
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1301988894
Short name T788
Test name
Test status
Simulation time 115965231 ps
CPU time 1.18 seconds
Started Jan 03 01:00:56 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 196980 kb
Host smart-64a3cda8-8df7-4d71-9be0-1ba48ad4713e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301988894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1301988894
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1249826660
Short name T653
Test name
Test status
Simulation time 21601652 ps
CPU time 0.72 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 195300 kb
Host smart-c56d3283-67f0-4ce0-9487-f22a5cc614b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249826660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1249826660
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2071575722
Short name T706
Test name
Test status
Simulation time 1193189909 ps
CPU time 5.08 seconds
Started Jan 03 01:00:58 PM PST 24
Finished Jan 03 01:02:15 PM PST 24
Peak memory 198064 kb
Host smart-a0f0c527-2489-4b6f-a0b8-24364782d939
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071575722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2071575722
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3636892680
Short name T379
Test name
Test status
Simulation time 230948392 ps
CPU time 1.29 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:02 PM PST 24
Peak memory 196880 kb
Host smart-cdd4a522-8879-477f-810b-e5cf58b27444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636892680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3636892680
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.370357028
Short name T244
Test name
Test status
Simulation time 96351302 ps
CPU time 0.98 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:01 PM PST 24
Peak memory 195888 kb
Host smart-ae16e9be-6937-462a-89fa-94c803c7c033
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370357028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.370357028
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3822326185
Short name T874
Test name
Test status
Simulation time 15933568798 ps
CPU time 221.27 seconds
Started Jan 03 01:01:01 PM PST 24
Finished Jan 03 01:05:50 PM PST 24
Peak memory 198076 kb
Host smart-c53c73a5-e1f2-4e4f-8555-93811403b35d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822326185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3822326185
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.2134803605
Short name T411
Test name
Test status
Simulation time 377085058657 ps
CPU time 1162.43 seconds
Started Jan 03 01:00:54 PM PST 24
Finished Jan 03 01:21:19 PM PST 24
Peak memory 198300 kb
Host smart-e615c25c-05a7-4b34-9533-4e29b48b20e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2134803605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.2134803605
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1502430974
Short name T405
Test name
Test status
Simulation time 16525984 ps
CPU time 0.56 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:27 PM PST 24
Peak memory 194300 kb
Host smart-7f537aa5-e469-48c2-b72c-a47914333c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502430974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1502430974
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.4087851466
Short name T793
Test name
Test status
Simulation time 53096021 ps
CPU time 0.95 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 195868 kb
Host smart-ef5ad0a8-9c57-4ce1-9783-e86410c93a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087851466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.4087851466
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2437131671
Short name T467
Test name
Test status
Simulation time 547876899 ps
CPU time 9.03 seconds
Started Jan 03 01:01:22 PM PST 24
Finished Jan 03 01:02:38 PM PST 24
Peak memory 196136 kb
Host smart-304b3ce2-4744-4c58-bb21-5afbf71cb7e6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437131671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2437131671
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1000921579
Short name T541
Test name
Test status
Simulation time 24120799 ps
CPU time 0.62 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:22 PM PST 24
Peak memory 194740 kb
Host smart-84c1e264-b0c2-426c-8c2f-69b80f37dc7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000921579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1000921579
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.902450102
Short name T558
Test name
Test status
Simulation time 82190140 ps
CPU time 1.03 seconds
Started Jan 03 01:01:03 PM PST 24
Finished Jan 03 01:02:10 PM PST 24
Peak memory 196180 kb
Host smart-6e2bd23e-feed-4b9b-b2e9-f0169365a594
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902450102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.902450102
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.516854918
Short name T842
Test name
Test status
Simulation time 56133407 ps
CPU time 1.19 seconds
Started Jan 03 01:01:20 PM PST 24
Finished Jan 03 01:02:28 PM PST 24
Peak memory 196964 kb
Host smart-8c1d1a09-08e0-46a6-8e8c-b8b80f58418f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516854918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.516854918
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1496193904
Short name T678
Test name
Test status
Simulation time 481358052 ps
CPU time 3.71 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:02:28 PM PST 24
Peak memory 195872 kb
Host smart-101d3546-cfaa-4d9a-80b9-3fd5a276c4b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496193904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1496193904
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.177274851
Short name T479
Test name
Test status
Simulation time 60749238 ps
CPU time 1.08 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:26 PM PST 24
Peak memory 196880 kb
Host smart-6299e33a-b212-45ac-b7c3-94867ce1a864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177274851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.177274851
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.497301315
Short name T300
Test name
Test status
Simulation time 31738330 ps
CPU time 0.78 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:23 PM PST 24
Peak memory 195416 kb
Host smart-5cecea49-651b-475e-a722-45f6375f33e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497301315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.497301315
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2469624866
Short name T321
Test name
Test status
Simulation time 100972624 ps
CPU time 4.34 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:02:28 PM PST 24
Peak memory 197996 kb
Host smart-4829421f-ff3d-4166-970b-4981c5c07b00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469624866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2469624866
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.4002783779
Short name T417
Test name
Test status
Simulation time 327274899 ps
CPU time 1.35 seconds
Started Jan 03 01:01:10 PM PST 24
Finished Jan 03 01:02:18 PM PST 24
Peak memory 198028 kb
Host smart-d7c346c0-8f29-4f8b-8c3e-ce774c7d8357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002783779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.4002783779
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.536013766
Short name T713
Test name
Test status
Simulation time 209780616 ps
CPU time 1.32 seconds
Started Jan 03 01:01:14 PM PST 24
Finished Jan 03 01:02:21 PM PST 24
Peak memory 196864 kb
Host smart-d4a879d3-72c0-479b-bfb8-0ed175cfc7c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536013766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.536013766
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.721668231
Short name T745
Test name
Test status
Simulation time 43067995166 ps
CPU time 157.17 seconds
Started Jan 03 01:01:11 PM PST 24
Finished Jan 03 01:04:54 PM PST 24
Peak memory 198148 kb
Host smart-fa914928-acb5-40e8-9aa9-120cedee49ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721668231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.721668231
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.1098049123
Short name T687
Test name
Test status
Simulation time 112742871107 ps
CPU time 626.32 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:12:50 PM PST 24
Peak memory 198328 kb
Host smart-883f72b9-76dc-4076-b1f6-6d6599d86346
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1098049123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.1098049123
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3525862389
Short name T511
Test name
Test status
Simulation time 10408632 ps
CPU time 0.53 seconds
Started Jan 03 01:00:56 PM PST 24
Finished Jan 03 01:01:59 PM PST 24
Peak memory 192556 kb
Host smart-c6501175-1398-4f2e-b988-2ad3aa3bde91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525862389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3525862389
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3904682886
Short name T476
Test name
Test status
Simulation time 25510110 ps
CPU time 0.7 seconds
Started Jan 03 01:01:28 PM PST 24
Finished Jan 03 01:02:39 PM PST 24
Peak memory 194884 kb
Host smart-bf37b457-a151-4e95-9ec1-865de95dee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904682886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3904682886
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.4216769149
Short name T725
Test name
Test status
Simulation time 1742504573 ps
CPU time 22.26 seconds
Started Jan 03 01:01:23 PM PST 24
Finished Jan 03 01:02:53 PM PST 24
Peak memory 197000 kb
Host smart-180f2580-4a8b-41c3-9ffc-98b8d0aeed0c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216769149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.4216769149
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.329624795
Short name T64
Test name
Test status
Simulation time 173785209 ps
CPU time 1.04 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:27 PM PST 24
Peak memory 196392 kb
Host smart-a7f49b67-6a1a-4e18-be1b-eb1e5567568e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329624795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.329624795
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2658125578
Short name T561
Test name
Test status
Simulation time 105083367 ps
CPU time 1.02 seconds
Started Jan 03 01:01:29 PM PST 24
Finished Jan 03 01:02:41 PM PST 24
Peak memory 196816 kb
Host smart-0a4d881a-653a-4499-9501-9b847a71bcb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658125578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2658125578
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.431223324
Short name T718
Test name
Test status
Simulation time 67905027 ps
CPU time 2.66 seconds
Started Jan 03 01:01:27 PM PST 24
Finished Jan 03 01:02:40 PM PST 24
Peak memory 196452 kb
Host smart-9da7bc71-a67b-4941-8602-1d2a2abc99e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431223324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.431223324
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1596211822
Short name T764
Test name
Test status
Simulation time 543607951 ps
CPU time 2.79 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:02:37 PM PST 24
Peak memory 197056 kb
Host smart-080cf073-50fa-4587-804f-2e02180b986c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596211822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1596211822
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.161904126
Short name T517
Test name
Test status
Simulation time 49137521 ps
CPU time 0.98 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:25 PM PST 24
Peak memory 195860 kb
Host smart-06f45f35-5204-4963-a6b6-b6d2fa7acb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161904126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.161904126
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.328737975
Short name T612
Test name
Test status
Simulation time 37901721 ps
CPU time 0.86 seconds
Started Jan 03 01:01:24 PM PST 24
Finished Jan 03 01:02:33 PM PST 24
Peak memory 195820 kb
Host smart-1afeb016-1fd7-4229-b1ad-d384e6648f7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328737975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.328737975
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.184652224
Short name T780
Test name
Test status
Simulation time 1344334051 ps
CPU time 5.51 seconds
Started Jan 03 01:01:26 PM PST 24
Finished Jan 03 01:02:41 PM PST 24
Peak memory 198084 kb
Host smart-7d6cb661-c6a7-4eea-a707-aff1c5fcc418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184652224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.184652224
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3138352923
Short name T782
Test name
Test status
Simulation time 48367965 ps
CPU time 1.2 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:26 PM PST 24
Peak memory 195628 kb
Host smart-5be91ee1-65ab-4c41-972a-59c956721402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138352923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3138352923
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3253304773
Short name T242
Test name
Test status
Simulation time 292855561 ps
CPU time 1.19 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:27 PM PST 24
Peak memory 196744 kb
Host smart-3deeeafe-f79c-4089-9792-c0bff4050026
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253304773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3253304773
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2846572354
Short name T585
Test name
Test status
Simulation time 2080224904 ps
CPU time 51.85 seconds
Started Jan 03 01:01:24 PM PST 24
Finished Jan 03 01:03:24 PM PST 24
Peak memory 198028 kb
Host smart-016e41b2-97bb-4e02-be0f-c3497909d324
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846572354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2846572354
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.4141999945
Short name T344
Test name
Test status
Simulation time 73878322997 ps
CPU time 1022.09 seconds
Started Jan 03 01:00:54 PM PST 24
Finished Jan 03 01:18:58 PM PST 24
Peak memory 198388 kb
Host smart-e034f870-6143-4d5a-8886-9e4f4fe61690
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4141999945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.4141999945
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3133574460
Short name T311
Test name
Test status
Simulation time 17601616 ps
CPU time 0.54 seconds
Started Jan 03 01:01:26 PM PST 24
Finished Jan 03 01:02:36 PM PST 24
Peak memory 194076 kb
Host smart-b59f7d88-aa26-4550-b154-dec950a262e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133574460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3133574460
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2507311941
Short name T592
Test name
Test status
Simulation time 141574483 ps
CPU time 0.89 seconds
Started Jan 03 01:00:57 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 195872 kb
Host smart-2ccae79d-760f-474c-a563-ea674582968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507311941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2507311941
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3133718713
Short name T373
Test name
Test status
Simulation time 304788225 ps
CPU time 8.84 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:02:32 PM PST 24
Peak memory 195668 kb
Host smart-d917ed5c-87c1-4ff0-a462-f93b19767944
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133718713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3133718713
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.4098343356
Short name T483
Test name
Test status
Simulation time 30442552 ps
CPU time 0.7 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:27 PM PST 24
Peak memory 195332 kb
Host smart-b5944593-4b45-4fa5-be8e-24910fdca4c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098343356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.4098343356
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.498639587
Short name T670
Test name
Test status
Simulation time 331344324 ps
CPU time 0.93 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:02:24 PM PST 24
Peak memory 195920 kb
Host smart-a525a3da-3ec3-4467-ac89-a60d92085767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498639587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.498639587
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1249454848
Short name T620
Test name
Test status
Simulation time 89247681 ps
CPU time 3.44 seconds
Started Jan 03 01:01:13 PM PST 24
Finished Jan 03 01:02:22 PM PST 24
Peak memory 197996 kb
Host smart-2b33fe44-3584-484b-83f3-065fd120e0bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249454848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1249454848
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.450215129
Short name T756
Test name
Test status
Simulation time 88126228 ps
CPU time 1.16 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:23 PM PST 24
Peak memory 196576 kb
Host smart-83d0d966-4092-406d-9d65-700ae02999be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450215129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
450215129
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.929993856
Short name T871
Test name
Test status
Simulation time 46312716 ps
CPU time 0.95 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 195624 kb
Host smart-2fd8ef4f-74a5-4758-9778-d36bec358b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929993856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.929993856
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2796621597
Short name T615
Test name
Test status
Simulation time 117483331 ps
CPU time 1.1 seconds
Started Jan 03 01:00:48 PM PST 24
Finished Jan 03 01:01:52 PM PST 24
Peak memory 196108 kb
Host smart-0260ba6b-6454-438e-be4b-67ee9020a096
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796621597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2796621597
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3977307325
Short name T109
Test name
Test status
Simulation time 237519929 ps
CPU time 3.1 seconds
Started Jan 03 01:01:11 PM PST 24
Finished Jan 03 01:02:20 PM PST 24
Peak memory 198024 kb
Host smart-c53f285f-d18d-4875-a165-3a8bcfed8bb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977307325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3977307325
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1051655462
Short name T559
Test name
Test status
Simulation time 173653958 ps
CPU time 1.13 seconds
Started Jan 03 01:00:59 PM PST 24
Finished Jan 03 01:02:06 PM PST 24
Peak memory 195624 kb
Host smart-6f4fafa9-1c52-43bb-908a-1d5233a0be0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051655462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1051655462
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2406773044
Short name T526
Test name
Test status
Simulation time 315085582 ps
CPU time 1.33 seconds
Started Jan 03 01:00:55 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 196740 kb
Host smart-448c3015-7c8d-4c92-9a23-27b1014c21f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406773044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2406773044
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3819328165
Short name T220
Test name
Test status
Simulation time 7025434573 ps
CPU time 73.56 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:03:38 PM PST 24
Peak memory 198236 kb
Host smart-fbf54baa-a846-4ccc-a47f-288516fb156e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819328165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3819328165
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1073394052
Short name T836
Test name
Test status
Simulation time 9070453515 ps
CPU time 148.66 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:04:50 PM PST 24
Peak memory 198336 kb
Host smart-43b06abc-3e58-4704-bc35-23479d2cc352
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1073394052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1073394052
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.4198233941
Short name T390
Test name
Test status
Simulation time 85746637 ps
CPU time 0.56 seconds
Started Jan 03 12:59:26 PM PST 24
Finished Jan 03 01:00:21 PM PST 24
Peak memory 194056 kb
Host smart-f56bdf6b-d1fc-4e24-9acc-18945e99a87d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198233941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.4198233941
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1105272838
Short name T211
Test name
Test status
Simulation time 22409432 ps
CPU time 0.62 seconds
Started Jan 03 12:59:22 PM PST 24
Finished Jan 03 01:00:17 PM PST 24
Peak memory 193916 kb
Host smart-f3ea0456-20e3-43e1-86f3-6ea90295afd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105272838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1105272838
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3482584821
Short name T449
Test name
Test status
Simulation time 211257884 ps
CPU time 6.93 seconds
Started Jan 03 12:59:38 PM PST 24
Finished Jan 03 01:00:37 PM PST 24
Peak memory 196692 kb
Host smart-af329435-dad8-4ea0-8e11-81e671dedc0d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482584821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3482584821
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3390412615
Short name T338
Test name
Test status
Simulation time 162507011 ps
CPU time 0.72 seconds
Started Jan 03 12:59:32 PM PST 24
Finished Jan 03 01:00:25 PM PST 24
Peak memory 194756 kb
Host smart-28050106-5e95-46a0-963d-3ac80887b063
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390412615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3390412615
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.634985453
Short name T560
Test name
Test status
Simulation time 16617444 ps
CPU time 0.64 seconds
Started Jan 03 12:59:37 PM PST 24
Finished Jan 03 01:00:30 PM PST 24
Peak memory 194280 kb
Host smart-dcccc1e3-7a4c-4feb-91ba-34ed550ec8f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634985453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.634985453
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4265976883
Short name T610
Test name
Test status
Simulation time 80467765 ps
CPU time 1.64 seconds
Started Jan 03 12:59:25 PM PST 24
Finished Jan 03 01:00:21 PM PST 24
Peak memory 196748 kb
Host smart-70d64d85-538b-47b8-b4a3-db5ec7f36dbb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265976883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.4265976883
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2504935129
Short name T586
Test name
Test status
Simulation time 33685865 ps
CPU time 0.95 seconds
Started Jan 03 12:59:48 PM PST 24
Finished Jan 03 01:00:47 PM PST 24
Peak memory 195452 kb
Host smart-f259540e-1251-4d87-ab74-90dc7c2e8297
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504935129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2504935129
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2169397784
Short name T734
Test name
Test status
Simulation time 190288448 ps
CPU time 1.02 seconds
Started Jan 03 12:59:50 PM PST 24
Finished Jan 03 01:00:51 PM PST 24
Peak memory 196052 kb
Host smart-270c6018-566b-46f7-953d-26cffaeb0425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169397784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2169397784
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1451146292
Short name T505
Test name
Test status
Simulation time 173645609 ps
CPU time 1.23 seconds
Started Jan 03 12:59:47 PM PST 24
Finished Jan 03 01:00:46 PM PST 24
Peak memory 197012 kb
Host smart-59911e3c-2817-400b-8e2a-5439a1cc1627
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451146292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1451146292
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2239974234
Short name T457
Test name
Test status
Simulation time 269085678 ps
CPU time 4.27 seconds
Started Jan 03 12:59:25 PM PST 24
Finished Jan 03 01:00:24 PM PST 24
Peak memory 198036 kb
Host smart-29dded77-e51a-478e-9e9d-a4693f846d27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239974234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2239974234
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.172570847
Short name T601
Test name
Test status
Simulation time 26615714 ps
CPU time 0.88 seconds
Started Jan 03 12:59:41 PM PST 24
Finished Jan 03 01:00:36 PM PST 24
Peak memory 195844 kb
Host smart-a67eceed-3c00-40a8-b9f5-eacf849e78b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172570847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.172570847
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.978525472
Short name T209
Test name
Test status
Simulation time 141973617 ps
CPU time 1.16 seconds
Started Jan 03 12:59:44 PM PST 24
Finished Jan 03 01:00:42 PM PST 24
Peak memory 195636 kb
Host smart-9a3c980b-473f-4dff-b1d9-46aa5280bd95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978525472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.978525472
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.313441592
Short name T596
Test name
Test status
Simulation time 3415017465 ps
CPU time 24.79 seconds
Started Jan 03 12:59:25 PM PST 24
Finished Jan 03 01:00:44 PM PST 24
Peak memory 198180 kb
Host smart-9c7b8e5b-722d-4491-be30-83babd4e197a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313441592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.313441592
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1922774654
Short name T692
Test name
Test status
Simulation time 160924020494 ps
CPU time 1032.28 seconds
Started Jan 03 12:59:26 PM PST 24
Finished Jan 03 01:17:33 PM PST 24
Peak memory 198340 kb
Host smart-e95166e1-7fc1-4249-9d80-b5e710c75197
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1922774654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1922774654
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1836235489
Short name T801
Test name
Test status
Simulation time 74868073 ps
CPU time 0.55 seconds
Started Jan 03 12:59:39 PM PST 24
Finished Jan 03 01:00:34 PM PST 24
Peak memory 194680 kb
Host smart-93adb706-931a-4dc2-a1ed-93a4a9e7a7d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836235489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1836235489
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1972026139
Short name T395
Test name
Test status
Simulation time 26375004 ps
CPU time 0.6 seconds
Started Jan 03 12:59:36 PM PST 24
Finished Jan 03 01:00:29 PM PST 24
Peak memory 194080 kb
Host smart-0100f170-fadf-4e5a-8ce2-7110db2a478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972026139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1972026139
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.180033309
Short name T491
Test name
Test status
Simulation time 137839884 ps
CPU time 6.82 seconds
Started Jan 03 12:59:36 PM PST 24
Finished Jan 03 01:00:35 PM PST 24
Peak memory 195568 kb
Host smart-fb872105-8652-4016-8f52-a53486c56085
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180033309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.180033309
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3091554611
Short name T603
Test name
Test status
Simulation time 444641277 ps
CPU time 1.06 seconds
Started Jan 03 12:59:32 PM PST 24
Finished Jan 03 01:00:26 PM PST 24
Peak memory 198088 kb
Host smart-a3951a7f-85a1-45a3-ae57-56ab2b32e4b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091554611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3091554611
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.616959491
Short name T363
Test name
Test status
Simulation time 60885006 ps
CPU time 0.75 seconds
Started Jan 03 12:59:33 PM PST 24
Finished Jan 03 01:00:26 PM PST 24
Peak memory 195372 kb
Host smart-f6e837b5-7254-4116-ac84-591e1d5ec49b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616959491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.616959491
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2341855736
Short name T684
Test name
Test status
Simulation time 26722127 ps
CPU time 1.05 seconds
Started Jan 03 12:59:44 PM PST 24
Finished Jan 03 01:00:43 PM PST 24
Peak memory 197164 kb
Host smart-956156a8-7fe4-4127-b2c3-b6de1bfbc51b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341855736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2341855736
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1725323511
Short name T735
Test name
Test status
Simulation time 304808535 ps
CPU time 2.28 seconds
Started Jan 03 12:59:28 PM PST 24
Finished Jan 03 01:00:24 PM PST 24
Peak memory 198140 kb
Host smart-5c1949d5-c5bb-4dfa-b5d9-1b2110b413ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725323511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1725323511
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.4159108809
Short name T637
Test name
Test status
Simulation time 52051885 ps
CPU time 1.16 seconds
Started Jan 03 12:59:27 PM PST 24
Finished Jan 03 01:00:23 PM PST 24
Peak memory 198200 kb
Host smart-69c2aab1-0481-4e00-acf2-ab6fdaaca999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159108809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.4159108809
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1636999390
Short name T752
Test name
Test status
Simulation time 26570782 ps
CPU time 1.01 seconds
Started Jan 03 12:59:26 PM PST 24
Finished Jan 03 01:00:21 PM PST 24
Peak memory 196092 kb
Host smart-d00e72b6-60c1-4e2b-a8be-b98f8a505788
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636999390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1636999390
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.4288936693
Short name T840
Test name
Test status
Simulation time 1624285937 ps
CPU time 3.47 seconds
Started Jan 03 12:59:49 PM PST 24
Finished Jan 03 01:00:51 PM PST 24
Peak memory 198036 kb
Host smart-74c4a5ea-7b9a-4574-bca4-4169af1d0641
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288936693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.4288936693
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3154051876
Short name T513
Test name
Test status
Simulation time 145081866 ps
CPU time 1.05 seconds
Started Jan 03 12:59:27 PM PST 24
Finished Jan 03 01:00:22 PM PST 24
Peak memory 195936 kb
Host smart-5df35802-0767-4042-b1d6-a855f0616a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154051876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3154051876
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2826635451
Short name T238
Test name
Test status
Simulation time 228476040 ps
CPU time 1.23 seconds
Started Jan 03 12:59:27 PM PST 24
Finished Jan 03 01:00:22 PM PST 24
Peak memory 195588 kb
Host smart-b7499fe9-ae1d-4544-bc1c-e8d620dfb8ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826635451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2826635451
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.769414647
Short name T342
Test name
Test status
Simulation time 209666711729 ps
CPU time 1272.79 seconds
Started Jan 03 12:59:24 PM PST 24
Finished Jan 03 01:21:32 PM PST 24
Peak memory 198328 kb
Host smart-0042c6e0-0c3d-457e-9746-ec426af824b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=769414647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.769414647
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.400916794
Short name T640
Test name
Test status
Simulation time 26983906 ps
CPU time 0.59 seconds
Started Jan 03 12:59:34 PM PST 24
Finished Jan 03 01:00:27 PM PST 24
Peak memory 194100 kb
Host smart-b5f6d4a8-8515-43f5-9980-9f2a8572585e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400916794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.400916794
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4230937689
Short name T810
Test name
Test status
Simulation time 24336685 ps
CPU time 0.63 seconds
Started Jan 03 12:59:33 PM PST 24
Finished Jan 03 01:00:27 PM PST 24
Peak memory 193936 kb
Host smart-1ea69a72-1c6f-4b4a-beed-85d70d926b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230937689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.4230937689
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3748415281
Short name T628
Test name
Test status
Simulation time 302442274 ps
CPU time 14.65 seconds
Started Jan 03 12:59:39 PM PST 24
Finished Jan 03 01:00:49 PM PST 24
Peak memory 196948 kb
Host smart-a5c6427c-68e8-4432-bd84-3abc73783ab9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748415281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3748415281
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3842101839
Short name T759
Test name
Test status
Simulation time 63638242 ps
CPU time 0.94 seconds
Started Jan 03 12:59:33 PM PST 24
Finished Jan 03 01:00:26 PM PST 24
Peak memory 197132 kb
Host smart-32fa09d1-a6b3-4c3b-9554-4daf8984fc70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842101839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3842101839
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3484988227
Short name T870
Test name
Test status
Simulation time 75056180 ps
CPU time 1.11 seconds
Started Jan 03 12:59:34 PM PST 24
Finished Jan 03 01:00:28 PM PST 24
Peak memory 195860 kb
Host smart-6a14a8c0-36ea-4a30-af92-94780979b1a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484988227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3484988227
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.614664566
Short name T269
Test name
Test status
Simulation time 187064886 ps
CPU time 3.23 seconds
Started Jan 03 12:59:35 PM PST 24
Finished Jan 03 01:00:30 PM PST 24
Peak memory 196404 kb
Host smart-480fe962-7891-4a15-be39-480cc9130018
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614664566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.614664566
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.922363381
Short name T487
Test name
Test status
Simulation time 63440469 ps
CPU time 1 seconds
Started Jan 03 12:59:33 PM PST 24
Finished Jan 03 01:00:26 PM PST 24
Peak memory 195396 kb
Host smart-c355a66e-642e-407a-9bfa-8e00d8ad43b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922363381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.922363381
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2306348107
Short name T589
Test name
Test status
Simulation time 130980268 ps
CPU time 1.22 seconds
Started Jan 03 12:59:36 PM PST 24
Finished Jan 03 01:00:30 PM PST 24
Peak memory 198084 kb
Host smart-e0acecc6-cbfe-4927-89b0-dd6a573c6d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306348107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2306348107
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2906432999
Short name T719
Test name
Test status
Simulation time 65788664 ps
CPU time 1.21 seconds
Started Jan 03 12:59:39 PM PST 24
Finished Jan 03 01:00:35 PM PST 24
Peak memory 195984 kb
Host smart-a70bb42e-be86-4923-8a06-e447162228b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906432999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2906432999
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1789275185
Short name T550
Test name
Test status
Simulation time 74811611 ps
CPU time 1.65 seconds
Started Jan 03 12:59:32 PM PST 24
Finished Jan 03 01:00:26 PM PST 24
Peak memory 197976 kb
Host smart-d4a12d92-196f-4c15-aa24-ac8a11dc9544
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789275185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1789275185
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1817121535
Short name T748
Test name
Test status
Simulation time 231226118 ps
CPU time 0.85 seconds
Started Jan 03 12:59:35 PM PST 24
Finished Jan 03 01:00:28 PM PST 24
Peak memory 195320 kb
Host smart-7e2ccc74-813c-49ce-9026-eea37c9adb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817121535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1817121535
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3275380311
Short name T261
Test name
Test status
Simulation time 423540342 ps
CPU time 0.96 seconds
Started Jan 03 12:59:35 PM PST 24
Finished Jan 03 01:00:28 PM PST 24
Peak memory 195672 kb
Host smart-1d9a7dec-34b4-4ff3-94d5-881562fd01f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275380311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3275380311
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2653599747
Short name T364
Test name
Test status
Simulation time 46448999925 ps
CPU time 160.96 seconds
Started Jan 03 12:59:33 PM PST 24
Finished Jan 03 01:03:07 PM PST 24
Peak memory 198208 kb
Host smart-c44f62c7-999a-455d-9c1e-6a1c46acb81a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653599747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2653599747
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2163192721
Short name T461
Test name
Test status
Simulation time 428901973251 ps
CPU time 1449.33 seconds
Started Jan 03 12:59:34 PM PST 24
Finished Jan 03 01:24:36 PM PST 24
Peak memory 206600 kb
Host smart-04d14b70-8361-4251-aa9a-2aa205590c10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2163192721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2163192721
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1090812936
Short name T588
Test name
Test status
Simulation time 12129841 ps
CPU time 0.56 seconds
Started Jan 03 12:59:34 PM PST 24
Finished Jan 03 01:00:27 PM PST 24
Peak memory 195012 kb
Host smart-9aef175d-d65b-4e8d-a117-a21643626f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090812936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1090812936
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2796441143
Short name T666
Test name
Test status
Simulation time 82161008 ps
CPU time 0.66 seconds
Started Jan 03 12:59:25 PM PST 24
Finished Jan 03 01:00:20 PM PST 24
Peak memory 194784 kb
Host smart-d47a26a1-d8e0-4287-b4d1-2b3157826f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796441143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2796441143
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3373771303
Short name T594
Test name
Test status
Simulation time 11884161893 ps
CPU time 18.8 seconds
Started Jan 03 12:59:43 PM PST 24
Finished Jan 03 01:00:59 PM PST 24
Peak memory 198068 kb
Host smart-6043d8b2-8641-4a43-ac88-9ee3776a2843
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373771303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3373771303
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2280161575
Short name T877
Test name
Test status
Simulation time 361505219 ps
CPU time 1.04 seconds
Started Jan 03 12:59:26 PM PST 24
Finished Jan 03 01:00:21 PM PST 24
Peak memory 196704 kb
Host smart-be29af1a-2f73-4128-9887-b35925758b40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280161575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2280161575
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1686768399
Short name T683
Test name
Test status
Simulation time 50812339 ps
CPU time 1.29 seconds
Started Jan 03 12:59:45 PM PST 24
Finished Jan 03 01:00:44 PM PST 24
Peak memory 197204 kb
Host smart-b3ec5387-6307-4f2b-acdf-0b7789c8d4ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686768399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1686768399
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.184946200
Short name T309
Test name
Test status
Simulation time 187445177 ps
CPU time 3.43 seconds
Started Jan 03 12:59:35 PM PST 24
Finished Jan 03 01:00:30 PM PST 24
Peak memory 198228 kb
Host smart-0ac8ef09-be3a-4311-b128-0796e952e2e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184946200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.184946200
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1359401980
Short name T838
Test name
Test status
Simulation time 109097096 ps
CPU time 2.35 seconds
Started Jan 03 12:59:31 PM PST 24
Finished Jan 03 01:00:26 PM PST 24
Peak memory 197280 kb
Host smart-7b7cf8ae-c16c-4cf3-8b17-1a7223a1893f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359401980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1359401980
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2640962325
Short name T325
Test name
Test status
Simulation time 16080375 ps
CPU time 0.69 seconds
Started Jan 03 12:59:36 PM PST 24
Finished Jan 03 01:00:29 PM PST 24
Peak memory 196072 kb
Host smart-7c6ddec1-7a79-4642-8ec0-3633576d0a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640962325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2640962325
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.587689591
Short name T721
Test name
Test status
Simulation time 172775329 ps
CPU time 1.21 seconds
Started Jan 03 12:59:34 PM PST 24
Finished Jan 03 01:00:28 PM PST 24
Peak memory 196600 kb
Host smart-61cb88bf-ef74-4a7f-ae4e-7ce20ef3917d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587689591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.587689591
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1426078292
Short name T532
Test name
Test status
Simulation time 1592365172 ps
CPU time 6.62 seconds
Started Jan 03 12:59:29 PM PST 24
Finished Jan 03 01:00:29 PM PST 24
Peak memory 198164 kb
Host smart-cb2c3210-4728-4a5f-ac20-5de88eee4b42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426078292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1426078292
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1189392039
Short name T607
Test name
Test status
Simulation time 21168422 ps
CPU time 0.74 seconds
Started Jan 03 12:59:31 PM PST 24
Finished Jan 03 01:00:24 PM PST 24
Peak memory 194184 kb
Host smart-bb59b62c-4a60-46ab-aa72-6b79cfe76481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189392039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1189392039
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.21670708
Short name T568
Test name
Test status
Simulation time 38597364 ps
CPU time 1.03 seconds
Started Jan 03 12:59:37 PM PST 24
Finished Jan 03 01:00:30 PM PST 24
Peak memory 195924 kb
Host smart-060eae34-2bde-4e94-8189-d632db45d2a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21670708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.21670708
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.602148556
Short name T665
Test name
Test status
Simulation time 48091616539 ps
CPU time 184.1 seconds
Started Jan 03 12:59:35 PM PST 24
Finished Jan 03 01:03:31 PM PST 24
Peak memory 198256 kb
Host smart-1d0996e6-e3b1-4ff6-a8ac-9b73ff05674c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602148556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.602148556
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1593798812
Short name T276
Test name
Test status
Simulation time 109866960937 ps
CPU time 2075.64 seconds
Started Jan 03 12:59:38 PM PST 24
Finished Jan 03 01:35:06 PM PST 24
Peak memory 198292 kb
Host smart-bdfab9f4-e883-4483-9055-5bda671c421b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1593798812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.1593798812
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3890649352
Short name T498
Test name
Test status
Simulation time 14573584 ps
CPU time 0.55 seconds
Started Jan 03 12:59:35 PM PST 24
Finished Jan 03 01:00:27 PM PST 24
Peak memory 194020 kb
Host smart-ade6c7b8-20fb-43b2-9fa9-bc6b2d5108aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890649352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3890649352
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2672936800
Short name T737
Test name
Test status
Simulation time 20447612 ps
CPU time 0.64 seconds
Started Jan 03 12:59:34 PM PST 24
Finished Jan 03 01:00:27 PM PST 24
Peak memory 194064 kb
Host smart-f7b04b02-355d-45a9-a0e6-e0037c4d5a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672936800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2672936800
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3195574520
Short name T800
Test name
Test status
Simulation time 1492703309 ps
CPU time 10.5 seconds
Started Jan 03 12:59:35 PM PST 24
Finished Jan 03 01:00:38 PM PST 24
Peak memory 196816 kb
Host smart-7a2e0c80-19df-43a8-99d3-3da3373b30ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195574520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3195574520
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.575018534
Short name T374
Test name
Test status
Simulation time 170598026 ps
CPU time 0.81 seconds
Started Jan 03 12:59:47 PM PST 24
Finished Jan 03 01:00:46 PM PST 24
Peak memory 195892 kb
Host smart-425f3c6e-cd6e-4873-bfdb-0ea0c182121f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575018534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.575018534
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.157277385
Short name T728
Test name
Test status
Simulation time 525167071 ps
CPU time 1.39 seconds
Started Jan 03 12:59:38 PM PST 24
Finished Jan 03 01:00:33 PM PST 24
Peak memory 197132 kb
Host smart-dceafafa-bd30-4635-89d3-229ac0d5d867
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157277385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.157277385
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.886248836
Short name T741
Test name
Test status
Simulation time 58182224 ps
CPU time 2.24 seconds
Started Jan 03 12:59:31 PM PST 24
Finished Jan 03 01:00:26 PM PST 24
Peak memory 198168 kb
Host smart-5f0b4045-96ed-4d2f-84aa-8bbd6d8414e5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886248836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.886248836
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3529625204
Short name T778
Test name
Test status
Simulation time 77744373 ps
CPU time 1.18 seconds
Started Jan 03 12:59:37 PM PST 24
Finished Jan 03 01:00:30 PM PST 24
Peak memory 195724 kb
Host smart-e7808a50-716e-4e90-8489-d6c785ceccee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529625204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3529625204
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.765536121
Short name T581
Test name
Test status
Simulation time 25266385 ps
CPU time 0.72 seconds
Started Jan 03 12:59:36 PM PST 24
Finished Jan 03 01:00:29 PM PST 24
Peak memory 196224 kb
Host smart-2ac7e451-9b54-4a05-87c3-ee4f05168e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765536121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.765536121
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2674313684
Short name T270
Test name
Test status
Simulation time 42472055 ps
CPU time 0.95 seconds
Started Jan 03 12:59:29 PM PST 24
Finished Jan 03 01:00:23 PM PST 24
Peak memory 196724 kb
Host smart-44d922d5-e082-42ed-839e-2cbb38b7a04d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674313684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2674313684
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1274632774
Short name T495
Test name
Test status
Simulation time 210011258 ps
CPU time 2.87 seconds
Started Jan 03 12:59:47 PM PST 24
Finished Jan 03 01:00:49 PM PST 24
Peak memory 197520 kb
Host smart-f6499963-79cc-4f4f-bda1-4f4e484a2286
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274632774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1274632774
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3778338111
Short name T410
Test name
Test status
Simulation time 1257470611 ps
CPU time 1.31 seconds
Started Jan 03 12:59:44 PM PST 24
Finished Jan 03 01:00:43 PM PST 24
Peak memory 195956 kb
Host smart-eebb962a-e87b-44b9-8194-c2d851ba7ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778338111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3778338111
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2535539443
Short name T396
Test name
Test status
Simulation time 42507691 ps
CPU time 0.99 seconds
Started Jan 03 12:59:32 PM PST 24
Finished Jan 03 01:00:26 PM PST 24
Peak memory 195916 kb
Host smart-6f9cf57e-78d4-4910-a6b8-843f3d6fe0c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535539443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2535539443
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1778965673
Short name T451
Test name
Test status
Simulation time 4015014756 ps
CPU time 56.27 seconds
Started Jan 03 12:59:33 PM PST 24
Finished Jan 03 01:01:22 PM PST 24
Peak memory 198224 kb
Host smart-24888342-e6ab-4877-809c-008e2f904d37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778965673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1778965673
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.898766456
Short name T702
Test name
Test status
Simulation time 685148675478 ps
CPU time 1836.35 seconds
Started Jan 03 12:59:39 PM PST 24
Finished Jan 03 01:31:10 PM PST 24
Peak memory 198340 kb
Host smart-ab4c51b3-2829-49c6-9c65-a4281f4a845f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=898766456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.898766456
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.249423139
Short name T203
Test name
Test status
Simulation time 140971347 ps
CPU time 0.77 seconds
Started Jan 03 12:35:11 PM PST 24
Finished Jan 03 12:36:32 PM PST 24
Peak memory 194960 kb
Host smart-0ce7a1eb-430f-4429-a0b8-95cb4d7b1d4d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=249423139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.249423139
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2327637744
Short name T59
Test name
Test status
Simulation time 88147496 ps
CPU time 0.84 seconds
Started Jan 03 12:35:06 PM PST 24
Finished Jan 03 12:36:40 PM PST 24
Peak memory 195884 kb
Host smart-1b536a85-3d53-4984-9d15-213b970be128
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327637744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2327637744
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2284969999
Short name T155
Test name
Test status
Simulation time 130873706 ps
CPU time 1.21 seconds
Started Jan 03 12:36:31 PM PST 24
Finished Jan 03 12:37:58 PM PST 24
Peak memory 195624 kb
Host smart-544ce361-6e27-4374-8a09-b0d4c30b5365
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2284969999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2284969999
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2401075865
Short name T150
Test name
Test status
Simulation time 1070035531 ps
CPU time 1.07 seconds
Started Jan 03 12:35:01 PM PST 24
Finished Jan 03 12:36:34 PM PST 24
Peak memory 196240 kb
Host smart-7dea7bc3-af12-49b3-a902-af8d40fd4206
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401075865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2401075865
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1046749459
Short name T196
Test name
Test status
Simulation time 37223849 ps
CPU time 0.93 seconds
Started Jan 03 12:33:47 PM PST 24
Finished Jan 03 12:35:20 PM PST 24
Peak memory 197512 kb
Host smart-7fc34848-dd46-41d3-9344-b0395c8ca408
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1046749459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1046749459
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1101535176
Short name T136
Test name
Test status
Simulation time 150222939 ps
CPU time 1.11 seconds
Started Jan 03 12:33:10 PM PST 24
Finished Jan 03 12:34:32 PM PST 24
Peak memory 196316 kb
Host smart-c1f25f74-2367-4ea2-baa3-1eaed63e56ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101535176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1101535176
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2338431272
Short name T142
Test name
Test status
Simulation time 725328429 ps
CPU time 1.1 seconds
Started Jan 03 12:33:33 PM PST 24
Finished Jan 03 12:34:47 PM PST 24
Peak memory 195308 kb
Host smart-8edc5894-d17d-4dde-a69a-9c27edee0a6e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2338431272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2338431272
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1654087735
Short name T144
Test name
Test status
Simulation time 256061704 ps
CPU time 1.09 seconds
Started Jan 03 12:33:41 PM PST 24
Finished Jan 03 12:35:08 PM PST 24
Peak memory 196424 kb
Host smart-ac0d8886-3aa9-4b3e-b51c-4ec3c6ec31d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1654087735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1654087735
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.86926383
Short name T152
Test name
Test status
Simulation time 79046244 ps
CPU time 1.31 seconds
Started Jan 03 12:33:41 PM PST 24
Finished Jan 03 12:35:08 PM PST 24
Peak memory 196216 kb
Host smart-958a4702-02f7-48b2-b8c9-5c2aa5ca0799
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86926383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.86926383
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.56755018
Short name T43
Test name
Test status
Simulation time 49677473 ps
CPU time 1.06 seconds
Started Jan 03 12:33:42 PM PST 24
Finished Jan 03 12:35:14 PM PST 24
Peak memory 196120 kb
Host smart-3b39ac0a-1845-408f-9f45-e558c0883d08
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56755018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.56755018
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1020024429
Short name T171
Test name
Test status
Simulation time 236042668 ps
CPU time 0.97 seconds
Started Jan 03 12:32:47 PM PST 24
Finished Jan 03 12:34:10 PM PST 24
Peak memory 197564 kb
Host smart-a3471b36-ab14-46ef-848d-b14ba0eda993
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1020024429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1020024429
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2124265472
Short name T172
Test name
Test status
Simulation time 136183726 ps
CPU time 0.89 seconds
Started Jan 03 12:33:15 PM PST 24
Finished Jan 03 12:34:43 PM PST 24
Peak memory 194992 kb
Host smart-785884e8-db7b-478e-ad0f-823749aa8889
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124265472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2124265472
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1263225923
Short name T132
Test name
Test status
Simulation time 28376856 ps
CPU time 0.89 seconds
Started Jan 03 12:32:59 PM PST 24
Finished Jan 03 12:35:08 PM PST 24
Peak memory 196192 kb
Host smart-0e71d8d6-03fb-4263-b0aa-a8d81dac38ce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1263225923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1263225923
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3583835836
Short name T190
Test name
Test status
Simulation time 415182366 ps
CPU time 0.88 seconds
Started Jan 03 12:33:41 PM PST 24
Finished Jan 03 12:35:12 PM PST 24
Peak memory 196160 kb
Host smart-514537a4-a8f2-423f-aa84-7f3da7fc7804
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583835836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3583835836
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.896521915
Short name T176
Test name
Test status
Simulation time 122698845 ps
CPU time 1 seconds
Started Jan 03 12:33:31 PM PST 24
Finished Jan 03 12:34:43 PM PST 24
Peak memory 196176 kb
Host smart-46ec8b7f-84d4-443a-baaf-08058bf820d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=896521915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.896521915
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1809282692
Short name T153
Test name
Test status
Simulation time 50930034 ps
CPU time 0.99 seconds
Started Jan 03 12:32:58 PM PST 24
Finished Jan 03 12:34:28 PM PST 24
Peak memory 195896 kb
Host smart-3af54174-d0bb-419e-a9cf-d95884e84755
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1809282692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1809282692
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.817781982
Short name T189
Test name
Test status
Simulation time 75375082 ps
CPU time 1.27 seconds
Started Jan 03 12:33:18 PM PST 24
Finished Jan 03 12:35:01 PM PST 24
Peak memory 196428 kb
Host smart-4ba83347-ba36-44ad-b889-66641951eab5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817781982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.817781982
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3942214047
Short name T134
Test name
Test status
Simulation time 143762216 ps
CPU time 1.07 seconds
Started Jan 03 12:33:16 PM PST 24
Finished Jan 03 12:34:39 PM PST 24
Peak memory 196256 kb
Host smart-f87899b7-8ead-4c2d-b9a6-ab26cc6a5146
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3942214047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3942214047
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3775353968
Short name T147
Test name
Test status
Simulation time 41475851 ps
CPU time 1.21 seconds
Started Jan 03 12:33:11 PM PST 24
Finished Jan 03 12:34:42 PM PST 24
Peak memory 197636 kb
Host smart-d94ecc4d-8d4b-43a4-bff7-2e769f87e6fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775353968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3775353968
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.402215092
Short name T195
Test name
Test status
Simulation time 146237793 ps
CPU time 1.14 seconds
Started Jan 03 12:34:35 PM PST 24
Finished Jan 03 12:35:49 PM PST 24
Peak memory 196132 kb
Host smart-e52bc8ab-28ab-42e3-a402-1123f2c76f45
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=402215092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.402215092
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2696359464
Short name T188
Test name
Test status
Simulation time 34514183 ps
CPU time 0.78 seconds
Started Jan 03 12:35:05 PM PST 24
Finished Jan 03 12:36:44 PM PST 24
Peak memory 194888 kb
Host smart-95b4405d-86ca-4f6a-9439-02df8983ec11
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696359464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2696359464
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1680731182
Short name T164
Test name
Test status
Simulation time 62874401 ps
CPU time 0.84 seconds
Started Jan 03 12:32:56 PM PST 24
Finished Jan 03 12:34:56 PM PST 24
Peak memory 195824 kb
Host smart-536cce9a-e3df-4271-9cf2-de0ecfab231d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1680731182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1680731182
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2922067599
Short name T165
Test name
Test status
Simulation time 44266606 ps
CPU time 1.17 seconds
Started Jan 03 12:33:04 PM PST 24
Finished Jan 03 12:34:45 PM PST 24
Peak memory 196480 kb
Host smart-0588e986-ab62-4eda-91b0-d8cb00eb3e32
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922067599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2922067599
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2259694729
Short name T151
Test name
Test status
Simulation time 33516669 ps
CPU time 0.97 seconds
Started Jan 03 12:33:30 PM PST 24
Finished Jan 03 12:35:00 PM PST 24
Peak memory 196216 kb
Host smart-7015682d-d06f-485c-9eb0-0d893cdad805
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259694729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2259694729
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.413586130
Short name T185
Test name
Test status
Simulation time 80497360 ps
CPU time 1.03 seconds
Started Jan 03 12:33:10 PM PST 24
Finished Jan 03 12:34:26 PM PST 24
Peak memory 196304 kb
Host smart-824c62b8-ae6a-43a5-a967-712ad02a0b04
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=413586130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.413586130
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2332926019
Short name T163
Test name
Test status
Simulation time 57940961 ps
CPU time 1.16 seconds
Started Jan 03 12:33:39 PM PST 24
Finished Jan 03 12:35:23 PM PST 24
Peak memory 196092 kb
Host smart-f9a6bc49-5ffd-44b7-b2b9-a72c56b4db3f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2332926019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2332926019
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4270709880
Short name T173
Test name
Test status
Simulation time 57643572 ps
CPU time 0.83 seconds
Started Jan 03 12:33:39 PM PST 24
Finished Jan 03 12:34:55 PM PST 24
Peak memory 195140 kb
Host smart-54e3b630-7f88-4d2f-9d7c-1d0917725bdb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270709880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4270709880
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2107724958
Short name T199
Test name
Test status
Simulation time 133687352 ps
CPU time 1.22 seconds
Started Jan 03 12:33:07 PM PST 24
Finished Jan 03 12:34:28 PM PST 24
Peak memory 196456 kb
Host smart-97e6c3f0-294a-4ef2-9289-747205a357f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2107724958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2107724958
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3302138979
Short name T167
Test name
Test status
Simulation time 341575252 ps
CPU time 1.25 seconds
Started Jan 03 12:37:03 PM PST 24
Finished Jan 03 12:38:11 PM PST 24
Peak memory 197460 kb
Host smart-f4805a60-eac3-46cf-8e41-1c9cf9dab888
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3302138979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3302138979
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3813185008
Short name T186
Test name
Test status
Simulation time 355688194 ps
CPU time 1.03 seconds
Started Jan 03 12:33:31 PM PST 24
Finished Jan 03 12:34:50 PM PST 24
Peak memory 196316 kb
Host smart-8893871d-3f7a-4f63-a6cf-d2d94bb167f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813185008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3813185008
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2539987784
Short name T154
Test name
Test status
Simulation time 58247236 ps
CPU time 1.08 seconds
Started Jan 03 12:33:00 PM PST 24
Finished Jan 03 12:34:19 PM PST 24
Peak memory 195356 kb
Host smart-a4f1f904-4621-492a-aaaf-e5b3e3ef0ad2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2539987784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2539987784
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3092044633
Short name T174
Test name
Test status
Simulation time 152369113 ps
CPU time 1.26 seconds
Started Jan 03 12:33:39 PM PST 24
Finished Jan 03 12:35:08 PM PST 24
Peak memory 196212 kb
Host smart-9be2868c-83a5-4629-b232-bd2a980023cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092044633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3092044633
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.330791385
Short name T57
Test name
Test status
Simulation time 146516683 ps
CPU time 0.87 seconds
Started Jan 03 12:32:46 PM PST 24
Finished Jan 03 12:34:32 PM PST 24
Peak memory 196212 kb
Host smart-f5fe6958-8d7a-4a2f-919b-32c3d6105726
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=330791385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.330791385
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.921174444
Short name T202
Test name
Test status
Simulation time 67897327 ps
CPU time 1.25 seconds
Started Jan 03 12:33:42 PM PST 24
Finished Jan 03 12:35:10 PM PST 24
Peak memory 196204 kb
Host smart-d0f95ad8-3c96-455a-adcb-1d2ce256f5ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921174444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.921174444
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3029234943
Short name T169
Test name
Test status
Simulation time 452722975 ps
CPU time 0.87 seconds
Started Jan 03 12:33:35 PM PST 24
Finished Jan 03 12:34:45 PM PST 24
Peak memory 197584 kb
Host smart-3992a09d-af0a-4c7a-bdf0-066a4a077011
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029234943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3029234943
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3917034933
Short name T149
Test name
Test status
Simulation time 24653875 ps
CPU time 0.7 seconds
Started Jan 03 12:33:23 PM PST 24
Finished Jan 03 12:34:47 PM PST 24
Peak memory 194096 kb
Host smart-df115ae5-d507-4e3d-b0d2-6bd56e207877
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3917034933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3917034933
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.863379169
Short name T143
Test name
Test status
Simulation time 468837375 ps
CPU time 0.99 seconds
Started Jan 03 12:34:47 PM PST 24
Finished Jan 03 12:36:02 PM PST 24
Peak memory 195908 kb
Host smart-8008ee45-eff7-442e-8754-335795c5f331
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=863379169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.863379169
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.512608788
Short name T197
Test name
Test status
Simulation time 24285808 ps
CPU time 0.79 seconds
Started Jan 03 12:35:16 PM PST 24
Finished Jan 03 12:36:48 PM PST 24
Peak memory 194960 kb
Host smart-34d9829c-9fef-4cc9-bdf1-d512a420980e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512608788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.512608788
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3736367991
Short name T183
Test name
Test status
Simulation time 163976817 ps
CPU time 1.07 seconds
Started Jan 03 12:33:27 PM PST 24
Finished Jan 03 12:35:14 PM PST 24
Peak memory 197692 kb
Host smart-d57b36c2-c028-46f9-b70e-5604d44386a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3736367991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3736367991
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3430240116
Short name T178
Test name
Test status
Simulation time 64898156 ps
CPU time 0.94 seconds
Started Jan 03 12:32:56 PM PST 24
Finished Jan 03 12:34:35 PM PST 24
Peak memory 195500 kb
Host smart-e49886b7-e542-4016-9cf3-a87d952ee143
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430240116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3430240116
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3828295669
Short name T148
Test name
Test status
Simulation time 111812535 ps
CPU time 0.85 seconds
Started Jan 03 12:33:04 PM PST 24
Finished Jan 03 12:34:28 PM PST 24
Peak memory 196112 kb
Host smart-bdf9f1c2-256b-4e28-a3cb-d73921713c4a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828295669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3828295669
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3630372254
Short name T198
Test name
Test status
Simulation time 154398009 ps
CPU time 0.83 seconds
Started Jan 03 12:33:31 PM PST 24
Finished Jan 03 12:34:56 PM PST 24
Peak memory 195004 kb
Host smart-8633505c-6a3a-4caa-adb7-95cdda631425
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3630372254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3630372254
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.723756692
Short name T158
Test name
Test status
Simulation time 33458469 ps
CPU time 0.91 seconds
Started Jan 03 12:45:15 PM PST 24
Finished Jan 03 12:46:57 PM PST 24
Peak memory 195272 kb
Host smart-fe4471e3-3d4d-4853-9d72-f9868db0ba30
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723756692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.723756692
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2565473158
Short name T170
Test name
Test status
Simulation time 50209382 ps
CPU time 1.03 seconds
Started Jan 03 12:33:53 PM PST 24
Finished Jan 03 12:35:10 PM PST 24
Peak memory 195500 kb
Host smart-39119e24-3cbb-4999-b127-c45705215d57
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2565473158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2565473158
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3336100161
Short name T168
Test name
Test status
Simulation time 188148985 ps
CPU time 1.29 seconds
Started Jan 03 12:36:34 PM PST 24
Finished Jan 03 12:38:02 PM PST 24
Peak memory 196784 kb
Host smart-8e17218c-ce89-490c-8cf3-f1f3a8752735
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336100161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3336100161
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4136962691
Short name T180
Test name
Test status
Simulation time 72356917 ps
CPU time 1.3 seconds
Started Jan 03 12:33:20 PM PST 24
Finished Jan 03 12:34:45 PM PST 24
Peak memory 196424 kb
Host smart-f117a683-0cec-4bf6-ba67-72e9a223e36d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4136962691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.4136962691
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2151606162
Short name T193
Test name
Test status
Simulation time 125821330 ps
CPU time 1.29 seconds
Started Jan 03 12:33:11 PM PST 24
Finished Jan 03 12:34:49 PM PST 24
Peak memory 197696 kb
Host smart-4c8e7f58-b13d-416e-bdd2-5788d4d752ff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151606162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2151606162
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2283215352
Short name T139
Test name
Test status
Simulation time 81422430 ps
CPU time 0.72 seconds
Started Jan 03 12:34:22 PM PST 24
Finished Jan 03 12:35:39 PM PST 24
Peak memory 194080 kb
Host smart-c4f054d6-f044-4dbe-b677-0f9dd0959c8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2283215352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2283215352
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2375449794
Short name T166
Test name
Test status
Simulation time 168456081 ps
CPU time 1.22 seconds
Started Jan 03 12:33:19 PM PST 24
Finished Jan 03 12:34:35 PM PST 24
Peak memory 196168 kb
Host smart-39727181-669e-4f99-a6ee-e816f076ae21
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375449794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2375449794
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2528861434
Short name T141
Test name
Test status
Simulation time 56731609 ps
CPU time 1.2 seconds
Started Jan 03 12:33:28 PM PST 24
Finished Jan 03 12:34:51 PM PST 24
Peak memory 196452 kb
Host smart-058acbdb-19ed-4c19-9c5b-338d3ab86408
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2528861434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2528861434
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2394104617
Short name T192
Test name
Test status
Simulation time 128684941 ps
CPU time 0.68 seconds
Started Jan 03 12:35:12 PM PST 24
Finished Jan 03 12:36:46 PM PST 24
Peak memory 195640 kb
Host smart-e6ec0d19-0779-448c-bf35-8e31ea0e05af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394104617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2394104617
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3853492474
Short name T58
Test name
Test status
Simulation time 42984414 ps
CPU time 0.92 seconds
Started Jan 03 12:33:48 PM PST 24
Finished Jan 03 12:35:23 PM PST 24
Peak memory 197604 kb
Host smart-ef5b0203-158b-4846-9442-ddc628a2a025
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3853492474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3853492474
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2884452565
Short name T60
Test name
Test status
Simulation time 166012254 ps
CPU time 0.89 seconds
Started Jan 03 12:35:35 PM PST 24
Finished Jan 03 12:37:09 PM PST 24
Peak memory 195184 kb
Host smart-fef0c247-7f38-48f5-9b12-43a784f0c278
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2884452565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2884452565
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2267493884
Short name T138
Test name
Test status
Simulation time 224365342 ps
CPU time 0.96 seconds
Started Jan 03 12:35:35 PM PST 24
Finished Jan 03 12:37:07 PM PST 24
Peak memory 196196 kb
Host smart-8dcb1d84-e266-453f-a301-6524ece22210
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267493884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2267493884
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3878004918
Short name T184
Test name
Test status
Simulation time 36786290 ps
CPU time 1 seconds
Started Jan 03 12:33:24 PM PST 24
Finished Jan 03 12:35:00 PM PST 24
Peak memory 196364 kb
Host smart-f39262d5-34b8-46b2-be90-ccc4d521e825
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3878004918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3878004918
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3320812065
Short name T162
Test name
Test status
Simulation time 121331657 ps
CPU time 0.96 seconds
Started Jan 03 12:33:34 PM PST 24
Finished Jan 03 12:35:00 PM PST 24
Peak memory 197588 kb
Host smart-39dd8c52-b2ec-4477-83be-455de8fa109f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320812065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3320812065
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1465918124
Short name T146
Test name
Test status
Simulation time 80117899 ps
CPU time 1.26 seconds
Started Jan 03 12:33:29 PM PST 24
Finished Jan 03 12:34:55 PM PST 24
Peak memory 196508 kb
Host smart-dfc224a4-d97c-427f-861d-d4583bd423f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1465918124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1465918124
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1042214480
Short name T56
Test name
Test status
Simulation time 43663747 ps
CPU time 1.15 seconds
Started Jan 03 12:32:55 PM PST 24
Finished Jan 03 12:34:15 PM PST 24
Peak memory 196564 kb
Host smart-d99b6ada-6267-4329-a342-45cf8cdc16b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042214480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1042214480
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1233887048
Short name T42
Test name
Test status
Simulation time 325795584 ps
CPU time 1.16 seconds
Started Jan 03 12:33:12 PM PST 24
Finished Jan 03 12:34:26 PM PST 24
Peak memory 195556 kb
Host smart-e375477d-0f8d-4981-a16d-42e1c6a65881
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1233887048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1233887048
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.175571933
Short name T130
Test name
Test status
Simulation time 107251700 ps
CPU time 0.73 seconds
Started Jan 03 12:32:45 PM PST 24
Finished Jan 03 12:34:49 PM PST 24
Peak memory 195740 kb
Host smart-566a7706-86d6-441a-b8a9-5c1bf38c3035
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175571933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.175571933
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1061259504
Short name T187
Test name
Test status
Simulation time 187398701 ps
CPU time 1.28 seconds
Started Jan 03 12:33:07 PM PST 24
Finished Jan 03 12:34:49 PM PST 24
Peak memory 196544 kb
Host smart-6900e9fd-e46e-473f-b1da-ccb8cf046820
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1061259504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1061259504
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.900030058
Short name T191
Test name
Test status
Simulation time 81680163 ps
CPU time 1.26 seconds
Started Jan 03 12:33:11 PM PST 24
Finished Jan 03 12:34:54 PM PST 24
Peak memory 197648 kb
Host smart-755b4f1c-eac4-4540-8fac-65725aaee66f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900030058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.900030058
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1978646050
Short name T133
Test name
Test status
Simulation time 139554224 ps
CPU time 1.05 seconds
Started Jan 03 12:33:40 PM PST 24
Finished Jan 03 12:35:09 PM PST 24
Peak memory 196324 kb
Host smart-9d2cd7e7-9103-491e-a1b1-4d57cd5046a5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1978646050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1978646050
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.887800553
Short name T156
Test name
Test status
Simulation time 41752828 ps
CPU time 1.24 seconds
Started Jan 03 12:33:35 PM PST 24
Finished Jan 03 12:34:50 PM PST 24
Peak memory 196264 kb
Host smart-934e1732-a4a9-4037-893f-e245d4854a4b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887800553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.887800553
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3000826446
Short name T137
Test name
Test status
Simulation time 99622207 ps
CPU time 0.73 seconds
Started Jan 03 12:33:30 PM PST 24
Finished Jan 03 12:35:00 PM PST 24
Peak memory 195084 kb
Host smart-1ed50ad4-00ba-4728-9999-4831839207e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3000826446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3000826446
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4259963856
Short name T204
Test name
Test status
Simulation time 233363395 ps
CPU time 1.17 seconds
Started Jan 03 12:33:40 PM PST 24
Finished Jan 03 12:35:13 PM PST 24
Peak memory 195536 kb
Host smart-27935214-2fb5-4577-ba55-be4637940295
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259963856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4259963856
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2679042357
Short name T44
Test name
Test status
Simulation time 202648301 ps
CPU time 1.26 seconds
Started Jan 03 12:33:43 PM PST 24
Finished Jan 03 12:35:04 PM PST 24
Peak memory 196200 kb
Host smart-d892c893-628a-41b2-9cd8-8801e5fdd61a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2679042357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2679042357
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1493673280
Short name T177
Test name
Test status
Simulation time 109067848 ps
CPU time 1.13 seconds
Started Jan 03 12:33:44 PM PST 24
Finished Jan 03 12:35:13 PM PST 24
Peak memory 197240 kb
Host smart-edbf4b7c-d477-4bdd-893a-0a7470bde14e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493673280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1493673280
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2494252554
Short name T160
Test name
Test status
Simulation time 238025636 ps
CPU time 1.05 seconds
Started Jan 03 12:37:09 PM PST 24
Finished Jan 03 12:38:29 PM PST 24
Peak memory 195108 kb
Host smart-7b9bd251-c3e1-49c2-b567-f6ca290d65e7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2494252554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2494252554
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3556850356
Short name T140
Test name
Test status
Simulation time 98068634 ps
CPU time 1.41 seconds
Started Jan 03 12:33:27 PM PST 24
Finished Jan 03 12:34:50 PM PST 24
Peak memory 196436 kb
Host smart-cea729a3-5929-47d6-9fb1-256adbd31e4b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556850356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3556850356
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1146370335
Short name T161
Test name
Test status
Simulation time 119140798 ps
CPU time 0.68 seconds
Started Jan 03 12:33:12 PM PST 24
Finished Jan 03 12:34:42 PM PST 24
Peak memory 194068 kb
Host smart-54717700-1502-46a5-8b01-9787051cdbc1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1146370335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1146370335
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.903956151
Short name T182
Test name
Test status
Simulation time 76331679 ps
CPU time 1.34 seconds
Started Jan 03 12:33:39 PM PST 24
Finished Jan 03 12:35:01 PM PST 24
Peak memory 197608 kb
Host smart-0ac58a40-b43d-4f0c-b90e-bceb0599de93
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903956151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.903956151
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2738072258
Short name T179
Test name
Test status
Simulation time 36712454 ps
CPU time 0.78 seconds
Started Jan 03 12:33:50 PM PST 24
Finished Jan 03 12:35:42 PM PST 24
Peak memory 195080 kb
Host smart-06fd2052-e970-4d60-86e6-73fccc97e2c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2738072258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2738072258
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.578519439
Short name T159
Test name
Test status
Simulation time 63894519 ps
CPU time 1.17 seconds
Started Jan 03 12:35:22 PM PST 24
Finished Jan 03 12:36:59 PM PST 24
Peak memory 196204 kb
Host smart-28b8ce35-cf2d-49b2-b513-d7fdce625036
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578519439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.578519439
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.684814366
Short name T145
Test name
Test status
Simulation time 124016121 ps
CPU time 0.89 seconds
Started Jan 03 12:34:33 PM PST 24
Finished Jan 03 12:35:44 PM PST 24
Peak memory 196324 kb
Host smart-dd018634-a333-4a60-bbf1-b03b24f543ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=684814366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.684814366
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2986373014
Short name T200
Test name
Test status
Simulation time 179246138 ps
CPU time 1.34 seconds
Started Jan 03 12:33:19 PM PST 24
Finished Jan 03 12:34:30 PM PST 24
Peak memory 196412 kb
Host smart-6e3c86f2-61fb-4a8f-8674-5355eaf76265
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986373014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2986373014
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3406410365
Short name T131
Test name
Test status
Simulation time 69976438 ps
CPU time 1.15 seconds
Started Jan 03 12:34:47 PM PST 24
Finished Jan 03 12:36:06 PM PST 24
Peak memory 195868 kb
Host smart-fb3ccf37-b66e-40ee-92f7-1e676ebb31b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3406410365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3406410365
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3587065622
Short name T175
Test name
Test status
Simulation time 184325087 ps
CPU time 1.02 seconds
Started Jan 03 12:33:21 PM PST 24
Finished Jan 03 12:34:35 PM PST 24
Peak memory 196168 kb
Host smart-3702c6c4-18c8-4a42-87a3-7e2a47802615
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587065622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3587065622
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.295740066
Short name T201
Test name
Test status
Simulation time 60061098 ps
CPU time 0.93 seconds
Started Jan 03 12:33:36 PM PST 24
Finished Jan 03 12:35:14 PM PST 24
Peak memory 195560 kb
Host smart-c5fd0abe-13ca-4834-9f08-71bb7d646659
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=295740066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.295740066
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1482602559
Short name T129
Test name
Test status
Simulation time 68791032 ps
CPU time 1.09 seconds
Started Jan 03 12:33:33 PM PST 24
Finished Jan 03 12:34:46 PM PST 24
Peak memory 195584 kb
Host smart-a4281ccb-b831-4fa3-b642-dd511b50c271
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482602559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1482602559
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.523712202
Short name T205
Test name
Test status
Simulation time 159771098 ps
CPU time 0.92 seconds
Started Jan 03 12:33:37 PM PST 24
Finished Jan 03 12:35:07 PM PST 24
Peak memory 197544 kb
Host smart-8c98bd02-6dc7-4e18-82fa-9c8072eafc08
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=523712202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.523712202
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1991109526
Short name T55
Test name
Test status
Simulation time 54677374 ps
CPU time 1.35 seconds
Started Jan 03 12:34:35 PM PST 24
Finished Jan 03 12:35:49 PM PST 24
Peak memory 194772 kb
Host smart-b1866376-c746-4bfd-b581-03f9c6fd5585
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991109526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1991109526
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.857329127
Short name T135
Test name
Test status
Simulation time 186996511 ps
CPU time 1.19 seconds
Started Jan 03 12:32:58 PM PST 24
Finished Jan 03 12:34:21 PM PST 24
Peak memory 196440 kb
Host smart-fffd792d-c13a-438e-907a-2c3bdd6ec479
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=857329127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.857329127
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4097118903
Short name T157
Test name
Test status
Simulation time 136677308 ps
CPU time 1.17 seconds
Started Jan 03 12:34:41 PM PST 24
Finished Jan 03 12:36:03 PM PST 24
Peak memory 195388 kb
Host smart-9eaa3700-952d-4931-a9f5-5e23f6c5c408
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097118903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4097118903
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3915345217
Short name T194
Test name
Test status
Simulation time 64224964 ps
CPU time 0.96 seconds
Started Jan 03 12:33:37 PM PST 24
Finished Jan 03 12:34:56 PM PST 24
Peak memory 196524 kb
Host smart-ec9286c3-cb39-4421-a64b-b3b250f361bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3915345217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3915345217
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.946852787
Short name T181
Test name
Test status
Simulation time 351707282 ps
CPU time 1.28 seconds
Started Jan 03 12:33:03 PM PST 24
Finished Jan 03 12:34:26 PM PST 24
Peak memory 195228 kb
Host smart-e6179884-2a5e-44f4-86ee-b87041789d80
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946852787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.946852787
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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