Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5506966	1			T23	10		T24	8		T25	11
all_pins[1]	5506966	1			T23	10		T24	8		T25	11
all_pins[2]	5506966	1			T23	10		T24	8		T25	11
all_pins[3]	5506966	1			T23	10		T24	8		T25	11
all_pins[4]	5506966	1			T23	10		T24	8		T25	11
all_pins[5]	5506966	1			T23	10		T24	8		T25	11
all_pins[6]	5506966	1			T23	10		T24	8		T25	11
all_pins[7]	5506966	1			T23	10		T24	8		T25	11
all_pins[8]	5506966	1			T23	10		T24	8		T25	11
all_pins[9]	5506966	1			T23	10		T24	8		T25	11
all_pins[10]	5506966	1			T23	10		T24	8		T25	11
all_pins[11]	5506966	1			T23	10		T24	8		T25	11
all_pins[12]	5506966	1			T23	10		T24	8		T25	11
all_pins[13]	5506966	1			T23	10		T24	8		T25	11
all_pins[14]	5506966	1			T23	10		T24	8		T25	11
all_pins[15]	5506966	1			T23	10		T24	8		T25	11
all_pins[16]	5506966	1			T23	10		T24	8		T25	11
all_pins[17]	5506966	1			T23	10		T24	8		T25	11
all_pins[18]	5506966	1			T23	10		T24	8		T25	11
all_pins[19]	5506966	1			T23	10		T24	8		T25	11
all_pins[20]	5506966	1			T23	10		T24	8		T25	11
all_pins[21]	5506966	1			T23	10		T24	8		T25	11
all_pins[22]	5506966	1			T23	10		T24	8		T25	11
all_pins[23]	5506966	1			T23	10		T24	8		T25	11
all_pins[24]	5506966	1			T23	10		T24	8		T25	11
all_pins[25]	5506966	1			T23	10		T24	8		T25	11
all_pins[26]	5506966	1			T23	10		T24	8		T25	11
all_pins[27]	5506966	1			T23	10		T24	8		T25	11
all_pins[28]	5506966	1			T23	10		T24	8		T25	11
all_pins[29]	5506966	1			T23	10		T24	8		T25	11
all_pins[30]	5506966	1			T23	10		T24	8		T25	11
all_pins[31]	5506966	1			T23	10		T24	8		T25	11

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	109218058	1			T23	274		T24	185		T25	211
values[0x1]	67004854	1			T23	46		T24	71		T25	141
transitions[0x0=>0x1]	40078955	1			T23	31		T24	43		T25	77
transitions[0x1=>0x0]	40078800	1			T23	31		T24	43		T25	76

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3409564	1			T23	8		T24	2		T25	3
all_pins[0]	values[0x1]	2097402	1			T23	2		T24	6		T25	8
all_pins[0]	transitions[0x0=>0x1]	1297515	1			T23	2		T24	6		T25	5
all_pins[0]	transitions[0x1=>0x0]	1292072	1			T23	2		T26	5		T21	1
all_pins[1]	values[0x0]	3414826	1			T23	8		T24	8		T25	6
all_pins[1]	values[0x1]	2092140	1			T23	2		T25	5		T26	7
all_pins[1]	transitions[0x0=>0x1]	1246745	1			T23	2		T25	1		T26	3
all_pins[1]	transitions[0x1=>0x0]	1252007	1			T23	2		T24	6		T25	4
all_pins[2]	values[0x0]	3416154	1			T23	9		T24	4		T25	4
all_pins[2]	values[0x1]	2090812	1			T23	1		T24	4		T25	7
all_pins[2]	transitions[0x0=>0x1]	1247831	1			T23	1		T24	4		T25	3
all_pins[2]	transitions[0x1=>0x0]	1249159	1			T23	2		T25	1		T26	4
all_pins[3]	values[0x0]	3414049	1			T23	10		T24	3		T25	5
all_pins[3]	values[0x1]	2092917	1			T24	5		T25	6		T27	1
all_pins[3]	transitions[0x0=>0x1]	1252464	1			T24	1		T25	1		T27	1
all_pins[3]	transitions[0x1=>0x0]	1250359	1			T23	1		T25	2		T26	3
all_pins[4]	values[0x0]	3418225	1			T23	8		T24	2		T25	7
all_pins[4]	values[0x1]	2088741	1			T23	2		T24	6		T25	4
all_pins[4]	transitions[0x0=>0x1]	1245876	1			T23	2		T24	2		T25	2
all_pins[4]	transitions[0x1=>0x0]	1250052	1			T24	1		T25	4		T27	1
all_pins[5]	values[0x0]	3411746	1			T23	8		T24	1		T25	9
all_pins[5]	values[0x1]	2095220	1			T23	2		T24	7		T25	2
all_pins[5]	transitions[0x0=>0x1]	1254302	1			T23	2		T24	1		T25	2
all_pins[5]	transitions[0x1=>0x0]	1247823	1			T23	2		T25	4		T26	1
all_pins[6]	values[0x0]	3413548	1			T23	8		T24	3		T25	8
all_pins[6]	values[0x1]	2093418	1			T23	2		T24	5		T25	3
all_pins[6]	transitions[0x0=>0x1]	1249539	1			T25	2		T26	4		T27	1
all_pins[6]	transitions[0x1=>0x0]	1251341	1			T24	2		T25	1		T26	4
all_pins[7]	values[0x0]	3419238	1			T23	8		T24	7		T25	9
all_pins[7]	values[0x1]	2087728	1			T23	2		T24	1		T25	2
all_pins[7]	transitions[0x0=>0x1]	1248820	1			T24	1		T25	1		T26	1
all_pins[7]	transitions[0x1=>0x0]	1254510	1			T24	5		T25	2		T26	5
all_pins[8]	values[0x0]	3417262	1			T23	10		T24	2		T25	9
all_pins[8]	values[0x1]	2089704	1			T24	6		T25	2		T28	9
all_pins[8]	transitions[0x0=>0x1]	1252092	1			T24	5		T28	4		T21	4
all_pins[8]	transitions[0x1=>0x0]	1250116	1			T23	2		T26	2		T28	1
all_pins[9]	values[0x0]	3403831	1			T23	10		T24	8		T25	4
all_pins[9]	values[0x1]	2103135	1			T25	7		T26	7		T27	1
all_pins[9]	transitions[0x0=>0x1]	1255845	1			T25	7		T26	7		T27	1
all_pins[9]	transitions[0x1=>0x0]	1242414	1			T24	6		T25	2		T28	4
all_pins[10]	values[0x0]	3413771	1			T23	8		T24	7		T25	7
all_pins[10]	values[0x1]	2093195	1			T23	2		T24	1		T25	4
all_pins[10]	transitions[0x0=>0x1]	1247844	1			T23	2		T24	1		T25	2
all_pins[10]	transitions[0x1=>0x0]	1257784	1			T25	5		T26	4		T27	1
all_pins[11]	values[0x0]	3409917	1			T23	10		T24	8		T25	9
all_pins[11]	values[0x1]	2097049	1			T25	2		T26	4		T21	8
all_pins[11]	transitions[0x0=>0x1]	1253106	1			T26	3		T21	6		T1	1
all_pins[11]	transitions[0x1=>0x0]	1249252	1			T23	2		T24	1		T25	2
all_pins[12]	values[0x0]	3412344	1			T23	10		T24	2		T25	11
all_pins[12]	values[0x1]	2094622	1			T24	6		T26	3		T28	2
all_pins[12]	transitions[0x0=>0x1]	1251710	1			T24	6		T26	3		T28	2
all_pins[12]	transitions[0x1=>0x0]	1254137	1			T25	2		T26	4		T21	6
all_pins[13]	values[0x0]	3420244	1			T23	9		T24	4		T25	2
all_pins[13]	values[0x1]	2086722	1			T23	1		T24	4		T25	9
all_pins[13]	transitions[0x0=>0x1]	1247318	1			T23	1		T24	1		T25	9
all_pins[13]	transitions[0x1=>0x0]	1255218	1			T24	3		T26	1		T21	3
all_pins[14]	values[0x0]	3411705	1			T23	10		T24	7		T25	2
all_pins[14]	values[0x1]	2095261	1			T24	1		T25	9		T26	2
all_pins[14]	transitions[0x0=>0x1]	1254520	1			T25	1		T26	2		T21	2
all_pins[14]	transitions[0x1=>0x0]	1245981	1			T23	1		T24	3		T25	1
all_pins[15]	values[0x0]	3409657	1			T23	8		T24	8		T25	11
all_pins[15]	values[0x1]	2097309	1			T23	2		T26	1		T28	8
all_pins[15]	transitions[0x0=>0x1]	1253632	1			T23	2		T26	1		T28	8
all_pins[15]	transitions[0x1=>0x0]	1251584	1			T24	1		T25	9		T26	2
all_pins[16]	values[0x0]	3409409	1			T23	8		T24	8		T25	3
all_pins[16]	values[0x1]	2097557	1			T23	2		T25	8		T26	8
all_pins[16]	transitions[0x0=>0x1]	1252969	1			T25	8		T26	7		T28	1
all_pins[16]	transitions[0x1=>0x0]	1252721	1			T28	3		T21	10		T1	2
all_pins[17]	values[0x0]	3416276	1			T23	8		T24	8		T25	9
all_pins[17]	values[0x1]	2090690	1			T23	2		T25	2		T26	4
all_pins[17]	transitions[0x0=>0x1]	1248055	1			T21	3		T1	1		T11	1
all_pins[17]	transitions[0x1=>0x0]	1254922	1			T25	6		T26	4		T28	3
all_pins[18]	values[0x0]	3412795	1			T23	8		T24	3		T25	5
all_pins[18]	values[0x1]	2094171	1			T23	2		T24	5		T25	6
all_pins[18]	transitions[0x0=>0x1]	1254563	1			T23	2		T24	5		T25	4
all_pins[18]	transitions[0x1=>0x0]	1251082	1			T23	2		T26	4		T28	3
all_pins[19]	values[0x0]	3406500	1			T23	9		T24	6		T25	8
all_pins[19]	values[0x1]	2100466	1			T23	1		T24	2		T25	3
all_pins[19]	transitions[0x0=>0x1]	1255313	1			T23	1		T25	1		T26	10
all_pins[19]	transitions[0x1=>0x0]	1249018	1			T23	2		T24	3		T25	4
all_pins[20]	values[0x0]	3414818	1			T23	8		T24	7		T25	8
all_pins[20]	values[0x1]	2092148	1			T23	2		T24	1		T25	3
all_pins[20]	transitions[0x0=>0x1]	1244362	1			T23	1		T24	1		T25	1
all_pins[20]	transitions[0x1=>0x0]	1252680	1			T24	2		T25	1		T26	9
all_pins[21]	values[0x0]	3411245	1			T23	6		T24	8		T25	6
all_pins[21]	values[0x1]	2095721	1			T23	4		T25	5		T26	5
all_pins[21]	transitions[0x0=>0x1]	1253629	1			T23	2		T25	5		T26	4
all_pins[21]	transitions[0x1=>0x0]	1250056	1			T24	1		T25	3		T26	2
all_pins[22]	values[0x0]	3413291	1			T23	8		T24	8		T25	2
all_pins[22]	values[0x1]	2093675	1			T23	2		T25	9		T26	4
all_pins[22]	transitions[0x0=>0x1]	1254614	1			T25	5		T26	3		T27	1
all_pins[22]	transitions[0x1=>0x0]	1256660	1			T23	2		T25	1		T26	4
all_pins[23]	values[0x0]	3411888	1			T23	10		T24	8		T25	3
all_pins[23]	values[0x1]	2095078	1			T25	8		T26	7		T28	6
all_pins[23]	transitions[0x0=>0x1]	1253020	1			T26	7		T28	3		T21	10
all_pins[23]	transitions[0x1=>0x0]	1251617	1			T23	2		T25	1		T26	4
all_pins[24]	values[0x0]	3414434	1			T23	7		T24	6		T25	10
all_pins[24]	values[0x1]	2092532	1			T23	3		T24	2		T25	1
all_pins[24]	transitions[0x0=>0x1]	1249902	1			T23	3		T24	2		T26	6
all_pins[24]	transitions[0x1=>0x0]	1252448	1			T25	7		T26	5		T28	5
all_pins[25]	values[0x0]	3409994	1			T23	10		T24	8		T25	9
all_pins[25]	values[0x1]	2096972	1			T25	2		T26	11		T28	3
all_pins[25]	transitions[0x0=>0x1]	1252569	1			T25	1		T26	3		T21	7
all_pins[25]	transitions[0x1=>0x0]	1248129	1			T23	3		T24	2		T27	1
all_pins[26]	values[0x0]	3419957	1			T23	8		T24	7		T25	6
all_pins[26]	values[0x1]	2087009	1			T23	2		T24	1		T25	5
all_pins[26]	transitions[0x0=>0x1]	1244757	1			T23	2		T24	1		T25	3
all_pins[26]	transitions[0x1=>0x0]	1254720	1			T26	9		T21	9		T1	2
all_pins[27]	values[0x0]	3409587	1			T23	10		T24	6		T25	10
all_pins[27]	values[0x1]	2097379	1			T24	2		T25	1		T26	5
all_pins[27]	transitions[0x0=>0x1]	1256873	1			T24	2		T26	2		T21	4
all_pins[27]	transitions[0x1=>0x0]	1246503	1			T23	2		T24	1		T25	4
all_pins[28]	values[0x0]	3415555	1			T23	6		T24	7		T25	5
all_pins[28]	values[0x1]	2091411	1			T23	4		T24	1		T25	6
all_pins[28]	transitions[0x0=>0x1]	1248496	1			T23	4		T25	6		T21	6
all_pins[28]	transitions[0x1=>0x0]	1254464	1			T24	1		T25	1		T26	4
all_pins[29]	values[0x0]	3408206	1			T23	8		T24	6		T25	3
all_pins[29]	values[0x1]	2098760	1			T23	2		T24	2		T25	8
all_pins[29]	transitions[0x0=>0x1]	1253698	1			T24	1		T25	3		T28	4
all_pins[29]	transitions[0x1=>0x0]	1246349	1			T23	2		T25	1		T26	1
all_pins[30]	values[0x0]	3413170	1			T23	10		T24	5		T25	11
all_pins[30]	values[0x1]	2093796	1			T24	3		T26	8		T21	8
all_pins[30]	transitions[0x0=>0x1]	1247333	1			T24	3		T26	8		T21	8
all_pins[30]	transitions[0x1=>0x0]	1252297	1			T23	2		T24	2		T25	8
all_pins[31]	values[0x0]	3414852	1			T23	8		T24	8		T25	7
all_pins[31]	values[0x1]	2092114	1			T23	2		T25	4		T26	10
all_pins[31]	transitions[0x0=>0x1]	1249643	1			T23	2		T25	4		T26	4
all_pins[31]	transitions[0x1=>0x0]	1251325	1			T24	3		T26	2		T21	8