Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18870327	1			T23	7		T24	6		T25	16
all_values[1]	18870327	1			T23	7		T24	6		T25	16
all_values[2]	18870327	1			T23	7		T24	6		T25	16
all_values[3]	18870327	1			T23	7		T24	6		T25	16
all_values[4]	18870327	1			T23	7		T24	6		T25	16
all_values[5]	18870327	1			T23	7		T24	6		T25	16
all_values[6]	18870327	1			T23	7		T24	6		T25	16
all_values[7]	18870327	1			T23	7		T24	6		T25	16
all_values[8]	18870327	1			T23	7		T24	6		T25	16
all_values[9]	18870327	1			T23	7		T24	6		T25	16
all_values[10]	18870327	1			T23	7		T24	6		T25	16
all_values[11]	18870327	1			T23	7		T24	6		T25	16
all_values[12]	18870327	1			T23	7		T24	6		T25	16
all_values[13]	18870327	1			T23	7		T24	6		T25	16
all_values[14]	18870327	1			T23	7		T24	6		T25	16
all_values[15]	18870327	1			T23	7		T24	6		T25	16
all_values[16]	18870327	1			T23	7		T24	6		T25	16
all_values[17]	18870327	1			T23	7		T24	6		T25	16
all_values[18]	18870327	1			T23	7		T24	6		T25	16
all_values[19]	18870327	1			T23	7		T24	6		T25	16
all_values[20]	18870327	1			T23	7		T24	6		T25	16
all_values[21]	18870327	1			T23	7		T24	6		T25	16
all_values[22]	18870327	1			T23	7		T24	6		T25	16
all_values[23]	18870327	1			T23	7		T24	6		T25	16
all_values[24]	18870327	1			T23	7		T24	6		T25	16
all_values[25]	18870327	1			T23	7		T24	6		T25	16
all_values[26]	18870327	1			T23	7		T24	6		T25	16
all_values[27]	18870327	1			T23	7		T24	6		T25	16
all_values[28]	18870327	1			T23	7		T24	6		T25	16
all_values[29]	18870327	1			T23	7		T24	6		T25	16
all_values[30]	18870327	1			T23	7		T24	6		T25	16
all_values[31]	18870327	1			T23	7		T24	6		T25	16

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

339231233

1

T23

197

T24

115

T25

257

auto[1]

264619231

1

T23

27

T24

77

T25

255

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123324630

1

T23

178

T24

85

T25

210

auto[1]

480525834

1

T23

46

T24

107

T25

302

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

597187325

1

T23

224

T24

192

T25

512

auto[1]

6663139

1

T26

105

T21

138

T12

103

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3085947	1			T23	6		T24	1		T25	1
all_values[0]	auto[0]	auto[0]	auto[1]	7382726	1			T23	1		T26	5		T21	2
all_values[0]	auto[0]	auto[1]	auto[0]	761968	1			T26	6		T21	12		T11	1
all_values[0]	auto[0]	auto[1]	auto[1]	7431135	1			T24	5		T25	15		T26	3
all_values[0]	auto[1]	auto[0]	auto[1]	104632	1			T26	1		T21	2		T14	1
all_values[0]	auto[1]	auto[1]	auto[1]	103919	1			T26	2		T21	3		T12	1
all_values[1]	auto[0]	auto[0]	auto[0]	3086053	1			T23	5		T24	6		T25	1
all_values[1]	auto[0]	auto[0]	auto[1]	7412433	1			T23	1		T26	2		T21	5
all_values[1]	auto[0]	auto[1]	auto[0]	765684	1			T26	4		T28	7		T21	3
all_values[1]	auto[0]	auto[1]	auto[1]	7398302	1			T23	1		T25	15		T26	4
all_values[1]	auto[1]	auto[0]	auto[1]	104424	1			T26	1		T21	3		T12	2
all_values[1]	auto[1]	auto[1]	auto[1]	103431	1			T26	3		T14	2		T17	2
all_values[2]	auto[0]	auto[0]	auto[0]	3090246	1			T23	6		T24	1		T25	1
all_values[2]	auto[0]	auto[0]	auto[1]	7420957	1			T24	2		T26	2		T27	1
all_values[2]	auto[0]	auto[1]	auto[0]	762903	1			T24	1		T25	15		T26	3
all_values[2]	auto[0]	auto[1]	auto[1]	7387982	1			T23	1		T24	2		T26	3
all_values[2]	auto[1]	auto[0]	auto[1]	104451	1			T26	4		T21	1		T12	2
all_values[2]	auto[1]	auto[1]	auto[1]	103788	1			T21	3		T16	4		T94	5
all_values[3]	auto[0]	auto[0]	auto[0]	3084326	1			T23	6		T24	1		T25	1
all_values[3]	auto[0]	auto[0]	auto[1]	7393533	1			T23	1		T24	2		T28	15
all_values[3]	auto[0]	auto[1]	auto[0]	760980	1			T25	1		T26	10		T21	15
all_values[3]	auto[0]	auto[1]	auto[1]	7423691	1			T24	3		T25	14		T1	8
all_values[3]	auto[1]	auto[0]	auto[1]	103952	1			T26	1		T12	1		T14	2
all_values[3]	auto[1]	auto[1]	auto[1]	103845	1			T21	4		T12	2		T14	2
all_values[4]	auto[0]	auto[0]	auto[0]	3093449	1			T23	6		T24	1		T25	1
all_values[4]	auto[0]	auto[0]	auto[1]	7453403	1			T26	5		T27	1		T21	2
all_values[4]	auto[0]	auto[1]	auto[0]	751130	1			T26	3		T28	3		T21	8
all_values[4]	auto[0]	auto[1]	auto[1]	7364029	1			T23	1		T24	5		T25	15
all_values[4]	auto[1]	auto[0]	auto[1]	104650	1			T26	1		T21	2		T12	1
all_values[4]	auto[1]	auto[1]	auto[1]	103666	1			T26	1		T21	1		T12	2
all_values[5]	auto[0]	auto[0]	auto[0]	3092792	1			T23	5		T24	1		T25	1
all_values[5]	auto[0]	auto[0]	auto[1]	7446199	1			T23	2		T25	15		T26	3
all_values[5]	auto[0]	auto[1]	auto[0]	764922	1			T26	4		T28	7		T21	16
all_values[5]	auto[0]	auto[1]	auto[1]	7357699	1			T24	5		T26	4		T21	7
all_values[5]	auto[1]	auto[0]	auto[1]	104106	1			T26	2		T21	2		T12	3
all_values[5]	auto[1]	auto[1]	auto[1]	104609	1			T26	2		T21	1		T12	1
all_values[6]	auto[0]	auto[0]	auto[0]	3090978	1			T23	4		T24	1		T25	1
all_values[6]	auto[0]	auto[0]	auto[1]	7450083	1			T23	3		T24	2		T26	2
all_values[6]	auto[0]	auto[1]	auto[0]	771161	1			T25	12		T26	3		T21	10
all_values[6]	auto[0]	auto[1]	auto[1]	7349917	1			T24	3		T25	3		T26	5
all_values[6]	auto[1]	auto[0]	auto[1]	104087	1			T26	1		T21	4		T12	1
all_values[6]	auto[1]	auto[1]	auto[1]	104101	1			T26	1		T21	2		T12	1
all_values[7]	auto[0]	auto[0]	auto[0]	3099606	1			T23	4		T24	4		T25	1
all_values[7]	auto[0]	auto[0]	auto[1]	7399863	1			T23	2		T25	15		T26	3
all_values[7]	auto[0]	auto[1]	auto[0]	773440	1			T23	1		T26	7		T28	7
all_values[7]	auto[0]	auto[1]	auto[1]	7389681	1			T24	2		T21	2		T1	2
all_values[7]	auto[1]	auto[0]	auto[1]	103911	1			T26	3		T21	1		T12	1
all_values[7]	auto[1]	auto[1]	auto[1]	103826	1			T26	2		T21	2		T12	1
all_values[8]	auto[0]	auto[0]	auto[0]	3095265	1			T23	5		T24	1		T25	16
all_values[8]	auto[0]	auto[0]	auto[1]	7405680	1			T23	2		T21	5		T11	1
all_values[8]	auto[0]	auto[1]	auto[0]	761248	1			T26	9		T21	7		T11	1
all_values[8]	auto[0]	auto[1]	auto[1]	7400374	1			T24	5		T28	7		T21	4
all_values[8]	auto[1]	auto[0]	auto[1]	103998	1			T21	4		T12	2		T14	6
all_values[8]	auto[1]	auto[1]	auto[1]	103762	1			T21	1		T12	2		T14	1
all_values[9]	auto[0]	auto[0]	auto[0]	3084242	1			T23	5		T24	4		T25	1
all_values[9]	auto[0]	auto[0]	auto[1]	7381536	1			T23	1		T26	2		T11	1
all_values[9]	auto[0]	auto[1]	auto[0]	765486	1			T23	1		T24	2		T25	3
all_values[9]	auto[0]	auto[1]	auto[1]	7430547	1			T25	12		T26	4		T28	6
all_values[9]	auto[1]	auto[0]	auto[1]	103907	1			T26	1		T14	3		T16	1
all_values[9]	auto[1]	auto[1]	auto[1]	104609	1			T26	3		T21	5		T12	4
all_values[10]	auto[0]	auto[0]	auto[0]	3089299	1			T23	5		T24	1		T25	1
all_values[10]	auto[0]	auto[0]	auto[1]	7400781	1			T24	5		T25	15		T26	1
all_values[10]	auto[0]	auto[1]	auto[0]	770324	1			T23	2		T26	7		T21	8
all_values[10]	auto[0]	auto[1]	auto[1]	7401501	1			T26	2		T28	7		T21	4
all_values[10]	auto[1]	auto[0]	auto[1]	104444	1			T26	2		T21	2		T12	1
all_values[10]	auto[1]	auto[1]	auto[1]	103978	1			T26	4		T21	1		T12	3
all_values[11]	auto[0]	auto[0]	auto[0]	3095055	1			T23	6		T24	1		T25	16
all_values[11]	auto[0]	auto[0]	auto[1]	7401912	1			T23	1		T26	2		T21	1
all_values[11]	auto[0]	auto[1]	auto[0]	759809	1			T24	5		T26	4		T21	9
all_values[11]	auto[0]	auto[1]	auto[1]	7405015	1			T26	3		T21	6		T12	7
all_values[11]	auto[1]	auto[0]	auto[1]	104567	1			T26	1		T21	2		T14	2
all_values[11]	auto[1]	auto[1]	auto[1]	103969	1			T26	2		T21	2		T12	4
all_values[12]	auto[0]	auto[0]	auto[0]	3102366	1			T23	6		T24	1		T25	2
all_values[12]	auto[0]	auto[0]	auto[1]	7376314	1			T25	14		T21	5		T11	1
all_values[12]	auto[0]	auto[1]	auto[0]	763899	1			T23	1		T26	8		T28	7
all_values[12]	auto[0]	auto[1]	auto[1]	7420030	1			T24	5		T26	1		T21	5
all_values[12]	auto[1]	auto[0]	auto[1]	103915	1			T21	3		T12	2		T14	1
all_values[12]	auto[1]	auto[1]	auto[1]	103803	1			T26	2		T21	3		T12	2
all_values[13]	auto[0]	auto[0]	auto[0]	3095341	1			T23	6		T24	1		T25	1
all_values[13]	auto[0]	auto[0]	auto[1]	7404208	1			T26	4		T21	4		T11	1
all_values[13]	auto[0]	auto[1]	auto[0]	769217	1			T23	1		T24	1		T26	6
all_values[13]	auto[0]	auto[1]	auto[1]	7393028	1			T24	4		T25	15		T26	2
all_values[13]	auto[1]	auto[0]	auto[1]	104832	1			T26	2		T21	2		T12	2
all_values[13]	auto[1]	auto[1]	auto[1]	103701	1			T26	1		T21	6		T12	1
all_values[14]	auto[0]	auto[0]	auto[0]	3084750	1			T23	7		T24	1		T25	1
all_values[14]	auto[0]	auto[0]	auto[1]	7407648	1			T24	2		T27	1		T28	7
all_values[14]	auto[0]	auto[1]	auto[0]	772380	1			T24	3		T25	5		T26	6
all_values[14]	auto[0]	auto[1]	auto[1]	7397403	1			T25	10		T26	1		T21	1
all_values[14]	auto[1]	auto[0]	auto[1]	104187	1			T26	1		T21	1		T12	1
all_values[14]	auto[1]	auto[1]	auto[1]	103959	1			T26	1		T21	2		T12	2
all_values[15]	auto[0]	auto[0]	auto[0]	3087708	1			T23	6		T24	6		T25	1
all_values[15]	auto[0]	auto[0]	auto[1]	7373293	1			T25	15		T21	4		T1	6
all_values[15]	auto[0]	auto[1]	auto[0]	765997	1			T26	6		T28	7		T21	9
all_values[15]	auto[0]	auto[1]	auto[1]	7435329	1			T23	1		T21	11		T1	2
all_values[15]	auto[1]	auto[0]	auto[1]	103961	1			T21	1		T14	3		T16	2
all_values[15]	auto[1]	auto[1]	auto[1]	104039	1			T26	1		T21	3		T12	5
all_values[16]	auto[0]	auto[0]	auto[0]	3092583	1			T23	4		T24	1		T25	1
all_values[16]	auto[0]	auto[0]	auto[1]	7392940	1			T23	1		T24	5		T28	8
all_values[16]	auto[0]	auto[1]	auto[0]	759365	1			T23	1		T26	9		T21	2
all_values[16]	auto[0]	auto[1]	auto[1]	7417166	1			T23	1		T25	15		T26	6
all_values[16]	auto[1]	auto[0]	auto[1]	104815	1			T26	1		T21	2		T12	2
all_values[16]	auto[1]	auto[1]	auto[1]	103458	1			T26	2		T21	2		T12	1
all_values[17]	auto[0]	auto[0]	auto[0]	3088570	1			T23	5		T24	4		T25	1
all_values[17]	auto[0]	auto[0]	auto[1]	7451739	1			T23	1		T24	2		T25	15
all_values[17]	auto[0]	auto[1]	auto[0]	774142	1			T26	4		T28	7		T21	11
all_values[17]	auto[0]	auto[1]	auto[1]	7347785	1			T23	1		T26	3		T21	5
all_values[17]	auto[1]	auto[0]	auto[1]	104232	1			T26	2		T21	4		T12	4
all_values[17]	auto[1]	auto[1]	auto[1]	103859	1			T26	1		T12	1		T16	1
all_values[18]	auto[0]	auto[0]	auto[0]	3084946	1			T23	5		T24	1		T25	1
all_values[18]	auto[0]	auto[0]	auto[1]	7401568	1			T23	1		T24	2		T26	2
all_values[18]	auto[0]	auto[1]	auto[0]	759738	1			T23	1		T26	6		T21	14
all_values[18]	auto[0]	auto[1]	auto[1]	7415808	1			T24	3		T25	15		T26	1
all_values[18]	auto[1]	auto[0]	auto[1]	104669	1			T26	3		T21	1		T12	3
all_values[18]	auto[1]	auto[1]	auto[1]	103598	1			T26	1		T21	3		T14	4
all_values[19]	auto[0]	auto[0]	auto[0]	3092407	1			T23	5		T24	1		T25	13
all_values[19]	auto[0]	auto[0]	auto[1]	7381665	1			T23	1		T24	2		T25	3
all_values[19]	auto[0]	auto[1]	auto[0]	766863	1			T24	1		T26	4		T28	7
all_values[19]	auto[0]	auto[1]	auto[1]	7421048	1			T23	1		T24	2		T26	9
all_values[19]	auto[1]	auto[0]	auto[1]	103928	1			T26	1		T21	4		T16	2
all_values[19]	auto[1]	auto[1]	auto[1]	104416	1			T26	3		T12	3		T14	6
all_values[20]	auto[0]	auto[0]	auto[0]	3090089	1			T23	6		T24	1		T25	14
all_values[20]	auto[0]	auto[0]	auto[1]	7435583	1			T24	5		T25	2		T26	6
all_values[20]	auto[0]	auto[1]	auto[0]	757954	1			T26	2		T21	13		T1	2
all_values[20]	auto[0]	auto[1]	auto[1]	7378342	1			T23	1		T26	1		T21	2
all_values[20]	auto[1]	auto[0]	auto[1]	104655	1			T26	3		T21	1		T12	1
all_values[20]	auto[1]	auto[1]	auto[1]	103704	1			T26	2		T21	4		T12	3
all_values[21]	auto[0]	auto[0]	auto[0]	3089439	1			T23	4		T24	3		T25	1
all_values[21]	auto[0]	auto[0]	auto[1]	7392408	1			T23	1		T24	3		T26	2
all_values[21]	auto[0]	auto[1]	auto[0]	759274	1			T23	1		T25	2		T26	9
all_values[21]	auto[0]	auto[1]	auto[1]	7420785	1			T23	1		T25	13		T26	2
all_values[21]	auto[1]	auto[0]	auto[1]	104373	1			T12	3		T14	3		T16	2
all_values[21]	auto[1]	auto[1]	auto[1]	104048	1			T26	3		T21	6		T12	2
all_values[22]	auto[0]	auto[0]	auto[0]	3084984	1			T23	4		T24	4		T25	1
all_values[22]	auto[0]	auto[0]	auto[1]	7399939	1			T23	2		T24	2		T26	5
all_values[22]	auto[0]	auto[1]	auto[0]	770550	1			T23	1		T25	1		T26	3
all_values[22]	auto[0]	auto[1]	auto[1]	7406885	1			T25	14		T26	2		T28	7
all_values[22]	auto[1]	auto[0]	auto[1]	104432	1			T21	1		T12	2		T16	1
all_values[22]	auto[1]	auto[1]	auto[1]	103537	1			T26	2		T21	3		T12	2
all_values[23]	auto[0]	auto[0]	auto[0]	3088130	1			T23	6		T24	1		T25	1
all_values[23]	auto[0]	auto[0]	auto[1]	7416246	1			T23	1		T26	2		T21	1
all_values[23]	auto[0]	auto[1]	auto[0]	768144	1			T24	5		T25	15		T26	1
all_values[23]	auto[0]	auto[1]	auto[1]	7389887	1			T26	6		T21	7		T1	2
all_values[23]	auto[1]	auto[0]	auto[1]	104207	1			T26	4		T21	1		T14	3
all_values[23]	auto[1]	auto[1]	auto[1]	103713	1			T26	2		T21	4		T12	5
all_values[24]	auto[0]	auto[0]	auto[0]	3080971	1			T23	4		T24	1		T25	1
all_values[24]	auto[0]	auto[0]	auto[1]	7435485	1			T23	1		T24	2		T25	15
all_values[24]	auto[0]	auto[1]	auto[0]	760457	1			T24	1		T26	6		T21	5
all_values[24]	auto[0]	auto[1]	auto[1]	7385766	1			T23	2		T24	2		T26	6
all_values[24]	auto[1]	auto[0]	auto[1]	104328	1			T21	3		T12	3		T14	4
all_values[24]	auto[1]	auto[1]	auto[1]	103320	1			T26	2		T21	1		T12	1
all_values[25]	auto[0]	auto[0]	auto[0]	3100005	1			T23	4		T24	1		T25	1
all_values[25]	auto[0]	auto[0]	auto[1]	7377791	1			T23	3		T24	5		T25	15
all_values[25]	auto[0]	auto[1]	auto[0]	768721	1			T26	2		T21	9		T12	11
all_values[25]	auto[0]	auto[1]	auto[1]	7414947	1			T26	10		T28	7		T21	6
all_values[25]	auto[1]	auto[0]	auto[1]	104267	1			T26	2		T21	3		T12	1
all_values[25]	auto[1]	auto[1]	auto[1]	104596	1			T26	2		T21	3		T12	1
all_values[26]	auto[0]	auto[0]	auto[0]	3086877	1			T23	5		T24	3		T25	1
all_values[26]	auto[0]	auto[0]	auto[1]	7415448	1			T23	1		T25	15		T26	5
all_values[26]	auto[0]	auto[1]	auto[0]	753510	1			T23	1		T24	3		T26	3
all_values[26]	auto[0]	auto[1]	auto[1]	7405895	1			T26	4		T28	7		T11	1
all_values[26]	auto[1]	auto[0]	auto[1]	104066	1			T26	3		T21	2		T16	1
all_values[26]	auto[1]	auto[1]	auto[1]	104531	1			T26	2		T12	1		T14	5
all_values[27]	auto[0]	auto[0]	auto[0]	3084361	1			T23	4		T24	1		T25	16
all_values[27]	auto[0]	auto[0]	auto[1]	7401399	1			T23	1		T24	3		T26	4
all_values[27]	auto[0]	auto[1]	auto[0]	763212	1			T23	2		T26	3		T28	7
all_values[27]	auto[0]	auto[1]	auto[1]	7412863	1			T24	2		T26	4		T21	2
all_values[27]	auto[1]	auto[0]	auto[1]	104374	1			T26	3		T21	2		T12	4
all_values[27]	auto[1]	auto[1]	auto[1]	104118	1			T26	2		T21	2		T14	1
all_values[28]	auto[0]	auto[0]	auto[0]	3089622	1			T23	5		T24	4		T25	1
all_values[28]	auto[0]	auto[0]	auto[1]	7410836	1			T23	1		T26	8		T21	2
all_values[28]	auto[0]	auto[1]	auto[0]	765168	1			T25	11		T26	1		T28	1
all_values[28]	auto[0]	auto[1]	auto[1]	7396588	1			T23	1		T24	2		T25	4
all_values[28]	auto[1]	auto[0]	auto[1]	103928	1			T26	4		T21	2		T14	1
all_values[28]	auto[1]	auto[1]	auto[1]	104185	1			T21	3		T12	3		T14	3
all_values[29]	auto[0]	auto[0]	auto[0]	3084350	1			T23	5		T24	3		T25	1
all_values[29]	auto[0]	auto[0]	auto[1]	7415655	1			T23	1		T24	1		T28	7
all_values[29]	auto[0]	auto[1]	auto[0]	757683	1			T23	1		T25	12		T26	11
all_values[29]	auto[0]	auto[1]	auto[1]	7404862	1			T24	2		T25	3		T21	2
all_values[29]	auto[1]	auto[0]	auto[1]	103937	1			T26	1		T21	4		T12	1
all_values[29]	auto[1]	auto[1]	auto[1]	103840	1			T12	3		T14	2		T16	2
all_values[30]	auto[0]	auto[0]	auto[0]	3088454	1			T23	5		T24	1		T25	16
all_values[30]	auto[0]	auto[0]	auto[1]	7412401	1			T23	2		T24	2		T28	6
all_values[30]	auto[0]	auto[1]	auto[0]	767811	1			T26	6		T21	7		T11	2
all_values[30]	auto[0]	auto[1]	auto[1]	7393516	1			T24	3		T26	6		T21	3
all_values[30]	auto[1]	auto[0]	auto[1]	104620	1			T12	1		T14	1		T16	1
all_values[30]	auto[1]	auto[1]	auto[1]	103525	1			T26	2		T21	5		T12	1
all_values[31]	auto[0]	auto[0]	auto[0]	3085410	1			T23	5		T24	1		T25	1
all_values[31]	auto[0]	auto[0]	auto[1]	7373472	1			T23	1		T24	5		T26	2
all_values[31]	auto[0]	auto[1]	auto[0]	762869	1			T25	15		T26	4		T28	1
all_values[31]	auto[0]	auto[1]	auto[1]	7439745	1			T23	1		T26	6		T28	6
all_values[31]	auto[1]	auto[0]	auto[1]	104613	1			T26	2		T21	2		T14	2
all_values[31]	auto[1]	auto[1]	auto[1]	104218	1			T26	4		T21	1		T12	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal