Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[1]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[2]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[3]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[4]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[5]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[6]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[7]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[8]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[9]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[10]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[11]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[12]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[13]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[14]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[15]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[16]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[17]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[18]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[19]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[20]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[21]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[22]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[23]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[24]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[25]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[26]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[27]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[28]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[29]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[30]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[31]	18566791	1			T23	7		T24	6		T25	16

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

365658675

1

T23

224

T24

192

T25

512

auto[1]

228478637

1

T41

1421

T42

3013

T43

4312

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

476369326

1

T23

224

T24

192

T25

512

auto[1]

117767986

1

T41

1908

T42

1817

T43

3457

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

441587537

1

T23

224

T24

192

T25

512

auto[1]

152549775

1

T41

1955

T42

1834

T43

3513

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	7054758	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4894182	1			T41	17		T42	71		T43	77
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1852197	1			T41	18		T42	18		T43	54
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2513418	1			T41	58		T42	37		T43	69
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	418851	1			T55	50		T95	137		T96	114
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1833385	1			T41	18		T42	42		T43	58
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	7047082	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4901833	1			T41	11		T42	60		T43	92
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1850405	1			T41	28		T42	41		T43	56
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2514595	1			T41	40		T42	16		T43	60
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	416491	1			T55	42		T95	178		T96	139
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1836385	1			T41	24		T42	36		T43	44
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	7056652	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4886405	1			T41	19		T42	63		T43	77
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1851948	1			T41	25		T42	31		T43	55
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2515949	1			T41	40		T42	26		T43	58
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	417864	1			T55	24		T95	142		T96	102
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1837973	1			T41	32		T42	30		T43	46
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	7057463	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4892284	1			T41	13		T42	67		T43	70
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1853016	1			T41	32		T42	43		T43	72
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2515844	1			T41	30		T42	22		T43	36
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	415453	1			T55	29		T95	192		T96	113
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1832731	1			T41	33		T42	22		T43	68
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	7050933	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4894140	1			T41	11		T42	71		T43	77
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1851787	1			T41	46		T42	32		T43	57
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2520617	1			T41	17		T42	23		T43	60
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	416691	1			T55	44		T95	137		T96	96
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1832623	1			T41	46		T42	28		T43	56
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	7049420	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4897976	1			T41	18		T42	65		T43	83
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1849506	1			T41	34		T42	20		T43	66
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2522029	1			T41	26		T42	30		T43	53
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	416031	1			T55	60		T95	148		T96	128
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1831829	1			T41	26		T42	29		T43	42
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	7047315	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4893483	1			T41	17		T42	68		T43	78
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1851326	1			T41	30		T42	23		T43	42
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2516955	1			T41	18		T42	38		T43	52
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	418260	1			T55	54		T95	176		T96	130
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1839452	1			T41	38		T42	14		T43	51
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	7059743	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4898064	1			T41	10		T42	67		T43	84
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1852172	1			T41	48		T42	30		T43	60
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2514935	1			T41	18		T42	26		T43	67
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	416491	1			T55	36		T95	126		T96	122
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1825386	1			T41	25		T42	26		T43	64
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	7072632	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4878143	1			T41	17		T42	61		T43	85
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1852262	1			T41	22		T42	33		T43	53
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2511395	1			T41	33		T42	20		T43	60
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	418896	1			T55	40		T95	164		T96	110
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1833463	1			T41	46		T42	32		T43	56
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	7054214	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4891194	1			T41	17		T42	71		T43	80
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1850850	1			T41	40		T42	31		T43	52
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2517164	1			T41	34		T42	18		T43	60
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	416371	1			T55	40		T95	122		T96	86
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1836998	1			T41	29		T42	30		T43	44
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	7051056	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4889824	1			T41	20		T42	76		T43	77
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1848456	1			T41	32		T42	21		T43	39
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2518942	1			T41	44		T42	32		T43	70
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	418734	1			T55	32		T95	151		T96	142
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1839779	1			T41	24		T42	20		T43	34
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	7051103	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4887511	1			T41	12		T42	69		T43	98
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1855291	1			T41	27		T42	22		T43	45
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2514225	1			T41	38		T42	44		T43	84
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	420038	1			T55	32		T95	152		T96	130
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1838623	1			T41	22		T42	19		T43	68
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	7065400	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4882312	1			T41	15		T42	61		T43	86
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1853526	1			T41	17		T42	27		T43	44
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2508388	1			T41	28		T42	38		T43	55
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	419906	1			T55	39		T95	182		T96	126
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1837259	1			T41	36		T42	26		T43	64
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	7058541	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4887840	1			T41	13		T42	74		T43	81
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1853245	1			T41	30		T42	26		T43	77
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2517392	1			T41	30		T42	36		T43	40
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	415056	1			T55	53		T95	176		T96	122
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1834717	1			T41	30		T42	23		T43	68
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	7061992	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4884115	1			T41	15		T42	68		T43	79
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1851122	1			T41	14		T42	20		T43	64
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2516722	1			T41	37		T42	27		T43	55
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	415765	1			T55	20		T95	126		T96	124
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1837075	1			T41	42		T42	16		T43	52
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	7054328	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4894278	1			T41	12		T42	67		T43	90
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1856044	1			T41	22		T42	40		T43	70
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2514122	1			T41	42		T42	31		T43	60
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	416880	1			T55	14		T95	156		T96	149
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1831139	1			T41	26		T42	28		T43	35
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	7062150	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4888558	1			T41	13		T42	59		T43	75
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1844306	1			T41	27		T42	22		T43	59
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2524621	1			T41	30		T42	37		T43	58
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	418745	1			T55	48		T95	151		T96	128
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1828411	1			T41	34		T42	18		T43	50
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	7065953	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4901469	1			T41	17		T42	68		T43	86
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1846788	1			T41	36		T42	30		T43	49
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2508438	1			T41	24		T42	33		T43	64
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	415846	1			T55	30		T95	130		T96	120
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1828297	1			T41	24		T42	18		T43	68
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	7047611	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4901803	1			T41	12		T42	64		T43	78
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1845338	1			T41	40		T42	23		T43	54
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2529278	1			T41	24		T42	34		T43	49
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	417498	1			T55	34		T95	103		T96	84
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1825263	1			T41	16		T42	26		T43	50
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	7053623	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4899328	1			T41	14		T42	65		T43	84
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1845439	1			T41	38		T42	34		T43	74
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2524576	1			T41	34		T42	22		T43	46
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	417329	1			T55	40		T95	117		T96	143
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1826496	1			T41	14		T42	22		T43	30
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	7064518	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4884279	1			T41	10		T42	69		T43	80
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1847384	1			T41	35		T42	8		T43	32
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2523482	1			T41	26		T42	54		T43	58
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	418245	1			T55	36		T95	139		T96	152
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1828883	1			T41	34		T42	37		T43	69
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	7054009	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4892113	1			T41	10		T42	58		T43	79
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1842787	1			T41	32		T42	29		T43	56
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2525601	1			T41	23		T42	16		T43	54
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	421147	1			T55	39		T95	143		T96	120
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1831134	1			T41	20		T42	44		T43	53
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	7068671	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4886467	1			T41	14		T42	69		T43	80
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1847450	1			T41	30		T42	46		T43	50
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2516149	1			T41	33		T42	22		T43	42
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	418043	1			T55	36		T95	153		T96	158
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1830011	1			T41	30		T42	30		T43	70
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	7059023	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4897568	1			T41	14		T42	61		T43	73
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1843296	1			T41	45		T42	32		T43	66
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2521046	1			T41	32		T42	22		T43	48
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	416915	1			T55	39		T95	125		T96	117
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1828943	1			T41	12		T42	37		T43	43
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	7060613	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4899070	1			T41	17		T42	66		T43	70
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1848167	1			T41	32		T42	24		T43	44
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2518071	1			T41	28		T42	54		T43	71
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	417415	1			T55	30		T95	138		T96	128
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1823455	1			T41	44		T42	17		T43	44
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	7073338	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4883062	1			T41	15		T42	63		T43	81
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1847942	1			T41	27		T42	26		T43	38
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2519595	1			T41	42		T42	24		T43	41
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	419267	1			T55	34		T95	122		T96	144
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1823587	1			T41	18		T42	35		T43	62
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	7069863	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4889842	1			T41	15		T42	68		T43	80
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1844111	1			T41	24		T42	37		T43	48
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2516039	1			T41	24		T42	20		T43	52
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	418204	1			T55	34		T95	146		T96	152
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1828732	1			T41	40		T42	40		T43	52
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	7066014	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4887624	1			T41	14		T42	67		T43	71
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1854701	1			T41	32		T42	40		T43	32
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2515203	1			T41	24		T42	27		T43	54
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	416319	1			T55	54		T95	172		T96	128
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1826930	1			T41	36		T42	16		T43	65
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	7069076	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4891412	1			T41	13		T42	60		T43	73
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1844923	1			T41	20		T42	30		T43	57
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2519606	1			T41	32		T42	22		T43	64
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	417037	1			T55	48		T95	164		T96	144
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1824737	1			T41	36		T42	22		T43	48
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	7075094	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4874107	1			T41	13		T42	66		T43	85
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1843284	1			T41	21		T42	23		T43	50
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2524368	1			T41	24		T42	38		T43	49
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	420539	1			T55	38		T95	144		T96	122
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1829399	1			T41	40		T42	34		T43	54
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	7062790	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4889987	1			T41	17		T42	70		T43	87
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1840988	1			T41	22		T42	39		T43	59
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2528595	1			T41	38		T42	22		T43	54
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	417019	1			T55	35		T95	150		T96	86
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1827412	1			T41	34		T42	38		T43	38
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	7060698	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4893280	1			T41	16		T42	68		T43	88
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1848251	1			T41	22		T42	23		T43	55
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2517331	1			T41	24		T42	30		T43	42
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	418060	1			T55	28		T95	146		T96	100
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1829171	1			T41	31		T42	38		T43	82

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal