Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[1]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[2]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[3]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[4]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[5]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[6]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[7]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[8]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[9]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[10]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[11]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[12]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[13]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[14]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[15]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[16]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[17]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[18]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[19]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[20]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[21]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[22]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[23]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[24]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[25]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[26]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[27]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[28]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[29]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[30]	18566791	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[31]	18566791	1			T23	7		T24	6		T25	16

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

365658675

1

T23

224

T24

192

T25

512

auto[1]

228478637

1

T41

1421

T42

3013

T43

4312

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

365649899

1

T23

194

T24

161

T25

389

auto[1]

228487413

1

T23

30

T24

31

T25

123

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	11091565	1			T23	6		T24	5		T25	10
bins_for_gpio_bits[0]	auto[0]	auto[1]	328529	1			T41	4		T42	9		T43	18
bins_for_gpio_bits[0]	auto[1]	auto[0]	328808	1			T23	1		T24	1		T25	6
bins_for_gpio_bits[0]	auto[1]	auto[1]	6817889	1			T41	31		T42	104		T43	117
bins_for_gpio_bits[1]	auto[0]	auto[0]	11083702	1			T23	7		T24	6		T25	12
bins_for_gpio_bits[1]	auto[0]	auto[1]	328124	1			T41	9		T42	10		T43	11
bins_for_gpio_bits[1]	auto[1]	auto[0]	328380	1			T25	4		T28	4		T11	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	6826585	1			T41	26		T42	86		T43	125
bins_for_gpio_bits[2]	auto[0]	auto[0]	11095470	1			T23	4		T24	4		T25	16
bins_for_gpio_bits[2]	auto[0]	auto[1]	328767	1			T41	8		T42	10		T43	13
bins_for_gpio_bits[2]	auto[1]	auto[0]	329079	1			T23	3		T24	2		T27	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	6813475	1			T41	43		T42	83		T43	110
bins_for_gpio_bits[3]	auto[0]	auto[0]	11097329	1			T23	7		T24	6		T25	6
bins_for_gpio_bits[3]	auto[0]	auto[1]	328688	1			T41	9		T42	8		T43	17
bins_for_gpio_bits[3]	auto[1]	auto[0]	328994	1			T25	10		T28	4		T1	2
bins_for_gpio_bits[3]	auto[1]	auto[1]	6811780	1			T41	37		T42	81		T43	121
bins_for_gpio_bits[4]	auto[0]	auto[0]	11094100	1			T23	7		T24	5		T25	5
bins_for_gpio_bits[4]	auto[0]	auto[1]	328982	1			T41	9		T42	6		T43	13
bins_for_gpio_bits[4]	auto[1]	auto[0]	329237	1			T24	1		T25	11		T27	1
bins_for_gpio_bits[4]	auto[1]	auto[1]	6814472	1			T41	48		T42	93		T43	120
bins_for_gpio_bits[5]	auto[0]	auto[0]	11092556	1			T23	6		T24	6		T25	7
bins_for_gpio_bits[5]	auto[0]	auto[1]	328106	1			T41	9		T42	7		T43	11
bins_for_gpio_bits[5]	auto[1]	auto[0]	328399	1			T23	1		T25	9		T28	9
bins_for_gpio_bits[5]	auto[1]	auto[1]	6817730	1			T41	35		T42	87		T43	114
bins_for_gpio_bits[6]	auto[0]	auto[0]	11086596	1			T23	7		T24	6		T25	13
bins_for_gpio_bits[6]	auto[0]	auto[1]	328692	1			T41	5		T42	4		T43	11
bins_for_gpio_bits[6]	auto[1]	auto[0]	329000	1			T25	3		T27	1		T28	9
bins_for_gpio_bits[6]	auto[1]	auto[1]	6822503	1			T41	50		T42	78		T43	118
bins_for_gpio_bits[7]	auto[0]	auto[0]	11099417	1			T23	6		T24	6		T25	15
bins_for_gpio_bits[7]	auto[0]	auto[1]	327163	1			T41	7		T42	7		T43	13
bins_for_gpio_bits[7]	auto[1]	auto[0]	327433	1			T23	1		T25	1		T13	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	6812778	1			T41	28		T42	86		T43	135
bins_for_gpio_bits[8]	auto[0]	auto[0]	11108491	1			T23	7		T24	3		T25	16
bins_for_gpio_bits[8]	auto[0]	auto[1]	327507	1			T41	10		T42	5		T43	13
bins_for_gpio_bits[8]	auto[1]	auto[0]	327798	1			T24	3		T28	3		T11	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	6802995	1			T41	53		T42	88		T43	128
bins_for_gpio_bits[9]	auto[0]	auto[0]	11093825	1			T23	7		T24	6		T25	9
bins_for_gpio_bits[9]	auto[0]	auto[1]	328125	1			T41	10		T42	5		T43	14
bins_for_gpio_bits[9]	auto[1]	auto[0]	328403	1			T25	7		T1	2		T18	9
bins_for_gpio_bits[9]	auto[1]	auto[1]	6816438	1			T41	36		T42	96		T43	110
bins_for_gpio_bits[10]	auto[0]	auto[0]	11089763	1			T23	5		T24	6		T25	14
bins_for_gpio_bits[10]	auto[0]	auto[1]	328407	1			T41	8		T42	7		T43	12
bins_for_gpio_bits[10]	auto[1]	auto[0]	328691	1			T23	2		T25	2		T28	10
bins_for_gpio_bits[10]	auto[1]	auto[1]	6819930	1			T41	36		T42	89		T43	99
bins_for_gpio_bits[11]	auto[0]	auto[0]	11091628	1			T23	6		T24	6		T25	16
bins_for_gpio_bits[11]	auto[0]	auto[1]	328696	1			T41	7		T42	7		T43	16
bins_for_gpio_bits[11]	auto[1]	auto[0]	328991	1			T23	1		T1	4		T15	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	6817476	1			T41	27		T42	81		T43	150
bins_for_gpio_bits[12]	auto[0]	auto[0]	11099019	1			T23	6		T24	4		T25	12
bins_for_gpio_bits[12]	auto[0]	auto[1]	328072	1			T41	6		T42	8		T43	14
bins_for_gpio_bits[12]	auto[1]	auto[0]	328295	1			T23	1		T24	2		T25	4
bins_for_gpio_bits[12]	auto[1]	auto[1]	6811405	1			T41	45		T42	79		T43	136
bins_for_gpio_bits[13]	auto[0]	auto[0]	11100369	1			T23	4		T24	5		T25	15
bins_for_gpio_bits[13]	auto[0]	auto[1]	328531	1			T41	7		T42	4		T43	14
bins_for_gpio_bits[13]	auto[1]	auto[0]	328809	1			T23	3		T24	1		T25	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	6809082	1			T41	36		T42	93		T43	135
bins_for_gpio_bits[14]	auto[0]	auto[0]	11100937	1			T23	6		T24	6		T25	10
bins_for_gpio_bits[14]	auto[0]	auto[1]	328609	1			T41	9		T42	4		T43	16
bins_for_gpio_bits[14]	auto[1]	auto[0]	328899	1			T23	1		T25	6		T27	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	6808346	1			T41	48		T42	80		T43	115
bins_for_gpio_bits[15]	auto[0]	auto[0]	11096206	1			T23	6		T24	6		T25	12
bins_for_gpio_bits[15]	auto[0]	auto[1]	328053	1			T41	7		T42	7		T43	13
bins_for_gpio_bits[15]	auto[1]	auto[0]	328288	1			T23	1		T25	4		T13	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	6814244	1			T41	31		T42	88		T43	112
bins_for_gpio_bits[16]	auto[0]	auto[0]	11102647	1			T23	7		T24	4		T25	9
bins_for_gpio_bits[16]	auto[0]	auto[1]	328174	1			T41	7		T42	5		T43	15
bins_for_gpio_bits[16]	auto[1]	auto[0]	328430	1			T24	2		T25	7		T28	3
bins_for_gpio_bits[16]	auto[1]	auto[1]	6807540	1			T41	40		T42	72		T43	110
bins_for_gpio_bits[17]	auto[0]	auto[0]	11092765	1			T23	6		T24	6		T25	16
bins_for_gpio_bits[17]	auto[0]	auto[1]	328127	1			T41	9		T42	6		T43	13
bins_for_gpio_bits[17]	auto[1]	auto[0]	328414	1			T23	1		T28	6		T1	2
bins_for_gpio_bits[17]	auto[1]	auto[1]	6817485	1			T41	32		T42	80		T43	141
bins_for_gpio_bits[18]	auto[0]	auto[0]	11093285	1			T23	6		T24	4		T25	13
bins_for_gpio_bits[18]	auto[0]	auto[1]	328674	1			T41	6		T42	8		T43	15
bins_for_gpio_bits[18]	auto[1]	auto[0]	328942	1			T23	1		T24	2		T25	3
bins_for_gpio_bits[18]	auto[1]	auto[1]	6815890	1			T41	22		T42	82		T43	113
bins_for_gpio_bits[19]	auto[0]	auto[0]	11094967	1			T23	5		T24	2		T25	14
bins_for_gpio_bits[19]	auto[0]	auto[1]	328399	1			T41	6		T42	7		T43	9
bins_for_gpio_bits[19]	auto[1]	auto[0]	328671	1			T23	2		T24	4		T25	2
bins_for_gpio_bits[19]	auto[1]	auto[1]	6814754	1			T41	22		T42	80		T43	105
bins_for_gpio_bits[20]	auto[0]	auto[0]	11106158	1			T23	7		T24	5		T25	14
bins_for_gpio_bits[20]	auto[0]	auto[1]	328945	1			T41	10		T42	9		T43	16
bins_for_gpio_bits[20]	auto[1]	auto[0]	329226	1			T24	1		T25	2		T27	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	6802462	1			T41	34		T42	97		T43	133
bins_for_gpio_bits[21]	auto[0]	auto[0]	11093771	1			T23	6		T24	5		T25	9
bins_for_gpio_bits[21]	auto[0]	auto[1]	328346	1			T41	7		T42	6		T43	13
bins_for_gpio_bits[21]	auto[1]	auto[0]	328626	1			T23	1		T24	1		T25	7
bins_for_gpio_bits[21]	auto[1]	auto[1]	6816048	1			T41	23		T42	96		T43	119
bins_for_gpio_bits[22]	auto[0]	auto[0]	11103460	1			T23	7		T24	3		T25	5
bins_for_gpio_bits[22]	auto[0]	auto[1]	328517	1			T41	9		T42	7		T43	15
bins_for_gpio_bits[22]	auto[1]	auto[0]	328810	1			T24	3		T25	11		T27	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	6806004	1			T41	35		T42	92		T43	135
bins_for_gpio_bits[23]	auto[0]	auto[0]	11095016	1			T23	7		T24	6		T25	16
bins_for_gpio_bits[23]	auto[0]	auto[1]	328116	1			T41	5		T42	8		T43	11
bins_for_gpio_bits[23]	auto[1]	auto[0]	328349	1			T27	1		T28	6		T1	3
bins_for_gpio_bits[23]	auto[1]	auto[1]	6815310	1			T41	21		T42	90		T43	105
bins_for_gpio_bits[24]	auto[0]	auto[0]	11098409	1			T23	5		T24	4		T25	10
bins_for_gpio_bits[24]	auto[0]	auto[1]	328197	1			T41	8		T42	6		T43	14
bins_for_gpio_bits[24]	auto[1]	auto[0]	328442	1			T23	2		T24	2		T25	6
bins_for_gpio_bits[24]	auto[1]	auto[1]	6811743	1			T41	53		T42	77		T43	100
bins_for_gpio_bits[25]	auto[0]	auto[0]	11113012	1			T23	6		T24	6		T25	14
bins_for_gpio_bits[25]	auto[0]	auto[1]	327578	1			T41	6		T42	8		T43	12
bins_for_gpio_bits[25]	auto[1]	auto[0]	327863	1			T23	1		T25	2		T27	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	6798338	1			T41	27		T42	90		T43	131
bins_for_gpio_bits[26]	auto[0]	auto[0]	11101942	1			T23	6		T24	4		T25	10
bins_for_gpio_bits[26]	auto[0]	auto[1]	327802	1			T41	9		T42	9		T43	12
bins_for_gpio_bits[26]	auto[1]	auto[0]	328071	1			T23	1		T24	2		T25	6
bins_for_gpio_bits[26]	auto[1]	auto[1]	6808976	1			T41	46		T42	99		T43	120
bins_for_gpio_bits[27]	auto[0]	auto[0]	11107377	1			T23	7		T24	6		T25	12
bins_for_gpio_bits[27]	auto[0]	auto[1]	328242	1			T41	9		T42	6		T43	12
bins_for_gpio_bits[27]	auto[1]	auto[0]	328541	1			T25	4		T28	2		T1	4
bins_for_gpio_bits[27]	auto[1]	auto[1]	6802631	1			T41	41		T42	77		T43	124
bins_for_gpio_bits[28]	auto[0]	auto[0]	11105629	1			T23	4		T24	6		T25	13
bins_for_gpio_bits[28]	auto[0]	auto[1]	327699	1			T41	9		T42	5		T43	12
bins_for_gpio_bits[28]	auto[1]	auto[0]	327976	1			T23	3		T25	3		T1	6
bins_for_gpio_bits[28]	auto[1]	auto[1]	6805487	1			T41	40		T42	77		T43	109
bins_for_gpio_bits[29]	auto[0]	auto[0]	11113682	1			T23	6		T24	5		T25	14
bins_for_gpio_bits[29]	auto[0]	auto[1]	328807	1			T41	6		T42	10		T43	13
bins_for_gpio_bits[29]	auto[1]	auto[0]	329064	1			T23	1		T24	1		T25	2
bins_for_gpio_bits[29]	auto[1]	auto[1]	6795238	1			T41	47		T42	90		T43	126
bins_for_gpio_bits[30]	auto[0]	auto[0]	11104018	1			T23	6		T24	4		T25	16
bins_for_gpio_bits[30]	auto[0]	auto[1]	328085	1			T41	8		T42	9		T43	13
bins_for_gpio_bits[30]	auto[1]	auto[0]	328355	1			T23	1		T24	2		T1	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	6806333	1			T41	43		T42	99		T43	112
bins_for_gpio_bits[31]	auto[0]	auto[0]	11096948	1			T23	6		T24	5		T25	16
bins_for_gpio_bits[31]	auto[0]	auto[1]	329081	1			T41	7		T42	7		T43	15
bins_for_gpio_bits[31]	auto[1]	auto[0]	329332	1			T23	1		T24	1		T27	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	6811430	1			T41	40		T42	99		T43	155