Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10573305 |
1 |
|
|
T23 |
7 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
8297022 |
1 |
|
|
T24 |
5 |
|
T25 |
15 |
|
T26 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17785517 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
12 |
| auto[1] |
1084810 |
1 |
|
|
T25 |
4 |
|
T28 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10592178 |
1 |
|
|
T23 |
6 |
|
T24 |
1 |
|
T25 |
4 |
| auto[1] |
8278149 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3581805 |
1 |
|
|
T23 |
1 |
|
T13 |
1 |
|
T18 |
6 |
| auto[1] |
auto[0] |
auto[1] |
539603 |
1 |
|
|
T92 |
205 |
|
T8 |
10356 |
|
T9 |
21 |
| auto[1] |
auto[1] |
auto[0] |
3611534 |
1 |
|
|
T24 |
5 |
|
T25 |
8 |
|
T28 |
6 |
| auto[1] |
auto[1] |
auto[1] |
545207 |
1 |
|
|
T25 |
4 |
|
T28 |
1 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10602910 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8267417 |
1 |
|
|
T23 |
1 |
|
T25 |
15 |
|
T26 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17787237 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1083090 |
1 |
|
|
T15 |
2 |
|
T92 |
315 |
|
T8 |
21480 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10592402 |
1 |
|
|
T23 |
7 |
|
T24 |
4 |
|
T25 |
16 |
| auto[1] |
8277925 |
1 |
|
|
T24 |
2 |
|
T1 |
2 |
|
T11 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3589570 |
1 |
|
|
T24 |
2 |
|
T1 |
2 |
|
T15 |
6 |
| auto[1] |
auto[0] |
auto[1] |
539749 |
1 |
|
|
T15 |
2 |
|
T92 |
205 |
|
T8 |
10548 |
| auto[1] |
auto[1] |
auto[0] |
3605265 |
1 |
|
|
T11 |
2 |
|
T15 |
5 |
|
T18 |
2 |
| auto[1] |
auto[1] |
auto[1] |
543341 |
1 |
|
|
T92 |
110 |
|
T8 |
10932 |
|
T9 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10594524 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8275803 |
1 |
|
|
T23 |
2 |
|
T26 |
13 |
|
T28 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17787499 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1082828 |
1 |
|
|
T28 |
1 |
|
T72 |
1 |
|
T92 |
358 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10602712 |
1 |
|
|
T23 |
7 |
|
T24 |
3 |
|
T25 |
16 |
| auto[1] |
8267615 |
1 |
|
|
T24 |
3 |
|
T28 |
7 |
|
T1 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3588816 |
1 |
|
|
T24 |
3 |
|
T1 |
6 |
|
T18 |
7 |
| auto[1] |
auto[0] |
auto[1] |
540261 |
1 |
|
|
T72 |
1 |
|
T92 |
212 |
|
T8 |
10913 |
| auto[1] |
auto[1] |
auto[0] |
3595971 |
1 |
|
|
T28 |
6 |
|
T13 |
1 |
|
T18 |
3 |
| auto[1] |
auto[1] |
auto[1] |
542567 |
1 |
|
|
T28 |
1 |
|
T92 |
146 |
|
T8 |
9922 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10601534 |
1 |
|
|
T23 |
7 |
|
T24 |
1 |
|
T25 |
16 |
| auto[1] |
8268793 |
1 |
|
|
T24 |
5 |
|
T26 |
9 |
|
T21 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17789530 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1080797 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T87 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10619491 |
1 |
|
|
T23 |
7 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
8250836 |
1 |
|
|
T24 |
2 |
|
T25 |
12 |
|
T28 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3579806 |
1 |
|
|
T25 |
12 |
|
T28 |
7 |
|
T1 |
5 |
| auto[1] |
auto[0] |
auto[1] |
538727 |
1 |
|
|
T1 |
1 |
|
T87 |
3 |
|
T92 |
128 |
| auto[1] |
auto[1] |
auto[0] |
3590233 |
1 |
|
|
T24 |
2 |
|
T15 |
12 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[1] |
542070 |
1 |
|
|
T15 |
1 |
|
T92 |
217 |
|
T8 |
10372 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10582595 |
1 |
|
|
T23 |
6 |
|
T24 |
1 |
|
T25 |
16 |
| auto[1] |
8287732 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T26 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17784879 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
15 |
| auto[1] |
1085448 |
1 |
|
|
T24 |
1 |
|
T25 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10590053 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
4 |
| auto[1] |
8280274 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3585359 |
1 |
|
|
T23 |
1 |
|
T25 |
11 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
540783 |
1 |
|
|
T25 |
1 |
|
T92 |
138 |
|
T8 |
10415 |
| auto[1] |
auto[1] |
auto[0] |
3609467 |
1 |
|
|
T24 |
2 |
|
T28 |
7 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[1] |
544665 |
1 |
|
|
T24 |
1 |
|
T1 |
1 |
|
T92 |
147 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10604381 |
1 |
|
|
T23 |
6 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
8265946 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17791342 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
15 |
| auto[1] |
1078985 |
1 |
|
|
T24 |
1 |
|
T25 |
1 |
|
T92 |
345 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10614075 |
1 |
|
|
T23 |
5 |
|
T24 |
3 |
|
T25 |
4 |
| auto[1] |
8256252 |
1 |
|
|
T23 |
2 |
|
T24 |
3 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3577705 |
1 |
|
|
T23 |
1 |
|
T11 |
1 |
|
T18 |
6 |
| auto[1] |
auto[0] |
auto[1] |
536512 |
1 |
|
|
T92 |
170 |
|
T8 |
10752 |
|
T9 |
24 |
| auto[1] |
auto[1] |
auto[0] |
3599562 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[1] |
542473 |
1 |
|
|
T24 |
1 |
|
T25 |
1 |
|
T92 |
175 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10596585 |
1 |
|
|
T23 |
7 |
|
T24 |
3 |
|
T25 |
1 |
| auto[1] |
8273742 |
1 |
|
|
T24 |
3 |
|
T25 |
15 |
|
T26 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17786424 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
14 |
| auto[1] |
1083903 |
1 |
|
|
T25 |
2 |
|
T28 |
1 |
|
T1 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10587880 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
4 |
| auto[1] |
8282447 |
1 |
|
|
T23 |
1 |
|
T25 |
12 |
|
T28 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3604885 |
1 |
|
|
T23 |
1 |
|
T28 |
6 |
|
T1 |
4 |
| auto[1] |
auto[0] |
auto[1] |
541858 |
1 |
|
|
T28 |
1 |
|
T1 |
2 |
|
T15 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3593659 |
1 |
|
|
T25 |
10 |
|
T13 |
1 |
|
T18 |
5 |
| auto[1] |
auto[1] |
auto[1] |
542045 |
1 |
|
|
T25 |
2 |
|
T92 |
207 |
|
T8 |
10973 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10564962 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8305365 |
1 |
|
|
T23 |
1 |
|
T26 |
7 |
|
T28 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17790651 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1079676 |
1 |
|
|
T92 |
365 |
|
T8 |
20579 |
|
T9 |
48 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10610332 |
1 |
|
|
T23 |
7 |
|
T24 |
1 |
|
T25 |
16 |
| auto[1] |
8259995 |
1 |
|
|
T24 |
5 |
|
T28 |
7 |
|
T1 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3552804 |
1 |
|
|
T24 |
5 |
|
T1 |
6 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
533559 |
1 |
|
|
T92 |
174 |
|
T8 |
10220 |
|
T9 |
25 |
| auto[1] |
auto[1] |
auto[0] |
3627515 |
1 |
|
|
T28 |
7 |
|
T1 |
2 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[1] |
546117 |
1 |
|
|
T92 |
191 |
|
T8 |
10359 |
|
T9 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10590338 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8279989 |
1 |
|
|
T23 |
2 |
|
T25 |
15 |
|
T26 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17787976 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1082351 |
1 |
|
|
T1 |
2 |
|
T72 |
1 |
|
T92 |
247 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10595115 |
1 |
|
|
T23 |
5 |
|
T24 |
4 |
|
T25 |
16 |
| auto[1] |
8275212 |
1 |
|
|
T23 |
2 |
|
T24 |
2 |
|
T1 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3601496 |
1 |
|
|
T24 |
2 |
|
T13 |
1 |
|
T18 |
7 |
| auto[1] |
auto[0] |
auto[1] |
541143 |
1 |
|
|
T92 |
126 |
|
T8 |
9814 |
|
T9 |
22 |
| auto[1] |
auto[1] |
auto[0] |
3591365 |
1 |
|
|
T23 |
2 |
|
T1 |
6 |
|
T18 |
5 |
| auto[1] |
auto[1] |
auto[1] |
541208 |
1 |
|
|
T1 |
2 |
|
T72 |
1 |
|
T92 |
121 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10644541 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8225786 |
1 |
|
|
T23 |
1 |
|
T26 |
8 |
|
T28 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17789230 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1081097 |
1 |
|
|
T72 |
1 |
|
T74 |
1 |
|
T92 |
332 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10603881 |
1 |
|
|
T23 |
6 |
|
T24 |
1 |
|
T25 |
4 |
| auto[1] |
8266446 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3613505 |
1 |
|
|
T24 |
5 |
|
T25 |
12 |
|
T18 |
9 |
| auto[1] |
auto[0] |
auto[1] |
544575 |
1 |
|
|
T72 |
1 |
|
T74 |
1 |
|
T92 |
170 |
| auto[1] |
auto[1] |
auto[0] |
3571844 |
1 |
|
|
T23 |
1 |
|
T13 |
1 |
|
T15 |
5 |
| auto[1] |
auto[1] |
auto[1] |
536522 |
1 |
|
|
T92 |
162 |
|
T8 |
10699 |
|
T9 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10591183 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
1 |
| auto[1] |
8279144 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17789334 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
15 |
| auto[1] |
1080993 |
1 |
|
|
T24 |
1 |
|
T25 |
1 |
|
T72 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10616875 |
1 |
|
|
T23 |
5 |
|
T24 |
3 |
|
T25 |
4 |
| auto[1] |
8253452 |
1 |
|
|
T23 |
2 |
|
T24 |
3 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3579333 |
1 |
|
|
T23 |
1 |
|
T28 |
7 |
|
T11 |
2 |
| auto[1] |
auto[0] |
auto[1] |
539674 |
1 |
|
|
T72 |
1 |
|
T92 |
156 |
|
T8 |
10176 |
| auto[1] |
auto[1] |
auto[0] |
3593126 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[1] |
541319 |
1 |
|
|
T24 |
1 |
|
T25 |
1 |
|
T92 |
98 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10578000 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
16 |
| auto[1] |
8292327 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T26 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17791140 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
15 |
| auto[1] |
1079187 |
1 |
|
|
T25 |
1 |
|
T1 |
1 |
|
T92 |
356 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10620727 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
4 |
| auto[1] |
8249600 |
1 |
|
|
T23 |
1 |
|
T25 |
12 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3579923 |
1 |
|
|
T25 |
11 |
|
T1 |
1 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
539092 |
1 |
|
|
T25 |
1 |
|
T1 |
1 |
|
T92 |
170 |
| auto[1] |
auto[1] |
auto[0] |
3590490 |
1 |
|
|
T23 |
1 |
|
T11 |
1 |
|
T18 |
6 |
| auto[1] |
auto[1] |
auto[1] |
540095 |
1 |
|
|
T92 |
186 |
|
T8 |
10346 |
|
T9 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10615654 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
1 |
| auto[1] |
8254673 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17785761 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1084566 |
1 |
|
|
T15 |
1 |
|
T87 |
2 |
|
T74 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10585752 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
4 |
| auto[1] |
8284575 |
1 |
|
|
T23 |
2 |
|
T25 |
12 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3597564 |
1 |
|
|
T23 |
1 |
|
T15 |
12 |
|
T18 |
7 |
| auto[1] |
auto[0] |
auto[1] |
541493 |
1 |
|
|
T15 |
1 |
|
T92 |
183 |
|
T8 |
10425 |
| auto[1] |
auto[1] |
auto[0] |
3602445 |
1 |
|
|
T23 |
1 |
|
T25 |
12 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
543073 |
1 |
|
|
T87 |
2 |
|
T74 |
1 |
|
T92 |
193 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10630327 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8240000 |
1 |
|
|
T23 |
1 |
|
T26 |
5 |
|
T21 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17786629 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
15 |
| auto[1] |
1083698 |
1 |
|
|
T24 |
1 |
|
T25 |
1 |
|
T1 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10589278 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
4 |
| auto[1] |
8281049 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3609853 |
1 |
|
|
T24 |
2 |
|
T25 |
11 |
|
T18 |
5 |
| auto[1] |
auto[0] |
auto[1] |
542978 |
1 |
|
|
T24 |
1 |
|
T25 |
1 |
|
T72 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3587498 |
1 |
|
|
T23 |
1 |
|
T1 |
6 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
540720 |
1 |
|
|
T1 |
2 |
|
T15 |
2 |
|
T92 |
151 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10586220 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8284107 |
1 |
|
|
T23 |
2 |
|
T25 |
15 |
|
T26 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17787590 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
16 |
| auto[1] |
1082737 |
1 |
|
|
T24 |
1 |
|
T1 |
1 |
|
T15 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10600512 |
1 |
|
|
T23 |
5 |
|
T24 |
4 |
|
T25 |
16 |
| auto[1] |
8269815 |
1 |
|
|
T23 |
2 |
|
T24 |
2 |
|
T1 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3579765 |
1 |
|
|
T24 |
1 |
|
T1 |
6 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
538284 |
1 |
|
|
T24 |
1 |
|
T15 |
2 |
|
T92 |
140 |
| auto[1] |
auto[1] |
auto[0] |
3607313 |
1 |
|
|
T23 |
2 |
|
T1 |
1 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[1] |
544453 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T87 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10589355 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8280972 |
1 |
|
|
T23 |
1 |
|
T25 |
15 |
|
T26 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17787727 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
13 |
| auto[1] |
1082600 |
1 |
|
|
T24 |
1 |
|
T25 |
3 |
|
T15 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10599554 |
1 |
|
|
T23 |
5 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
8270773 |
1 |
|
|
T23 |
2 |
|
T24 |
2 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3587095 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T1 |
2 |
| auto[1] |
auto[0] |
auto[1] |
540144 |
1 |
|
|
T24 |
1 |
|
T15 |
2 |
|
T87 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3601078 |
1 |
|
|
T23 |
1 |
|
T25 |
9 |
|
T28 |
7 |
| auto[1] |
auto[1] |
auto[1] |
542456 |
1 |
|
|
T25 |
3 |
|
T92 |
169 |
|
T8 |
10790 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10608583 |
1 |
|
|
T23 |
7 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
8261744 |
1 |
|
|
T24 |
5 |
|
T25 |
15 |
|
T26 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17784326 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1086001 |
1 |
|
|
T72 |
1 |
|
T92 |
212 |
|
T8 |
20896 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10568984 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
8301343 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3626441 |
1 |
|
|
T23 |
1 |
|
T28 |
7 |
|
T11 |
2 |
| auto[1] |
auto[0] |
auto[1] |
545850 |
1 |
|
|
T72 |
1 |
|
T92 |
110 |
|
T8 |
10353 |
| auto[1] |
auto[1] |
auto[0] |
3588901 |
1 |
|
|
T24 |
2 |
|
T25 |
12 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
540151 |
1 |
|
|
T92 |
102 |
|
T8 |
10543 |
|
T9 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10620784 |
1 |
|
|
T23 |
5 |
|
T24 |
3 |
|
T25 |
16 |
| auto[1] |
8249543 |
1 |
|
|
T23 |
2 |
|
T24 |
3 |
|
T26 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17787314 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
16 |
| auto[1] |
1083013 |
1 |
|
|
T24 |
1 |
|
T72 |
2 |
|
T92 |
395 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10604941 |
1 |
|
|
T23 |
6 |
|
T24 |
1 |
|
T25 |
16 |
| auto[1] |
8265386 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T28 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3608430 |
1 |
|
|
T24 |
1 |
|
T18 |
7 |
|
T72 |
4 |
| auto[1] |
auto[0] |
auto[1] |
544289 |
1 |
|
|
T24 |
1 |
|
T72 |
2 |
|
T92 |
204 |
| auto[1] |
auto[1] |
auto[0] |
3573943 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T28 |
7 |
| auto[1] |
auto[1] |
auto[1] |
538724 |
1 |
|
|
T92 |
191 |
|
T8 |
11441 |
|
T9 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10582063 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8288264 |
1 |
|
|
T26 |
14 |
|
T28 |
7 |
|
T21 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17790586 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1079741 |
1 |
|
|
T28 |
1 |
|
T15 |
1 |
|
T72 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10616797 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8253530 |
1 |
|
|
T28 |
7 |
|
T11 |
2 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3576608 |
1 |
|
|
T11 |
2 |
|
T13 |
1 |
|
T18 |
7 |
| auto[1] |
auto[0] |
auto[1] |
537893 |
1 |
|
|
T87 |
2 |
|
T92 |
172 |
|
T8 |
10741 |
| auto[1] |
auto[1] |
auto[0] |
3597181 |
1 |
|
|
T28 |
6 |
|
T15 |
4 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[1] |
541848 |
1 |
|
|
T28 |
1 |
|
T15 |
1 |
|
T72 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |