Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10643097 |
1 |
|
|
T23 |
7 |
|
T24 |
1 |
|
T25 |
16 |
| auto[1] |
8227230 |
1 |
|
|
T24 |
5 |
|
T26 |
10 |
|
T28 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17788916 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
12 |
| auto[1] |
1081411 |
1 |
|
|
T25 |
4 |
|
T15 |
1 |
|
T92 |
379 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10605695 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
8264632 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3619188 |
1 |
|
|
T23 |
1 |
|
T25 |
8 |
|
T1 |
6 |
| auto[1] |
auto[0] |
auto[1] |
545924 |
1 |
|
|
T25 |
4 |
|
T92 |
161 |
|
T8 |
10861 |
| auto[1] |
auto[1] |
auto[0] |
3564033 |
1 |
|
|
T24 |
2 |
|
T11 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
535487 |
1 |
|
|
T15 |
1 |
|
T92 |
218 |
|
T8 |
11279 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |