Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10569685 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
1 |
| auto[1] |
8300642 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17786274 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1084053 |
1 |
|
|
T92 |
340 |
|
T8 |
20881 |
|
T9 |
41 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10589377 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
16 |
| auto[1] |
8280950 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T28 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3586118 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T15 |
8 |
| auto[1] |
auto[0] |
auto[1] |
539787 |
1 |
|
|
T92 |
210 |
|
T8 |
10704 |
|
T9 |
23 |
| auto[1] |
auto[1] |
auto[0] |
3610779 |
1 |
|
|
T28 |
7 |
|
T1 |
2 |
|
T18 |
3 |
| auto[1] |
auto[1] |
auto[1] |
544266 |
1 |
|
|
T92 |
130 |
|
T8 |
10177 |
|
T9 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |