Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10603942 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
1 |
| auto[1] |
8266385 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17785897 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
16 |
| auto[1] |
1084430 |
1 |
|
|
T24 |
1 |
|
T72 |
1 |
|
T92 |
320 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10582388 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
16 |
| auto[1] |
8287939 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T28 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3612304 |
1 |
|
|
T28 |
7 |
|
T11 |
2 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
543046 |
1 |
|
|
T72 |
1 |
|
T92 |
193 |
|
T8 |
10622 |
| auto[1] |
auto[1] |
auto[0] |
3591205 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[1] |
541384 |
1 |
|
|
T24 |
1 |
|
T92 |
127 |
|
T8 |
11105 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |