Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10581811 |
1 |
|
|
T23 |
7 |
|
T24 |
3 |
|
T25 |
1 |
| auto[1] |
8288516 |
1 |
|
|
T24 |
3 |
|
T25 |
15 |
|
T26 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17793826 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
12 |
| auto[1] |
1076501 |
1 |
|
|
T25 |
4 |
|
T15 |
3 |
|
T87 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10630780 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
8239547 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3565913 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T28 |
7 |
| auto[1] |
auto[0] |
auto[1] |
535292 |
1 |
|
|
T15 |
3 |
|
T87 |
1 |
|
T92 |
195 |
| auto[1] |
auto[1] |
auto[0] |
3597133 |
1 |
|
|
T25 |
8 |
|
T1 |
6 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[1] |
541209 |
1 |
|
|
T25 |
4 |
|
T92 |
161 |
|
T8 |
10825 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |