Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10602910 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8267417 |
1 |
|
|
T23 |
1 |
|
T25 |
15 |
|
T26 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13932869 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
5 |
| auto[1] |
4937458 |
1 |
|
|
T23 |
2 |
|
T25 |
11 |
|
T1 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10637790 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8232537 |
1 |
|
|
T23 |
2 |
|
T25 |
15 |
|
T1 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1645782 |
1 |
|
|
T15 |
4 |
|
T18 |
1 |
|
T29 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2468659 |
1 |
|
|
T23 |
1 |
|
T1 |
2 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1649297 |
1 |
|
|
T25 |
4 |
|
T15 |
3 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2468799 |
1 |
|
|
T23 |
1 |
|
T25 |
11 |
|
T1 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10594524 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8275803 |
1 |
|
|
T23 |
2 |
|
T26 |
13 |
|
T28 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13934096 |
1 |
|
|
T23 |
7 |
|
T24 |
1 |
|
T25 |
3 |
| auto[1] |
4936231 |
1 |
|
|
T24 |
5 |
|
T25 |
13 |
|
T1 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10642810 |
1 |
|
|
T23 |
6 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
8227517 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T25 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1646132 |
1 |
|
|
T25 |
2 |
|
T18 |
1 |
|
T72 |
7 |
| auto[1] |
auto[0] |
auto[1] |
2458086 |
1 |
|
|
T24 |
5 |
|
T25 |
13 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1645154 |
1 |
|
|
T23 |
1 |
|
T28 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2478145 |
1 |
|
|
T1 |
2 |
|
T15 |
3 |
|
T18 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10601534 |
1 |
|
|
T23 |
7 |
|
T24 |
1 |
|
T25 |
16 |
| auto[1] |
8268793 |
1 |
|
|
T24 |
5 |
|
T26 |
9 |
|
T21 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13934487 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
4935840 |
1 |
|
|
T11 |
1 |
|
T15 |
8 |
|
T18 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10649930 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8220397 |
1 |
|
|
T11 |
1 |
|
T15 |
8 |
|
T18 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1643068 |
1 |
|
|
T18 |
1 |
|
T72 |
3 |
|
T3 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2464795 |
1 |
|
|
T11 |
1 |
|
T18 |
5 |
|
T72 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1641489 |
1 |
|
|
T18 |
1 |
|
T72 |
5 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2471045 |
1 |
|
|
T15 |
8 |
|
T18 |
5 |
|
T72 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10582595 |
1 |
|
|
T23 |
6 |
|
T24 |
1 |
|
T25 |
16 |
| auto[1] |
8287732 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T26 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13912480 |
1 |
|
|
T23 |
7 |
|
T24 |
4 |
|
T25 |
16 |
| auto[1] |
4957847 |
1 |
|
|
T24 |
2 |
|
T1 |
7 |
|
T13 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10605420 |
1 |
|
|
T23 |
7 |
|
T24 |
3 |
|
T25 |
16 |
| auto[1] |
8264907 |
1 |
|
|
T24 |
3 |
|
T1 |
8 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1647182 |
1 |
|
|
T18 |
1 |
|
T29 |
2 |
|
T3 |
3 |
| auto[1] |
auto[0] |
auto[1] |
2476103 |
1 |
|
|
T18 |
3 |
|
T29 |
4 |
|
T3 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1659878 |
1 |
|
|
T24 |
1 |
|
T1 |
1 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2481744 |
1 |
|
|
T24 |
2 |
|
T1 |
7 |
|
T13 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10604381 |
1 |
|
|
T23 |
6 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
8265946 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13923410 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
2 |
| auto[1] |
4946917 |
1 |
|
|
T25 |
14 |
|
T28 |
7 |
|
T11 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10621234 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8249093 |
1 |
|
|
T23 |
1 |
|
T25 |
15 |
|
T28 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1656432 |
1 |
|
|
T23 |
1 |
|
T18 |
1 |
|
T29 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2477353 |
1 |
|
|
T18 |
6 |
|
T29 |
5 |
|
T3 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1645744 |
1 |
|
|
T25 |
1 |
|
T18 |
2 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2469564 |
1 |
|
|
T25 |
14 |
|
T28 |
7 |
|
T11 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10596585 |
1 |
|
|
T23 |
7 |
|
T24 |
3 |
|
T25 |
1 |
| auto[1] |
8273742 |
1 |
|
|
T24 |
3 |
|
T25 |
15 |
|
T26 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13927437 |
1 |
|
|
T23 |
7 |
|
T24 |
4 |
|
T25 |
16 |
| auto[1] |
4942890 |
1 |
|
|
T24 |
2 |
|
T1 |
4 |
|
T15 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10630595 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
16 |
| auto[1] |
8239732 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T1 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1654408 |
1 |
|
|
T23 |
1 |
|
T1 |
4 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2483272 |
1 |
|
|
T24 |
2 |
|
T1 |
4 |
|
T15 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1642434 |
1 |
|
|
T18 |
2 |
|
T5 |
2 |
|
T34 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2459618 |
1 |
|
|
T72 |
6 |
|
T29 |
3 |
|
T3 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10564962 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8305365 |
1 |
|
|
T23 |
1 |
|
T26 |
7 |
|
T28 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13916321 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
4954006 |
1 |
|
|
T23 |
1 |
|
T1 |
1 |
|
T11 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10616051 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8254276 |
1 |
|
|
T23 |
2 |
|
T1 |
1 |
|
T11 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1636938 |
1 |
|
|
T23 |
1 |
|
T13 |
1 |
|
T72 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2453907 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T15 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1663332 |
1 |
|
|
T29 |
1 |
|
T3 |
2 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2500099 |
1 |
|
|
T23 |
1 |
|
T18 |
5 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10590338 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8279989 |
1 |
|
|
T23 |
2 |
|
T25 |
15 |
|
T26 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13922894 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
8 |
| auto[1] |
4947433 |
1 |
|
|
T23 |
2 |
|
T25 |
8 |
|
T28 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10626769 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8243558 |
1 |
|
|
T23 |
2 |
|
T25 |
15 |
|
T28 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1641992 |
1 |
|
|
T18 |
1 |
|
T29 |
1 |
|
T34 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2464804 |
1 |
|
|
T23 |
1 |
|
T18 |
4 |
|
T72 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1654133 |
1 |
|
|
T25 |
7 |
|
T1 |
6 |
|
T72 |
5 |
| auto[1] |
auto[1] |
auto[1] |
2482629 |
1 |
|
|
T23 |
1 |
|
T25 |
8 |
|
T28 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10644541 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8225786 |
1 |
|
|
T23 |
1 |
|
T26 |
8 |
|
T28 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13915861 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
1 |
| auto[1] |
4954466 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T25 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10610745 |
1 |
|
|
T23 |
5 |
|
T24 |
4 |
|
T25 |
1 |
| auto[1] |
8259582 |
1 |
|
|
T23 |
2 |
|
T24 |
2 |
|
T25 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1664438 |
1 |
|
|
T15 |
3 |
|
T18 |
1 |
|
T72 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2502850 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T25 |
15 |
| auto[1] |
auto[1] |
auto[0] |
1640678 |
1 |
|
|
T23 |
1 |
|
T18 |
1 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2451616 |
1 |
|
|
T1 |
1 |
|
T13 |
1 |
|
T18 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10591183 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
1 |
| auto[1] |
8279144 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13921626 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
4 |
| auto[1] |
4948701 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T25 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10629757 |
1 |
|
|
T23 |
6 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
8240570 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T25 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1645746 |
1 |
|
|
T11 |
1 |
|
T18 |
2 |
|
T72 |
5 |
| auto[1] |
auto[0] |
auto[1] |
2470207 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T28 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1646123 |
1 |
|
|
T24 |
2 |
|
T25 |
3 |
|
T18 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2478494 |
1 |
|
|
T24 |
1 |
|
T25 |
12 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10578000 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
16 |
| auto[1] |
8292327 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T26 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13935497 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
4934830 |
1 |
|
|
T11 |
1 |
|
T18 |
8 |
|
T72 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10645853 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8224474 |
1 |
|
|
T11 |
1 |
|
T13 |
1 |
|
T18 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1646249 |
1 |
|
|
T29 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2469007 |
1 |
|
|
T18 |
4 |
|
T72 |
6 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1643395 |
1 |
|
|
T13 |
1 |
|
T72 |
1 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2465823 |
1 |
|
|
T11 |
1 |
|
T18 |
4 |
|
T72 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10615654 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
1 |
| auto[1] |
8254673 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13908716 |
1 |
|
|
T23 |
7 |
|
T24 |
4 |
|
T25 |
16 |
| auto[1] |
4961611 |
1 |
|
|
T24 |
2 |
|
T28 |
6 |
|
T1 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10597055 |
1 |
|
|
T23 |
7 |
|
T24 |
3 |
|
T25 |
16 |
| auto[1] |
8273272 |
1 |
|
|
T24 |
3 |
|
T28 |
6 |
|
T1 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1656060 |
1 |
|
|
T1 |
2 |
|
T18 |
3 |
|
T29 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2479858 |
1 |
|
|
T28 |
6 |
|
T1 |
3 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1655601 |
1 |
|
|
T24 |
1 |
|
T1 |
2 |
|
T18 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2481753 |
1 |
|
|
T24 |
2 |
|
T18 |
1 |
|
T72 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10630327 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8240000 |
1 |
|
|
T23 |
1 |
|
T26 |
5 |
|
T21 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13888057 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
16 |
| auto[1] |
4982270 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T11 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10578423 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
16 |
| auto[1] |
8291904 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T28 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1659868 |
1 |
|
|
T28 |
1 |
|
T18 |
2 |
|
T72 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2498758 |
1 |
|
|
T24 |
2 |
|
T15 |
8 |
|
T18 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1649766 |
1 |
|
|
T18 |
1 |
|
T39 |
1 |
|
T92 |
466 |
| auto[1] |
auto[1] |
auto[1] |
2483512 |
1 |
|
|
T23 |
1 |
|
T11 |
1 |
|
T18 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10586220 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8284107 |
1 |
|
|
T23 |
2 |
|
T25 |
15 |
|
T26 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13898532 |
1 |
|
|
T23 |
5 |
|
T24 |
4 |
|
T25 |
8 |
| auto[1] |
4971795 |
1 |
|
|
T23 |
2 |
|
T24 |
2 |
|
T25 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10574794 |
1 |
|
|
T23 |
5 |
|
T24 |
4 |
|
T25 |
1 |
| auto[1] |
8295533 |
1 |
|
|
T23 |
2 |
|
T24 |
2 |
|
T25 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1655733 |
1 |
|
|
T18 |
2 |
|
T72 |
6 |
|
T29 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2476749 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1668005 |
1 |
|
|
T25 |
7 |
|
T15 |
4 |
|
T18 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2495046 |
1 |
|
|
T23 |
1 |
|
T25 |
8 |
|
T15 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10589355 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8280972 |
1 |
|
|
T23 |
1 |
|
T25 |
15 |
|
T26 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13909972 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
4960355 |
1 |
|
|
T23 |
2 |
|
T28 |
1 |
|
T1 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10593843 |
1 |
|
|
T23 |
5 |
|
T24 |
3 |
|
T25 |
16 |
| auto[1] |
8276484 |
1 |
|
|
T23 |
2 |
|
T24 |
3 |
|
T28 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1660051 |
1 |
|
|
T24 |
3 |
|
T15 |
5 |
|
T18 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2478352 |
1 |
|
|
T23 |
2 |
|
T1 |
7 |
|
T15 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1656078 |
1 |
|
|
T15 |
2 |
|
T18 |
2 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2482003 |
1 |
|
|
T28 |
1 |
|
T15 |
3 |
|
T29 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |