Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10630327 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8240000 |
1 |
|
|
T23 |
1 |
|
T26 |
5 |
|
T21 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17789464 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1080863 |
1 |
|
|
T27 |
1 |
|
T28 |
1 |
|
T15 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10610309 |
1 |
|
|
T23 |
5 |
|
T24 |
5 |
|
T25 |
13 |
| auto[1] |
8260018 |
1 |
|
|
T23 |
2 |
|
T24 |
1 |
|
T25 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3612721 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T25 |
3 |
| auto[1] |
auto[0] |
auto[1] |
544066 |
1 |
|
|
T27 |
1 |
|
T28 |
1 |
|
T18 |
6 |
| auto[1] |
auto[1] |
auto[0] |
3566434 |
1 |
|
|
T23 |
1 |
|
T11 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
536797 |
1 |
|
|
T15 |
1 |
|
T72 |
3 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10586220 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8284107 |
1 |
|
|
T23 |
2 |
|
T25 |
15 |
|
T26 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17784327 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
13 |
| auto[1] |
1086000 |
1 |
|
|
T24 |
1 |
|
T25 |
3 |
|
T15 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10576628 |
1 |
|
|
T23 |
5 |
|
T24 |
1 |
|
T25 |
4 |
| auto[1] |
8293699 |
1 |
|
|
T23 |
2 |
|
T24 |
5 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3591309 |
1 |
|
|
T23 |
1 |
|
T24 |
4 |
|
T27 |
1 |
| auto[1] |
auto[0] |
auto[1] |
539781 |
1 |
|
|
T24 |
1 |
|
T18 |
1 |
|
T72 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3616390 |
1 |
|
|
T23 |
1 |
|
T25 |
9 |
|
T15 |
7 |
| auto[1] |
auto[1] |
auto[1] |
546219 |
1 |
|
|
T25 |
3 |
|
T15 |
1 |
|
T18 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10589355 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8280972 |
1 |
|
|
T23 |
1 |
|
T25 |
15 |
|
T26 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17787343 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1082984 |
1 |
|
|
T27 |
1 |
|
T15 |
3 |
|
T18 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10583318 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
16 |
| auto[1] |
8287009 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T27 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3601912 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T1 |
7 |
| auto[1] |
auto[0] |
auto[1] |
542105 |
1 |
|
|
T27 |
1 |
|
T15 |
2 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3602113 |
1 |
|
|
T28 |
7 |
|
T11 |
2 |
|
T15 |
4 |
| auto[1] |
auto[1] |
auto[1] |
540879 |
1 |
|
|
T15 |
1 |
|
T18 |
2 |
|
T29 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10608583 |
1 |
|
|
T23 |
7 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
8261744 |
1 |
|
|
T24 |
5 |
|
T25 |
15 |
|
T26 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17798161 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1072166 |
1 |
|
|
T1 |
1 |
|
T18 |
4 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10666928 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
1 |
| auto[1] |
8203399 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T25 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3550707 |
1 |
|
|
T23 |
1 |
|
T1 |
4 |
|
T11 |
2 |
| auto[1] |
auto[0] |
auto[1] |
532714 |
1 |
|
|
T1 |
1 |
|
T18 |
3 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3580526 |
1 |
|
|
T24 |
3 |
|
T25 |
15 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
539452 |
1 |
|
|
T18 |
1 |
|
T3 |
1 |
|
T5 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10620784 |
1 |
|
|
T23 |
5 |
|
T24 |
3 |
|
T25 |
16 |
| auto[1] |
8249543 |
1 |
|
|
T23 |
2 |
|
T24 |
3 |
|
T26 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17786071 |
1 |
|
|
T23 |
5 |
|
T24 |
5 |
|
T25 |
12 |
| auto[1] |
1084256 |
1 |
|
|
T23 |
2 |
|
T24 |
1 |
|
T25 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10587391 |
1 |
|
|
T23 |
4 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
8282936 |
1 |
|
|
T23 |
3 |
|
T24 |
5 |
|
T25 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3611945 |
1 |
|
|
T24 |
2 |
|
T25 |
11 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
544195 |
1 |
|
|
T23 |
1 |
|
T25 |
4 |
|
T18 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3586735 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T28 |
7 |
| auto[1] |
auto[1] |
auto[1] |
540061 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10582063 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8288264 |
1 |
|
|
T26 |
14 |
|
T28 |
7 |
|
T21 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17799835 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1070492 |
1 |
|
|
T23 |
1 |
|
T27 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10674570 |
1 |
|
|
T23 |
5 |
|
T24 |
5 |
|
T25 |
16 |
| auto[1] |
8195757 |
1 |
|
|
T23 |
2 |
|
T24 |
1 |
|
T27 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3556723 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T1 |
7 |
| auto[1] |
auto[0] |
auto[1] |
534776 |
1 |
|
|
T23 |
1 |
|
T27 |
1 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3568542 |
1 |
|
|
T28 |
7 |
|
T18 |
4 |
|
T72 |
4 |
| auto[1] |
auto[1] |
auto[1] |
535716 |
1 |
|
|
T18 |
1 |
|
T72 |
2 |
|
T34 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10606391 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
16 |
| auto[1] |
8263936 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T26 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17785210 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1085117 |
1 |
|
|
T28 |
2 |
|
T11 |
2 |
|
T13 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10579529 |
1 |
|
|
T23 |
6 |
|
T24 |
5 |
|
T25 |
16 |
| auto[1] |
8290798 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T27 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3612470 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T27 |
1 |
| auto[1] |
auto[0] |
auto[1] |
545142 |
1 |
|
|
T28 |
2 |
|
T11 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3593211 |
1 |
|
|
T1 |
2 |
|
T11 |
1 |
|
T18 |
2 |
| auto[1] |
auto[1] |
auto[1] |
539975 |
1 |
|
|
T11 |
1 |
|
T72 |
2 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10590134 |
1 |
|
|
T23 |
5 |
|
T24 |
4 |
|
T25 |
16 |
| auto[1] |
8280193 |
1 |
|
|
T23 |
2 |
|
T24 |
2 |
|
T26 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17790380 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1079947 |
1 |
|
|
T1 |
2 |
|
T15 |
3 |
|
T18 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10617430 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
13 |
| auto[1] |
8252897 |
1 |
|
|
T24 |
1 |
|
T25 |
3 |
|
T27 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3573352 |
1 |
|
|
T25 |
3 |
|
T27 |
1 |
|
T1 |
2 |
| auto[1] |
auto[0] |
auto[1] |
537554 |
1 |
|
|
T18 |
2 |
|
T29 |
2 |
|
T3 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3599598 |
1 |
|
|
T24 |
1 |
|
T1 |
3 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[1] |
542393 |
1 |
|
|
T1 |
2 |
|
T15 |
3 |
|
T33 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10604386 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
1 |
| auto[1] |
8265941 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17792551 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
15 |
| auto[1] |
1077776 |
1 |
|
|
T23 |
2 |
|
T25 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10614224 |
1 |
|
|
T23 |
5 |
|
T24 |
2 |
|
T25 |
4 |
| auto[1] |
8256103 |
1 |
|
|
T23 |
2 |
|
T24 |
4 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3588754 |
1 |
|
|
T24 |
3 |
|
T28 |
8 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
538960 |
1 |
|
|
T23 |
1 |
|
T11 |
1 |
|
T18 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3589573 |
1 |
|
|
T24 |
1 |
|
T25 |
11 |
|
T28 |
7 |
| auto[1] |
auto[1] |
auto[1] |
538816 |
1 |
|
|
T23 |
1 |
|
T25 |
1 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10603942 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
1 |
| auto[1] |
8266385 |
1 |
|
|
T23 |
1 |
|
T24 |
2 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17789928 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
14 |
| auto[1] |
1080399 |
1 |
|
|
T23 |
1 |
|
T25 |
2 |
|
T15 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10616033 |
1 |
|
|
T23 |
5 |
|
T24 |
5 |
|
T25 |
4 |
| auto[1] |
8254294 |
1 |
|
|
T23 |
2 |
|
T24 |
1 |
|
T25 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3588850 |
1 |
|
|
T27 |
1 |
|
T1 |
2 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
540308 |
1 |
|
|
T23 |
1 |
|
T15 |
2 |
|
T18 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3585045 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T25 |
10 |
| auto[1] |
auto[1] |
auto[1] |
540091 |
1 |
|
|
T25 |
2 |
|
T18 |
1 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10581811 |
1 |
|
|
T23 |
7 |
|
T24 |
3 |
|
T25 |
1 |
| auto[1] |
8288516 |
1 |
|
|
T24 |
3 |
|
T25 |
15 |
|
T26 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17787057 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1083270 |
1 |
|
|
T28 |
3 |
|
T15 |
1 |
|
T18 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10598978 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
8271349 |
1 |
|
|
T28 |
15 |
|
T15 |
5 |
|
T18 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3562019 |
1 |
|
|
T28 |
12 |
|
T15 |
4 |
|
T18 |
5 |
| auto[1] |
auto[0] |
auto[1] |
536124 |
1 |
|
|
T28 |
3 |
|
T15 |
1 |
|
T18 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3626060 |
1 |
|
|
T18 |
1 |
|
T29 |
1 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[1] |
547146 |
1 |
|
|
T18 |
2 |
|
T3 |
2 |
|
T6 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10605475 |
1 |
|
|
T23 |
7 |
|
T24 |
3 |
|
T25 |
16 |
| auto[1] |
8264852 |
1 |
|
|
T24 |
3 |
|
T26 |
14 |
|
T21 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17787857 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
16 |
| auto[1] |
1082470 |
1 |
|
|
T23 |
1 |
|
T1 |
1 |
|
T11 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10599236 |
1 |
|
|
T23 |
6 |
|
T24 |
5 |
|
T25 |
13 |
| auto[1] |
8271091 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T25 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3602359 |
1 |
|
|
T24 |
1 |
|
T25 |
3 |
|
T27 |
1 |
| auto[1] |
auto[0] |
auto[1] |
541731 |
1 |
|
|
T23 |
1 |
|
T1 |
1 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3586262 |
1 |
|
|
T15 |
4 |
|
T18 |
3 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[1] |
540739 |
1 |
|
|
T15 |
1 |
|
T18 |
1 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10563495 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
1 |
| auto[1] |
8306832 |
1 |
|
|
T23 |
1 |
|
T25 |
15 |
|
T26 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17785172 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
16 |
| auto[1] |
1085155 |
1 |
|
|
T24 |
1 |
|
T1 |
1 |
|
T15 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10594907 |
1 |
|
|
T23 |
7 |
|
T24 |
3 |
|
T25 |
1 |
| auto[1] |
8275420 |
1 |
|
|
T24 |
3 |
|
T25 |
15 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3579387 |
1 |
|
|
T24 |
2 |
|
T11 |
1 |
|
T15 |
11 |
| auto[1] |
auto[0] |
auto[1] |
539771 |
1 |
|
|
T24 |
1 |
|
T1 |
1 |
|
T15 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3610878 |
1 |
|
|
T25 |
15 |
|
T18 |
4 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[1] |
545384 |
1 |
|
|
T29 |
1 |
|
T39 |
1 |
|
T92 |
134 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10651502 |
1 |
|
|
T23 |
6 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
8218825 |
1 |
|
|
T23 |
1 |
|
T24 |
5 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17786624 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
12 |
| auto[1] |
1083703 |
1 |
|
|
T25 |
4 |
|
T27 |
1 |
|
T28 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10602724 |
1 |
|
|
T23 |
5 |
|
T24 |
5 |
|
T25 |
1 |
| auto[1] |
8267603 |
1 |
|
|
T23 |
2 |
|
T24 |
1 |
|
T25 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3601698 |
1 |
|
|
T23 |
1 |
|
T11 |
1 |
|
T18 |
5 |
| auto[1] |
auto[0] |
auto[1] |
543277 |
1 |
|
|
T27 |
1 |
|
T18 |
1 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3582202 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[1] |
540426 |
1 |
|
|
T25 |
4 |
|
T28 |
1 |
|
T18 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |