| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.61 | 99.06 | 99.10 | 100.00 | 99.80 | 99.68 | 100.00 |
| T769 | /workspace/coverage/default/38.gpio_alert_test.3454741455 | Jan 07 01:32:20 PM PST 24 | Jan 07 01:32:29 PM PST 24 | 23030572 ps | ||
| T770 | /workspace/coverage/default/23.gpio_alert_test.468196074 | Jan 07 01:32:59 PM PST 24 | Jan 07 01:33:04 PM PST 24 | 14985743 ps | ||
| T771 | /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.179901156 | Jan 07 01:32:11 PM PST 24 | Jan 07 01:32:16 PM PST 24 | 64577115 ps | ||
| T772 | /workspace/coverage/default/20.gpio_alert_test.2816873952 | Jan 07 01:32:55 PM PST 24 | Jan 07 01:32:57 PM PST 24 | 74126277 ps | ||
| T773 | /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1535626819 | Jan 07 01:31:58 PM PST 24 | Jan 07 01:32:09 PM PST 24 | 259697308 ps | ||
| T774 | /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.4174319784 | Jan 07 01:33:03 PM PST 24 | Jan 07 01:33:13 PM PST 24 | 56690536 ps | ||
| T775 | /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1228478960 | Jan 07 01:33:19 PM PST 24 | Jan 07 01:33:28 PM PST 24 | 47979894 ps | ||
| T776 | /workspace/coverage/default/25.gpio_stress_all.4007902522 | Jan 07 01:31:57 PM PST 24 | Jan 07 01:32:40 PM PST 24 | 2593145575 ps | ||
| T777 | /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3726058993 | Jan 07 01:31:56 PM PST 24 | Jan 07 01:32:03 PM PST 24 | 108610758 ps | ||
| T778 | /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3465102129 | Jan 07 01:32:20 PM PST 24 | Jan 07 01:32:32 PM PST 24 | 383248773 ps | ||
| T779 | /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3849899010 | Jan 07 01:31:20 PM PST 24 | Jan 07 01:31:33 PM PST 24 | 17994140 ps | ||
| T780 | /workspace/coverage/default/8.gpio_filter_stress.3168310038 | Jan 07 01:31:23 PM PST 24 | Jan 07 01:31:43 PM PST 24 | 250777018 ps | ||
| T781 | /workspace/coverage/default/25.gpio_smoke.1373825529 | Jan 07 01:33:16 PM PST 24 | Jan 07 01:33:25 PM PST 24 | 221998550 ps | ||
| T782 | /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.2691539084 | Jan 07 01:32:52 PM PST 24 | Jan 07 01:39:02 PM PST 24 | 20335089951 ps | ||
| T783 | /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1442656367 | Jan 07 01:31:53 PM PST 24 | Jan 07 01:31:58 PM PST 24 | 115664571 ps | ||
| T784 | /workspace/coverage/default/8.gpio_alert_test.2108336580 | Jan 07 01:31:29 PM PST 24 | Jan 07 01:31:48 PM PST 24 | 113266444 ps | ||
| T785 | /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.762964255 | Jan 07 01:32:16 PM PST 24 | Jan 07 01:32:25 PM PST 24 | 31300596 ps | ||
| T786 | /workspace/coverage/default/42.gpio_intr_rand_pgm.1305590758 | Jan 07 01:33:02 PM PST 24 | Jan 07 01:33:12 PM PST 24 | 185916840 ps | ||
| T787 | /workspace/coverage/default/43.gpio_filter_stress.2339460980 | Jan 07 01:33:13 PM PST 24 | Jan 07 01:33:42 PM PST 24 | 1715294208 ps | ||
| T788 | /workspace/coverage/default/33.gpio_alert_test.3571437965 | Jan 07 01:33:15 PM PST 24 | Jan 07 01:33:24 PM PST 24 | 20502733 ps | ||
| T789 | /workspace/coverage/default/1.gpio_random_dout_din.537605285 | Jan 07 01:31:21 PM PST 24 | Jan 07 01:31:33 PM PST 24 | 22406531 ps | ||
| T790 | /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1457852784 | Jan 07 01:31:12 PM PST 24 | Jan 07 01:31:25 PM PST 24 | 37493079 ps | ||
| T791 | /workspace/coverage/default/31.gpio_rand_intr_trigger.1164513316 | Jan 07 01:32:12 PM PST 24 | Jan 07 01:32:19 PM PST 24 | 440880761 ps | ||
| T792 | /workspace/coverage/default/48.gpio_rand_intr_trigger.1317537679 | Jan 07 01:33:27 PM PST 24 | Jan 07 01:33:36 PM PST 24 | 210173900 ps | ||
| T793 | /workspace/coverage/default/24.gpio_full_random.1197432544 | Jan 07 01:33:05 PM PST 24 | Jan 07 01:33:16 PM PST 24 | 72795864 ps | ||
| T794 | /workspace/coverage/default/46.gpio_filter_stress.1538645212 | Jan 07 01:32:34 PM PST 24 | Jan 07 01:32:59 PM PST 24 | 1737439362 ps | ||
| T795 | /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.4113492215 | Jan 07 01:31:27 PM PST 24 | Jan 07 01:31:46 PM PST 24 | 84672022 ps | ||
| T796 | /workspace/coverage/default/39.gpio_smoke.2671417937 | Jan 07 01:32:18 PM PST 24 | Jan 07 01:32:28 PM PST 24 | 50682784 ps | ||
| T797 | /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1088613795 | Jan 07 01:33:01 PM PST 24 | Jan 07 01:33:08 PM PST 24 | 85531296 ps | ||
| T798 | /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.4156907198 | Jan 07 01:32:53 PM PST 24 | Jan 07 01:33:00 PM PST 24 | 548687291 ps | ||
| T799 | /workspace/coverage/default/39.gpio_alert_test.1913549336 | Jan 07 01:33:15 PM PST 24 | Jan 07 01:33:24 PM PST 24 | 14300785 ps | ||
| T800 | /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3264572120 | Jan 07 01:32:13 PM PST 24 | Jan 07 01:32:20 PM PST 24 | 46667684 ps | ||
| T801 | /workspace/coverage/default/26.gpio_stress_all.3150460175 | Jan 07 01:32:13 PM PST 24 | Jan 07 01:34:43 PM PST 24 | 44898963254 ps | ||
| T802 | /workspace/coverage/default/38.gpio_intr_rand_pgm.2874571782 | Jan 07 01:32:20 PM PST 24 | Jan 07 01:32:30 PM PST 24 | 96242525 ps | ||
| T803 | /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3156721375 | Jan 07 01:31:23 PM PST 24 | Jan 07 01:31:38 PM PST 24 | 336196052 ps | ||
| T804 | /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2045395261 | Jan 07 01:32:53 PM PST 24 | Jan 07 01:32:59 PM PST 24 | 998186902 ps | ||
| T805 | /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3952934596 | Jan 07 01:33:38 PM PST 24 | Jan 07 01:33:40 PM PST 24 | 200174828 ps | ||
| T806 | /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1298392283 | Jan 07 01:33:00 PM PST 24 | Jan 07 01:33:06 PM PST 24 | 15076089 ps | ||
| T807 | /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.4190628677 | Jan 07 01:33:03 PM PST 24 | Jan 07 01:33:14 PM PST 24 | 28759164 ps | ||
| T808 | /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4041197042 | Jan 07 01:31:23 PM PST 24 | Jan 07 01:31:39 PM PST 24 | 165548647 ps | ||
| T809 | /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.1666811432 | Jan 07 01:33:03 PM PST 24 | Jan 07 01:54:04 PM PST 24 | 398419727161 ps | ||
| T810 | /workspace/coverage/default/6.gpio_alert_test.3332623592 | Jan 07 01:31:22 PM PST 24 | Jan 07 01:31:36 PM PST 24 | 61370124 ps | ||
| T811 | /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1941785780 | Jan 07 01:33:37 PM PST 24 | Jan 07 01:33:39 PM PST 24 | 37274209 ps | ||
| T812 | /workspace/coverage/default/29.gpio_filter_stress.459191314 | Jan 07 01:32:52 PM PST 24 | Jan 07 01:33:19 PM PST 24 | 5637650902 ps | ||
| T813 | /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.483869994 | Jan 07 01:33:07 PM PST 24 | Jan 07 01:33:18 PM PST 24 | 213043203 ps | ||
| T814 | /workspace/coverage/default/44.gpio_alert_test.3187763586 | Jan 07 01:32:34 PM PST 24 | Jan 07 01:32:37 PM PST 24 | 29559951 ps | ||
| T815 | /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3495511283 | Jan 07 01:33:00 PM PST 24 | Jan 07 01:33:10 PM PST 24 | 285383853 ps | ||
| T816 | /workspace/coverage/default/19.gpio_full_random.368403782 | Jan 07 01:33:00 PM PST 24 | Jan 07 01:33:08 PM PST 24 | 216118700 ps | ||
| T817 | /workspace/coverage/default/45.gpio_filter_stress.1657585022 | Jan 07 01:32:35 PM PST 24 | Jan 07 01:32:48 PM PST 24 | 1575206558 ps | ||
| T818 | /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3276917298 | Jan 07 01:33:00 PM PST 24 | Jan 07 01:33:07 PM PST 24 | 130270974 ps | ||
| T819 | /workspace/coverage/default/3.gpio_full_random.435055270 | Jan 07 01:31:20 PM PST 24 | Jan 07 01:31:33 PM PST 24 | 364724931 ps | ||
| T820 | /workspace/coverage/default/10.gpio_alert_test.1180090316 | Jan 07 01:31:21 PM PST 24 | Jan 07 01:31:33 PM PST 24 | 50628799 ps | ||
| T821 | /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2354244515 | Jan 07 01:32:55 PM PST 24 | Jan 07 01:32:59 PM PST 24 | 318173333 ps | ||
| T822 | /workspace/coverage/default/48.gpio_random_dout_din.3622777149 | Jan 07 01:33:42 PM PST 24 | Jan 07 01:33:44 PM PST 24 | 155669997 ps | ||
| T823 | /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3028783466 | Jan 07 01:32:14 PM PST 24 | Jan 07 01:32:21 PM PST 24 | 255125186 ps | ||
| T824 | /workspace/coverage/default/14.gpio_alert_test.3350897267 | Jan 07 01:31:37 PM PST 24 | Jan 07 01:31:51 PM PST 24 | 14889135 ps | ||
| T825 | /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3804121176 | Jan 07 01:33:40 PM PST 24 | Jan 07 01:33:42 PM PST 24 | 207364828 ps | ||
| T826 | /workspace/coverage/default/31.gpio_random_dout_din.1577798374 | Jan 07 01:32:10 PM PST 24 | Jan 07 01:32:15 PM PST 24 | 19768964 ps | ||
| T827 | /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3268119500 | Jan 07 01:31:52 PM PST 24 | Jan 07 01:31:58 PM PST 24 | 44164286 ps | ||
| T828 | /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1851931416 | Jan 07 01:31:23 PM PST 24 | Jan 07 01:31:38 PM PST 24 | 43143255 ps | ||
| T829 | /workspace/coverage/default/12.gpio_filter_stress.2689856887 | Jan 07 01:31:36 PM PST 24 | Jan 07 01:32:10 PM PST 24 | 1287849272 ps | ||
| T830 | /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1524242910 | Jan 07 01:31:24 PM PST 24 | Jan 07 01:31:41 PM PST 24 | 1098633546 ps | ||
| T831 | /workspace/coverage/default/45.gpio_stress_all.1783269099 | Jan 07 01:32:34 PM PST 24 | Jan 07 01:35:15 PM PST 24 | 11114108808 ps | ||
| T832 | /workspace/coverage/default/23.gpio_intr_rand_pgm.672557703 | Jan 07 01:32:14 PM PST 24 | Jan 07 01:32:21 PM PST 24 | 275212207 ps | ||
| T833 | /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2374685191 | Jan 07 01:32:12 PM PST 24 | Jan 07 01:32:20 PM PST 24 | 134929100 ps | ||
| T834 | /workspace/coverage/default/4.gpio_random_dout_din.1038652675 | Jan 07 01:31:19 PM PST 24 | Jan 07 01:31:33 PM PST 24 | 23747489 ps | ||
| T835 | /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.446098540 | Jan 07 01:33:03 PM PST 24 | Jan 07 01:33:13 PM PST 24 | 91011558 ps | ||
| T60 | /workspace/coverage/default/2.gpio_sec_cm.606524014 | Jan 07 01:31:18 PM PST 24 | Jan 07 01:31:31 PM PST 24 | 287803059 ps | ||
| T836 | /workspace/coverage/default/29.gpio_random_dout_din.3231084305 | Jan 07 01:32:08 PM PST 24 | Jan 07 01:32:14 PM PST 24 | 23763358 ps | ||
| T837 | /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1092622673 | Jan 07 01:31:24 PM PST 24 | Jan 07 01:45:56 PM PST 24 | 120218761092 ps | ||
| T838 | /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.141265019 | Jan 07 01:32:59 PM PST 24 | Jan 07 01:38:11 PM PST 24 | 23155534304 ps | ||
| T839 | /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3434688317 | Jan 07 01:33:20 PM PST 24 | Jan 07 01:33:29 PM PST 24 | 25957857 ps | ||
| T840 | /workspace/coverage/default/23.gpio_stress_all.3871988727 | Jan 07 01:32:56 PM PST 24 | Jan 07 01:35:56 PM PST 24 | 6429345073 ps | ||
| T841 | /workspace/coverage/default/5.gpio_full_random.3051744100 | Jan 07 01:31:22 PM PST 24 | Jan 07 01:31:33 PM PST 24 | 21950964 ps | ||
| T842 | /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2518819548 | Jan 07 01:33:17 PM PST 24 | Jan 07 01:33:26 PM PST 24 | 72861776 ps | ||
| T843 | /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.535983402 | Jan 07 01:31:54 PM PST 24 | Jan 07 01:36:53 PM PST 24 | 80378441199 ps | ||
| T844 | /workspace/coverage/default/5.gpio_alert_test.3978973662 | Jan 07 01:31:22 PM PST 24 | Jan 07 01:31:35 PM PST 24 | 36075655 ps | ||
| T845 | /workspace/coverage/default/49.gpio_rand_intr_trigger.1570599937 | Jan 07 01:33:47 PM PST 24 | Jan 07 01:33:50 PM PST 24 | 133335973 ps | ||
| T846 | /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.3081174286 | Jan 07 01:33:05 PM PST 24 | Jan 07 02:00:45 PM PST 24 | 455584431400 ps | ||
| T847 | /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1638216155 | Jan 07 01:32:54 PM PST 24 | Jan 07 01:33:02 PM PST 24 | 418399419 ps | ||
| T848 | /workspace/coverage/default/34.gpio_random_dout_din.1757951079 | Jan 07 01:33:13 PM PST 24 | Jan 07 01:33:23 PM PST 24 | 47888456 ps | ||
| T849 | /workspace/coverage/default/41.gpio_random_dout_din.1966975225 | Jan 07 01:32:59 PM PST 24 | Jan 07 01:33:04 PM PST 24 | 374082241 ps | ||
| T850 | /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.4185429759 | Jan 07 01:31:56 PM PST 24 | Jan 07 01:32:04 PM PST 24 | 68982677 ps | ||
| T851 | /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1973863395 | Jan 07 12:50:19 PM PST 24 | Jan 07 12:52:02 PM PST 24 | 66501312 ps | ||
| T88 | /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2871698932 | Jan 07 12:49:59 PM PST 24 | Jan 07 12:51:43 PM PST 24 | 32703909 ps | ||
| T852 | /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3797617020 | Jan 07 12:49:30 PM PST 24 | Jan 07 12:50:36 PM PST 24 | 47404280 ps | ||
| T76 | /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3042169015 | Jan 07 12:49:59 PM PST 24 | Jan 07 12:51:17 PM PST 24 | 12567151 ps | ||
| T853 | /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1750772201 | Jan 07 12:50:17 PM PST 24 | Jan 07 12:52:00 PM PST 24 | 16213934 ps | ||
| T854 | /workspace/coverage/cover_reg_top/34.gpio_intr_test.3174464598 | Jan 07 12:50:08 PM PST 24 | Jan 07 12:51:40 PM PST 24 | 53878135 ps | ||
| T855 | /workspace/coverage/cover_reg_top/11.gpio_tl_errors.4171494551 | Jan 07 12:50:11 PM PST 24 | Jan 07 12:51:41 PM PST 24 | 52046559 ps | ||
| T856 | /workspace/coverage/cover_reg_top/2.gpio_intr_test.79227855 | Jan 07 12:50:00 PM PST 24 | Jan 07 12:51:40 PM PST 24 | 67463338 ps | ||
| T89 | /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3062056260 | Jan 07 12:50:11 PM PST 24 | Jan 07 12:51:39 PM PST 24 | 68738412 ps | ||
| T857 | /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1880478527 | Jan 07 12:51:02 PM PST 24 | Jan 07 12:52:37 PM PST 24 | 21583869 ps | ||
| T858 | /workspace/coverage/cover_reg_top/10.gpio_intr_test.3872573574 | Jan 07 12:50:54 PM PST 24 | Jan 07 12:52:06 PM PST 24 | 15811473 ps | ||
| T859 | /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2951046205 | Jan 07 12:49:44 PM PST 24 | Jan 07 12:51:19 PM PST 24 | 41019563 ps | ||
| T90 | /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3258690239 | Jan 07 12:50:03 PM PST 24 | Jan 07 12:52:13 PM PST 24 | 51695091 ps | ||
| T860 | /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3766332847 | Jan 07 12:50:01 PM PST 24 | Jan 07 12:51:10 PM PST 24 | 15257587 ps | ||
| T861 | /workspace/coverage/cover_reg_top/18.gpio_intr_test.2429580518 | Jan 07 01:01:36 PM PST 24 | Jan 07 01:02:02 PM PST 24 | 19451212 ps | ||
| T862 | /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1003198942 | Jan 07 12:49:57 PM PST 24 | Jan 07 12:52:01 PM PST 24 | 780737891 ps | ||
| T91 | /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4222413370 | Jan 07 12:50:44 PM PST 24 | Jan 07 12:51:56 PM PST 24 | 64104360 ps | ||
| T863 | /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2045614625 | Jan 07 12:50:20 PM PST 24 | Jan 07 12:51:36 PM PST 24 | 187265202 ps | ||
| T864 | /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3063583802 | Jan 07 12:50:15 PM PST 24 | Jan 07 12:51:19 PM PST 24 | 179279906 ps | ||
| T37 | /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1633328340 | Jan 07 12:50:07 PM PST 24 | Jan 07 12:51:37 PM PST 24 | 171916308 ps | ||
| T865 | /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1312481504 | Jan 07 12:49:58 PM PST 24 | Jan 07 12:51:21 PM PST 24 | 23443845 ps | ||
| T866 | /workspace/coverage/cover_reg_top/21.gpio_intr_test.2695187371 | Jan 07 12:56:49 PM PST 24 | Jan 07 12:58:26 PM PST 24 | 58077223 ps | ||
| T867 | /workspace/coverage/cover_reg_top/4.gpio_tl_errors.786744092 | Jan 07 12:49:45 PM PST 24 | Jan 07 12:50:55 PM PST 24 | 222436625 ps | ||
| T868 | /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1190178699 | Jan 07 12:50:10 PM PST 24 | Jan 07 12:51:38 PM PST 24 | 769171871 ps | ||
| T869 | /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1876617637 | Jan 07 12:49:58 PM PST 24 | Jan 07 12:51:21 PM PST 24 | 23323648 ps | ||
| T870 | /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.926377371 | Jan 07 12:49:49 PM PST 24 | Jan 07 12:51:08 PM PST 24 | 46285999 ps | ||
| T871 | /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3306832060 | Jan 07 12:50:12 PM PST 24 | Jan 07 12:51:25 PM PST 24 | 242044961 ps | ||
| T872 | /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2111208496 | Jan 07 12:50:18 PM PST 24 | Jan 07 12:51:53 PM PST 24 | 30297782 ps | ||
| T77 | /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3907570958 | Jan 07 12:50:30 PM PST 24 | Jan 07 12:53:07 PM PST 24 | 20579332 ps | ||
| T82 | /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2025619631 | Jan 07 12:49:57 PM PST 24 | Jan 07 12:51:47 PM PST 24 | 11803491 ps | ||
| T83 | /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1291864020 | Jan 07 12:50:10 PM PST 24 | Jan 07 12:51:59 PM PST 24 | 150558046 ps | ||
| T84 | /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2352270087 | Jan 07 12:50:02 PM PST 24 | Jan 07 12:51:42 PM PST 24 | 225328617 ps | ||
| T85 | /workspace/coverage/cover_reg_top/30.gpio_intr_test.654745993 | Jan 07 12:50:08 PM PST 24 | Jan 07 12:51:18 PM PST 24 | 64377089 ps | ||
| T86 | /workspace/coverage/cover_reg_top/25.gpio_intr_test.696847630 | Jan 07 12:50:15 PM PST 24 | Jan 07 12:51:20 PM PST 24 | 12791279 ps | ||
| T78 | /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3406361796 | Jan 07 12:51:42 PM PST 24 | Jan 07 12:53:15 PM PST 24 | 12518164 ps | ||
| T873 | /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.785079092 | Jan 07 12:50:26 PM PST 24 | Jan 07 12:52:28 PM PST 24 | 37348169 ps | ||
| T874 | /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3671561420 | Jan 07 12:49:58 PM PST 24 | Jan 07 12:51:04 PM PST 24 | 47004137 ps | ||
| T875 | /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2239446693 | Jan 07 12:50:06 PM PST 24 | Jan 07 12:51:48 PM PST 24 | 181990003 ps | ||
| T876 | /workspace/coverage/cover_reg_top/19.gpio_csr_rw.957424447 | Jan 07 12:56:49 PM PST 24 | Jan 07 12:58:29 PM PST 24 | 14793137 ps | ||
| T877 | /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1670149028 | Jan 07 12:50:01 PM PST 24 | Jan 07 12:51:20 PM PST 24 | 39087533 ps | ||
| T878 | /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1956214794 | Jan 07 12:49:55 PM PST 24 | Jan 07 12:51:17 PM PST 24 | 79885682 ps | ||
| T40 | /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2016738645 | Jan 07 12:49:58 PM PST 24 | Jan 07 12:51:39 PM PST 24 | 234413503 ps | ||
| T879 | /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1880373697 | Jan 07 12:49:48 PM PST 24 | Jan 07 12:50:59 PM PST 24 | 14609563 ps | ||
| T880 | /workspace/coverage/cover_reg_top/39.gpio_intr_test.3557065788 | Jan 07 12:50:24 PM PST 24 | Jan 07 12:51:38 PM PST 24 | 21977524 ps | ||
| T881 | /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2338066789 | Jan 07 12:50:07 PM PST 24 | Jan 07 12:51:34 PM PST 24 | 341908757 ps | ||
| T882 | /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2654963771 | Jan 07 12:49:43 PM PST 24 | Jan 07 12:50:57 PM PST 24 | 48401821 ps | ||
| T883 | /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1678912593 | Jan 07 12:49:44 PM PST 24 | Jan 07 12:50:55 PM PST 24 | 637289890 ps | ||
| T884 | /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3022132821 | Jan 07 12:50:10 PM PST 24 | Jan 07 12:51:37 PM PST 24 | 17445962 ps | ||
| T885 | /workspace/coverage/cover_reg_top/31.gpio_intr_test.127334709 | Jan 07 12:50:09 PM PST 24 | Jan 07 12:51:18 PM PST 24 | 16627137 ps | ||
| T886 | /workspace/coverage/cover_reg_top/46.gpio_intr_test.2518018255 | Jan 07 12:50:10 PM PST 24 | Jan 07 12:51:33 PM PST 24 | 14741191 ps | ||
| T887 | /workspace/coverage/cover_reg_top/37.gpio_intr_test.2188581424 | Jan 07 12:50:05 PM PST 24 | Jan 07 12:51:16 PM PST 24 | 76867856 ps | ||
| T888 | /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1215270024 | Jan 07 12:50:16 PM PST 24 | Jan 07 12:51:20 PM PST 24 | 60340781 ps | ||
| T889 | /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3696082378 | Jan 07 12:50:35 PM PST 24 | Jan 07 12:51:53 PM PST 24 | 65404248 ps | ||
| T890 | /workspace/coverage/cover_reg_top/0.gpio_intr_test.3554926999 | Jan 07 12:50:21 PM PST 24 | Jan 07 12:51:39 PM PST 24 | 33187344 ps | ||
| T891 | /workspace/coverage/cover_reg_top/9.gpio_intr_test.3512938986 | Jan 07 12:49:52 PM PST 24 | Jan 07 12:51:13 PM PST 24 | 11833486 ps | ||
| T892 | /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1339877609 | Jan 07 12:50:01 PM PST 24 | Jan 07 12:51:08 PM PST 24 | 362928547 ps | ||
| T893 | /workspace/coverage/cover_reg_top/19.gpio_intr_test.1669537635 | Jan 07 12:50:28 PM PST 24 | Jan 07 12:51:37 PM PST 24 | 81534280 ps | ||
| T79 | /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1493678631 | Jan 07 12:49:51 PM PST 24 | Jan 07 12:51:10 PM PST 24 | 67206809 ps | ||
| T894 | /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1284047207 | Jan 07 12:50:18 PM PST 24 | Jan 07 12:51:48 PM PST 24 | 49213714 ps | ||
| T895 | /workspace/coverage/cover_reg_top/38.gpio_intr_test.1932008287 | Jan 07 12:50:42 PM PST 24 | Jan 07 12:52:20 PM PST 24 | 24225335 ps | ||
| T896 | /workspace/coverage/cover_reg_top/8.gpio_intr_test.2561756594 | Jan 07 12:50:18 PM PST 24 | Jan 07 12:51:54 PM PST 24 | 16389941 ps | ||
| T897 | /workspace/coverage/cover_reg_top/6.gpio_tl_errors.372536859 | Jan 07 12:49:52 PM PST 24 | Jan 07 12:51:23 PM PST 24 | 410972116 ps | ||
| T898 | /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1612663350 | Jan 07 12:50:27 PM PST 24 | Jan 07 12:51:47 PM PST 24 | 42470286 ps | ||
| T899 | /workspace/coverage/cover_reg_top/16.gpio_tl_errors.971447277 | Jan 07 12:50:23 PM PST 24 | Jan 07 12:51:43 PM PST 24 | 86884015 ps | ||
| T900 | /workspace/coverage/cover_reg_top/41.gpio_intr_test.284903859 | Jan 07 12:50:22 PM PST 24 | Jan 07 12:51:53 PM PST 24 | 20098146 ps | ||
| T901 | /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3928309411 | Jan 07 12:50:04 PM PST 24 | Jan 07 12:52:03 PM PST 24 | 54843796 ps | ||
| T80 | /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1264716460 | Jan 07 12:49:55 PM PST 24 | Jan 07 12:51:27 PM PST 24 | 12171322 ps | ||
| T902 | /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3210292187 | Jan 07 12:50:12 PM PST 24 | Jan 07 12:51:38 PM PST 24 | 1529128285 ps | ||
| T903 | /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4094459675 | Jan 07 12:49:54 PM PST 24 | Jan 07 12:51:38 PM PST 24 | 43458119 ps | ||
| T904 | /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3934771991 | Jan 07 12:50:40 PM PST 24 | Jan 07 12:52:29 PM PST 24 | 332185645 ps | ||
| T905 | /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2084799204 | Jan 07 12:50:10 PM PST 24 | Jan 07 12:51:37 PM PST 24 | 62409237 ps | ||
| T906 | /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.408474039 | Jan 07 12:50:24 PM PST 24 | Jan 07 12:51:34 PM PST 24 | 293982571 ps | ||
| T907 | /workspace/coverage/cover_reg_top/45.gpio_intr_test.3508288004 | Jan 07 12:50:07 PM PST 24 | Jan 07 12:51:33 PM PST 24 | 13080239 ps | ||
| T908 | /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.143597138 | Jan 07 12:50:20 PM PST 24 | Jan 07 12:51:38 PM PST 24 | 154492412 ps | ||
| T93 | /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1198681002 | Jan 07 12:50:10 PM PST 24 | Jan 07 12:52:00 PM PST 24 | 140663283 ps | ||
| T909 | /workspace/coverage/cover_reg_top/33.gpio_intr_test.2996944311 | Jan 07 12:50:15 PM PST 24 | Jan 07 12:51:20 PM PST 24 | 93157230 ps | ||
| T910 | /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.103988939 | Jan 07 12:50:03 PM PST 24 | Jan 07 12:51:21 PM PST 24 | 63203654 ps | ||
| T911 | /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3840946716 | Jan 07 12:50:32 PM PST 24 | Jan 07 12:52:05 PM PST 24 | 42444027 ps | ||
| T912 | /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1775566898 | Jan 07 12:49:52 PM PST 24 | Jan 07 12:51:40 PM PST 24 | 19251935 ps | ||
| T913 | /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1330322706 | Jan 07 12:50:07 PM PST 24 | Jan 07 12:51:39 PM PST 24 | 652085477 ps | ||
| T914 | /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3751096282 | Jan 07 12:49:40 PM PST 24 | Jan 07 12:51:38 PM PST 24 | 32050929 ps | ||
| T915 | /workspace/coverage/cover_reg_top/49.gpio_intr_test.2300005698 | Jan 07 12:50:24 PM PST 24 | Jan 07 12:51:38 PM PST 24 | 55969605 ps | ||
| T916 | /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2022867278 | Jan 07 12:50:29 PM PST 24 | Jan 07 12:51:51 PM PST 24 | 46368832 ps | ||
| T917 | /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3153239645 | Jan 07 12:49:54 PM PST 24 | Jan 07 12:51:18 PM PST 24 | 15276881 ps | ||
| T918 | /workspace/coverage/cover_reg_top/1.gpio_intr_test.1730505383 | Jan 07 12:50:03 PM PST 24 | Jan 07 12:51:24 PM PST 24 | 40067433 ps | ||
| T919 | /workspace/coverage/cover_reg_top/8.gpio_csr_rw.690691945 | Jan 07 12:50:25 PM PST 24 | Jan 07 12:51:30 PM PST 24 | 15399157 ps | ||
| T920 | /workspace/coverage/cover_reg_top/17.gpio_intr_test.242908818 | Jan 07 12:50:40 PM PST 24 | Jan 07 12:53:37 PM PST 24 | 17125888 ps | ||
| T921 | /workspace/coverage/cover_reg_top/35.gpio_intr_test.974544644 | Jan 07 12:50:32 PM PST 24 | Jan 07 12:51:53 PM PST 24 | 40134441 ps | ||
| T922 | /workspace/coverage/cover_reg_top/36.gpio_intr_test.3563770732 | Jan 07 12:50:34 PM PST 24 | Jan 07 12:51:54 PM PST 24 | 15441710 ps | ||
| T923 | /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.295255257 | Jan 07 12:49:54 PM PST 24 | Jan 07 12:51:30 PM PST 24 | 30438168 ps | ||
| T924 | /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1420685110 | Jan 07 12:50:28 PM PST 24 | Jan 07 12:52:19 PM PST 24 | 13575074 ps | ||
| T925 | /workspace/coverage/cover_reg_top/26.gpio_intr_test.1344032189 | Jan 07 12:50:10 PM PST 24 | Jan 07 12:51:36 PM PST 24 | 48191545 ps | ||
| T926 | /workspace/coverage/cover_reg_top/22.gpio_intr_test.1185106778 | Jan 07 12:50:45 PM PST 24 | Jan 07 12:52:07 PM PST 24 | 38540046 ps | ||
| T927 | /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.251638380 | Jan 07 12:50:37 PM PST 24 | Jan 07 12:52:05 PM PST 24 | 46106547 ps | ||
| T928 | /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1387702247 | Jan 07 12:49:54 PM PST 24 | Jan 07 12:51:26 PM PST 24 | 19531003 ps |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1800473973 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 51471403 ps |
| CPU time | 0.69 seconds |
| Started | Jan 07 12:49:50 PM PST 24 |
| Finished | Jan 07 12:51:07 PM PST 24 |
| Peak memory | 196164 kb |
| Host | smart-a34d289d-2159-497e-b4df-0cfaaedbe291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800473973 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 15.gpio_same_csr_outstanding.1800473973 |
| Directory | /workspace/15.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1903237829 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 592755616 ps |
| CPU time | 0.92 seconds |
| Started | Jan 07 12:38:28 PM PST 24 |
| Finished | Jan 07 12:39:58 PM PST 24 |
| Peak memory | 195948 kb |
| Host | smart-f48d939f-7813-4e5a-9a59-8a5a0b0e8c7c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903237829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1903237829 |
| Directory | /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.990446299 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 225460484847 ps |
| CPU time | 1515.8 seconds |
| Started | Jan 07 01:31:11 PM PST 24 |
| Finished | Jan 07 01:56:39 PM PST 24 |
| Peak memory | 198272 kb |
| Host | smart-2eb3d44a-aa13-4a66-8205-7b44be4097c8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =990446299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.990446299 |
| Directory | /workspace/1.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1193211038 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 77173642 ps |
| CPU time | 2.87 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:32:08 PM PST 24 |
| Peak memory | 198196 kb |
| Host | smart-777c0675-f69c-4284-bcb9-b6639c8d4858 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193211038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1193211038 |
| Directory | /workspace/14.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1378346321 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 781643699 ps |
| CPU time | 1.31 seconds |
| Started | Jan 07 12:49:52 PM PST 24 |
| Finished | Jan 07 12:51:23 PM PST 24 |
| Peak memory | 198304 kb |
| Host | smart-b976155d-b721-475c-b754-c522ea0a1634 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378346321 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.gpio_tl_intg_err.1378346321 |
| Directory | /workspace/4.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/32.gpio_intr_test.3686421768 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12852376 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 12:50:37 PM PST 24 |
| Finished | Jan 07 12:51:55 PM PST 24 |
| Peak memory | 194036 kb |
| Host | smart-4936fbfd-adae-4002-96e0-f4ca19f7a823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686421768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3686421768 |
| Directory | /workspace/32.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3907570958 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 20579332 ps |
| CPU time | 0.65 seconds |
| Started | Jan 07 12:50:30 PM PST 24 |
| Finished | Jan 07 12:53:07 PM PST 24 |
| Peak memory | 195184 kb |
| Host | smart-4479678c-518d-4ef6-9806-56cdf6e90640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907570958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_aliasing.3907570958 |
| Directory | /workspace/2.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2436679908 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 120603756 ps |
| CPU time | 1.38 seconds |
| Started | Jan 07 12:50:08 PM PST 24 |
| Finished | Jan 07 12:51:15 PM PST 24 |
| Peak memory | 198380 kb |
| Host | smart-53f61a65-5e55-40b2-8e10-aac10c403345 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436679908 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 16.gpio_tl_intg_err.2436679908 |
| Directory | /workspace/16.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/default/4.gpio_sec_cm.2242092197 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 102331514 ps |
| CPU time | 0.85 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 213432 kb |
| Host | smart-98aa68f9-24dc-4d46-ad85-2a7e5f8de407 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242092197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2242092197 |
| Directory | /workspace/4.gpio_sec_cm/latest |
| Test location | /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.606338657 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 165944258 ps |
| CPU time | 0.97 seconds |
| Started | Jan 07 12:37:56 PM PST 24 |
| Finished | Jan 07 12:39:17 PM PST 24 |
| Peak memory | 197436 kb |
| Host | smart-ae90d68c-adfa-4db7-b86e-30b504e86176 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=606338657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.606338657 |
| Directory | /workspace/19.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3406361796 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 12518164 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 12:51:42 PM PST 24 |
| Finished | Jan 07 12:53:15 PM PST 24 |
| Peak memory | 194640 kb |
| Host | smart-59bb14f1-141e-4e02-926f-f0293e0fb61a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406361796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi o_csr_rw.3406361796 |
| Directory | /workspace/10.gpio_csr_rw/latest |
| Test location | /workspace/coverage/default/12.gpio_alert_test.3387707111 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 33834070 ps |
| CPU time | 0.55 seconds |
| Started | Jan 07 01:31:39 PM PST 24 |
| Finished | Jan 07 01:31:52 PM PST 24 |
| Peak memory | 194012 kb |
| Host | smart-d0ba1dbd-94ab-4f36-94d5-11d9d5780af4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387707111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3387707111 |
| Directory | /workspace/12.gpio_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3304434623 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 34588220 ps |
| CPU time | 0.84 seconds |
| Started | Jan 07 12:50:05 PM PST 24 |
| Finished | Jan 07 12:51:32 PM PST 24 |
| Peak memory | 196772 kb |
| Host | smart-9c048309-0c59-4563-b064-3b5a1f94e565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304434623 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.gpio_same_csr_outstanding.3304434623 |
| Directory | /workspace/3.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_intr_test.3878890106 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 50831572 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 12:50:01 PM PST 24 |
| Finished | Jan 07 12:51:14 PM PST 24 |
| Peak memory | 194824 kb |
| Host | smart-de8bb2f2-37be-4f2d-9e7b-c75a4c776ddc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878890106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3878890106 |
| Directory | /workspace/6.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.4246218880 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1293568222 ps |
| CPU time | 1.14 seconds |
| Started | Jan 07 12:50:35 PM PST 24 |
| Finished | Jan 07 12:52:02 PM PST 24 |
| Peak memory | 197832 kb |
| Host | smart-cd215dc4-b0a0-4e71-bcc5-696fdd5de1e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246218880 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 12.gpio_tl_intg_err.4246218880 |
| Directory | /workspace/12.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.320069481 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 651678140 ps |
| CPU time | 2.13 seconds |
| Started | Jan 07 12:49:53 PM PST 24 |
| Finished | Jan 07 12:52:01 PM PST 24 |
| Peak memory | 196812 kb |
| Host | smart-0b9ae220-4e64-419d-94d4-3b7109ad5609 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320069481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.320069481 |
| Directory | /workspace/0.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2025619631 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 11803491 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 12:49:57 PM PST 24 |
| Finished | Jan 07 12:51:47 PM PST 24 |
| Peak memory | 194840 kb |
| Host | smart-77d59729-3035-4b8d-86ea-d1baeaa9ed21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025619631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2025619631 |
| Directory | /workspace/0.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1387702247 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 19531003 ps |
| CPU time | 0.68 seconds |
| Started | Jan 07 12:49:54 PM PST 24 |
| Finished | Jan 07 12:51:26 PM PST 24 |
| Peak memory | 197740 kb |
| Host | smart-43947f8e-a18d-4fd5-b97c-ed263044f460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387702247 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1387702247 |
| Directory | /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2165743814 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 38380046 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 12:50:02 PM PST 24 |
| Finished | Jan 07 12:51:40 PM PST 24 |
| Peak memory | 193508 kb |
| Host | smart-bde21b00-6790-43ca-8faf-39c2b0232317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165743814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio _csr_rw.2165743814 |
| Directory | /workspace/0.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_intr_test.3554926999 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 33187344 ps |
| CPU time | 0.6 seconds |
| Started | Jan 07 12:50:21 PM PST 24 |
| Finished | Jan 07 12:51:39 PM PST 24 |
| Peak memory | 194060 kb |
| Host | smart-a282a6c4-bdb0-4114-8906-c4b32e0383b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554926999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3554926999 |
| Directory | /workspace/0.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2084799204 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 62409237 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 12:50:10 PM PST 24 |
| Finished | Jan 07 12:51:37 PM PST 24 |
| Peak memory | 197372 kb |
| Host | smart-a13eb4c8-fad1-4512-b5c5-521686ca3298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084799204 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.gpio_same_csr_outstanding.2084799204 |
| Directory | /workspace/0.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1973863395 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 66501312 ps |
| CPU time | 1.34 seconds |
| Started | Jan 07 12:50:19 PM PST 24 |
| Finished | Jan 07 12:52:02 PM PST 24 |
| Peak memory | 198424 kb |
| Host | smart-f2a2ccc0-0dc1-46e1-962c-3955d30ac739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973863395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1973863395 |
| Directory | /workspace/0.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.235911705 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 199892296 ps |
| CPU time | 0.82 seconds |
| Started | Jan 07 12:50:29 PM PST 24 |
| Finished | Jan 07 12:51:50 PM PST 24 |
| Peak memory | 197264 kb |
| Host | smart-969261c0-83b9-42db-92b1-7a7e0df8df9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235911705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.gpio_tl_intg_err.235911705 |
| Directory | /workspace/0.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.295255257 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 30438168 ps |
| CPU time | 0.63 seconds |
| Started | Jan 07 12:49:54 PM PST 24 |
| Finished | Jan 07 12:51:30 PM PST 24 |
| Peak memory | 195484 kb |
| Host | smart-27eadae3-dbbf-452d-8b1a-61157dd46331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295255257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.295255257 |
| Directory | /workspace/1.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1312481504 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 23443845 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 12:49:58 PM PST 24 |
| Finished | Jan 07 12:51:21 PM PST 24 |
| Peak memory | 195580 kb |
| Host | smart-14e65546-cd9b-4571-bb51-9959b8604b0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312481504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio _csr_rw.1312481504 |
| Directory | /workspace/1.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_intr_test.1730505383 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 40067433 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 12:50:03 PM PST 24 |
| Finished | Jan 07 12:51:24 PM PST 24 |
| Peak memory | 194816 kb |
| Host | smart-e962d012-70ed-469a-a61c-8e17501326a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730505383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1730505383 |
| Directory | /workspace/1.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.4221505291 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 96586269 ps |
| CPU time | 0.72 seconds |
| Started | Jan 07 12:50:17 PM PST 24 |
| Finished | Jan 07 12:51:52 PM PST 24 |
| Peak memory | 196196 kb |
| Host | smart-b6efc513-ec0f-4c1b-a5ec-2ce93f263dde |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221505291 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.gpio_same_csr_outstanding.4221505291 |
| Directory | /workspace/1.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2951046205 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 41019563 ps |
| CPU time | 1.92 seconds |
| Started | Jan 07 12:49:44 PM PST 24 |
| Finished | Jan 07 12:51:19 PM PST 24 |
| Peak memory | 198328 kb |
| Host | smart-9bcae407-b698-4d07-a13e-fbdeaad8de1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951046205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2951046205 |
| Directory | /workspace/1.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1678912593 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 637289890 ps |
| CPU time | 1.21 seconds |
| Started | Jan 07 12:49:44 PM PST 24 |
| Finished | Jan 07 12:50:55 PM PST 24 |
| Peak memory | 197876 kb |
| Host | smart-5d7f265a-5c76-47a6-a4ec-b10dc5c09aaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678912593 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 1.gpio_tl_intg_err.1678912593 |
| Directory | /workspace/1.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1062152581 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 30838620 ps |
| CPU time | 0.94 seconds |
| Started | Jan 07 12:50:13 PM PST 24 |
| Finished | Jan 07 12:51:51 PM PST 24 |
| Peak memory | 198160 kb |
| Host | smart-1210840e-7dad-43fb-8339-251c97835ca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062152581 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1062152581 |
| Directory | /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_intr_test.3872573574 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 15811473 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 12:50:54 PM PST 24 |
| Finished | Jan 07 12:52:06 PM PST 24 |
| Peak memory | 192152 kb |
| Host | smart-98ad2929-9851-4aea-8375-958483f8b624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872573574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3872573574 |
| Directory | /workspace/10.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.103988939 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 63203654 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 12:50:03 PM PST 24 |
| Finished | Jan 07 12:51:21 PM PST 24 |
| Peak memory | 194744 kb |
| Host | smart-158bab30-74a3-4e63-8a3c-b3715b52c2bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103988939 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 10.gpio_same_csr_outstanding.103988939 |
| Directory | /workspace/10.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1339877609 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 362928547 ps |
| CPU time | 1.94 seconds |
| Started | Jan 07 12:50:01 PM PST 24 |
| Finished | Jan 07 12:51:08 PM PST 24 |
| Peak memory | 198348 kb |
| Host | smart-862f5cc3-464e-4823-bc69-3e81236e9ef0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339877609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1339877609 |
| Directory | /workspace/10.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.251638380 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 46106547 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 12:50:37 PM PST 24 |
| Finished | Jan 07 12:52:05 PM PST 24 |
| Peak memory | 197776 kb |
| Host | smart-5b8de696-0e4b-4e81-bae9-7654d4c4a818 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251638380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.gpio_tl_intg_err.251638380 |
| Directory | /workspace/10.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2473438697 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 31419330 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 12:50:54 PM PST 24 |
| Finished | Jan 07 12:52:06 PM PST 24 |
| Peak memory | 193120 kb |
| Host | smart-528f2058-9c46-47fc-a9a2-cf133f00d06d |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473438697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi o_csr_rw.2473438697 |
| Directory | /workspace/11.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2871698932 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 32703909 ps |
| CPU time | 0.83 seconds |
| Started | Jan 07 12:49:59 PM PST 24 |
| Finished | Jan 07 12:51:43 PM PST 24 |
| Peak memory | 196680 kb |
| Host | smart-b0a4b1a6-75df-41b8-8790-3a8e0677074e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871698932 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 11.gpio_same_csr_outstanding.2871698932 |
| Directory | /workspace/11.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_tl_errors.4171494551 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 52046559 ps |
| CPU time | 2.38 seconds |
| Started | Jan 07 12:50:11 PM PST 24 |
| Finished | Jan 07 12:51:41 PM PST 24 |
| Peak memory | 198352 kb |
| Host | smart-2d7127d7-c981-4441-a58e-e5c9ac433a31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171494551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.4171494551 |
| Directory | /workspace/11.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1198681002 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 140663283 ps |
| CPU time | 1.46 seconds |
| Started | Jan 07 12:50:10 PM PST 24 |
| Finished | Jan 07 12:52:00 PM PST 24 |
| Peak memory | 198324 kb |
| Host | smart-3b119461-851a-4c07-bcd1-61b081daa73e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198681002 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 11.gpio_tl_intg_err.1198681002 |
| Directory | /workspace/11.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2111208496 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 30297782 ps |
| CPU time | 1.58 seconds |
| Started | Jan 07 12:50:18 PM PST 24 |
| Finished | Jan 07 12:51:53 PM PST 24 |
| Peak memory | 198352 kb |
| Host | smart-023654c3-c6c9-458c-a761-f7463d133968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111208496 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2111208496 |
| Directory | /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3042169015 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 12567151 ps |
| CPU time | 0.64 seconds |
| Started | Jan 07 12:49:59 PM PST 24 |
| Finished | Jan 07 12:51:17 PM PST 24 |
| Peak memory | 195896 kb |
| Host | smart-8df06655-28bb-45ab-82c3-f438e52d15e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042169015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi o_csr_rw.3042169015 |
| Directory | /workspace/12.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_intr_test.2916427950 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 63357482 ps |
| CPU time | 0.63 seconds |
| Started | Jan 07 12:50:24 PM PST 24 |
| Finished | Jan 07 12:51:47 PM PST 24 |
| Peak memory | 194632 kb |
| Host | smart-ba3ef174-e3c3-40fb-b237-f2d0736be5e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916427950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2916427950 |
| Directory | /workspace/12.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3022132821 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 17445962 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 12:50:10 PM PST 24 |
| Finished | Jan 07 12:51:37 PM PST 24 |
| Peak memory | 194932 kb |
| Host | smart-297e1efe-f940-4ecc-b793-8bf452b4481c |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022132821 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 12.gpio_same_csr_outstanding.3022132821 |
| Directory | /workspace/12.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2338066789 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 341908757 ps |
| CPU time | 1.36 seconds |
| Started | Jan 07 12:50:07 PM PST 24 |
| Finished | Jan 07 12:51:34 PM PST 24 |
| Peak memory | 198388 kb |
| Host | smart-a6187466-0492-4e17-8244-3530756b7e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338066789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2338066789 |
| Directory | /workspace/12.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1876617637 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 23323648 ps |
| CPU time | 0.78 seconds |
| Started | Jan 07 12:49:58 PM PST 24 |
| Finished | Jan 07 12:51:21 PM PST 24 |
| Peak memory | 198148 kb |
| Host | smart-6fc7a3cd-b456-4b3a-b91f-63a6f9c1c66a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876617637 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1876617637 |
| Directory | /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1750772201 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 16213934 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 12:50:17 PM PST 24 |
| Finished | Jan 07 12:52:00 PM PST 24 |
| Peak memory | 195272 kb |
| Host | smart-f1474488-ced0-4f4c-bfef-f1b5b7c0eeb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750772201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi o_csr_rw.1750772201 |
| Directory | /workspace/13.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.785079092 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 37348169 ps |
| CPU time | 0.65 seconds |
| Started | Jan 07 12:50:26 PM PST 24 |
| Finished | Jan 07 12:52:28 PM PST 24 |
| Peak memory | 195608 kb |
| Host | smart-a8ceb692-7113-4582-83b2-dfcce27132d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785079092 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 13.gpio_same_csr_outstanding.785079092 |
| Directory | /workspace/13.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.926377371 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 46285999 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 12:49:49 PM PST 24 |
| Finished | Jan 07 12:51:08 PM PST 24 |
| Peak memory | 197364 kb |
| Host | smart-c7309c00-fcab-4bd5-8ead-b45500fdf6e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926377371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.gpio_tl_intg_err.926377371 |
| Directory | /workspace/13.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3692961884 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 22419887 ps |
| CPU time | 1.05 seconds |
| Started | Jan 07 12:50:01 PM PST 24 |
| Finished | Jan 07 12:51:07 PM PST 24 |
| Peak memory | 198132 kb |
| Host | smart-dafa1a3b-74d5-4493-83db-42417abb9fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692961884 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3692961884 |
| Directory | /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2022867278 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 46368832 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 12:50:29 PM PST 24 |
| Finished | Jan 07 12:51:51 PM PST 24 |
| Peak memory | 195428 kb |
| Host | smart-8d4bb886-db29-4cd6-b442-c8c31cdf536e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022867278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi o_csr_rw.2022867278 |
| Directory | /workspace/14.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_intr_test.4167578675 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 16271007 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 12:50:05 PM PST 24 |
| Finished | Jan 07 12:51:31 PM PST 24 |
| Peak memory | 193916 kb |
| Host | smart-fe08130f-3fa6-453e-8b6f-0cfeaf175b9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167578675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4167578675 |
| Directory | /workspace/14.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3306832060 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 242044961 ps |
| CPU time | 0.81 seconds |
| Started | Jan 07 12:50:12 PM PST 24 |
| Finished | Jan 07 12:51:25 PM PST 24 |
| Peak memory | 196580 kb |
| Host | smart-9ddbf03f-b414-4fd2-837e-048033e0d50b |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306832060 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 14.gpio_same_csr_outstanding.3306832060 |
| Directory | /workspace/14.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1330322706 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 652085477 ps |
| CPU time | 3.04 seconds |
| Started | Jan 07 12:50:07 PM PST 24 |
| Finished | Jan 07 12:51:39 PM PST 24 |
| Peak memory | 198320 kb |
| Host | smart-e9d7aef1-5d6b-4548-a633-6d3e837d6a12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330322706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1330322706 |
| Directory | /workspace/14.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3905890365 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 126324527 ps |
| CPU time | 1.4 seconds |
| Started | Jan 07 12:49:58 PM PST 24 |
| Finished | Jan 07 12:51:41 PM PST 24 |
| Peak memory | 198292 kb |
| Host | smart-2e8ffeb7-e529-476e-aacb-c65f04bc2181 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905890365 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 14.gpio_tl_intg_err.3905890365 |
| Directory | /workspace/14.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3766332847 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 15257587 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 12:50:01 PM PST 24 |
| Finished | Jan 07 12:51:10 PM PST 24 |
| Peak memory | 194896 kb |
| Host | smart-adc605d5-4bde-4c93-9eef-bba0a2232252 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766332847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi o_csr_rw.3766332847 |
| Directory | /workspace/15.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1633328340 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 171916308 ps |
| CPU time | 0.85 seconds |
| Started | Jan 07 12:50:07 PM PST 24 |
| Finished | Jan 07 12:51:37 PM PST 24 |
| Peak memory | 197356 kb |
| Host | smart-05957135-4fcf-4f3e-a3ef-38a2605d3068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633328340 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 15.gpio_tl_intg_err.1633328340 |
| Directory | /workspace/15.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1264716460 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 12171322 ps |
| CPU time | 0.59 seconds |
| Started | Jan 07 12:49:55 PM PST 24 |
| Finished | Jan 07 12:51:27 PM PST 24 |
| Peak memory | 194928 kb |
| Host | smart-46cb8c00-4b3a-4749-be6e-cfaf538da397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264716460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi o_csr_rw.1264716460 |
| Directory | /workspace/16.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_intr_test.2062943146 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 18295898 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 12:49:53 PM PST 24 |
| Finished | Jan 07 12:51:09 PM PST 24 |
| Peak memory | 193908 kb |
| Host | smart-34133502-91ab-49a2-a4ff-db242b14f36b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062943146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2062943146 |
| Directory | /workspace/16.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1775566898 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 19251935 ps |
| CPU time | 0.73 seconds |
| Started | Jan 07 12:49:52 PM PST 24 |
| Finished | Jan 07 12:51:40 PM PST 24 |
| Peak memory | 196476 kb |
| Host | smart-c7de5e73-4eb4-4831-b5fb-c547b1a71f84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775566898 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 16.gpio_same_csr_outstanding.1775566898 |
| Directory | /workspace/16.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_tl_errors.971447277 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 86884015 ps |
| CPU time | 1.94 seconds |
| Started | Jan 07 12:50:23 PM PST 24 |
| Finished | Jan 07 12:51:43 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-1e6b2edf-00cf-4077-a600-d44d99e7a660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971447277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.971447277 |
| Directory | /workspace/16.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1880478527 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 21583869 ps |
| CPU time | 0.55 seconds |
| Started | Jan 07 12:51:02 PM PST 24 |
| Finished | Jan 07 12:52:37 PM PST 24 |
| Peak memory | 193900 kb |
| Host | smart-2d4cfa2e-b833-4273-ac7a-b50cde8a70d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880478527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi o_csr_rw.1880478527 |
| Directory | /workspace/17.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_intr_test.242908818 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 17125888 ps |
| CPU time | 0.6 seconds |
| Started | Jan 07 12:50:40 PM PST 24 |
| Finished | Jan 07 12:53:37 PM PST 24 |
| Peak memory | 194032 kb |
| Host | smart-2b100cad-b3a6-4d6f-985d-1c42134de6e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242908818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.242908818 |
| Directory | /workspace/17.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.110707801 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 18185793 ps |
| CPU time | 0.72 seconds |
| Started | Jan 07 12:50:02 PM PST 24 |
| Finished | Jan 07 12:51:13 PM PST 24 |
| Peak memory | 195928 kb |
| Host | smart-4c218716-09e0-437a-93cf-419d3e7cf992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110707801 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 17.gpio_same_csr_outstanding.110707801 |
| Directory | /workspace/17.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1215270024 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 60340781 ps |
| CPU time | 1.48 seconds |
| Started | Jan 07 12:50:16 PM PST 24 |
| Finished | Jan 07 12:51:20 PM PST 24 |
| Peak memory | 198452 kb |
| Host | smart-690d3ca9-b92f-4dc5-8f9a-f032bba0c0e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215270024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1215270024 |
| Directory | /workspace/17.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_intr_test.2429580518 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 19451212 ps |
| CPU time | 0.65 seconds |
| Started | Jan 07 01:01:36 PM PST 24 |
| Finished | Jan 07 01:02:02 PM PST 24 |
| Peak memory | 193988 kb |
| Host | smart-66d2a654-1b88-4ba2-b062-1b69208f2fd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429580518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2429580518 |
| Directory | /workspace/18.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3840946716 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 42444027 ps |
| CPU time | 1.13 seconds |
| Started | Jan 07 12:50:32 PM PST 24 |
| Finished | Jan 07 12:52:05 PM PST 24 |
| Peak memory | 198380 kb |
| Host | smart-c2835fdf-7332-4497-86c3-50195d57b61b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840946716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3840946716 |
| Directory | /workspace/18.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3934771991 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 332185645 ps |
| CPU time | 1.42 seconds |
| Started | Jan 07 12:50:40 PM PST 24 |
| Finished | Jan 07 12:52:29 PM PST 24 |
| Peak memory | 198272 kb |
| Host | smart-c85ac7c6-0c82-4c05-adec-4e280622895e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934771991 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 18.gpio_tl_intg_err.3934771991 |
| Directory | /workspace/18.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3696082378 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 65404248 ps |
| CPU time | 0.78 seconds |
| Started | Jan 07 12:50:35 PM PST 24 |
| Finished | Jan 07 12:51:53 PM PST 24 |
| Peak memory | 198160 kb |
| Host | smart-b3f9e11b-ba75-4103-9c2f-cd7eebe9e423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696082378 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3696082378 |
| Directory | /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_csr_rw.957424447 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 14793137 ps |
| CPU time | 0.6 seconds |
| Started | Jan 07 12:56:49 PM PST 24 |
| Finished | Jan 07 12:58:29 PM PST 24 |
| Peak memory | 194576 kb |
| Host | smart-1089d460-65e5-4172-86ce-03f47a887c98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957424447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio _csr_rw.957424447 |
| Directory | /workspace/19.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_intr_test.1669537635 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 81534280 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 12:50:28 PM PST 24 |
| Finished | Jan 07 12:51:37 PM PST 24 |
| Peak memory | 193924 kb |
| Host | smart-6750e6f8-f819-459f-9774-b7f59610d137 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669537635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1669537635 |
| Directory | /workspace/19.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2636900110 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 38685229 ps |
| CPU time | 0.86 seconds |
| Started | Jan 07 12:50:23 PM PST 24 |
| Finished | Jan 07 12:52:00 PM PST 24 |
| Peak memory | 197976 kb |
| Host | smart-19f9d01d-6c8e-4f76-9dc5-57cb0c21f09d |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636900110 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 19.gpio_same_csr_outstanding.2636900110 |
| Directory | /workspace/19.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2922743387 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1310240946 ps |
| CPU time | 2.04 seconds |
| Started | Jan 07 12:57:13 PM PST 24 |
| Finished | Jan 07 12:58:44 PM PST 24 |
| Peak memory | 197904 kb |
| Host | smart-59e3b597-c5b5-4ea1-8286-0fb2a318d2d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922743387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2922743387 |
| Directory | /workspace/19.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3671561420 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 47004137 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 12:49:58 PM PST 24 |
| Finished | Jan 07 12:51:04 PM PST 24 |
| Peak memory | 197476 kb |
| Host | smart-f6d463ea-bf8a-4bef-b82e-9804b23069a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671561420 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 19.gpio_tl_intg_err.3671561420 |
| Directory | /workspace/19.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1190178699 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 769171871 ps |
| CPU time | 2.35 seconds |
| Started | Jan 07 12:50:10 PM PST 24 |
| Finished | Jan 07 12:51:38 PM PST 24 |
| Peak memory | 197432 kb |
| Host | smart-81c4c623-107b-4b73-a7e3-79086fb6bb6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190178699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1190178699 |
| Directory | /workspace/2.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3063583802 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 179279906 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 12:50:15 PM PST 24 |
| Finished | Jan 07 12:51:19 PM PST 24 |
| Peak memory | 195080 kb |
| Host | smart-0ccfe15a-7f33-43fc-a873-1fdfd3c5ec4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063583802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3063583802 |
| Directory | /workspace/2.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_rw.520020082 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 42469345 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 12:50:28 PM PST 24 |
| Finished | Jan 07 12:52:19 PM PST 24 |
| Peak memory | 195232 kb |
| Host | smart-4bd36c21-9ff5-4789-9797-89f8c57ad626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520020082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_ csr_rw.520020082 |
| Directory | /workspace/2.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_intr_test.79227855 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 67463338 ps |
| CPU time | 0.59 seconds |
| Started | Jan 07 12:50:00 PM PST 24 |
| Finished | Jan 07 12:51:40 PM PST 24 |
| Peak memory | 194124 kb |
| Host | smart-1be4e604-944b-4623-922e-c79d6836dd8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79227855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.79227855 |
| Directory | /workspace/2.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1880373697 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 14609563 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 12:49:48 PM PST 24 |
| Finished | Jan 07 12:50:59 PM PST 24 |
| Peak memory | 195736 kb |
| Host | smart-91421ccd-27d5-4089-a313-2059fca8e529 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880373697 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.gpio_same_csr_outstanding.1880373697 |
| Directory | /workspace/2.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4211069314 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 569448689 ps |
| CPU time | 1.06 seconds |
| Started | Jan 07 12:49:40 PM PST 24 |
| Finished | Jan 07 12:50:59 PM PST 24 |
| Peak memory | 198220 kb |
| Host | smart-f0dd08c9-9930-4937-b4dd-78c2d1436dc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211069314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.4211069314 |
| Directory | /workspace/2.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.318497164 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 309944637 ps |
| CPU time | 1.12 seconds |
| Started | Jan 07 12:49:33 PM PST 24 |
| Finished | Jan 07 12:51:00 PM PST 24 |
| Peak memory | 198284 kb |
| Host | smart-6af0bfe5-f0fe-4510-a001-142b970898cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318497164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.gpio_tl_intg_err.318497164 |
| Directory | /workspace/2.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.gpio_intr_test.1789687921 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 95573734 ps |
| CPU time | 0.66 seconds |
| Started | Jan 07 12:56:29 PM PST 24 |
| Finished | Jan 07 12:58:01 PM PST 24 |
| Peak memory | 192992 kb |
| Host | smart-e46895ff-e143-44fe-b892-277e0ac1c3cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789687921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1789687921 |
| Directory | /workspace/20.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.gpio_intr_test.2695187371 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 58077223 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 12:56:49 PM PST 24 |
| Finished | Jan 07 12:58:26 PM PST 24 |
| Peak memory | 193608 kb |
| Host | smart-780f0086-04f4-4dc0-81f1-fe79a2f15465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695187371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2695187371 |
| Directory | /workspace/21.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.gpio_intr_test.1185106778 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 38540046 ps |
| CPU time | 0.55 seconds |
| Started | Jan 07 12:50:45 PM PST 24 |
| Finished | Jan 07 12:52:07 PM PST 24 |
| Peak memory | 193968 kb |
| Host | smart-514cf3f4-ef9b-4313-8c87-088b4328a18a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185106778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1185106778 |
| Directory | /workspace/22.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.gpio_intr_test.503115858 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 14810507 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 12:50:09 PM PST 24 |
| Finished | Jan 07 12:51:16 PM PST 24 |
| Peak memory | 193980 kb |
| Host | smart-cd3cae7c-8044-45db-a43e-55e1eb9ff982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503115858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.503115858 |
| Directory | /workspace/23.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.gpio_intr_test.696847630 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 12791279 ps |
| CPU time | 0.59 seconds |
| Started | Jan 07 12:50:15 PM PST 24 |
| Finished | Jan 07 12:51:20 PM PST 24 |
| Peak memory | 194028 kb |
| Host | smart-6cc373e8-85f5-4276-8534-10e2bf1faaf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696847630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.696847630 |
| Directory | /workspace/25.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.gpio_intr_test.1344032189 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 48191545 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 12:50:10 PM PST 24 |
| Finished | Jan 07 12:51:36 PM PST 24 |
| Peak memory | 193920 kb |
| Host | smart-e01e34b7-2ed9-4aa6-9257-5ae281ff3feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344032189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1344032189 |
| Directory | /workspace/26.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.gpio_intr_test.2326165361 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 68387662 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 12:50:39 PM PST 24 |
| Finished | Jan 07 12:51:57 PM PST 24 |
| Peak memory | 194660 kb |
| Host | smart-62efd098-0895-4aa0-a803-754dee6314d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326165361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2326165361 |
| Directory | /workspace/28.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.gpio_intr_test.238386058 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 57457713 ps |
| CPU time | 0.6 seconds |
| Started | Jan 07 12:50:10 PM PST 24 |
| Finished | Jan 07 12:52:03 PM PST 24 |
| Peak memory | 193952 kb |
| Host | smart-d878b792-f49b-479e-be14-2ec8da0525e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238386058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.238386058 |
| Directory | /workspace/29.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1499177364 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 36050070 ps |
| CPU time | 0.83 seconds |
| Started | Jan 07 12:50:14 PM PST 24 |
| Finished | Jan 07 12:51:49 PM PST 24 |
| Peak memory | 196136 kb |
| Host | smart-de32ba83-1741-40a1-95c9-329295248dbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499177364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_aliasing.1499177364 |
| Directory | /workspace/3.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1003198942 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 780737891 ps |
| CPU time | 1.47 seconds |
| Started | Jan 07 12:49:57 PM PST 24 |
| Finished | Jan 07 12:52:01 PM PST 24 |
| Peak memory | 197228 kb |
| Host | smart-acb18fbf-9737-4f81-b840-630c168b562f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003198942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1003198942 |
| Directory | /workspace/3.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2045614625 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 187265202 ps |
| CPU time | 0.59 seconds |
| Started | Jan 07 12:50:20 PM PST 24 |
| Finished | Jan 07 12:51:36 PM PST 24 |
| Peak memory | 194700 kb |
| Host | smart-e5aede6d-02a0-4be0-9d2a-b7cb640ca515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045614625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2045614625 |
| Directory | /workspace/3.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1284047207 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 49213714 ps |
| CPU time | 0.84 seconds |
| Started | Jan 07 12:50:18 PM PST 24 |
| Finished | Jan 07 12:51:48 PM PST 24 |
| Peak memory | 198160 kb |
| Host | smart-50b4f265-21fd-440d-9959-56936fe3867e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284047207 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1284047207 |
| Directory | /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3797617020 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 47404280 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 12:49:30 PM PST 24 |
| Finished | Jan 07 12:50:36 PM PST 24 |
| Peak memory | 195460 kb |
| Host | smart-0f600087-08a3-4b8d-94ec-d95b3fac84c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797617020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio _csr_rw.3797617020 |
| Directory | /workspace/3.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3210292187 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 1529128285 ps |
| CPU time | 2.16 seconds |
| Started | Jan 07 12:50:12 PM PST 24 |
| Finished | Jan 07 12:51:38 PM PST 24 |
| Peak memory | 198388 kb |
| Host | smart-c57c84f0-fd18-4022-8751-722c5c35e4f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210292187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3210292187 |
| Directory | /workspace/3.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.143597138 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 154492412 ps |
| CPU time | 0.82 seconds |
| Started | Jan 07 12:50:20 PM PST 24 |
| Finished | Jan 07 12:51:38 PM PST 24 |
| Peak memory | 197216 kb |
| Host | smart-f4877dee-b0a2-42f0-9a00-8335ecf5cd30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143597138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.gpio_tl_intg_err.143597138 |
| Directory | /workspace/3.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.gpio_intr_test.654745993 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 64377089 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 12:50:08 PM PST 24 |
| Finished | Jan 07 12:51:18 PM PST 24 |
| Peak memory | 193976 kb |
| Host | smart-46dfd171-8c38-48b5-9d52-9fd487ed3928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654745993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.654745993 |
| Directory | /workspace/30.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.gpio_intr_test.127334709 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 16627137 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 12:50:09 PM PST 24 |
| Finished | Jan 07 12:51:18 PM PST 24 |
| Peak memory | 193988 kb |
| Host | smart-29edfa31-1f9c-48a4-a74a-20c8985361dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127334709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.127334709 |
| Directory | /workspace/31.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.gpio_intr_test.2996944311 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 93157230 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 12:50:15 PM PST 24 |
| Finished | Jan 07 12:51:20 PM PST 24 |
| Peak memory | 194164 kb |
| Host | smart-b1e77d04-e96b-4ced-8a2a-f03a12e271f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996944311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2996944311 |
| Directory | /workspace/33.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.gpio_intr_test.3174464598 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 53878135 ps |
| CPU time | 0.59 seconds |
| Started | Jan 07 12:50:08 PM PST 24 |
| Finished | Jan 07 12:51:40 PM PST 24 |
| Peak memory | 194004 kb |
| Host | smart-b7c59182-96ec-49e7-b7bd-b1ecdc5ed948 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174464598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3174464598 |
| Directory | /workspace/34.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.gpio_intr_test.974544644 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 40134441 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 12:50:32 PM PST 24 |
| Finished | Jan 07 12:51:53 PM PST 24 |
| Peak memory | 193852 kb |
| Host | smart-1e1d5f01-e3f4-4158-ab09-768803a8e4aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974544644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.974544644 |
| Directory | /workspace/35.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.gpio_intr_test.3563770732 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 15441710 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 12:50:34 PM PST 24 |
| Finished | Jan 07 12:51:54 PM PST 24 |
| Peak memory | 193924 kb |
| Host | smart-7b2b012e-b7e7-40d0-b891-799a090bfc36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563770732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3563770732 |
| Directory | /workspace/36.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.gpio_intr_test.2188581424 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 76867856 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 12:50:05 PM PST 24 |
| Finished | Jan 07 12:51:16 PM PST 24 |
| Peak memory | 194684 kb |
| Host | smart-cb415d06-1931-486a-b8ce-676f4e8f9c76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188581424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2188581424 |
| Directory | /workspace/37.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.gpio_intr_test.1932008287 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 24225335 ps |
| CPU time | 0.59 seconds |
| Started | Jan 07 12:50:42 PM PST 24 |
| Finished | Jan 07 12:52:20 PM PST 24 |
| Peak memory | 193992 kb |
| Host | smart-1658e678-61f9-4d16-a2af-e2bc2deeaa12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932008287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1932008287 |
| Directory | /workspace/38.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.gpio_intr_test.3557065788 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 21977524 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 12:50:24 PM PST 24 |
| Finished | Jan 07 12:51:38 PM PST 24 |
| Peak memory | 193984 kb |
| Host | smart-26753a97-a574-4908-9896-8b1edc4d861f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557065788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3557065788 |
| Directory | /workspace/39.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1291864020 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 150558046 ps |
| CPU time | 0.86 seconds |
| Started | Jan 07 12:50:10 PM PST 24 |
| Finished | Jan 07 12:51:59 PM PST 24 |
| Peak memory | 196972 kb |
| Host | smart-394c16a9-476d-42c7-a93d-a5f5e88d27d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291864020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_aliasing.1291864020 |
| Directory | /workspace/4.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2352270087 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 225328617 ps |
| CPU time | 2.1 seconds |
| Started | Jan 07 12:50:02 PM PST 24 |
| Finished | Jan 07 12:51:42 PM PST 24 |
| Peak memory | 197256 kb |
| Host | smart-853bf49f-9710-4505-b371-2d97b982fddf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352270087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2352270087 |
| Directory | /workspace/4.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3751096282 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 32050929 ps |
| CPU time | 0.84 seconds |
| Started | Jan 07 12:49:40 PM PST 24 |
| Finished | Jan 07 12:51:38 PM PST 24 |
| Peak memory | 197980 kb |
| Host | smart-c0fb6d5d-9d8f-423c-a771-4d9e826341bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751096282 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3751096282 |
| Directory | /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3153239645 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 15276881 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 12:49:54 PM PST 24 |
| Finished | Jan 07 12:51:18 PM PST 24 |
| Peak memory | 195168 kb |
| Host | smart-28af6a42-cbcb-46ae-8131-2d8b9a76018d |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153239645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio _csr_rw.3153239645 |
| Directory | /workspace/4.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1670149028 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 39087533 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 12:50:01 PM PST 24 |
| Finished | Jan 07 12:51:20 PM PST 24 |
| Peak memory | 195528 kb |
| Host | smart-631e0d2d-9d2a-46bf-a78f-cad1072a4241 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670149028 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.gpio_same_csr_outstanding.1670149028 |
| Directory | /workspace/4.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_tl_errors.786744092 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 222436625 ps |
| CPU time | 1.4 seconds |
| Started | Jan 07 12:49:45 PM PST 24 |
| Finished | Jan 07 12:50:55 PM PST 24 |
| Peak memory | 198392 kb |
| Host | smart-4ccb1514-2203-4213-bb61-2e102f7cff47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786744092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.786744092 |
| Directory | /workspace/4.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/40.gpio_intr_test.2016329926 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 56332432 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 12:49:57 PM PST 24 |
| Finished | Jan 07 12:51:36 PM PST 24 |
| Peak memory | 194084 kb |
| Host | smart-1232995a-37bc-477a-abb2-c5034a033848 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016329926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2016329926 |
| Directory | /workspace/40.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.gpio_intr_test.284903859 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 20098146 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 12:50:22 PM PST 24 |
| Finished | Jan 07 12:51:53 PM PST 24 |
| Peak memory | 194588 kb |
| Host | smart-35178c44-44b0-4359-84a0-74ae9b790152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284903859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.284903859 |
| Directory | /workspace/41.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.gpio_intr_test.617312715 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 14805253 ps |
| CPU time | 0.59 seconds |
| Started | Jan 07 12:50:20 PM PST 24 |
| Finished | Jan 07 12:51:40 PM PST 24 |
| Peak memory | 193904 kb |
| Host | smart-1e19a473-9820-443b-bcd1-789ecca9a2a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617312715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.617312715 |
| Directory | /workspace/44.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.gpio_intr_test.3508288004 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 13080239 ps |
| CPU time | 0.6 seconds |
| Started | Jan 07 12:50:07 PM PST 24 |
| Finished | Jan 07 12:51:33 PM PST 24 |
| Peak memory | 194108 kb |
| Host | smart-744b5117-3da6-417a-91f4-08ae7901e603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508288004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3508288004 |
| Directory | /workspace/45.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.gpio_intr_test.2518018255 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 14741191 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 12:50:10 PM PST 24 |
| Finished | Jan 07 12:51:33 PM PST 24 |
| Peak memory | 194056 kb |
| Host | smart-5fa996a0-2ec5-4a45-8d02-a9f8cb234968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518018255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2518018255 |
| Directory | /workspace/46.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.gpio_intr_test.4200381519 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 29284123 ps |
| CPU time | 0.59 seconds |
| Started | Jan 07 12:50:36 PM PST 24 |
| Finished | Jan 07 12:51:59 PM PST 24 |
| Peak memory | 194748 kb |
| Host | smart-6eadd3d9-b59f-445f-9541-d0ecf3b7a8c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200381519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.4200381519 |
| Directory | /workspace/48.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.gpio_intr_test.2300005698 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 55969605 ps |
| CPU time | 0.6 seconds |
| Started | Jan 07 12:50:24 PM PST 24 |
| Finished | Jan 07 12:51:38 PM PST 24 |
| Peak memory | 194644 kb |
| Host | smart-968fcedc-d437-4db5-974c-f13d0d31532c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300005698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2300005698 |
| Directory | /workspace/49.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2239446693 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 181990003 ps |
| CPU time | 1.36 seconds |
| Started | Jan 07 12:50:06 PM PST 24 |
| Finished | Jan 07 12:51:48 PM PST 24 |
| Peak memory | 198436 kb |
| Host | smart-51af4471-9c5c-4d61-b271-5628d3ac4ee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239446693 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2239446693 |
| Directory | /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3062056260 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 68738412 ps |
| CPU time | 0.68 seconds |
| Started | Jan 07 12:50:11 PM PST 24 |
| Finished | Jan 07 12:51:39 PM PST 24 |
| Peak memory | 194788 kb |
| Host | smart-fce991d8-d77f-4255-99c5-03bcda8c8523 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062056260 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 5.gpio_same_csr_outstanding.3062056260 |
| Directory | /workspace/5.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2654963771 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 48401821 ps |
| CPU time | 1.23 seconds |
| Started | Jan 07 12:49:43 PM PST 24 |
| Finished | Jan 07 12:50:57 PM PST 24 |
| Peak memory | 198404 kb |
| Host | smart-15e5d424-f3c7-4d08-a0db-90bd53e5709f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654963771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2654963771 |
| Directory | /workspace/5.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3928309411 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 54843796 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 12:50:04 PM PST 24 |
| Finished | Jan 07 12:52:03 PM PST 24 |
| Peak memory | 198080 kb |
| Host | smart-46a7c321-2b28-4515-8291-a1dda3336546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928309411 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 5.gpio_tl_intg_err.3928309411 |
| Directory | /workspace/5.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3452755842 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 38515769 ps |
| CPU time | 0.82 seconds |
| Started | Jan 07 12:49:57 PM PST 24 |
| Finished | Jan 07 12:51:43 PM PST 24 |
| Peak memory | 198136 kb |
| Host | smart-6c63a6d3-9a23-47a6-80ef-7b6cae2383af |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452755842 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3452755842 |
| Directory | /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1420685110 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 13575074 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 12:50:28 PM PST 24 |
| Finished | Jan 07 12:52:19 PM PST 24 |
| Peak memory | 195148 kb |
| Host | smart-7d7bc9ae-f0c5-411f-87ac-6e0e452e9dc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420685110 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 6.gpio_same_csr_outstanding.1420685110 |
| Directory | /workspace/6.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_tl_errors.372536859 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 410972116 ps |
| CPU time | 1.94 seconds |
| Started | Jan 07 12:49:52 PM PST 24 |
| Finished | Jan 07 12:51:23 PM PST 24 |
| Peak memory | 198284 kb |
| Host | smart-5b790b64-4236-4a2b-83cb-59bc91833413 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372536859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.372536859 |
| Directory | /workspace/6.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4094459675 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 43458119 ps |
| CPU time | 0.77 seconds |
| Started | Jan 07 12:49:54 PM PST 24 |
| Finished | Jan 07 12:51:38 PM PST 24 |
| Peak memory | 198180 kb |
| Host | smart-e5fc7f08-a9e6-4af7-8e36-f369d00a412e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094459675 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4094459675 |
| Directory | /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1612663350 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 42470286 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 12:50:27 PM PST 24 |
| Finished | Jan 07 12:51:47 PM PST 24 |
| Peak memory | 194884 kb |
| Host | smart-fecdc6eb-cc31-4da4-93a8-8d8e2f1422ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612663350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio _csr_rw.1612663350 |
| Directory | /workspace/7.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_intr_test.220378398 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13089684 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 12:49:55 PM PST 24 |
| Finished | Jan 07 12:51:12 PM PST 24 |
| Peak memory | 193936 kb |
| Host | smart-8c1d7e85-b0e5-4da2-8f31-1b28a8dc04a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220378398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.220378398 |
| Directory | /workspace/7.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1090295129 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 16136287 ps |
| CPU time | 0.71 seconds |
| Started | Jan 07 12:50:12 PM PST 24 |
| Finished | Jan 07 12:51:42 PM PST 24 |
| Peak memory | 196252 kb |
| Host | smart-b8f31b2c-07b8-4835-bc3c-48598d0c176a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090295129 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 7.gpio_same_csr_outstanding.1090295129 |
| Directory | /workspace/7.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3980306796 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 52735934 ps |
| CPU time | 1.32 seconds |
| Started | Jan 07 12:49:58 PM PST 24 |
| Finished | Jan 07 12:51:08 PM PST 24 |
| Peak memory | 198420 kb |
| Host | smart-5b9f5488-8691-4880-b599-c1bc80c00147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980306796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3980306796 |
| Directory | /workspace/7.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2016738645 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 234413503 ps |
| CPU time | 1.35 seconds |
| Started | Jan 07 12:49:58 PM PST 24 |
| Finished | Jan 07 12:51:39 PM PST 24 |
| Peak memory | 198248 kb |
| Host | smart-a56b2d41-d932-439d-97d7-0dfdab72cdf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016738645 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 7.gpio_tl_intg_err.2016738645 |
| Directory | /workspace/7.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.483231020 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 31992840 ps |
| CPU time | 1.43 seconds |
| Started | Jan 07 12:49:57 PM PST 24 |
| Finished | Jan 07 12:51:41 PM PST 24 |
| Peak memory | 198336 kb |
| Host | smart-672b6417-308d-427d-8f59-b64ed8e14288 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483231020 -asser t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.483231020 |
| Directory | /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_csr_rw.690691945 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 15399157 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 12:50:25 PM PST 24 |
| Finished | Jan 07 12:51:30 PM PST 24 |
| Peak memory | 195360 kb |
| Host | smart-c06111d3-4361-4c0b-a7b9-35402ee0aa34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690691945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_ csr_rw.690691945 |
| Directory | /workspace/8.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_intr_test.2561756594 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 16389941 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 12:50:18 PM PST 24 |
| Finished | Jan 07 12:51:54 PM PST 24 |
| Peak memory | 194736 kb |
| Host | smart-a94b0eea-69eb-43e1-b8b4-c37a6b84ccc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561756594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2561756594 |
| Directory | /workspace/8.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4222413370 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 64104360 ps |
| CPU time | 0.84 seconds |
| Started | Jan 07 12:50:44 PM PST 24 |
| Finished | Jan 07 12:51:56 PM PST 24 |
| Peak memory | 195480 kb |
| Host | smart-73e2b672-9452-4ec4-94b0-e46ec08b4d83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222413370 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 8.gpio_same_csr_outstanding.4222413370 |
| Directory | /workspace/8.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1956214794 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 79885682 ps |
| CPU time | 1.83 seconds |
| Started | Jan 07 12:49:55 PM PST 24 |
| Finished | Jan 07 12:51:17 PM PST 24 |
| Peak memory | 198464 kb |
| Host | smart-24c8cee9-61cd-4a4a-9802-31b52cec66ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956214794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1956214794 |
| Directory | /workspace/8.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2276592074 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 508764681 ps |
| CPU time | 1.29 seconds |
| Started | Jan 07 12:51:08 PM PST 24 |
| Finished | Jan 07 12:52:44 PM PST 24 |
| Peak memory | 197868 kb |
| Host | smart-8cd2a4d0-d93d-4d02-bbaf-48113931ff85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276592074 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 8.gpio_tl_intg_err.2276592074 |
| Directory | /workspace/8.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.4003608738 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 52633660 ps |
| CPU time | 0.86 seconds |
| Started | Jan 07 12:49:54 PM PST 24 |
| Finished | Jan 07 12:51:35 PM PST 24 |
| Peak memory | 198060 kb |
| Host | smart-f6e947f8-326c-4324-b74f-c40eb89f4d4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003608738 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.4003608738 |
| Directory | /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1493678631 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 67206809 ps |
| CPU time | 0.59 seconds |
| Started | Jan 07 12:49:51 PM PST 24 |
| Finished | Jan 07 12:51:10 PM PST 24 |
| Peak memory | 195228 kb |
| Host | smart-1b4117cb-1b4b-4fd6-899e-b1fd163fce84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493678631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio _csr_rw.1493678631 |
| Directory | /workspace/9.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_intr_test.3512938986 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 11833486 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 12:49:52 PM PST 24 |
| Finished | Jan 07 12:51:13 PM PST 24 |
| Peak memory | 193916 kb |
| Host | smart-fef7c64c-cd40-44fe-a0f9-544526712171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512938986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3512938986 |
| Directory | /workspace/9.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3258690239 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 51695091 ps |
| CPU time | 0.73 seconds |
| Started | Jan 07 12:50:03 PM PST 24 |
| Finished | Jan 07 12:52:13 PM PST 24 |
| Peak memory | 196508 kb |
| Host | smart-dc428993-d8eb-4351-809d-efc6985bd5ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258690239 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 9.gpio_same_csr_outstanding.3258690239 |
| Directory | /workspace/9.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.408474039 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 293982571 ps |
| CPU time | 1.11 seconds |
| Started | Jan 07 12:50:24 PM PST 24 |
| Finished | Jan 07 12:51:34 PM PST 24 |
| Peak memory | 198452 kb |
| Host | smart-3ed68fef-a4d8-4fec-97f0-a5dd6e917d5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408474039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.gpio_tl_intg_err.408474039 |
| Directory | /workspace/9.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.gpio_alert_test.567637557 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 14628296 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 01:31:07 PM PST 24 |
| Finished | Jan 07 01:31:15 PM PST 24 |
| Peak memory | 194260 kb |
| Host | smart-908de7de-c833-403d-93ce-012c551250a9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567637557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.567637557 |
| Directory | /workspace/0.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3150271430 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 50465237 ps |
| CPU time | 0.65 seconds |
| Started | Jan 07 01:31:09 PM PST 24 |
| Finished | Jan 07 01:31:18 PM PST 24 |
| Peak memory | 193932 kb |
| Host | smart-4acbed10-53aa-42b0-a595-8403be2d9a95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150271430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3150271430 |
| Directory | /workspace/0.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/0.gpio_filter_stress.1416161565 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 7100046344 ps |
| CPU time | 16.66 seconds |
| Started | Jan 07 01:31:07 PM PST 24 |
| Finished | Jan 07 01:31:31 PM PST 24 |
| Peak memory | 197164 kb |
| Host | smart-075ce19e-764c-41a1-8412-1eac8bdffa00 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416161565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres s.1416161565 |
| Directory | /workspace/0.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/0.gpio_full_random.942229983 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 60605822 ps |
| CPU time | 0.93 seconds |
| Started | Jan 07 01:31:06 PM PST 24 |
| Finished | Jan 07 01:31:14 PM PST 24 |
| Peak memory | 196704 kb |
| Host | smart-5a9ea7c7-ef5f-4830-82b2-3aecfd5b10bc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942229983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.942229983 |
| Directory | /workspace/0.gpio_full_random/latest |
| Test location | /workspace/coverage/default/0.gpio_intr_rand_pgm.1421828912 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 76251726 ps |
| CPU time | 1.17 seconds |
| Started | Jan 07 01:31:06 PM PST 24 |
| Finished | Jan 07 01:31:15 PM PST 24 |
| Peak memory | 195944 kb |
| Host | smart-01e18516-76ce-4754-b6fb-cdc8e91fe31e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421828912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1421828912 |
| Directory | /workspace/0.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.517995136 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 772077584 ps |
| CPU time | 3.32 seconds |
| Started | Jan 07 01:31:07 PM PST 24 |
| Finished | Jan 07 01:31:18 PM PST 24 |
| Peak memory | 198128 kb |
| Host | smart-fee7486a-82be-4d31-84e3-e8a577f47933 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517995136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.gpio_intr_with_filter_rand_intr_event.517995136 |
| Directory | /workspace/0.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/0.gpio_rand_intr_trigger.1965850546 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 90362621 ps |
| CPU time | 1.94 seconds |
| Started | Jan 07 01:31:06 PM PST 24 |
| Finished | Jan 07 01:31:15 PM PST 24 |
| Peak memory | 196128 kb |
| Host | smart-9f6d5116-fe3d-409a-8256-c8e6843ab5b6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965850546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger. 1965850546 |
| Directory | /workspace/0.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/0.gpio_random_dout_din.4272622723 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 101615770 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:31:03 PM PST 24 |
| Finished | Jan 07 01:31:11 PM PST 24 |
| Peak memory | 196820 kb |
| Host | smart-28e57eb3-ad8f-45bc-ad94-16a7c0501b39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4272622723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4272622723 |
| Directory | /workspace/0.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.81493331 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 24756488 ps |
| CPU time | 0.78 seconds |
| Started | Jan 07 01:31:05 PM PST 24 |
| Finished | Jan 07 01:31:13 PM PST 24 |
| Peak memory | 196168 kb |
| Host | smart-e082402a-906f-4cf5-b4d4-f2117ac3872d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81493331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_p ulldown.81493331 |
| Directory | /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2030212022 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 484607850 ps |
| CPU time | 5.88 seconds |
| Started | Jan 07 01:31:07 PM PST 24 |
| Finished | Jan 07 01:31:21 PM PST 24 |
| Peak memory | 198048 kb |
| Host | smart-be7a9d7e-175f-445f-9960-51bdb896733e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030212022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran dom_long_reg_writes_reg_reads.2030212022 |
| Directory | /workspace/0.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/0.gpio_sec_cm.100005532 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 80066194 ps |
| CPU time | 0.78 seconds |
| Started | Jan 07 01:31:03 PM PST 24 |
| Finished | Jan 07 01:31:11 PM PST 24 |
| Peak memory | 213492 kb |
| Host | smart-aa95f893-c62e-40e8-be26-d83beac5cc4f |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100005532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.100005532 |
| Directory | /workspace/0.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/0.gpio_smoke.4179981217 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 119612640 ps |
| CPU time | 1.28 seconds |
| Started | Jan 07 01:31:05 PM PST 24 |
| Finished | Jan 07 01:31:13 PM PST 24 |
| Peak memory | 198112 kb |
| Host | smart-856e7da6-1dfd-4f04-80d9-22b3f718d2c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4179981217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.4179981217 |
| Directory | /workspace/0.gpio_smoke/latest |
| Test location | /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3947733930 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 72351467 ps |
| CPU time | 1.27 seconds |
| Started | Jan 07 01:31:06 PM PST 24 |
| Finished | Jan 07 01:31:15 PM PST 24 |
| Peak memory | 195972 kb |
| Host | smart-9208f8ec-4659-4448-84e1-0b0adefd41ea |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947733930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3947733930 |
| Directory | /workspace/0.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/0.gpio_stress_all.116403908 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 39814030642 ps |
| CPU time | 104.42 seconds |
| Started | Jan 07 01:31:08 PM PST 24 |
| Finished | Jan 07 01:33:00 PM PST 24 |
| Peak memory | 198260 kb |
| Host | smart-bb8eaba1-adbe-49cc-ad8b-12829cd587a7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116403908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp io_stress_all.116403908 |
| Directory | /workspace/0.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.722728037 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 67896425228 ps |
| CPU time | 1481.82 seconds |
| Started | Jan 07 01:31:07 PM PST 24 |
| Finished | Jan 07 01:55:56 PM PST 24 |
| Peak memory | 198264 kb |
| Host | smart-5b74b647-5632-4dec-a3d5-2953db723477 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =722728037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.722728037 |
| Directory | /workspace/0.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.gpio_alert_test.429068813 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 44591725 ps |
| CPU time | 0.55 seconds |
| Started | Jan 07 01:31:18 PM PST 24 |
| Finished | Jan 07 01:31:32 PM PST 24 |
| Peak memory | 194068 kb |
| Host | smart-e551db88-3f01-4564-ac8f-ddca657b7e6e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429068813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.429068813 |
| Directory | /workspace/1.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.962349284 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 188026543 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:31:19 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 196616 kb |
| Host | smart-3a405264-40d4-4887-bf6a-27aa55630685 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962349284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.962349284 |
| Directory | /workspace/1.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/1.gpio_filter_stress.1953651082 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 381470610 ps |
| CPU time | 14.07 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:49 PM PST 24 |
| Peak memory | 196488 kb |
| Host | smart-45f8dbc3-6a05-4e9a-951f-386988022e7c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953651082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres s.1953651082 |
| Directory | /workspace/1.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/1.gpio_full_random.859532602 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 78128675 ps |
| CPU time | 0.99 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 196656 kb |
| Host | smart-62de556f-f7a7-44f9-8a61-bf098d2dd409 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859532602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.859532602 |
| Directory | /workspace/1.gpio_full_random/latest |
| Test location | /workspace/coverage/default/1.gpio_intr_rand_pgm.72354654 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 564843749 ps |
| CPU time | 1.28 seconds |
| Started | Jan 07 01:31:16 PM PST 24 |
| Finished | Jan 07 01:31:29 PM PST 24 |
| Peak memory | 197092 kb |
| Host | smart-3c397333-bc85-4f36-9519-27a0c7bb0075 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72354654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.72354654 |
| Directory | /workspace/1.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.773558890 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 105677489 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 01:31:18 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 198028 kb |
| Host | smart-ac898f16-67c1-4c56-b4fe-1c29fa5f3d80 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773558890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.gpio_intr_with_filter_rand_intr_event.773558890 |
| Directory | /workspace/1.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/1.gpio_rand_intr_trigger.2817419171 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 119881270 ps |
| CPU time | 2.45 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 198188 kb |
| Host | smart-5542af10-96c8-4aaa-b073-03ec71625004 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817419171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger. 2817419171 |
| Directory | /workspace/1.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/1.gpio_random_dout_din.537605285 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 22406531 ps |
| CPU time | 0.86 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 197360 kb |
| Host | smart-d115b60c-1cc4-430c-a6bf-b0c1efcd1052 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537605285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.537605285 |
| Directory | /workspace/1.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1169222844 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 167377658 ps |
| CPU time | 0.9 seconds |
| Started | Jan 07 01:31:19 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 196100 kb |
| Host | smart-3454dc65-2392-4658-a3e3-c51c15527a2f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169222844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup _pulldown.1169222844 |
| Directory | /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.648675143 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 979084613 ps |
| CPU time | 2.3 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 198096 kb |
| Host | smart-be900a3c-4794-4d10-bac9-0c84a89481e8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648675143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand om_long_reg_writes_reg_reads.648675143 |
| Directory | /workspace/1.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/1.gpio_sec_cm.2334831894 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 330159353 ps |
| CPU time | 0.96 seconds |
| Started | Jan 07 01:31:10 PM PST 24 |
| Finished | Jan 07 01:31:19 PM PST 24 |
| Peak memory | 214536 kb |
| Host | smart-1ab5c67f-8161-49a9-909c-60b80130177b |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334831894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2334831894 |
| Directory | /workspace/1.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/1.gpio_smoke.3290688871 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 272571223 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:31:09 PM PST 24 |
| Finished | Jan 07 01:31:18 PM PST 24 |
| Peak memory | 195648 kb |
| Host | smart-923d56de-6bbc-4cf8-8232-b73f046768d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3290688871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3290688871 |
| Directory | /workspace/1.gpio_smoke/latest |
| Test location | /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.4251407130 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 125652550 ps |
| CPU time | 1.17 seconds |
| Started | Jan 07 01:31:10 PM PST 24 |
| Finished | Jan 07 01:31:19 PM PST 24 |
| Peak memory | 196576 kb |
| Host | smart-a1449c17-816e-4425-8249-553a00b63c79 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251407130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.4251407130 |
| Directory | /workspace/1.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/1.gpio_stress_all.3311344401 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 19259874871 ps |
| CPU time | 143.37 seconds |
| Started | Jan 07 01:31:18 PM PST 24 |
| Finished | Jan 07 01:33:55 PM PST 24 |
| Peak memory | 198212 kb |
| Host | smart-b4725740-34c1-4a3f-acaa-454448b2d4fe |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311344401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g pio_stress_all.3311344401 |
| Directory | /workspace/1.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/10.gpio_alert_test.1180090316 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 50628799 ps |
| CPU time | 0.55 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 194004 kb |
| Host | smart-5e8dd64c-8788-4af5-8338-3dc193da2aa2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180090316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1180090316 |
| Directory | /workspace/10.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2666187392 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 517710905 ps |
| CPU time | 0.89 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 196056 kb |
| Host | smart-f6913fae-e603-44a5-b35a-5e1eafd4b099 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666187392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2666187392 |
| Directory | /workspace/10.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/10.gpio_filter_stress.508288003 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 566301262 ps |
| CPU time | 19.5 seconds |
| Started | Jan 07 01:31:27 PM PST 24 |
| Finished | Jan 07 01:32:05 PM PST 24 |
| Peak memory | 198052 kb |
| Host | smart-ccf21e7a-facd-4975-bd23-8ba76d960591 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508288003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres s.508288003 |
| Directory | /workspace/10.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/10.gpio_full_random.3138476200 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 117414408 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 195304 kb |
| Host | smart-36a80d2e-2692-4802-b4c6-3f58b70e4ec1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138476200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3138476200 |
| Directory | /workspace/10.gpio_full_random/latest |
| Test location | /workspace/coverage/default/10.gpio_intr_rand_pgm.3350109312 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 53926580 ps |
| CPU time | 1.3 seconds |
| Started | Jan 07 01:31:30 PM PST 24 |
| Finished | Jan 07 01:31:50 PM PST 24 |
| Peak memory | 196864 kb |
| Host | smart-0fd2af88-0143-495a-b8b4-28637dee68a9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350109312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3350109312 |
| Directory | /workspace/10.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.162151454 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 111705890 ps |
| CPU time | 2.09 seconds |
| Started | Jan 07 01:31:30 PM PST 24 |
| Finished | Jan 07 01:31:50 PM PST 24 |
| Peak memory | 196572 kb |
| Host | smart-e9ff6084-28b3-49e5-b6ae-01260a0f213c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162151454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 10.gpio_intr_with_filter_rand_intr_event.162151454 |
| Directory | /workspace/10.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/10.gpio_rand_intr_trigger.3968898019 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 177992154 ps |
| CPU time | 2.2 seconds |
| Started | Jan 07 01:31:27 PM PST 24 |
| Finished | Jan 07 01:31:47 PM PST 24 |
| Peak memory | 198060 kb |
| Host | smart-00e63327-8de0-4705-b4be-6d425f6fa78a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968898019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger .3968898019 |
| Directory | /workspace/10.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/10.gpio_random_dout_din.2430091318 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 45195765 ps |
| CPU time | 0.97 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 196116 kb |
| Host | smart-a9f0a5ee-b729-4604-9d44-ce56210023f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430091318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2430091318 |
| Directory | /workspace/10.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.4113492215 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 84672022 ps |
| CPU time | 0.72 seconds |
| Started | Jan 07 01:31:27 PM PST 24 |
| Finished | Jan 07 01:31:46 PM PST 24 |
| Peak memory | 194092 kb |
| Host | smart-b6542230-5939-4542-b025-629805b786e4 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113492215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu p_pulldown.4113492215 |
| Directory | /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.4024224922 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 346566731 ps |
| CPU time | 2.42 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 198008 kb |
| Host | smart-178520dd-f0e4-4b3f-aa35-0f71d8c43064 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024224922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra ndom_long_reg_writes_reg_reads.4024224922 |
| Directory | /workspace/10.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/10.gpio_smoke.1139103321 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 51682099 ps |
| CPU time | 1.36 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 195616 kb |
| Host | smart-d0d5d080-8796-4299-9f84-a5c93bcfaa1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1139103321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1139103321 |
| Directory | /workspace/10.gpio_smoke/latest |
| Test location | /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.529772565 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 326040745 ps |
| CPU time | 1 seconds |
| Started | Jan 07 01:31:26 PM PST 24 |
| Finished | Jan 07 01:31:43 PM PST 24 |
| Peak memory | 195620 kb |
| Host | smart-3615131f-50c2-4362-a451-3c80c2a69d91 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529772565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.529772565 |
| Directory | /workspace/10.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/10.gpio_stress_all.1944014033 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 1230094592 ps |
| CPU time | 34.7 seconds |
| Started | Jan 07 01:31:27 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 197976 kb |
| Host | smart-0b3b0b95-1c94-49a8-baa6-a0e5a6363cae |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944014033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. gpio_stress_all.1944014033 |
| Directory | /workspace/10.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.4263577873 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 90766013230 ps |
| CPU time | 1302.4 seconds |
| Started | Jan 07 01:31:27 PM PST 24 |
| Finished | Jan 07 01:53:28 PM PST 24 |
| Peak memory | 198288 kb |
| Host | smart-7b1ef2f0-d723-4d53-9a4f-970d1d88bbca |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4263577873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.4263577873 |
| Directory | /workspace/10.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.gpio_alert_test.1774607842 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 21075850 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 01:31:36 PM PST 24 |
| Finished | Jan 07 01:31:51 PM PST 24 |
| Peak memory | 194036 kb |
| Host | smart-d422da71-9f88-4fa4-b442-73cc370542f3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774607842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1774607842 |
| Directory | /workspace/11.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.958345631 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 47133088 ps |
| CPU time | 0.86 seconds |
| Started | Jan 07 01:31:26 PM PST 24 |
| Finished | Jan 07 01:31:42 PM PST 24 |
| Peak memory | 195516 kb |
| Host | smart-28172f62-9214-4198-a577-c1080fd2b3a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958345631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.958345631 |
| Directory | /workspace/11.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/11.gpio_filter_stress.3512666330 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 515014968 ps |
| CPU time | 27.48 seconds |
| Started | Jan 07 01:31:37 PM PST 24 |
| Finished | Jan 07 01:32:18 PM PST 24 |
| Peak memory | 198180 kb |
| Host | smart-673e48cc-cf5c-487e-be61-85c390e7cbdc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512666330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre ss.3512666330 |
| Directory | /workspace/11.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/11.gpio_full_random.4162400488 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 106222732 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:31:37 PM PST 24 |
| Finished | Jan 07 01:31:52 PM PST 24 |
| Peak memory | 196824 kb |
| Host | smart-9ae2473f-3c57-427e-a11f-780f444f798d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162400488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.4162400488 |
| Directory | /workspace/11.gpio_full_random/latest |
| Test location | /workspace/coverage/default/11.gpio_intr_rand_pgm.1468594752 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 86353280 ps |
| CPU time | 1.17 seconds |
| Started | Jan 07 01:31:35 PM PST 24 |
| Finished | Jan 07 01:31:51 PM PST 24 |
| Peak memory | 196092 kb |
| Host | smart-05789a8d-fae4-4cf7-82ee-0f9d01a9a6b6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468594752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1468594752 |
| Directory | /workspace/11.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3097359695 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 59864421 ps |
| CPU time | 2.44 seconds |
| Started | Jan 07 01:31:26 PM PST 24 |
| Finished | Jan 07 01:31:46 PM PST 24 |
| Peak memory | 198120 kb |
| Host | smart-831281b3-0754-46a1-8558-a1366c6b7d95 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097359695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3097359695 |
| Directory | /workspace/11.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/11.gpio_rand_intr_trigger.3032139130 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 115422213 ps |
| CPU time | 2.17 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:31:40 PM PST 24 |
| Peak memory | 197268 kb |
| Host | smart-19217b41-a29e-44c1-a819-d48d129f4a99 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032139130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger .3032139130 |
| Directory | /workspace/11.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/11.gpio_random_dout_din.3575628972 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 28791285 ps |
| CPU time | 0.63 seconds |
| Started | Jan 07 01:31:25 PM PST 24 |
| Finished | Jan 07 01:31:41 PM PST 24 |
| Peak memory | 195096 kb |
| Host | smart-c7925904-8921-4f94-9318-b77c10de663c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3575628972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3575628972 |
| Directory | /workspace/11.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3613601198 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 59949170 ps |
| CPU time | 1.41 seconds |
| Started | Jan 07 01:31:25 PM PST 24 |
| Finished | Jan 07 01:31:42 PM PST 24 |
| Peak memory | 197228 kb |
| Host | smart-8cb550fc-658a-4715-a272-6a29169d130d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613601198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu p_pulldown.3613601198 |
| Directory | /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2160373176 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 782892490 ps |
| CPU time | 4.78 seconds |
| Started | Jan 07 01:31:40 PM PST 24 |
| Finished | Jan 07 01:31:57 PM PST 24 |
| Peak memory | 198072 kb |
| Host | smart-b4c2e2cd-b111-4893-bf97-eb36ff838f95 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160373176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra ndom_long_reg_writes_reg_reads.2160373176 |
| Directory | /workspace/11.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/11.gpio_smoke.986390344 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 176519494 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:35 PM PST 24 |
| Peak memory | 195328 kb |
| Host | smart-e25a3921-19b5-4fb1-813c-a4b29f315b97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986390344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.986390344 |
| Directory | /workspace/11.gpio_smoke/latest |
| Test location | /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2987602914 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 54251173 ps |
| CPU time | 1.39 seconds |
| Started | Jan 07 01:31:37 PM PST 24 |
| Finished | Jan 07 01:31:52 PM PST 24 |
| Peak memory | 196940 kb |
| Host | smart-82fe9bf0-0fb1-4602-85d0-24b25b902b34 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987602914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2987602914 |
| Directory | /workspace/11.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/11.gpio_stress_all.1123470348 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3577669062 ps |
| CPU time | 44.33 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:32:19 PM PST 24 |
| Peak memory | 198244 kb |
| Host | smart-02796d99-699e-4b6d-8da5-df1efd525968 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123470348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. gpio_stress_all.1123470348 |
| Directory | /workspace/11.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.309159610 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 166547438842 ps |
| CPU time | 900.97 seconds |
| Started | Jan 07 01:31:37 PM PST 24 |
| Finished | Jan 07 01:46:52 PM PST 24 |
| Peak memory | 198440 kb |
| Host | smart-d1aff135-3f90-4a14-95b4-f7a223f56766 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =309159610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.309159610 |
| Directory | /workspace/11.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.555431168 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 436571569 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:31:25 PM PST 24 |
| Finished | Jan 07 01:31:42 PM PST 24 |
| Peak memory | 196508 kb |
| Host | smart-5049027a-eeb6-44e8-81d4-c4e25ffd4e27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555431168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.555431168 |
| Directory | /workspace/12.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/12.gpio_filter_stress.2689856887 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1287849272 ps |
| CPU time | 20 seconds |
| Started | Jan 07 01:31:36 PM PST 24 |
| Finished | Jan 07 01:32:10 PM PST 24 |
| Peak memory | 195636 kb |
| Host | smart-ce68640a-f11e-4809-a5f0-9a8444e7b5ae |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689856887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre ss.2689856887 |
| Directory | /workspace/12.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/12.gpio_full_random.4047408298 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 518785437 ps |
| CPU time | 0.95 seconds |
| Started | Jan 07 01:31:38 PM PST 24 |
| Finished | Jan 07 01:31:52 PM PST 24 |
| Peak memory | 197044 kb |
| Host | smart-f4c9ba8a-91ad-46dd-afc2-e5e910c9e922 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047408298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4047408298 |
| Directory | /workspace/12.gpio_full_random/latest |
| Test location | /workspace/coverage/default/12.gpio_intr_rand_pgm.3717733356 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 164735971 ps |
| CPU time | 1.27 seconds |
| Started | Jan 07 01:31:39 PM PST 24 |
| Finished | Jan 07 01:31:52 PM PST 24 |
| Peak memory | 196096 kb |
| Host | smart-12779a0a-1d4d-49d3-8a4b-3640a6f268c2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717733356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3717733356 |
| Directory | /workspace/12.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.4056154186 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 337050442 ps |
| CPU time | 2.36 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:04 PM PST 24 |
| Peak memory | 198144 kb |
| Host | smart-8b233cc6-7cb9-41b8-8b2e-b2914bb45188 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056154186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.gpio_intr_with_filter_rand_intr_event.4056154186 |
| Directory | /workspace/12.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/12.gpio_rand_intr_trigger.844758319 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 360432266 ps |
| CPU time | 2.61 seconds |
| Started | Jan 07 01:31:51 PM PST 24 |
| Finished | Jan 07 01:31:59 PM PST 24 |
| Peak memory | 198108 kb |
| Host | smart-0c135782-f555-4614-abb0-3ae236e1fb4e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844758319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger. 844758319 |
| Directory | /workspace/12.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/12.gpio_random_dout_din.3367059840 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 195601109 ps |
| CPU time | 1.08 seconds |
| Started | Jan 07 01:31:35 PM PST 24 |
| Finished | Jan 07 01:31:51 PM PST 24 |
| Peak memory | 196744 kb |
| Host | smart-0e3d53de-5b06-45c1-8ddb-88d93351ef2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3367059840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3367059840 |
| Directory | /workspace/12.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.200520551 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 279084901 ps |
| CPU time | 1.28 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:31:39 PM PST 24 |
| Peak memory | 197128 kb |
| Host | smart-76f826dc-e827-4753-ad08-ca5779929a9d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200520551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup _pulldown.200520551 |
| Directory | /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.4223449553 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 323331968 ps |
| CPU time | 5.49 seconds |
| Started | Jan 07 01:31:52 PM PST 24 |
| Finished | Jan 07 01:32:02 PM PST 24 |
| Peak memory | 198152 kb |
| Host | smart-d94f17f9-cad2-4afa-adb8-b09dcab4fcba |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223449553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra ndom_long_reg_writes_reg_reads.4223449553 |
| Directory | /workspace/12.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/12.gpio_smoke.406646314 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 68559878 ps |
| CPU time | 1.06 seconds |
| Started | Jan 07 01:31:26 PM PST 24 |
| Finished | Jan 07 01:31:44 PM PST 24 |
| Peak memory | 195840 kb |
| Host | smart-f60f51a9-915e-4415-bde6-9aab8ccfccf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406646314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.406646314 |
| Directory | /workspace/12.gpio_smoke/latest |
| Test location | /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3484557720 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 113740696 ps |
| CPU time | 0.95 seconds |
| Started | Jan 07 01:31:39 PM PST 24 |
| Finished | Jan 07 01:31:52 PM PST 24 |
| Peak memory | 196492 kb |
| Host | smart-cf9fbead-e538-4eb9-9c61-f43fbd41f776 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484557720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3484557720 |
| Directory | /workspace/12.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/12.gpio_stress_all.2902230058 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 17013152160 ps |
| CPU time | 41.13 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:44 PM PST 24 |
| Peak memory | 198136 kb |
| Host | smart-9253299c-7c84-4a99-a025-680ab7877a62 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902230058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. gpio_stress_all.2902230058 |
| Directory | /workspace/12.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.2926215713 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 54962252379 ps |
| CPU time | 916.29 seconds |
| Started | Jan 07 01:31:38 PM PST 24 |
| Finished | Jan 07 01:47:08 PM PST 24 |
| Peak memory | 198336 kb |
| Host | smart-b35d5398-15dc-4d14-9f53-925bbc373f55 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2926215713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.2926215713 |
| Directory | /workspace/12.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.gpio_alert_test.4009594428 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 85080367 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 01:31:37 PM PST 24 |
| Finished | Jan 07 01:31:51 PM PST 24 |
| Peak memory | 194776 kb |
| Host | smart-fdad3a5e-19fa-48c9-9c1a-a2f3f90b08ab |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009594428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.4009594428 |
| Directory | /workspace/13.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3064689635 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 226597704 ps |
| CPU time | 0.74 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:02 PM PST 24 |
| Peak memory | 195376 kb |
| Host | smart-342b5bec-4948-40ec-add3-70ee1b910224 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064689635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3064689635 |
| Directory | /workspace/13.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/13.gpio_filter_stress.4061478312 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 2266878007 ps |
| CPU time | 15.63 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:16 PM PST 24 |
| Peak memory | 197004 kb |
| Host | smart-397aa6f5-02d8-4a7f-bb9e-eb69aeeb18a1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061478312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre ss.4061478312 |
| Directory | /workspace/13.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/13.gpio_full_random.3586542058 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 33435709 ps |
| CPU time | 0.63 seconds |
| Started | Jan 07 01:32:08 PM PST 24 |
| Finished | Jan 07 01:32:13 PM PST 24 |
| Peak memory | 194312 kb |
| Host | smart-eb7cdf1c-bd56-475f-99a1-5e8456f90a18 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586542058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3586542058 |
| Directory | /workspace/13.gpio_full_random/latest |
| Test location | /workspace/coverage/default/13.gpio_intr_rand_pgm.3484091352 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 93306381 ps |
| CPU time | 0.83 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:32:07 PM PST 24 |
| Peak memory | 196812 kb |
| Host | smart-c1c17557-7ff3-462c-9b35-d13f53cee762 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484091352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3484091352 |
| Directory | /workspace/13.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3786962622 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 78530693 ps |
| CPU time | 1.3 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:07 PM PST 24 |
| Peak memory | 196488 kb |
| Host | smart-9fc7d8ba-c69d-44cf-a1ad-533ea6d55d0a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786962622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3786962622 |
| Directory | /workspace/13.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/13.gpio_rand_intr_trigger.358466459 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 218014402 ps |
| CPU time | 1.58 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:32:07 PM PST 24 |
| Peak memory | 196536 kb |
| Host | smart-b9d3c820-5e90-496b-9089-e8614ffa7f2d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358466459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger. 358466459 |
| Directory | /workspace/13.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/13.gpio_random_dout_din.626421896 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 200496900 ps |
| CPU time | 1.04 seconds |
| Started | Jan 07 01:31:52 PM PST 24 |
| Finished | Jan 07 01:31:58 PM PST 24 |
| Peak memory | 196044 kb |
| Host | smart-c7217e71-95b4-47ed-bf72-8113af53ab85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=626421896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.626421896 |
| Directory | /workspace/13.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3108729249 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 137190385 ps |
| CPU time | 1.13 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:32:05 PM PST 24 |
| Peak memory | 196548 kb |
| Host | smart-1af1ab56-1573-45e8-94c4-baa4fc85289d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108729249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu p_pulldown.3108729249 |
| Directory | /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.694804605 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 451119330 ps |
| CPU time | 6.07 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:13 PM PST 24 |
| Peak memory | 198132 kb |
| Host | smart-a9fc56ce-76b4-45f6-90ab-66d480f9e3d4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694804605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran dom_long_reg_writes_reg_reads.694804605 |
| Directory | /workspace/13.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/13.gpio_smoke.2023632403 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 88815295 ps |
| CPU time | 1.06 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:03 PM PST 24 |
| Peak memory | 195860 kb |
| Host | smart-7720b829-0764-4fb3-ac3f-926668fd9ff8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2023632403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2023632403 |
| Directory | /workspace/13.gpio_smoke/latest |
| Test location | /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1442656367 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 115664571 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:31:53 PM PST 24 |
| Finished | Jan 07 01:31:58 PM PST 24 |
| Peak memory | 195184 kb |
| Host | smart-f5285229-1014-479d-a58c-40534a48b5de |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442656367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1442656367 |
| Directory | /workspace/13.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/13.gpio_stress_all.2296341018 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 4518780301 ps |
| CPU time | 109.04 seconds |
| Started | Jan 07 01:31:30 PM PST 24 |
| Finished | Jan 07 01:33:37 PM PST 24 |
| Peak memory | 198192 kb |
| Host | smart-425717c1-fd54-4666-8fbe-4fc33becb332 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296341018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. gpio_stress_all.2296341018 |
| Directory | /workspace/13.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2922781825 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 43297005984 ps |
| CPU time | 588.07 seconds |
| Started | Jan 07 01:31:27 PM PST 24 |
| Finished | Jan 07 01:41:34 PM PST 24 |
| Peak memory | 198360 kb |
| Host | smart-6b763fd6-826d-477f-a518-2899bf4778d8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2922781825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2922781825 |
| Directory | /workspace/13.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.gpio_alert_test.3350897267 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 14889135 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 01:31:37 PM PST 24 |
| Finished | Jan 07 01:31:51 PM PST 24 |
| Peak memory | 194896 kb |
| Host | smart-1add13c7-195d-493b-8a71-362b2857701d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350897267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3350897267 |
| Directory | /workspace/14.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1775091146 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 29375377 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 01:31:53 PM PST 24 |
| Finished | Jan 07 01:31:58 PM PST 24 |
| Peak memory | 195908 kb |
| Host | smart-8b945bcf-b008-4125-879e-5353856d362e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775091146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1775091146 |
| Directory | /workspace/14.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/14.gpio_filter_stress.178335218 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 745369446 ps |
| CPU time | 21.86 seconds |
| Started | Jan 07 01:31:52 PM PST 24 |
| Finished | Jan 07 01:32:18 PM PST 24 |
| Peak memory | 197124 kb |
| Host | smart-0be8a0a2-fc78-4de1-839c-6daf843b2a64 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178335218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres s.178335218 |
| Directory | /workspace/14.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/14.gpio_full_random.285524094 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 82678607 ps |
| CPU time | 0.68 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:01 PM PST 24 |
| Peak memory | 194580 kb |
| Host | smart-4135c980-d3f6-4a78-ade6-e606a378060e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285524094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.285524094 |
| Directory | /workspace/14.gpio_full_random/latest |
| Test location | /workspace/coverage/default/14.gpio_intr_rand_pgm.2425488830 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 165138190 ps |
| CPU time | 1.32 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:09 PM PST 24 |
| Peak memory | 196044 kb |
| Host | smart-6185879b-3af9-42f9-a6b6-1c19e77cf571 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425488830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2425488830 |
| Directory | /workspace/14.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/14.gpio_rand_intr_trigger.2564136893 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 357952193 ps |
| CPU time | 2.37 seconds |
| Started | Jan 07 01:31:37 PM PST 24 |
| Finished | Jan 07 01:31:53 PM PST 24 |
| Peak memory | 198088 kb |
| Host | smart-7512b41f-a175-41b1-9a73-b2188ad2e877 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564136893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger .2564136893 |
| Directory | /workspace/14.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/14.gpio_random_dout_din.872924207 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 33832111 ps |
| CPU time | 0.8 seconds |
| Started | Jan 07 01:31:52 PM PST 24 |
| Finished | Jan 07 01:31:57 PM PST 24 |
| Peak memory | 196492 kb |
| Host | smart-6367decf-7a4f-4486-ac28-774208d0f576 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872924207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.872924207 |
| Directory | /workspace/14.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.849651047 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 109555368 ps |
| CPU time | 0.8 seconds |
| Started | Jan 07 01:31:51 PM PST 24 |
| Finished | Jan 07 01:31:57 PM PST 24 |
| Peak memory | 195612 kb |
| Host | smart-0ae7936b-d249-4de5-94c1-f1f0222141dc |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849651047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup _pulldown.849651047 |
| Directory | /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.748110584 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 93179491 ps |
| CPU time | 2.55 seconds |
| Started | Jan 07 01:31:39 PM PST 24 |
| Finished | Jan 07 01:31:54 PM PST 24 |
| Peak memory | 198056 kb |
| Host | smart-9573752d-0b8e-42c9-bbd9-00134ec72f5d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748110584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran dom_long_reg_writes_reg_reads.748110584 |
| Directory | /workspace/14.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/14.gpio_smoke.244097322 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 232095522 ps |
| CPU time | 1.17 seconds |
| Started | Jan 07 01:31:52 PM PST 24 |
| Finished | Jan 07 01:31:58 PM PST 24 |
| Peak memory | 196536 kb |
| Host | smart-98e7bba2-cf58-486e-9458-2cc0c266e3ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244097322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.244097322 |
| Directory | /workspace/14.gpio_smoke/latest |
| Test location | /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1431656865 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 180551462 ps |
| CPU time | 1.55 seconds |
| Started | Jan 07 01:31:59 PM PST 24 |
| Finished | Jan 07 01:32:10 PM PST 24 |
| Peak memory | 197000 kb |
| Host | smart-7fce88b2-7bf3-422b-8095-0255fbf72875 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431656865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1431656865 |
| Directory | /workspace/14.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/14.gpio_stress_all.3070558799 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3980815114 ps |
| CPU time | 99.24 seconds |
| Started | Jan 07 01:31:37 PM PST 24 |
| Finished | Jan 07 01:33:30 PM PST 24 |
| Peak memory | 198296 kb |
| Host | smart-32d8c074-77f2-4594-b8b5-fd7d3251c512 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070558799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. gpio_stress_all.3070558799 |
| Directory | /workspace/14.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3033520860 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 40045509081 ps |
| CPU time | 764.59 seconds |
| Started | Jan 07 01:31:51 PM PST 24 |
| Finished | Jan 07 01:44:41 PM PST 24 |
| Peak memory | 198300 kb |
| Host | smart-fbad128a-47c8-4393-9afa-2833f66bca6e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3033520860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3033520860 |
| Directory | /workspace/14.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.gpio_alert_test.2813578009 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 12980458 ps |
| CPU time | 0.54 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:00 PM PST 24 |
| Peak memory | 192800 kb |
| Host | smart-d621575c-a729-49af-89ca-56b7cc68b74a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813578009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2813578009 |
| Directory | /workspace/15.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.943824476 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 146374823 ps |
| CPU time | 0.84 seconds |
| Started | Jan 07 01:31:53 PM PST 24 |
| Finished | Jan 07 01:31:58 PM PST 24 |
| Peak memory | 195548 kb |
| Host | smart-1194ce1e-5a97-4e4a-a846-565f0bd056a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943824476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.943824476 |
| Directory | /workspace/15.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/15.gpio_filter_stress.374705519 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 710818041 ps |
| CPU time | 10.26 seconds |
| Started | Jan 07 01:31:50 PM PST 24 |
| Finished | Jan 07 01:32:06 PM PST 24 |
| Peak memory | 197196 kb |
| Host | smart-b42e9927-328f-4ea3-89f0-96e5b55dbe9a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374705519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres s.374705519 |
| Directory | /workspace/15.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/15.gpio_full_random.2295374038 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 260542416 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:31:53 PM PST 24 |
| Finished | Jan 07 01:31:58 PM PST 24 |
| Peak memory | 196156 kb |
| Host | smart-f2bc8376-3113-46e6-ac73-468510948725 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295374038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2295374038 |
| Directory | /workspace/15.gpio_full_random/latest |
| Test location | /workspace/coverage/default/15.gpio_intr_rand_pgm.3670813104 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 24127809 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:01 PM PST 24 |
| Peak memory | 195620 kb |
| Host | smart-6fbb041c-bcca-413d-a392-beefeaa0d451 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670813104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3670813104 |
| Directory | /workspace/15.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3896034837 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 75132146 ps |
| CPU time | 3.01 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:10 PM PST 24 |
| Peak memory | 198176 kb |
| Host | smart-06d0c224-7d2d-4a62-869a-e538f6fc756c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896034837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3896034837 |
| Directory | /workspace/15.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/15.gpio_rand_intr_trigger.1868038090 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 31024707 ps |
| CPU time | 0.94 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:01 PM PST 24 |
| Peak memory | 195488 kb |
| Host | smart-f24be408-e801-4757-8f42-33de1489475d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868038090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger .1868038090 |
| Directory | /workspace/15.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/15.gpio_random_dout_din.2380509108 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 111098021 ps |
| CPU time | 1.28 seconds |
| Started | Jan 07 01:31:39 PM PST 24 |
| Finished | Jan 07 01:31:53 PM PST 24 |
| Peak memory | 196040 kb |
| Host | smart-904d5f5a-8402-4f19-a5fb-b2b9c52bfd88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380509108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2380509108 |
| Directory | /workspace/15.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3315745996 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 570699622 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 01:31:51 PM PST 24 |
| Finished | Jan 07 01:31:57 PM PST 24 |
| Peak memory | 195860 kb |
| Host | smart-b88feeea-b8bc-4b84-98fc-209da8f0e218 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315745996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu p_pulldown.3315745996 |
| Directory | /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3833253751 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 379035966 ps |
| CPU time | 3.47 seconds |
| Started | Jan 07 01:31:54 PM PST 24 |
| Finished | Jan 07 01:32:02 PM PST 24 |
| Peak memory | 197996 kb |
| Host | smart-5e58c540-1f04-4554-9a79-25794ced4351 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833253751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra ndom_long_reg_writes_reg_reads.3833253751 |
| Directory | /workspace/15.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/15.gpio_smoke.1630712739 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 33461513 ps |
| CPU time | 0.97 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:02 PM PST 24 |
| Peak memory | 195920 kb |
| Host | smart-b0156500-8949-4db4-90b1-2303d8f20372 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1630712739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1630712739 |
| Directory | /workspace/15.gpio_smoke/latest |
| Test location | /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.426069288 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 104218507 ps |
| CPU time | 1.03 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:04 PM PST 24 |
| Peak memory | 195568 kb |
| Host | smart-37314e24-924c-482a-a993-36a8d39635f0 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426069288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.426069288 |
| Directory | /workspace/15.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/15.gpio_stress_all.3345639748 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 106820930932 ps |
| CPU time | 163.07 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:34:46 PM PST 24 |
| Peak memory | 198228 kb |
| Host | smart-dddedae3-9c61-4bec-a8e3-251ac07c50a6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345639748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. gpio_stress_all.3345639748 |
| Directory | /workspace/15.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.515820789 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 44219526428 ps |
| CPU time | 176.26 seconds |
| Started | Jan 07 01:31:40 PM PST 24 |
| Finished | Jan 07 01:34:48 PM PST 24 |
| Peak memory | 198304 kb |
| Host | smart-ae516d89-abbf-4925-aa5b-2306d4ff5601 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =515820789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.515820789 |
| Directory | /workspace/15.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.gpio_alert_test.3555752177 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 13301962 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 01:31:54 PM PST 24 |
| Finished | Jan 07 01:31:59 PM PST 24 |
| Peak memory | 194108 kb |
| Host | smart-505a8ea2-1bb5-4dca-afbf-ff90676cc4a7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555752177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3555752177 |
| Directory | /workspace/16.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3424100374 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 38616527 ps |
| CPU time | 0.72 seconds |
| Started | Jan 07 01:31:51 PM PST 24 |
| Finished | Jan 07 01:31:57 PM PST 24 |
| Peak memory | 195328 kb |
| Host | smart-19cd1a85-1ca0-4206-96cb-1e22902fc93b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424100374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3424100374 |
| Directory | /workspace/16.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/16.gpio_filter_stress.1482180854 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 349437332 ps |
| CPU time | 3.34 seconds |
| Started | Jan 07 01:31:41 PM PST 24 |
| Finished | Jan 07 01:31:56 PM PST 24 |
| Peak memory | 195944 kb |
| Host | smart-25c9a67b-4263-4761-89c5-f52d1419bd1f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482180854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre ss.1482180854 |
| Directory | /workspace/16.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/16.gpio_full_random.2440968715 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 51890180 ps |
| CPU time | 0.92 seconds |
| Started | Jan 07 01:31:40 PM PST 24 |
| Finished | Jan 07 01:31:53 PM PST 24 |
| Peak memory | 197904 kb |
| Host | smart-7f25055a-7322-4f93-b7f1-f24d1a071689 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440968715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2440968715 |
| Directory | /workspace/16.gpio_full_random/latest |
| Test location | /workspace/coverage/default/16.gpio_intr_rand_pgm.2281784657 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 344597548 ps |
| CPU time | 1.3 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:03 PM PST 24 |
| Peak memory | 196932 kb |
| Host | smart-563aec97-8277-4fb9-8f4b-d2d78d28947a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281784657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2281784657 |
| Directory | /workspace/16.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1007702206 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 92897089 ps |
| CPU time | 3.46 seconds |
| Started | Jan 07 01:31:52 PM PST 24 |
| Finished | Jan 07 01:32:00 PM PST 24 |
| Peak memory | 198180 kb |
| Host | smart-ec24d125-bc8d-47e6-b766-c59233ddbf55 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007702206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1007702206 |
| Directory | /workspace/16.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/16.gpio_rand_intr_trigger.3716620288 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 537556640 ps |
| CPU time | 1.4 seconds |
| Started | Jan 07 01:31:54 PM PST 24 |
| Finished | Jan 07 01:31:59 PM PST 24 |
| Peak memory | 196252 kb |
| Host | smart-f0069acb-1193-46eb-bd83-7ea85fff6efc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716620288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger .3716620288 |
| Directory | /workspace/16.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/16.gpio_random_dout_din.2717754290 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 51230682 ps |
| CPU time | 0.98 seconds |
| Started | Jan 07 01:31:37 PM PST 24 |
| Finished | Jan 07 01:31:52 PM PST 24 |
| Peak memory | 196056 kb |
| Host | smart-debbf751-ab8a-4994-a2c3-b455a300a3f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2717754290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2717754290 |
| Directory | /workspace/16.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1473226770 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 123325302 ps |
| CPU time | 1.08 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:04 PM PST 24 |
| Peak memory | 196208 kb |
| Host | smart-dec32767-e647-45f8-a42f-824b29679c4a |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473226770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu p_pulldown.1473226770 |
| Directory | /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1740775857 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 65763431 ps |
| CPU time | 2.97 seconds |
| Started | Jan 07 01:31:36 PM PST 24 |
| Finished | Jan 07 01:31:53 PM PST 24 |
| Peak memory | 198136 kb |
| Host | smart-ab27f852-07da-42a4-ae09-2c033f17a349 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740775857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra ndom_long_reg_writes_reg_reads.1740775857 |
| Directory | /workspace/16.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/16.gpio_smoke.1501943394 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 70971048 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 01:31:40 PM PST 24 |
| Finished | Jan 07 01:31:53 PM PST 24 |
| Peak memory | 198116 kb |
| Host | smart-5bc9a05d-abde-4ca4-8db0-3eabbb3924fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1501943394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1501943394 |
| Directory | /workspace/16.gpio_smoke/latest |
| Test location | /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3726058993 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 108610758 ps |
| CPU time | 1.19 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:03 PM PST 24 |
| Peak memory | 196904 kb |
| Host | smart-687f11dc-58bf-4a9e-92ce-ffb0afd37b7d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726058993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3726058993 |
| Directory | /workspace/16.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/16.gpio_stress_all.839721663 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 9566142390 ps |
| CPU time | 122.41 seconds |
| Started | Jan 07 01:31:38 PM PST 24 |
| Finished | Jan 07 01:33:53 PM PST 24 |
| Peak memory | 198272 kb |
| Host | smart-7533fc02-8ca1-44b1-bf30-ad906af0e2c5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839721663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g pio_stress_all.839721663 |
| Directory | /workspace/16.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.83354485 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 96188188664 ps |
| CPU time | 659.67 seconds |
| Started | Jan 07 01:31:51 PM PST 24 |
| Finished | Jan 07 01:42:56 PM PST 24 |
| Peak memory | 198344 kb |
| Host | smart-bc72ecff-ce64-4ab2-b34f-01d0135d855e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =83354485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.83354485 |
| Directory | /workspace/16.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.gpio_alert_test.1621591021 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 31300119 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:32:05 PM PST 24 |
| Peak memory | 194000 kb |
| Host | smart-bd52b742-aae6-455c-bd34-3094acc21034 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621591021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1621591021 |
| Directory | /workspace/17.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2872523800 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 27102640 ps |
| CPU time | 0.66 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:01 PM PST 24 |
| Peak memory | 194116 kb |
| Host | smart-44ba6600-24b2-4002-841f-53e8637a7371 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872523800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2872523800 |
| Directory | /workspace/17.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/17.gpio_filter_stress.3247961029 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2354067619 ps |
| CPU time | 19.18 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 198240 kb |
| Host | smart-e463e449-8cc4-474a-a17b-63ce98b81777 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247961029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre ss.3247961029 |
| Directory | /workspace/17.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/17.gpio_full_random.3985215930 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 89303820 ps |
| CPU time | 1.12 seconds |
| Started | Jan 07 01:31:52 PM PST 24 |
| Finished | Jan 07 01:31:58 PM PST 24 |
| Peak memory | 198020 kb |
| Host | smart-98314682-4811-49f2-be26-b1eb72f95cb7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985215930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3985215930 |
| Directory | /workspace/17.gpio_full_random/latest |
| Test location | /workspace/coverage/default/17.gpio_intr_rand_pgm.1161177920 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 105255011 ps |
| CPU time | 0.75 seconds |
| Started | Jan 07 01:31:54 PM PST 24 |
| Finished | Jan 07 01:32:00 PM PST 24 |
| Peak memory | 196040 kb |
| Host | smart-c1d7c1e5-fd96-4df0-be71-47a2435fcc92 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161177920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1161177920 |
| Directory | /workspace/17.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2964287522 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 101065090 ps |
| CPU time | 1.31 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:02 PM PST 24 |
| Peak memory | 198268 kb |
| Host | smart-3cb276de-c93c-4f46-8a79-a7eed9e9eb0f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964287522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2964287522 |
| Directory | /workspace/17.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/17.gpio_rand_intr_trigger.2414487589 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 222068684 ps |
| CPU time | 3.2 seconds |
| Started | Jan 07 01:31:38 PM PST 24 |
| Finished | Jan 07 01:31:54 PM PST 24 |
| Peak memory | 197308 kb |
| Host | smart-4606e924-06e7-4e55-b7fa-12c981863921 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414487589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger .2414487589 |
| Directory | /workspace/17.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/17.gpio_random_dout_din.504719776 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 54526722 ps |
| CPU time | 1.03 seconds |
| Started | Jan 07 01:31:52 PM PST 24 |
| Finished | Jan 07 01:31:58 PM PST 24 |
| Peak memory | 196744 kb |
| Host | smart-e14e66a0-d49d-48d9-a0d0-19a99e97706c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504719776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.504719776 |
| Directory | /workspace/17.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2006206201 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 34643331 ps |
| CPU time | 0.74 seconds |
| Started | Jan 07 01:31:38 PM PST 24 |
| Finished | Jan 07 01:31:52 PM PST 24 |
| Peak memory | 195540 kb |
| Host | smart-5ad842a9-e4a2-43cb-bac9-f7a00de879fd |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006206201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu p_pulldown.2006206201 |
| Directory | /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3212026828 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 268546412 ps |
| CPU time | 3.5 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:03 PM PST 24 |
| Peak memory | 198164 kb |
| Host | smart-a31ac1ed-1e49-4a93-88a0-d792eaedd883 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212026828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra ndom_long_reg_writes_reg_reads.3212026828 |
| Directory | /workspace/17.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/17.gpio_smoke.232954297 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 87089213 ps |
| CPU time | 0.91 seconds |
| Started | Jan 07 01:31:54 PM PST 24 |
| Finished | Jan 07 01:31:59 PM PST 24 |
| Peak memory | 195252 kb |
| Host | smart-5256fe3e-694e-477a-8e42-ba0c1b9d4fda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=232954297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.232954297 |
| Directory | /workspace/17.gpio_smoke/latest |
| Test location | /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3151053689 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 162136600 ps |
| CPU time | 1.25 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:09 PM PST 24 |
| Peak memory | 196500 kb |
| Host | smart-26c9842f-2422-42f5-9283-677f9ab4f190 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151053689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3151053689 |
| Directory | /workspace/17.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/17.gpio_stress_all.4058646723 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 18499501638 ps |
| CPU time | 120.13 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:34:04 PM PST 24 |
| Peak memory | 198140 kb |
| Host | smart-2caa7056-fa8c-4015-b740-7ca42478153f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058646723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. gpio_stress_all.4058646723 |
| Directory | /workspace/17.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1239163803 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 18743297484 ps |
| CPU time | 263.94 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:36:31 PM PST 24 |
| Peak memory | 198344 kb |
| Host | smart-a592c229-e723-4190-a88d-c870757e8a5b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1239163803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1239163803 |
| Directory | /workspace/17.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/18.gpio_alert_test.502056646 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 13861573 ps |
| CPU time | 0.63 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:08 PM PST 24 |
| Peak memory | 194236 kb |
| Host | smart-1aff12a6-d5d4-4fbb-a15c-da1a2d048845 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502056646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.502056646 |
| Directory | /workspace/18.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1635193951 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 71514628 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:09 PM PST 24 |
| Peak memory | 196068 kb |
| Host | smart-3226ece9-0e84-428c-a058-2101f29d3bb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1635193951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1635193951 |
| Directory | /workspace/18.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/18.gpio_filter_stress.270022938 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 13589397184 ps |
| CPU time | 23.39 seconds |
| Started | Jan 07 01:32:37 PM PST 24 |
| Finished | Jan 07 01:33:05 PM PST 24 |
| Peak memory | 197148 kb |
| Host | smart-25fce822-c685-4904-888e-d8e61dc61215 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270022938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres s.270022938 |
| Directory | /workspace/18.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/18.gpio_full_random.1435423342 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 101724563 ps |
| CPU time | 0.78 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:32:06 PM PST 24 |
| Peak memory | 195936 kb |
| Host | smart-20f83463-fe96-4e8d-bb7d-799b27909e90 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435423342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1435423342 |
| Directory | /workspace/18.gpio_full_random/latest |
| Test location | /workspace/coverage/default/18.gpio_intr_rand_pgm.4133920349 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 131481212 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:32:06 PM PST 24 |
| Peak memory | 196812 kb |
| Host | smart-ab194da9-007e-4a1d-94c4-5836f1b668b0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133920349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.4133920349 |
| Directory | /workspace/18.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1497203635 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 168519462 ps |
| CPU time | 3.21 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:23 PM PST 24 |
| Peak memory | 198168 kb |
| Host | smart-24503883-137b-4715-a17c-c1dcbcc54fb8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497203635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1497203635 |
| Directory | /workspace/18.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/18.gpio_rand_intr_trigger.320408040 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 220398817 ps |
| CPU time | 2.46 seconds |
| Started | Jan 07 01:32:10 PM PST 24 |
| Finished | Jan 07 01:32:16 PM PST 24 |
| Peak memory | 197024 kb |
| Host | smart-d67fcd05-561b-4980-be70-29a9f2c12e93 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320408040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger. 320408040 |
| Directory | /workspace/18.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/18.gpio_random_dout_din.2185996284 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 69874588 ps |
| CPU time | 1.24 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:01 PM PST 24 |
| Peak memory | 195836 kb |
| Host | smart-ce47f92c-ed4f-4daf-8c67-739ca23d8b3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2185996284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2185996284 |
| Directory | /workspace/18.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.4185429759 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 68982677 ps |
| CPU time | 0.68 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:04 PM PST 24 |
| Peak memory | 195316 kb |
| Host | smart-a5e42514-0173-4b96-b9ba-be7520cb14a6 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185429759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu p_pulldown.4185429759 |
| Directory | /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1801599288 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 300481396 ps |
| CPU time | 5.18 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:08 PM PST 24 |
| Peak memory | 198128 kb |
| Host | smart-aa475900-dfe9-497a-8314-165257ba2f47 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801599288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra ndom_long_reg_writes_reg_reads.1801599288 |
| Directory | /workspace/18.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/18.gpio_smoke.4276637542 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 47535578 ps |
| CPU time | 0.93 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:04 PM PST 24 |
| Peak memory | 196532 kb |
| Host | smart-ff3ea613-419b-45ba-b725-d68ddcfcd127 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4276637542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.4276637542 |
| Directory | /workspace/18.gpio_smoke/latest |
| Test location | /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2056231300 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 133288576 ps |
| CPU time | 0.93 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:09 PM PST 24 |
| Peak memory | 196428 kb |
| Host | smart-378fd0c7-bb8f-4b09-a94e-456b95e0b518 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056231300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2056231300 |
| Directory | /workspace/18.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/18.gpio_stress_all.1098118240 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 13092183161 ps |
| CPU time | 68.8 seconds |
| Started | Jan 07 01:32:10 PM PST 24 |
| Finished | Jan 07 01:33:22 PM PST 24 |
| Peak memory | 198160 kb |
| Host | smart-734ca399-8adc-4935-9bd7-dbcf94f97362 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098118240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. gpio_stress_all.1098118240 |
| Directory | /workspace/18.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3728688662 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 178754950480 ps |
| CPU time | 1224.67 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:52:33 PM PST 24 |
| Peak memory | 198340 kb |
| Host | smart-88def49c-73a0-4620-b069-2bfebd1dab30 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3728688662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3728688662 |
| Directory | /workspace/18.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.gpio_alert_test.4165966599 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 14718556 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 01:33:02 PM PST 24 |
| Finished | Jan 07 01:33:11 PM PST 24 |
| Peak memory | 194084 kb |
| Host | smart-7e045884-2946-45a0-96cb-4a718139b434 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165966599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.4165966599 |
| Directory | /workspace/19.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1360987507 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 84591625 ps |
| CPU time | 0.69 seconds |
| Started | Jan 07 01:32:12 PM PST 24 |
| Finished | Jan 07 01:32:18 PM PST 24 |
| Peak memory | 194164 kb |
| Host | smart-6e4b7436-0992-4d9b-bf64-9031d2a1057d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1360987507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1360987507 |
| Directory | /workspace/19.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/19.gpio_filter_stress.876416906 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1008372049 ps |
| CPU time | 13.82 seconds |
| Started | Jan 07 01:33:02 PM PST 24 |
| Finished | Jan 07 01:33:24 PM PST 24 |
| Peak memory | 197072 kb |
| Host | smart-440f536f-38b6-41b7-9b7f-9437c3f30e68 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876416906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres s.876416906 |
| Directory | /workspace/19.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/19.gpio_full_random.368403782 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 216118700 ps |
| CPU time | 0.84 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:08 PM PST 24 |
| Peak memory | 196588 kb |
| Host | smart-cf2b6802-8524-40e2-8b1c-77fcf4bc4e44 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368403782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.368403782 |
| Directory | /workspace/19.gpio_full_random/latest |
| Test location | /workspace/coverage/default/19.gpio_intr_rand_pgm.161266864 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 425584470 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 01:32:11 PM PST 24 |
| Finished | Jan 07 01:32:16 PM PST 24 |
| Peak memory | 196712 kb |
| Host | smart-61270b42-237f-43cc-94d5-7401d5a18819 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161266864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.161266864 |
| Directory | /workspace/19.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.898998373 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 114488120 ps |
| CPU time | 1.36 seconds |
| Started | Jan 07 01:32:18 PM PST 24 |
| Finished | Jan 07 01:32:28 PM PST 24 |
| Peak memory | 198300 kb |
| Host | smart-e02b95a6-f56f-47df-907b-47bd3eb4cf03 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898998373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 19.gpio_intr_with_filter_rand_intr_event.898998373 |
| Directory | /workspace/19.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/19.gpio_rand_intr_trigger.1902910062 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 485632749 ps |
| CPU time | 1.42 seconds |
| Started | Jan 07 01:32:15 PM PST 24 |
| Finished | Jan 07 01:32:23 PM PST 24 |
| Peak memory | 196544 kb |
| Host | smart-52498e9e-600d-4ecd-ab85-1081e69373ef |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902910062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger .1902910062 |
| Directory | /workspace/19.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/19.gpio_random_dout_din.1812962876 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 31631581 ps |
| CPU time | 0.79 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 195332 kb |
| Host | smart-67ff95d8-28ff-47ce-a1ed-23c58eb46097 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1812962876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1812962876 |
| Directory | /workspace/19.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3019053599 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 32572516 ps |
| CPU time | 1.2 seconds |
| Started | Jan 07 01:32:15 PM PST 24 |
| Finished | Jan 07 01:32:24 PM PST 24 |
| Peak memory | 195948 kb |
| Host | smart-94b2415b-5c2e-4c16-8926-3cfda2b582cd |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019053599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu p_pulldown.3019053599 |
| Directory | /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2531701388 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 184425716 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:32:36 PM PST 24 |
| Finished | Jan 07 01:32:41 PM PST 24 |
| Peak memory | 196672 kb |
| Host | smart-bd150ed5-f39d-4fde-91a1-cd5f393fe4f0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531701388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra ndom_long_reg_writes_reg_reads.2531701388 |
| Directory | /workspace/19.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/19.gpio_smoke.3202267396 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 372853038 ps |
| CPU time | 1 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:24 PM PST 24 |
| Peak memory | 196368 kb |
| Host | smart-d2c3051c-39ae-4d80-b37d-503435d6452d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202267396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3202267396 |
| Directory | /workspace/19.gpio_smoke/latest |
| Test location | /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.179901156 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 64577115 ps |
| CPU time | 1.21 seconds |
| Started | Jan 07 01:32:11 PM PST 24 |
| Finished | Jan 07 01:32:16 PM PST 24 |
| Peak memory | 196444 kb |
| Host | smart-5eccb5a8-4988-4a40-8710-5a7d8919c9de |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179901156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.179901156 |
| Directory | /workspace/19.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/19.gpio_stress_all.3709686904 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 5435156721 ps |
| CPU time | 137.58 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:34:36 PM PST 24 |
| Peak memory | 198076 kb |
| Host | smart-addeda96-240e-4594-aef1-ffec30dffacc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709686904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. gpio_stress_all.3709686904 |
| Directory | /workspace/19.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.3732390109 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 61512628706 ps |
| CPU time | 455.17 seconds |
| Started | Jan 07 01:32:55 PM PST 24 |
| Finished | Jan 07 01:40:32 PM PST 24 |
| Peak memory | 198392 kb |
| Host | smart-d5800fb1-e527-4f0d-9d9f-062b12f1b1ae |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3732390109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.3732390109 |
| Directory | /workspace/19.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.gpio_alert_test.1664347393 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 52138814 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:35 PM PST 24 |
| Peak memory | 195048 kb |
| Host | smart-a7174a2a-5ecd-4857-8f13-8b90b5ab89a1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664347393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1664347393 |
| Directory | /workspace/2.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3849899010 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 17994140 ps |
| CPU time | 0.74 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 194040 kb |
| Host | smart-8d3d8060-42d2-4e44-b050-461deb74fd6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849899010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3849899010 |
| Directory | /workspace/2.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/2.gpio_filter_stress.2721179525 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1717536581 ps |
| CPU time | 6.49 seconds |
| Started | Jan 07 01:31:19 PM PST 24 |
| Finished | Jan 07 01:31:39 PM PST 24 |
| Peak memory | 195688 kb |
| Host | smart-5daa3d62-95b3-47d5-af69-82df920bbd71 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721179525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres s.2721179525 |
| Directory | /workspace/2.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/2.gpio_full_random.2882987132 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 66565157 ps |
| CPU time | 0.85 seconds |
| Started | Jan 07 01:31:19 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 195748 kb |
| Host | smart-594dcd1d-67aa-4978-b0cc-bc6258e148cc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882987132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2882987132 |
| Directory | /workspace/2.gpio_full_random/latest |
| Test location | /workspace/coverage/default/2.gpio_intr_rand_pgm.2953799665 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 53651615 ps |
| CPU time | 1.08 seconds |
| Started | Jan 07 01:31:18 PM PST 24 |
| Finished | Jan 07 01:31:32 PM PST 24 |
| Peak memory | 195980 kb |
| Host | smart-b9cd41d7-9163-43b9-8ca9-d99fc306f5f1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953799665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2953799665 |
| Directory | /workspace/2.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3103911636 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 143563672 ps |
| CPU time | 1.66 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:34 PM PST 24 |
| Peak memory | 196620 kb |
| Host | smart-81dea19d-3f45-43e3-8049-309655635d75 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103911636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3103911636 |
| Directory | /workspace/2.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/2.gpio_rand_intr_trigger.2200856357 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 353625126 ps |
| CPU time | 3.32 seconds |
| Started | Jan 07 01:31:19 PM PST 24 |
| Finished | Jan 07 01:31:35 PM PST 24 |
| Peak memory | 197028 kb |
| Host | smart-654c49c2-db23-454b-b0cc-dcff2db4ee8b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200856357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger. 2200856357 |
| Directory | /workspace/2.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/2.gpio_random_dout_din.3171986504 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 139323769 ps |
| CPU time | 1.19 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 197060 kb |
| Host | smart-963a9fd0-bdd5-4581-80e8-9767bf5f4174 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3171986504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3171986504 |
| Directory | /workspace/2.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3202600106 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 58844953 ps |
| CPU time | 0.9 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 197444 kb |
| Host | smart-039ef7ca-686a-4c73-a02e-ccfd7f3a4841 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202600106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup _pulldown.3202600106 |
| Directory | /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3367806478 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 86727897 ps |
| CPU time | 4.24 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:39 PM PST 24 |
| Peak memory | 198000 kb |
| Host | smart-ed30ce90-f3fa-48a7-b838-9a7c92dae716 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367806478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran dom_long_reg_writes_reg_reads.3367806478 |
| Directory | /workspace/2.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/2.gpio_sec_cm.606524014 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 287803059 ps |
| CPU time | 0.94 seconds |
| Started | Jan 07 01:31:18 PM PST 24 |
| Finished | Jan 07 01:31:31 PM PST 24 |
| Peak memory | 214552 kb |
| Host | smart-da1e8116-d130-4ac4-94f3-cb4d5b938805 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606524014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.606524014 |
| Directory | /workspace/2.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/2.gpio_smoke.3830378527 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 48783142 ps |
| CPU time | 0.86 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 195368 kb |
| Host | smart-6d51fad5-7388-40c0-b4fc-10db2a9bcce2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3830378527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3830378527 |
| Directory | /workspace/2.gpio_smoke/latest |
| Test location | /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.636300341 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 141857221 ps |
| CPU time | 0.79 seconds |
| Started | Jan 07 01:31:08 PM PST 24 |
| Finished | Jan 07 01:31:17 PM PST 24 |
| Peak memory | 195184 kb |
| Host | smart-58091ef3-239c-4953-a6d9-afab8852cdc6 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636300341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.636300341 |
| Directory | /workspace/2.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/2.gpio_stress_all.973550654 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 3994966369 ps |
| CPU time | 23.49 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:56 PM PST 24 |
| Peak memory | 198160 kb |
| Host | smart-01dbadd4-bafa-4664-a821-31bef77a9e41 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973550654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp io_stress_all.973550654 |
| Directory | /workspace/2.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1386146584 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 99671615662 ps |
| CPU time | 688.95 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:43:01 PM PST 24 |
| Peak memory | 198460 kb |
| Host | smart-2ce71c0d-3f78-4542-8956-476a0175bdad |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1386146584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1386146584 |
| Directory | /workspace/2.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.gpio_alert_test.2816873952 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 74126277 ps |
| CPU time | 0.55 seconds |
| Started | Jan 07 01:32:55 PM PST 24 |
| Finished | Jan 07 01:32:57 PM PST 24 |
| Peak memory | 193988 kb |
| Host | smart-8fad7cd1-5bd3-4002-bfd0-c20d3615a5f1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816873952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2816873952 |
| Directory | /workspace/20.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1340868103 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 25790704 ps |
| CPU time | 0.93 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:33:04 PM PST 24 |
| Peak memory | 196548 kb |
| Host | smart-39770621-4e41-4955-9366-92d893f70836 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340868103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1340868103 |
| Directory | /workspace/20.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/20.gpio_filter_stress.793813960 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1466347162 ps |
| CPU time | 17.96 seconds |
| Started | Jan 07 01:32:55 PM PST 24 |
| Finished | Jan 07 01:33:15 PM PST 24 |
| Peak memory | 198148 kb |
| Host | smart-25a7276b-5f99-41f1-ac0f-62762bde92da |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793813960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres s.793813960 |
| Directory | /workspace/20.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/20.gpio_full_random.468655985 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 23730285 ps |
| CPU time | 0.69 seconds |
| Started | Jan 07 01:33:07 PM PST 24 |
| Finished | Jan 07 01:33:18 PM PST 24 |
| Peak memory | 194652 kb |
| Host | smart-71497643-fd05-4c3d-af48-773e9f8c0807 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468655985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.468655985 |
| Directory | /workspace/20.gpio_full_random/latest |
| Test location | /workspace/coverage/default/20.gpio_intr_rand_pgm.3013451071 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 165534029 ps |
| CPU time | 1.29 seconds |
| Started | Jan 07 01:32:53 PM PST 24 |
| Finished | Jan 07 01:32:56 PM PST 24 |
| Peak memory | 198108 kb |
| Host | smart-1f315c09-07fc-4170-bb53-6183d6f8abad |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013451071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3013451071 |
| Directory | /workspace/20.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.524252990 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 90718532 ps |
| CPU time | 1.13 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:14 PM PST 24 |
| Peak memory | 197272 kb |
| Host | smart-babefb1c-ddc4-4748-a19e-2e1be7d02499 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524252990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 20.gpio_intr_with_filter_rand_intr_event.524252990 |
| Directory | /workspace/20.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/20.gpio_rand_intr_trigger.6071566 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 92765360 ps |
| CPU time | 0.95 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:33:04 PM PST 24 |
| Peak memory | 195384 kb |
| Host | smart-b74c5fdc-e36b-4a92-b698-ee236d0e9070 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6071566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.6071566 |
| Directory | /workspace/20.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/20.gpio_random_dout_din.3380784693 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 88255477 ps |
| CPU time | 0.83 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:21 PM PST 24 |
| Peak memory | 195588 kb |
| Host | smart-713dd268-60d6-4afc-87bc-def2432c4ae3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3380784693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3380784693 |
| Directory | /workspace/20.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2403747699 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 117680098 ps |
| CPU time | 1.08 seconds |
| Started | Jan 07 01:32:20 PM PST 24 |
| Finished | Jan 07 01:32:30 PM PST 24 |
| Peak memory | 196076 kb |
| Host | smart-853ae14d-e133-4fec-bcef-bb748350680b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403747699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu p_pulldown.2403747699 |
| Directory | /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.689662435 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 138379560 ps |
| CPU time | 4.61 seconds |
| Started | Jan 07 01:32:55 PM PST 24 |
| Finished | Jan 07 01:33:02 PM PST 24 |
| Peak memory | 198032 kb |
| Host | smart-4b4e134b-b668-4bd5-b855-ecbd9ecd10c2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689662435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran dom_long_reg_writes_reg_reads.689662435 |
| Directory | /workspace/20.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/20.gpio_smoke.3019253661 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 247439470 ps |
| CPU time | 1.17 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:25 PM PST 24 |
| Peak memory | 195668 kb |
| Host | smart-6ae546c8-0244-404e-94cd-0b4311e237d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3019253661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3019253661 |
| Directory | /workspace/20.gpio_smoke/latest |
| Test location | /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2026090062 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 300786870 ps |
| CPU time | 1.44 seconds |
| Started | Jan 07 01:32:57 PM PST 24 |
| Finished | Jan 07 01:33:02 PM PST 24 |
| Peak memory | 196784 kb |
| Host | smart-784db022-514d-49fb-bd8e-4026fd32d254 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026090062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2026090062 |
| Directory | /workspace/20.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/20.gpio_stress_all.1980984669 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 17800530302 ps |
| CPU time | 60.71 seconds |
| Started | Jan 07 01:32:56 PM PST 24 |
| Finished | Jan 07 01:33:59 PM PST 24 |
| Peak memory | 198192 kb |
| Host | smart-af6fefcb-5e6b-4557-a3e2-98c73dfc48fc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980984669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. gpio_stress_all.1980984669 |
| Directory | /workspace/20.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.3081174286 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 455584431400 ps |
| CPU time | 1647.28 seconds |
| Started | Jan 07 01:33:05 PM PST 24 |
| Finished | Jan 07 02:00:45 PM PST 24 |
| Peak memory | 198304 kb |
| Host | smart-670c7146-9bf4-486a-9f5e-aa44bcf7b2f4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3081174286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.3081174286 |
| Directory | /workspace/20.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.gpio_alert_test.2725282912 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 23272134 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 01:32:10 PM PST 24 |
| Finished | Jan 07 01:32:15 PM PST 24 |
| Peak memory | 194052 kb |
| Host | smart-eef45f47-15d5-422f-a343-ba791e27da81 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725282912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2725282912 |
| Directory | /workspace/21.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.401366936 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 49601347 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:01 PM PST 24 |
| Peak memory | 194004 kb |
| Host | smart-c1bad3c0-132e-4f37-bb92-e2cc4b853a20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=401366936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.401366936 |
| Directory | /workspace/21.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/21.gpio_filter_stress.180750484 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 659534404 ps |
| CPU time | 8.03 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:09 PM PST 24 |
| Peak memory | 196684 kb |
| Host | smart-485834d6-8a5c-42d5-8eb7-662023cfcccb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180750484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres s.180750484 |
| Directory | /workspace/21.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/21.gpio_full_random.3403413923 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 74033190 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 195508 kb |
| Host | smart-1a8c1fb6-d80a-4000-831c-bd41e0e15fdd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403413923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3403413923 |
| Directory | /workspace/21.gpio_full_random/latest |
| Test location | /workspace/coverage/default/21.gpio_intr_rand_pgm.3237084354 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 741507526 ps |
| CPU time | 1.42 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:01 PM PST 24 |
| Peak memory | 197320 kb |
| Host | smart-184d935d-1421-498b-aa51-ea6c633c48dd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237084354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3237084354 |
| Directory | /workspace/21.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2823469260 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 157130040 ps |
| CPU time | 1.84 seconds |
| Started | Jan 07 01:32:09 PM PST 24 |
| Finished | Jan 07 01:32:15 PM PST 24 |
| Peak memory | 196472 kb |
| Host | smart-eeda945f-7c56-49d9-8643-2e1075afe000 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823469260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2823469260 |
| Directory | /workspace/21.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/21.gpio_rand_intr_trigger.1543445662 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 150139759 ps |
| CPU time | 3.13 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:09 PM PST 24 |
| Peak memory | 197180 kb |
| Host | smart-ea47de8e-90e1-4e78-a092-b09020874734 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543445662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger .1543445662 |
| Directory | /workspace/21.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/21.gpio_random_dout_din.1414887672 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 39626938 ps |
| CPU time | 0.93 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:32:06 PM PST 24 |
| Peak memory | 195852 kb |
| Host | smart-f4853a4b-60df-4586-acde-4abfa304b8e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1414887672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1414887672 |
| Directory | /workspace/21.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1562824540 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 17221482 ps |
| CPU time | 0.65 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:09 PM PST 24 |
| Peak memory | 194988 kb |
| Host | smart-b8620758-4ed9-4c96-9ba6-7d074ac8dd1f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562824540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu p_pulldown.1562824540 |
| Directory | /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3774892406 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 2273787324 ps |
| CPU time | 4.14 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:32:09 PM PST 24 |
| Peak memory | 198160 kb |
| Host | smart-f6d5bc7c-c6a7-4c2c-93a2-8a9a3a278214 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774892406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra ndom_long_reg_writes_reg_reads.3774892406 |
| Directory | /workspace/21.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/21.gpio_smoke.3493164341 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 73791623 ps |
| CPU time | 1.36 seconds |
| Started | Jan 07 01:33:13 PM PST 24 |
| Finished | Jan 07 01:33:23 PM PST 24 |
| Peak memory | 197264 kb |
| Host | smart-dff3a536-1d9f-4ee3-bfa0-3c17fbea8314 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493164341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3493164341 |
| Directory | /workspace/21.gpio_smoke/latest |
| Test location | /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3268119500 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 44164286 ps |
| CPU time | 1.33 seconds |
| Started | Jan 07 01:31:52 PM PST 24 |
| Finished | Jan 07 01:31:58 PM PST 24 |
| Peak memory | 196536 kb |
| Host | smart-32a33f9d-5c57-414f-abe3-aa634bfb1cec |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268119500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3268119500 |
| Directory | /workspace/21.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/21.gpio_stress_all.2696695723 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 35646385636 ps |
| CPU time | 103.54 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:33:49 PM PST 24 |
| Peak memory | 198196 kb |
| Host | smart-232b438b-7f65-44a7-a690-9f7e17e333c8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696695723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. gpio_stress_all.2696695723 |
| Directory | /workspace/21.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2990610383 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 8480503493 ps |
| CPU time | 236.55 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:36:01 PM PST 24 |
| Peak memory | 198296 kb |
| Host | smart-008a1461-04a3-4d33-8835-55179de2104e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2990610383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2990610383 |
| Directory | /workspace/21.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.gpio_alert_test.3674544421 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 24342129 ps |
| CPU time | 0.55 seconds |
| Started | Jan 07 01:32:09 PM PST 24 |
| Finished | Jan 07 01:32:14 PM PST 24 |
| Peak memory | 194716 kb |
| Host | smart-6976b3ba-dd59-4423-9803-867f095931cd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674544421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3674544421 |
| Directory | /workspace/22.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1535626819 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 259697308 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:09 PM PST 24 |
| Peak memory | 195428 kb |
| Host | smart-313ea0d7-4e3b-4e34-9b5a-bdddaefd70f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1535626819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1535626819 |
| Directory | /workspace/22.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/22.gpio_filter_stress.3009166562 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 6544252581 ps |
| CPU time | 18.21 seconds |
| Started | Jan 07 01:32:10 PM PST 24 |
| Finished | Jan 07 01:32:32 PM PST 24 |
| Peak memory | 197488 kb |
| Host | smart-80a26584-beda-4ddd-b744-f861a4c618b8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009166562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre ss.3009166562 |
| Directory | /workspace/22.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/22.gpio_full_random.2445313956 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 41633663 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 01:32:08 PM PST 24 |
| Finished | Jan 07 01:32:13 PM PST 24 |
| Peak memory | 195812 kb |
| Host | smart-1dd5a23b-e03a-4f25-983e-7e684e186821 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445313956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2445313956 |
| Directory | /workspace/22.gpio_full_random/latest |
| Test location | /workspace/coverage/default/22.gpio_intr_rand_pgm.2182139359 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 84607880 ps |
| CPU time | 1.38 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:03 PM PST 24 |
| Peak memory | 197160 kb |
| Host | smart-cfe3b63e-3f17-4e97-b64f-88f78d90fad7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182139359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2182139359 |
| Directory | /workspace/22.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2374685191 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 134929100 ps |
| CPU time | 2.84 seconds |
| Started | Jan 07 01:32:12 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 198100 kb |
| Host | smart-3f0d8283-8ba4-4862-89ab-e1a12665eb94 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374685191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2374685191 |
| Directory | /workspace/22.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/22.gpio_rand_intr_trigger.3746455547 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 48847861 ps |
| CPU time | 0.92 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:02 PM PST 24 |
| Peak memory | 195068 kb |
| Host | smart-a933eb69-5bdc-4863-b716-c786b0c37f0d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746455547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger .3746455547 |
| Directory | /workspace/22.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/22.gpio_random_dout_din.2625720432 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 25733602 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 01:32:11 PM PST 24 |
| Finished | Jan 07 01:32:17 PM PST 24 |
| Peak memory | 196736 kb |
| Host | smart-6d00061e-12fe-4fcb-ba66-430ee5705634 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625720432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2625720432 |
| Directory | /workspace/22.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2959939080 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 87985291 ps |
| CPU time | 1.14 seconds |
| Started | Jan 07 01:31:59 PM PST 24 |
| Finished | Jan 07 01:32:09 PM PST 24 |
| Peak memory | 196116 kb |
| Host | smart-082b8db7-460e-46e8-9ce1-ca8977205eee |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959939080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu p_pulldown.2959939080 |
| Directory | /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3572006866 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 60932907 ps |
| CPU time | 2.84 seconds |
| Started | Jan 07 01:32:11 PM PST 24 |
| Finished | Jan 07 01:32:18 PM PST 24 |
| Peak memory | 198128 kb |
| Host | smart-ace38a43-09a3-47c6-b734-8993da81ca19 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572006866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra ndom_long_reg_writes_reg_reads.3572006866 |
| Directory | /workspace/22.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/22.gpio_smoke.89557223 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 75107840 ps |
| CPU time | 1.03 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:04 PM PST 24 |
| Peak memory | 195876 kb |
| Host | smart-27b42e55-f645-4586-bf1f-aa1c566d3d6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89557223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.89557223 |
| Directory | /workspace/22.gpio_smoke/latest |
| Test location | /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2977230024 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 30441262 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:32:06 PM PST 24 |
| Peak memory | 196132 kb |
| Host | smart-9dce702c-2946-455f-a94a-50336829ec69 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977230024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2977230024 |
| Directory | /workspace/22.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/22.gpio_stress_all.3770019312 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 23443143156 ps |
| CPU time | 212.36 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:35:37 PM PST 24 |
| Peak memory | 198072 kb |
| Host | smart-d61e706d-432f-44b3-9e35-b2d1b25277cd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770019312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. gpio_stress_all.3770019312 |
| Directory | /workspace/22.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3121741950 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 151102998392 ps |
| CPU time | 1057.53 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:49:45 PM PST 24 |
| Peak memory | 198344 kb |
| Host | smart-20355331-0c48-4dd3-8498-1a364dbce8e9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3121741950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3121741950 |
| Directory | /workspace/22.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.gpio_alert_test.468196074 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 14985743 ps |
| CPU time | 0.54 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:33:04 PM PST 24 |
| Peak memory | 194700 kb |
| Host | smart-b947b337-69b0-4d08-9a6c-e4a43696d361 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468196074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.468196074 |
| Directory | /workspace/23.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2826532727 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 68316498 ps |
| CPU time | 0.64 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:33:04 PM PST 24 |
| Peak memory | 194808 kb |
| Host | smart-9f663215-4b40-462f-a490-975597da8b1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2826532727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2826532727 |
| Directory | /workspace/23.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/23.gpio_filter_stress.2759536017 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 682742393 ps |
| CPU time | 10.15 seconds |
| Started | Jan 07 01:32:54 PM PST 24 |
| Finished | Jan 07 01:33:05 PM PST 24 |
| Peak memory | 197388 kb |
| Host | smart-67d0caee-5d7a-4653-a6e7-3a3dc3250dcb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759536017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre ss.2759536017 |
| Directory | /workspace/23.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/23.gpio_full_random.1923509806 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 235435732 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 01:32:56 PM PST 24 |
| Finished | Jan 07 01:32:59 PM PST 24 |
| Peak memory | 197236 kb |
| Host | smart-1caade9a-d26d-428c-867a-05cea2c978e3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923509806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1923509806 |
| Directory | /workspace/23.gpio_full_random/latest |
| Test location | /workspace/coverage/default/23.gpio_intr_rand_pgm.672557703 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 275212207 ps |
| CPU time | 1.27 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:21 PM PST 24 |
| Peak memory | 195832 kb |
| Host | smart-c44def38-287e-46d2-b119-3e3f6d8e37ac |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672557703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.672557703 |
| Directory | /workspace/23.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2555065688 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 74963824 ps |
| CPU time | 3.08 seconds |
| Started | Jan 07 01:32:36 PM PST 24 |
| Finished | Jan 07 01:32:42 PM PST 24 |
| Peak memory | 198140 kb |
| Host | smart-aed2c9d0-da9d-4947-8cb7-135327e4d2a3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555065688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2555065688 |
| Directory | /workspace/23.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/23.gpio_rand_intr_trigger.2056811120 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 464830185 ps |
| CPU time | 3.02 seconds |
| Started | Jan 07 01:32:18 PM PST 24 |
| Finished | Jan 07 01:32:30 PM PST 24 |
| Peak memory | 197228 kb |
| Host | smart-d80fee4e-a14a-4690-862f-c7ebc49f004f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056811120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger .2056811120 |
| Directory | /workspace/23.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/23.gpio_random_dout_din.643770181 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 61842099 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 01:32:19 PM PST 24 |
| Finished | Jan 07 01:32:29 PM PST 24 |
| Peak memory | 195864 kb |
| Host | smart-5428fc59-17a9-4cb6-a753-b9bff18486c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643770181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.643770181 |
| Directory | /workspace/23.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.4154848032 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 295076659 ps |
| CPU time | 0.94 seconds |
| Started | Jan 07 01:32:36 PM PST 24 |
| Finished | Jan 07 01:32:40 PM PST 24 |
| Peak memory | 196088 kb |
| Host | smart-93da777d-1ab5-4f05-8e73-12d35028296f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154848032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu p_pulldown.4154848032 |
| Directory | /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.4224933217 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 52951607 ps |
| CPU time | 2.46 seconds |
| Started | Jan 07 01:32:19 PM PST 24 |
| Finished | Jan 07 01:32:30 PM PST 24 |
| Peak memory | 198072 kb |
| Host | smart-ecb1b3f7-809f-4b1a-8794-eb5289c4db6d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224933217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra ndom_long_reg_writes_reg_reads.4224933217 |
| Directory | /workspace/23.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/23.gpio_smoke.901319567 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 33938367 ps |
| CPU time | 0.93 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:33:04 PM PST 24 |
| Peak memory | 196568 kb |
| Host | smart-f2aa1fdb-c428-4ef5-979f-0d81b68c5e92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901319567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.901319567 |
| Directory | /workspace/23.gpio_smoke/latest |
| Test location | /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.449179699 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 184066100 ps |
| CPU time | 0.93 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 195680 kb |
| Host | smart-19190595-eb35-43a0-b0fa-e8649f1392bc |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449179699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.449179699 |
| Directory | /workspace/23.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/23.gpio_stress_all.3871988727 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 6429345073 ps |
| CPU time | 176.99 seconds |
| Started | Jan 07 01:32:56 PM PST 24 |
| Finished | Jan 07 01:35:56 PM PST 24 |
| Peak memory | 198216 kb |
| Host | smart-caa26b9e-252d-48d1-8ba0-d31e841721b7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871988727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. gpio_stress_all.3871988727 |
| Directory | /workspace/23.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3212599356 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 418637082167 ps |
| CPU time | 1883.33 seconds |
| Started | Jan 07 01:32:17 PM PST 24 |
| Finished | Jan 07 02:03:49 PM PST 24 |
| Peak memory | 197944 kb |
| Host | smart-86b14f7a-966a-4a10-a806-b3ff28627849 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3212599356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3212599356 |
| Directory | /workspace/23.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.gpio_alert_test.514784821 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 27742470 ps |
| CPU time | 0.59 seconds |
| Started | Jan 07 01:33:08 PM PST 24 |
| Finished | Jan 07 01:33:18 PM PST 24 |
| Peak memory | 194296 kb |
| Host | smart-587ecc90-62b6-4aec-9bba-aee8c8687e49 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514784821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.514784821 |
| Directory | /workspace/24.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3033627015 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 406025592 ps |
| CPU time | 0.95 seconds |
| Started | Jan 07 01:32:36 PM PST 24 |
| Finished | Jan 07 01:32:44 PM PST 24 |
| Peak memory | 196268 kb |
| Host | smart-84192e4a-081e-4ffa-8fcb-79d00f59a7ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3033627015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3033627015 |
| Directory | /workspace/24.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/24.gpio_filter_stress.3749800321 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1386943240 ps |
| CPU time | 15.63 seconds |
| Started | Jan 07 01:32:58 PM PST 24 |
| Finished | Jan 07 01:33:18 PM PST 24 |
| Peak memory | 196832 kb |
| Host | smart-f3a041e7-cbfd-4ba2-9050-17cc2bb5c6bb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749800321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre ss.3749800321 |
| Directory | /workspace/24.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/24.gpio_full_random.1197432544 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 72795864 ps |
| CPU time | 0.91 seconds |
| Started | Jan 07 01:33:05 PM PST 24 |
| Finished | Jan 07 01:33:16 PM PST 24 |
| Peak memory | 197072 kb |
| Host | smart-eeb98999-fddf-4b17-b3c2-376ce8514b73 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197432544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1197432544 |
| Directory | /workspace/24.gpio_full_random/latest |
| Test location | /workspace/coverage/default/24.gpio_intr_rand_pgm.1417190470 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 23393467 ps |
| CPU time | 0.74 seconds |
| Started | Jan 07 01:33:04 PM PST 24 |
| Finished | Jan 07 01:33:14 PM PST 24 |
| Peak memory | 196084 kb |
| Host | smart-9a78b4cb-74d0-489e-8e78-91f2a1c1f755 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417190470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1417190470 |
| Directory | /workspace/24.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2311279187 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 174023594 ps |
| CPU time | 3.18 seconds |
| Started | Jan 07 01:33:06 PM PST 24 |
| Finished | Jan 07 01:33:20 PM PST 24 |
| Peak memory | 196372 kb |
| Host | smart-12652a6f-9dda-4d09-bbc4-fcc90f1f9de5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311279187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2311279187 |
| Directory | /workspace/24.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/24.gpio_rand_intr_trigger.1100042923 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 579455933 ps |
| CPU time | 3.24 seconds |
| Started | Jan 07 01:32:53 PM PST 24 |
| Finished | Jan 07 01:32:57 PM PST 24 |
| Peak memory | 197124 kb |
| Host | smart-c3000afd-5099-4d7f-aa6f-f415afec34bc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100042923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger .1100042923 |
| Directory | /workspace/24.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/24.gpio_random_dout_din.4199723724 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 72706477 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:08 PM PST 24 |
| Peak memory | 196056 kb |
| Host | smart-26212e7c-4185-4c3c-ab89-cb0563e95c03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4199723724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.4199723724 |
| Directory | /workspace/24.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2716247952 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 92207913 ps |
| CPU time | 1.03 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:13 PM PST 24 |
| Peak memory | 196776 kb |
| Host | smart-f8429866-92d7-4c33-8dcd-1cff2446785a |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716247952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu p_pulldown.2716247952 |
| Directory | /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2790013794 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 838774985 ps |
| CPU time | 3.73 seconds |
| Started | Jan 07 01:33:13 PM PST 24 |
| Finished | Jan 07 01:33:26 PM PST 24 |
| Peak memory | 198048 kb |
| Host | smart-5f084f21-6d8a-4f73-a696-07f9769a1b3b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790013794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra ndom_long_reg_writes_reg_reads.2790013794 |
| Directory | /workspace/24.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/24.gpio_smoke.1390486315 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 164034779 ps |
| CPU time | 1.13 seconds |
| Started | Jan 07 01:32:17 PM PST 24 |
| Finished | Jan 07 01:32:26 PM PST 24 |
| Peak memory | 195876 kb |
| Host | smart-d5ff0d2d-6fe7-4d3b-bddb-4856bdc0f780 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1390486315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1390486315 |
| Directory | /workspace/24.gpio_smoke/latest |
| Test location | /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1187937428 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 49284887 ps |
| CPU time | 0.93 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:33:04 PM PST 24 |
| Peak memory | 195544 kb |
| Host | smart-eee95cfd-682d-4ceb-9535-fd201c7f4259 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187937428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1187937428 |
| Directory | /workspace/24.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/24.gpio_stress_all.981732278 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 17473392814 ps |
| CPU time | 175.94 seconds |
| Started | Jan 07 01:33:13 PM PST 24 |
| Finished | Jan 07 01:36:18 PM PST 24 |
| Peak memory | 198148 kb |
| Host | smart-f7438bab-be69-4585-b409-4cd7e409f19d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981732278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g pio_stress_all.981732278 |
| Directory | /workspace/24.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3305797891 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 28354305650 ps |
| CPU time | 371.4 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 01:39:35 PM PST 24 |
| Peak memory | 198432 kb |
| Host | smart-28b8f53f-a61a-4070-b9fd-d3315009f13f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3305797891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3305797891 |
| Directory | /workspace/24.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.gpio_alert_test.2026179122 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 20197749 ps |
| CPU time | 0.55 seconds |
| Started | Jan 07 01:32:11 PM PST 24 |
| Finished | Jan 07 01:32:16 PM PST 24 |
| Peak memory | 194244 kb |
| Host | smart-382a6147-54d2-4910-8e57-191d7275efa2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026179122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2026179122 |
| Directory | /workspace/25.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.735059607 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 90959584 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 01:33:43 PM PST 24 |
| Finished | Jan 07 01:33:45 PM PST 24 |
| Peak memory | 194032 kb |
| Host | smart-4ff56593-b9d7-42f2-b9a2-cecf7b41c691 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=735059607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.735059607 |
| Directory | /workspace/25.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/25.gpio_filter_stress.2223004208 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1799720302 ps |
| CPU time | 15.55 seconds |
| Started | Jan 07 01:32:15 PM PST 24 |
| Finished | Jan 07 01:32:38 PM PST 24 |
| Peak memory | 198084 kb |
| Host | smart-0f190ceb-20fe-432c-bb61-a239fc6c3b30 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223004208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre ss.2223004208 |
| Directory | /workspace/25.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/25.gpio_full_random.1361141762 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 753228410 ps |
| CPU time | 0.93 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:04 PM PST 24 |
| Peak memory | 197760 kb |
| Host | smart-f337ea4b-2beb-4b88-9381-4f491f85815e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361141762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1361141762 |
| Directory | /workspace/25.gpio_full_random/latest |
| Test location | /workspace/coverage/default/25.gpio_intr_rand_pgm.1574550194 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 57638554 ps |
| CPU time | 1.12 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:09 PM PST 24 |
| Peak memory | 196256 kb |
| Host | smart-30902038-d81b-47a2-93ba-f6f9c8795153 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574550194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1574550194 |
| Directory | /workspace/25.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2281264615 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 167677285 ps |
| CPU time | 0.99 seconds |
| Started | Jan 07 01:31:58 PM PST 24 |
| Finished | Jan 07 01:32:08 PM PST 24 |
| Peak memory | 196120 kb |
| Host | smart-9fa8b10f-3555-4153-a83f-373d698a585d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281264615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2281264615 |
| Directory | /workspace/25.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/25.gpio_rand_intr_trigger.2162645908 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 61246430 ps |
| CPU time | 1.27 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:32:07 PM PST 24 |
| Peak memory | 196764 kb |
| Host | smart-70b15bce-8636-4d3a-b49f-9882a1df6108 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162645908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger .2162645908 |
| Directory | /workspace/25.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/25.gpio_random_dout_din.3280826044 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 99161316 ps |
| CPU time | 1.25 seconds |
| Started | Jan 07 01:33:05 PM PST 24 |
| Finished | Jan 07 01:33:17 PM PST 24 |
| Peak memory | 197124 kb |
| Host | smart-2e989939-d59a-47a4-bc51-a41a8fe00005 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280826044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3280826044 |
| Directory | /workspace/25.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3804121176 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 207364828 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 01:33:40 PM PST 24 |
| Finished | Jan 07 01:33:42 PM PST 24 |
| Peak memory | 195448 kb |
| Host | smart-4b7792f5-5a60-4320-95da-70a2256518fc |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804121176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu p_pulldown.3804121176 |
| Directory | /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2861787140 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1816693834 ps |
| CPU time | 3.73 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:07 PM PST 24 |
| Peak memory | 197980 kb |
| Host | smart-c2ff1294-dc99-49fb-9ed2-c0fad3aa5e9b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861787140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra ndom_long_reg_writes_reg_reads.2861787140 |
| Directory | /workspace/25.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/25.gpio_smoke.1373825529 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 221998550 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:33:16 PM PST 24 |
| Finished | Jan 07 01:33:25 PM PST 24 |
| Peak memory | 196588 kb |
| Host | smart-028c84ee-8726-4639-9c86-90c9726feea8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373825529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1373825529 |
| Directory | /workspace/25.gpio_smoke/latest |
| Test location | /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1976953520 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 123834643 ps |
| CPU time | 1.11 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 01:33:25 PM PST 24 |
| Peak memory | 196500 kb |
| Host | smart-36e0f5be-40ad-4794-b154-7c0596a16bdf |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976953520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1976953520 |
| Directory | /workspace/25.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/25.gpio_stress_all.4007902522 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 2593145575 ps |
| CPU time | 33.43 seconds |
| Started | Jan 07 01:31:57 PM PST 24 |
| Finished | Jan 07 01:32:40 PM PST 24 |
| Peak memory | 198292 kb |
| Host | smart-b1092fdc-0589-401a-a708-0606d8e91eae |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007902522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. gpio_stress_all.4007902522 |
| Directory | /workspace/25.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.535983402 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 80378441199 ps |
| CPU time | 295.26 seconds |
| Started | Jan 07 01:31:54 PM PST 24 |
| Finished | Jan 07 01:36:53 PM PST 24 |
| Peak memory | 198408 kb |
| Host | smart-d902ce93-1bf2-4883-80e6-f54c3e20911d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =535983402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.535983402 |
| Directory | /workspace/25.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.gpio_alert_test.3637790600 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 218823347 ps |
| CPU time | 0.6 seconds |
| Started | Jan 07 01:32:55 PM PST 24 |
| Finished | Jan 07 01:32:58 PM PST 24 |
| Peak memory | 195008 kb |
| Host | smart-110cc00f-621b-48c5-adec-f50bee41937c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637790600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3637790600 |
| Directory | /workspace/26.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1216178756 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 64737061 ps |
| CPU time | 0.69 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:21 PM PST 24 |
| Peak memory | 194168 kb |
| Host | smart-7f7c4d44-297c-4a76-95fb-3097a4b7572d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1216178756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1216178756 |
| Directory | /workspace/26.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/26.gpio_filter_stress.1603657485 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2660595459 ps |
| CPU time | 21.29 seconds |
| Started | Jan 07 01:31:56 PM PST 24 |
| Finished | Jan 07 01:32:25 PM PST 24 |
| Peak memory | 196800 kb |
| Host | smart-4b255954-3bca-41e1-9d8b-de6919a8ac2d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603657485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre ss.1603657485 |
| Directory | /workspace/26.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/26.gpio_full_random.877191034 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 38192918 ps |
| CPU time | 0.71 seconds |
| Started | Jan 07 01:32:56 PM PST 24 |
| Finished | Jan 07 01:33:00 PM PST 24 |
| Peak memory | 194628 kb |
| Host | smart-7b008a63-febd-41ad-afd6-db597fd4ab28 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877191034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.877191034 |
| Directory | /workspace/26.gpio_full_random/latest |
| Test location | /workspace/coverage/default/26.gpio_intr_rand_pgm.3283827441 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 240196439 ps |
| CPU time | 1.43 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:25 PM PST 24 |
| Peak memory | 197272 kb |
| Host | smart-c00cd0e8-174f-45d6-8033-20e5bd0f98ce |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283827441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3283827441 |
| Directory | /workspace/26.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3623058821 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 627726381 ps |
| CPU time | 3.04 seconds |
| Started | Jan 07 01:32:18 PM PST 24 |
| Finished | Jan 07 01:32:30 PM PST 24 |
| Peak memory | 197976 kb |
| Host | smart-8b0c3361-12fe-44c2-a62f-f9bc7cd3aca2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623058821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3623058821 |
| Directory | /workspace/26.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/26.gpio_rand_intr_trigger.1432682604 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 130997474 ps |
| CPU time | 1.98 seconds |
| Started | Jan 07 01:32:12 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 196824 kb |
| Host | smart-3e05807f-4f12-4fee-a32a-e061f1d524ac |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432682604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger .1432682604 |
| Directory | /workspace/26.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/26.gpio_random_dout_din.2567158400 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 160742643 ps |
| CPU time | 1.03 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:32:19 PM PST 24 |
| Peak memory | 196032 kb |
| Host | smart-efa46088-4fd1-4efe-9175-1fd11907c3b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567158400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2567158400 |
| Directory | /workspace/26.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3631448053 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 194375296 ps |
| CPU time | 1.11 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:21 PM PST 24 |
| Peak memory | 195920 kb |
| Host | smart-40484ce5-0f53-4e64-850c-987bc6101a36 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631448053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu p_pulldown.3631448053 |
| Directory | /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2622670214 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 388027378 ps |
| CPU time | 6.24 seconds |
| Started | Jan 07 01:32:19 PM PST 24 |
| Finished | Jan 07 01:32:34 PM PST 24 |
| Peak memory | 198120 kb |
| Host | smart-fd32251b-c923-40a2-989f-e01ac36c4f93 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622670214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra ndom_long_reg_writes_reg_reads.2622670214 |
| Directory | /workspace/26.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/26.gpio_smoke.26813585 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 508382697 ps |
| CPU time | 1.31 seconds |
| Started | Jan 07 01:31:55 PM PST 24 |
| Finished | Jan 07 01:32:01 PM PST 24 |
| Peak memory | 198048 kb |
| Host | smart-854085aa-a33d-4040-833c-4678867fcb4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26813585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.26813585 |
| Directory | /workspace/26.gpio_smoke/latest |
| Test location | /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3264572120 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 46667684 ps |
| CPU time | 1.02 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 195460 kb |
| Host | smart-80a01772-24c8-4929-87fa-7486ef741fbc |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264572120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3264572120 |
| Directory | /workspace/26.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/26.gpio_stress_all.3150460175 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 44898963254 ps |
| CPU time | 144.3 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:34:43 PM PST 24 |
| Peak memory | 198144 kb |
| Host | smart-1c46801f-b109-4172-a0ae-625b20351b38 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150460175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. gpio_stress_all.3150460175 |
| Directory | /workspace/26.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2880339812 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 25490657232 ps |
| CPU time | 379.53 seconds |
| Started | Jan 07 01:32:53 PM PST 24 |
| Finished | Jan 07 01:39:14 PM PST 24 |
| Peak memory | 198164 kb |
| Host | smart-fbe3e442-d109-4b39-9e28-77011ddf6a71 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2880339812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2880339812 |
| Directory | /workspace/26.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.gpio_alert_test.4028183112 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 33104878 ps |
| CPU time | 0.64 seconds |
| Started | Jan 07 01:32:55 PM PST 24 |
| Finished | Jan 07 01:32:58 PM PST 24 |
| Peak memory | 194916 kb |
| Host | smart-04a20a75-0cce-47ea-a4dc-4cd3bfe35b5d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028183112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.4028183112 |
| Directory | /workspace/27.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3705789101 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 133642778 ps |
| CPU time | 0.82 seconds |
| Started | Jan 07 01:32:58 PM PST 24 |
| Finished | Jan 07 01:33:03 PM PST 24 |
| Peak memory | 195996 kb |
| Host | smart-0d952260-fecc-4737-9049-c89f26330aa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705789101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3705789101 |
| Directory | /workspace/27.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/27.gpio_filter_stress.3793020164 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1032028330 ps |
| CPU time | 28.23 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:48 PM PST 24 |
| Peak memory | 195636 kb |
| Host | smart-49aaf289-d424-4d7c-bd73-b6b2bbcf12f8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793020164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre ss.3793020164 |
| Directory | /workspace/27.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/27.gpio_full_random.4039078744 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 458203736 ps |
| CPU time | 0.95 seconds |
| Started | Jan 07 01:33:05 PM PST 24 |
| Finished | Jan 07 01:33:15 PM PST 24 |
| Peak memory | 196392 kb |
| Host | smart-0cb8ba5c-0c1a-4355-8956-887ed74ce7a4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039078744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.4039078744 |
| Directory | /workspace/27.gpio_full_random/latest |
| Test location | /workspace/coverage/default/27.gpio_intr_rand_pgm.820302109 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 60673192 ps |
| CPU time | 0.64 seconds |
| Started | Jan 07 01:32:34 PM PST 24 |
| Finished | Jan 07 01:32:38 PM PST 24 |
| Peak memory | 194352 kb |
| Host | smart-a1aaf22c-5119-4f7c-a7e4-792ce79f159d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820302109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.820302109 |
| Directory | /workspace/27.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2934944681 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 33534129 ps |
| CPU time | 1.38 seconds |
| Started | Jan 07 01:32:54 PM PST 24 |
| Finished | Jan 07 01:32:58 PM PST 24 |
| Peak memory | 196432 kb |
| Host | smart-01a5e272-d67c-4a0c-8739-abc9a9e9478f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934944681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2934944681 |
| Directory | /workspace/27.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/27.gpio_rand_intr_trigger.3014676218 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 81331338 ps |
| CPU time | 1.71 seconds |
| Started | Jan 07 01:32:20 PM PST 24 |
| Finished | Jan 07 01:32:30 PM PST 24 |
| Peak memory | 195124 kb |
| Host | smart-6f823f2f-cced-4aa0-80cb-738da1b158b4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014676218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger .3014676218 |
| Directory | /workspace/27.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/27.gpio_random_dout_din.2156167025 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 151033949 ps |
| CPU time | 1 seconds |
| Started | Jan 07 01:32:56 PM PST 24 |
| Finished | Jan 07 01:33:00 PM PST 24 |
| Peak memory | 195872 kb |
| Host | smart-4c23757c-6677-40bb-acc3-786456bfdef2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156167025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2156167025 |
| Directory | /workspace/27.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2366322061 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 55839079 ps |
| CPU time | 0.78 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:32:39 PM PST 24 |
| Peak memory | 195600 kb |
| Host | smart-5042515d-70fe-48ba-9513-9401b6a44f6a |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366322061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu p_pulldown.2366322061 |
| Directory | /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.4137469706 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1270318246 ps |
| CPU time | 3.76 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:33:08 PM PST 24 |
| Peak memory | 198052 kb |
| Host | smart-58299883-4cf8-409a-b37d-288508843bec |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137469706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra ndom_long_reg_writes_reg_reads.4137469706 |
| Directory | /workspace/27.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/27.gpio_smoke.1154510016 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 54592079 ps |
| CPU time | 1.37 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:26 PM PST 24 |
| Peak memory | 196408 kb |
| Host | smart-41ecdcff-76ba-42ce-9430-c474e0b69f1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1154510016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1154510016 |
| Directory | /workspace/27.gpio_smoke/latest |
| Test location | /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.984460321 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 45423046 ps |
| CPU time | 1.08 seconds |
| Started | Jan 07 01:32:58 PM PST 24 |
| Finished | Jan 07 01:33:03 PM PST 24 |
| Peak memory | 196520 kb |
| Host | smart-0ff0bfec-7fd1-405a-8abf-fa8bd3fb2c6a |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984460321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.984460321 |
| Directory | /workspace/27.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/27.gpio_stress_all.3958579897 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 10963074889 ps |
| CPU time | 156.01 seconds |
| Started | Jan 07 01:33:07 PM PST 24 |
| Finished | Jan 07 01:35:53 PM PST 24 |
| Peak memory | 198252 kb |
| Host | smart-43ff3f1b-4a66-4ff9-810a-0c54d08214ab |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958579897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. gpio_stress_all.3958579897 |
| Directory | /workspace/27.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2028531465 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 182971438367 ps |
| CPU time | 984.48 seconds |
| Started | Jan 07 01:33:05 PM PST 24 |
| Finished | Jan 07 01:49:40 PM PST 24 |
| Peak memory | 198412 kb |
| Host | smart-9232ecdd-1ec4-4426-860b-8006da0a4468 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2028531465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2028531465 |
| Directory | /workspace/27.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.gpio_alert_test.4241084543 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 23066048 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 01:32:33 PM PST 24 |
| Finished | Jan 07 01:32:36 PM PST 24 |
| Peak memory | 194216 kb |
| Host | smart-05d354df-8263-427a-beaa-46b427c860c7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241084543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.4241084543 |
| Directory | /workspace/28.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.4191914318 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 19824612 ps |
| CPU time | 0.75 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:33:04 PM PST 24 |
| Peak memory | 195996 kb |
| Host | smart-c5f01c63-80c0-4772-a9eb-b48e17be4f80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4191914318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.4191914318 |
| Directory | /workspace/28.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/28.gpio_filter_stress.224666325 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 316363149 ps |
| CPU time | 10.59 seconds |
| Started | Jan 07 01:32:15 PM PST 24 |
| Finished | Jan 07 01:32:33 PM PST 24 |
| Peak memory | 196308 kb |
| Host | smart-578f3d94-5788-40dd-89f6-504725b463fc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224666325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres s.224666325 |
| Directory | /workspace/28.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/28.gpio_full_random.4085054283 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 87787483 ps |
| CPU time | 0.66 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:32:19 PM PST 24 |
| Peak memory | 195272 kb |
| Host | smart-03885613-97da-45d0-add6-4ca694ff8329 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085054283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.4085054283 |
| Directory | /workspace/28.gpio_full_random/latest |
| Test location | /workspace/coverage/default/28.gpio_intr_rand_pgm.3908404998 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 155968411 ps |
| CPU time | 0.81 seconds |
| Started | Jan 07 01:32:56 PM PST 24 |
| Finished | Jan 07 01:33:00 PM PST 24 |
| Peak memory | 196440 kb |
| Host | smart-4862bd2c-eaf0-4289-95e2-e6858dfea2c6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908404998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3908404998 |
| Directory | /workspace/28.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2868557994 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 55786866 ps |
| CPU time | 2.21 seconds |
| Started | Jan 07 01:32:53 PM PST 24 |
| Finished | Jan 07 01:32:56 PM PST 24 |
| Peak memory | 198308 kb |
| Host | smart-08486e40-c522-49b9-ae04-996922d99d87 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868557994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2868557994 |
| Directory | /workspace/28.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/28.gpio_rand_intr_trigger.2502673196 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 179183956 ps |
| CPU time | 1.12 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 195548 kb |
| Host | smart-37431f6a-2eb1-4d05-8839-4c7d12a97a92 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502673196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger .2502673196 |
| Directory | /workspace/28.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/28.gpio_random_dout_din.1322141365 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 20047279 ps |
| CPU time | 0.7 seconds |
| Started | Jan 07 01:32:55 PM PST 24 |
| Finished | Jan 07 01:32:57 PM PST 24 |
| Peak memory | 194944 kb |
| Host | smart-3af892d9-6b10-4069-bad7-dd063eb49b0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1322141365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1322141365 |
| Directory | /workspace/28.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.4101276633 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 64770708 ps |
| CPU time | 1.27 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:22 PM PST 24 |
| Peak memory | 195828 kb |
| Host | smart-1a393092-c8e2-45a7-aa5d-72a7b9ea9fc2 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101276633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu p_pulldown.4101276633 |
| Directory | /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2171784669 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2259910291 ps |
| CPU time | 6.39 seconds |
| Started | Jan 07 01:32:11 PM PST 24 |
| Finished | Jan 07 01:32:21 PM PST 24 |
| Peak memory | 198204 kb |
| Host | smart-1b060dc9-e0e3-41ca-b251-4bf6b31a1f7f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171784669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra ndom_long_reg_writes_reg_reads.2171784669 |
| Directory | /workspace/28.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/28.gpio_smoke.4145655381 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 64418404 ps |
| CPU time | 1.4 seconds |
| Started | Jan 07 01:33:16 PM PST 24 |
| Finished | Jan 07 01:33:26 PM PST 24 |
| Peak memory | 196676 kb |
| Host | smart-8f2ef29a-b6cc-4f0b-8691-b07bb3b2d0b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4145655381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.4145655381 |
| Directory | /workspace/28.gpio_smoke/latest |
| Test location | /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3973411941 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 220724269 ps |
| CPU time | 1.35 seconds |
| Started | Jan 07 01:32:58 PM PST 24 |
| Finished | Jan 07 01:33:03 PM PST 24 |
| Peak memory | 196256 kb |
| Host | smart-9bb88fac-88c3-4714-af61-06796f8bdfce |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973411941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3973411941 |
| Directory | /workspace/28.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/28.gpio_stress_all.2748600270 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 30633923628 ps |
| CPU time | 229.36 seconds |
| Started | Jan 07 01:32:34 PM PST 24 |
| Finished | Jan 07 01:36:26 PM PST 24 |
| Peak memory | 198260 kb |
| Host | smart-edb335d7-4f41-4c2f-a7f6-9f7071e3ead0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748600270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. gpio_stress_all.2748600270 |
| Directory | /workspace/28.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2069806055 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 28003418335 ps |
| CPU time | 379.76 seconds |
| Started | Jan 07 01:33:01 PM PST 24 |
| Finished | Jan 07 01:39:29 PM PST 24 |
| Peak memory | 198284 kb |
| Host | smart-f209c845-d54f-4ba0-b006-2aef8e19bff2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2069806055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2069806055 |
| Directory | /workspace/28.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.gpio_alert_test.3442505698 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 13788237 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:21 PM PST 24 |
| Peak memory | 194184 kb |
| Host | smart-a901c425-0371-469d-a7ec-84d3802f68c4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442505698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3442505698 |
| Directory | /workspace/29.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2452104613 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 23348381 ps |
| CPU time | 0.72 seconds |
| Started | Jan 07 01:32:08 PM PST 24 |
| Finished | Jan 07 01:32:13 PM PST 24 |
| Peak memory | 195376 kb |
| Host | smart-56b385b8-ea40-4447-bde5-8465a7e6b066 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452104613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2452104613 |
| Directory | /workspace/29.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/29.gpio_filter_stress.459191314 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 5637650902 ps |
| CPU time | 26.19 seconds |
| Started | Jan 07 01:32:52 PM PST 24 |
| Finished | Jan 07 01:33:19 PM PST 24 |
| Peak memory | 198096 kb |
| Host | smart-255e1af4-c7ea-4d1e-b522-5fa9db77ed43 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459191314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres s.459191314 |
| Directory | /workspace/29.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/29.gpio_full_random.4260300933 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 78601501 ps |
| CPU time | 0.99 seconds |
| Started | Jan 07 01:32:15 PM PST 24 |
| Finished | Jan 07 01:32:22 PM PST 24 |
| Peak memory | 197876 kb |
| Host | smart-2da36f56-2105-44b8-89ca-b3566e798011 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260300933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.4260300933 |
| Directory | /workspace/29.gpio_full_random/latest |
| Test location | /workspace/coverage/default/29.gpio_intr_rand_pgm.235135294 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 39156844 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:32:12 PM PST 24 |
| Finished | Jan 07 01:32:17 PM PST 24 |
| Peak memory | 196488 kb |
| Host | smart-e04b6fda-470b-46de-99cb-480e9a0e1a5e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235135294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.235135294 |
| Directory | /workspace/29.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.299258873 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 26669285 ps |
| CPU time | 1.17 seconds |
| Started | Jan 07 01:32:20 PM PST 24 |
| Finished | Jan 07 01:32:30 PM PST 24 |
| Peak memory | 197400 kb |
| Host | smart-fbfa5706-a1dd-498b-a7bc-8c3dc5b6349a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299258873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 29.gpio_intr_with_filter_rand_intr_event.299258873 |
| Directory | /workspace/29.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/29.gpio_rand_intr_trigger.2722828586 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 384402609 ps |
| CPU time | 3.11 seconds |
| Started | Jan 07 01:33:01 PM PST 24 |
| Finished | Jan 07 01:33:13 PM PST 24 |
| Peak memory | 195624 kb |
| Host | smart-640942c4-1c62-4c85-87b5-693d10ca61e1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722828586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger .2722828586 |
| Directory | /workspace/29.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/29.gpio_random_dout_din.3231084305 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 23763358 ps |
| CPU time | 0.94 seconds |
| Started | Jan 07 01:32:08 PM PST 24 |
| Finished | Jan 07 01:32:14 PM PST 24 |
| Peak memory | 196680 kb |
| Host | smart-f127258f-1f71-4892-9160-e2fecf8893d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231084305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3231084305 |
| Directory | /workspace/29.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.4051194708 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 72604450 ps |
| CPU time | 0.97 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:25 PM PST 24 |
| Peak memory | 196180 kb |
| Host | smart-db5cb09d-80e5-4406-80ea-571c1c2d1a30 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051194708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu p_pulldown.4051194708 |
| Directory | /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1638216155 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 418399419 ps |
| CPU time | 5.64 seconds |
| Started | Jan 07 01:32:54 PM PST 24 |
| Finished | Jan 07 01:33:02 PM PST 24 |
| Peak memory | 198060 kb |
| Host | smart-aed94e53-69d3-4e6c-8e7a-f598bd5561c5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638216155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra ndom_long_reg_writes_reg_reads.1638216155 |
| Directory | /workspace/29.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/29.gpio_smoke.498997387 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 89010181 ps |
| CPU time | 1.29 seconds |
| Started | Jan 07 01:32:34 PM PST 24 |
| Finished | Jan 07 01:32:38 PM PST 24 |
| Peak memory | 197032 kb |
| Host | smart-6e938d7d-1967-4937-9d4d-83d11598c931 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=498997387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.498997387 |
| Directory | /workspace/29.gpio_smoke/latest |
| Test location | /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.178686377 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 36433022 ps |
| CPU time | 0.9 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:32:19 PM PST 24 |
| Peak memory | 196496 kb |
| Host | smart-d3be245f-179f-4576-a9db-bbc8088851bc |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178686377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.178686377 |
| Directory | /workspace/29.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/29.gpio_stress_all.4177061505 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 58599089286 ps |
| CPU time | 106.54 seconds |
| Started | Jan 07 01:32:56 PM PST 24 |
| Finished | Jan 07 01:34:44 PM PST 24 |
| Peak memory | 198232 kb |
| Host | smart-9984e90a-346f-4d09-bd43-eaa8765d1718 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177061505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. gpio_stress_all.4177061505 |
| Directory | /workspace/29.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.2691539084 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 20335089951 ps |
| CPU time | 369.54 seconds |
| Started | Jan 07 01:32:52 PM PST 24 |
| Finished | Jan 07 01:39:02 PM PST 24 |
| Peak memory | 198348 kb |
| Host | smart-4674f68d-24e7-4633-977a-7b2a0b50a83b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2691539084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.2691539084 |
| Directory | /workspace/29.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.gpio_alert_test.3377782886 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 15832809 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 01:31:10 PM PST 24 |
| Finished | Jan 07 01:31:23 PM PST 24 |
| Peak memory | 193968 kb |
| Host | smart-28aa702d-9db6-498b-9305-bb7b961100d3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377782886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3377782886 |
| Directory | /workspace/3.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2051634750 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 27085392 ps |
| CPU time | 0.71 seconds |
| Started | Jan 07 01:31:08 PM PST 24 |
| Finished | Jan 07 01:31:17 PM PST 24 |
| Peak memory | 195284 kb |
| Host | smart-978e6986-3806-4515-aa5d-1ffa375fcd9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051634750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2051634750 |
| Directory | /workspace/3.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/3.gpio_filter_stress.3223234736 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1008761060 ps |
| CPU time | 28.66 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:32:01 PM PST 24 |
| Peak memory | 195644 kb |
| Host | smart-1b778910-d524-454d-895c-6feb16bacc79 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223234736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres s.3223234736 |
| Directory | /workspace/3.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/3.gpio_full_random.435055270 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 364724931 ps |
| CPU time | 1.07 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 198016 kb |
| Host | smart-1b71c0e6-8eeb-41d3-9019-8cb2636ce6d4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435055270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.435055270 |
| Directory | /workspace/3.gpio_full_random/latest |
| Test location | /workspace/coverage/default/3.gpio_intr_rand_pgm.3312850192 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 150385481 ps |
| CPU time | 1.21 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:34 PM PST 24 |
| Peak memory | 196252 kb |
| Host | smart-6fbe7590-7948-48ae-8fe1-501aa0d60027 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312850192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3312850192 |
| Directory | /workspace/3.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1151958268 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 33509412 ps |
| CPU time | 1.4 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:34 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-8c23abe4-2db9-4353-a25b-e2cb2c65075b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151958268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1151958268 |
| Directory | /workspace/3.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/3.gpio_rand_intr_trigger.981631185 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 189844328 ps |
| CPU time | 2.25 seconds |
| Started | Jan 07 01:31:19 PM PST 24 |
| Finished | Jan 07 01:31:34 PM PST 24 |
| Peak memory | 196592 kb |
| Host | smart-5d1656dc-b22a-48f8-b1a0-4b3fa668004e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981631185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.981631185 |
| Directory | /workspace/3.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/3.gpio_random_dout_din.251001331 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 28289511 ps |
| CPU time | 1.02 seconds |
| Started | Jan 07 01:31:18 PM PST 24 |
| Finished | Jan 07 01:31:31 PM PST 24 |
| Peak memory | 196840 kb |
| Host | smart-5a1d3dce-efba-40d6-8e6d-8b685b6ad3c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251001331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.251001331 |
| Directory | /workspace/3.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.552066823 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 27353907 ps |
| CPU time | 0.7 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 195360 kb |
| Host | smart-6cd60590-11c7-42f6-9d47-ace91e4a5523 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552066823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_ pulldown.552066823 |
| Directory | /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1885220328 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 224068209 ps |
| CPU time | 3.62 seconds |
| Started | Jan 07 01:31:09 PM PST 24 |
| Finished | Jan 07 01:31:21 PM PST 24 |
| Peak memory | 198144 kb |
| Host | smart-521f9d98-e0f4-49b9-8153-b263c90b3fae |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885220328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran dom_long_reg_writes_reg_reads.1885220328 |
| Directory | /workspace/3.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/3.gpio_sec_cm.2088229556 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 38308633 ps |
| CPU time | 0.78 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 213552 kb |
| Host | smart-e8c47b7d-592f-40bd-acfb-128fc35fc1f6 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088229556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2088229556 |
| Directory | /workspace/3.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/3.gpio_smoke.1413552563 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 115308339 ps |
| CPU time | 0.98 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 195868 kb |
| Host | smart-cdc46fe1-fa77-4a1e-bd68-8ea092441203 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413552563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1413552563 |
| Directory | /workspace/3.gpio_smoke/latest |
| Test location | /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1215111276 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 46609129 ps |
| CPU time | 0.74 seconds |
| Started | Jan 07 01:31:27 PM PST 24 |
| Finished | Jan 07 01:31:45 PM PST 24 |
| Peak memory | 194076 kb |
| Host | smart-8b393303-349d-464b-a2fe-147ef3e291c4 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215111276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1215111276 |
| Directory | /workspace/3.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/3.gpio_stress_all.3477601261 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 42981189932 ps |
| CPU time | 82.54 seconds |
| Started | Jan 07 01:31:09 PM PST 24 |
| Finished | Jan 07 01:32:40 PM PST 24 |
| Peak memory | 198228 kb |
| Host | smart-b6eda691-6544-424f-91d2-496f0caa3272 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477601261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g pio_stress_all.3477601261 |
| Directory | /workspace/3.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.3042366881 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 51475535332 ps |
| CPU time | 1239.47 seconds |
| Started | Jan 07 01:31:11 PM PST 24 |
| Finished | Jan 07 01:52:04 PM PST 24 |
| Peak memory | 198376 kb |
| Host | smart-026d2901-5696-4170-92cf-6b6fa3988ada |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3042366881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.3042366881 |
| Directory | /workspace/3.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.gpio_alert_test.2316500667 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 18689251 ps |
| CPU time | 0.6 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:25 PM PST 24 |
| Peak memory | 194984 kb |
| Host | smart-851b6618-4bd0-424c-9e35-64f2c6a330d6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316500667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2316500667 |
| Directory | /workspace/30.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1357534513 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 34013263 ps |
| CPU time | 0.85 seconds |
| Started | Jan 07 01:32:34 PM PST 24 |
| Finished | Jan 07 01:32:38 PM PST 24 |
| Peak memory | 195488 kb |
| Host | smart-753d6a84-1db5-48be-b187-bfe722b1eef7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1357534513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1357534513 |
| Directory | /workspace/30.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/30.gpio_filter_stress.2736294515 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 2850778514 ps |
| CPU time | 23.2 seconds |
| Started | Jan 07 01:32:39 PM PST 24 |
| Finished | Jan 07 01:33:06 PM PST 24 |
| Peak memory | 197088 kb |
| Host | smart-14aab091-989c-40d4-94e0-76db60684182 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736294515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre ss.2736294515 |
| Directory | /workspace/30.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/30.gpio_full_random.15851900 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 126603805 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:32:58 PM PST 24 |
| Finished | Jan 07 01:33:03 PM PST 24 |
| Peak memory | 197720 kb |
| Host | smart-79e9efcb-1c8d-4429-8ce9-be267bbe785d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15851900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.15851900 |
| Directory | /workspace/30.gpio_full_random/latest |
| Test location | /workspace/coverage/default/30.gpio_intr_rand_pgm.2876617650 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 92364814 ps |
| CPU time | 1.28 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:21 PM PST 24 |
| Peak memory | 196044 kb |
| Host | smart-efb62bd6-3f23-478e-af2d-063384fc531b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876617650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2876617650 |
| Directory | /workspace/30.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2354244515 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 318173333 ps |
| CPU time | 2.99 seconds |
| Started | Jan 07 01:32:55 PM PST 24 |
| Finished | Jan 07 01:32:59 PM PST 24 |
| Peak memory | 197452 kb |
| Host | smart-ca314bbd-cebe-4604-8437-5843ae44b399 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354244515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2354244515 |
| Directory | /workspace/30.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/30.gpio_rand_intr_trigger.386359376 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 537215947 ps |
| CPU time | 3.3 seconds |
| Started | Jan 07 01:32:12 PM PST 24 |
| Finished | Jan 07 01:32:19 PM PST 24 |
| Peak memory | 195856 kb |
| Host | smart-6f6cac97-8e12-41f7-824c-deb59808351b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386359376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger. 386359376 |
| Directory | /workspace/30.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/30.gpio_random_dout_din.3722553847 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 55070639 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 01:32:11 PM PST 24 |
| Finished | Jan 07 01:32:15 PM PST 24 |
| Peak memory | 194184 kb |
| Host | smart-ec734de8-5c45-4e32-bb68-863a4483c2fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3722553847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3722553847 |
| Directory | /workspace/30.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2034494730 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 47574374 ps |
| CPU time | 1.05 seconds |
| Started | Jan 07 01:32:15 PM PST 24 |
| Finished | Jan 07 01:32:23 PM PST 24 |
| Peak memory | 195996 kb |
| Host | smart-1a7868e2-719a-4ea9-ac7d-311a2b9e8c49 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034494730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu p_pulldown.2034494730 |
| Directory | /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1502074596 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 383690635 ps |
| CPU time | 2.36 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:32:21 PM PST 24 |
| Peak memory | 197988 kb |
| Host | smart-e2793721-8acf-4ea2-aa2c-5b93cd054de0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502074596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra ndom_long_reg_writes_reg_reads.1502074596 |
| Directory | /workspace/30.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/30.gpio_smoke.3286220031 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 82115149 ps |
| CPU time | 1.24 seconds |
| Started | Jan 07 01:32:53 PM PST 24 |
| Finished | Jan 07 01:32:55 PM PST 24 |
| Peak memory | 195796 kb |
| Host | smart-1da9c915-420e-40c3-a4c0-fb5d44ad279d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3286220031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3286220031 |
| Directory | /workspace/30.gpio_smoke/latest |
| Test location | /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.748563109 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 62871410 ps |
| CPU time | 1.04 seconds |
| Started | Jan 07 01:32:11 PM PST 24 |
| Finished | Jan 07 01:32:16 PM PST 24 |
| Peak memory | 197120 kb |
| Host | smart-f8899111-4a62-49f0-8838-f473684a4559 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748563109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.748563109 |
| Directory | /workspace/30.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/30.gpio_stress_all.1644087680 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 33183901363 ps |
| CPU time | 92.67 seconds |
| Started | Jan 07 01:32:54 PM PST 24 |
| Finished | Jan 07 01:34:27 PM PST 24 |
| Peak memory | 198248 kb |
| Host | smart-975614a0-3132-48eb-bcee-a7d3ffa7095c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644087680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. gpio_stress_all.1644087680 |
| Directory | /workspace/30.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.2636918289 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 82972147332 ps |
| CPU time | 1214.61 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:52:39 PM PST 24 |
| Peak memory | 198156 kb |
| Host | smart-13727c86-a1c2-4b7f-a71b-cfcc8cfc769e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2636918289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.2636918289 |
| Directory | /workspace/30.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.gpio_alert_test.2214485847 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 20760042 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:32:18 PM PST 24 |
| Peak memory | 194340 kb |
| Host | smart-8db44252-f803-4a79-afcc-6ab23bac9e60 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214485847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2214485847 |
| Directory | /workspace/31.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1943760262 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 70222002 ps |
| CPU time | 0.84 seconds |
| Started | Jan 07 01:32:19 PM PST 24 |
| Finished | Jan 07 01:32:29 PM PST 24 |
| Peak memory | 195320 kb |
| Host | smart-e03359f2-ba49-46b1-a801-2c8b7daaf0f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1943760262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1943760262 |
| Directory | /workspace/31.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/31.gpio_filter_stress.3233623150 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 659787399 ps |
| CPU time | 16.04 seconds |
| Started | Jan 07 01:32:30 PM PST 24 |
| Finished | Jan 07 01:32:50 PM PST 24 |
| Peak memory | 195652 kb |
| Host | smart-75649ab8-572a-4530-a741-3d98a842e695 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233623150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre ss.3233623150 |
| Directory | /workspace/31.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/31.gpio_full_random.463983248 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 73754223 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 196104 kb |
| Host | smart-51e8d8dd-6053-48e8-808a-573cfd111d35 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463983248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.463983248 |
| Directory | /workspace/31.gpio_full_random/latest |
| Test location | /workspace/coverage/default/31.gpio_intr_rand_pgm.1195520488 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 18714181 ps |
| CPU time | 0.69 seconds |
| Started | Jan 07 01:32:15 PM PST 24 |
| Finished | Jan 07 01:32:23 PM PST 24 |
| Peak memory | 194336 kb |
| Host | smart-a7af5706-417a-4b0b-b8fb-af0427788825 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195520488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1195520488 |
| Directory | /workspace/31.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1640197398 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 190690460 ps |
| CPU time | 1.86 seconds |
| Started | Jan 07 01:32:15 PM PST 24 |
| Finished | Jan 07 01:32:24 PM PST 24 |
| Peak memory | 196468 kb |
| Host | smart-232f6c15-71d2-4e73-b17d-89e02fc4fdaa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640197398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1640197398 |
| Directory | /workspace/31.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/31.gpio_rand_intr_trigger.1164513316 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 440880761 ps |
| CPU time | 2.53 seconds |
| Started | Jan 07 01:32:12 PM PST 24 |
| Finished | Jan 07 01:32:19 PM PST 24 |
| Peak memory | 198116 kb |
| Host | smart-2a1c152d-1774-4516-b848-48dbbf0345f5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164513316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger .1164513316 |
| Directory | /workspace/31.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/31.gpio_random_dout_din.1577798374 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 19768964 ps |
| CPU time | 0.79 seconds |
| Started | Jan 07 01:32:10 PM PST 24 |
| Finished | Jan 07 01:32:15 PM PST 24 |
| Peak memory | 195532 kb |
| Host | smart-0045636e-9a63-4531-8148-016dd48ab7ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1577798374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1577798374 |
| Directory | /workspace/31.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.4234969427 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 120084522 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 01:32:57 PM PST 24 |
| Finished | Jan 07 01:33:02 PM PST 24 |
| Peak memory | 196156 kb |
| Host | smart-2d2f3ab0-969e-4dfd-8b10-6f874d44bc92 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234969427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu p_pulldown.4234969427 |
| Directory | /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1461156487 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 178261245 ps |
| CPU time | 1.77 seconds |
| Started | Jan 07 01:32:20 PM PST 24 |
| Finished | Jan 07 01:32:30 PM PST 24 |
| Peak memory | 197064 kb |
| Host | smart-93fd00ec-34f0-4c68-909b-40d73d249b9b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461156487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra ndom_long_reg_writes_reg_reads.1461156487 |
| Directory | /workspace/31.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/31.gpio_smoke.2141086170 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 42812164 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:22 PM PST 24 |
| Peak memory | 195920 kb |
| Host | smart-d15a7b88-9aab-49c6-a66b-330cd831a6f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2141086170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2141086170 |
| Directory | /workspace/31.gpio_smoke/latest |
| Test location | /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2128767209 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 131000567 ps |
| CPU time | 1 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 195824 kb |
| Host | smart-e0655f7e-2f89-4e19-b012-2dd6fb160497 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128767209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2128767209 |
| Directory | /workspace/31.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/31.gpio_stress_all.2938015249 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 28586026868 ps |
| CPU time | 160.12 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:34:58 PM PST 24 |
| Peak memory | 198168 kb |
| Host | smart-eb28b6e4-7c7c-4502-b6cd-360ef37551aa |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938015249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. gpio_stress_all.2938015249 |
| Directory | /workspace/31.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3010118366 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 282136936441 ps |
| CPU time | 816.74 seconds |
| Started | Jan 07 01:32:58 PM PST 24 |
| Finished | Jan 07 01:46:39 PM PST 24 |
| Peak memory | 206544 kb |
| Host | smart-afcab330-1e17-4b4a-b862-2ce63c1f5c50 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3010118366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3010118366 |
| Directory | /workspace/31.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.gpio_alert_test.609939148 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 41751444 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 01:32:19 PM PST 24 |
| Finished | Jan 07 01:32:29 PM PST 24 |
| Peak memory | 193984 kb |
| Host | smart-e5451686-7ccf-4471-b479-15365d399a45 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609939148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.609939148 |
| Directory | /workspace/32.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2589490489 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 275074980 ps |
| CPU time | 0.77 seconds |
| Started | Jan 07 01:32:17 PM PST 24 |
| Finished | Jan 07 01:32:26 PM PST 24 |
| Peak memory | 195008 kb |
| Host | smart-9e9aebba-883b-49ed-b7b7-07171859ba42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2589490489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2589490489 |
| Directory | /workspace/32.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/32.gpio_filter_stress.519386423 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 582283363 ps |
| CPU time | 11.36 seconds |
| Started | Jan 07 01:32:57 PM PST 24 |
| Finished | Jan 07 01:33:12 PM PST 24 |
| Peak memory | 196808 kb |
| Host | smart-8a6a2950-b097-49f0-843d-e7ceb4ae4dff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519386423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres s.519386423 |
| Directory | /workspace/32.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/32.gpio_full_random.4072366435 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 271804926 ps |
| CPU time | 1.05 seconds |
| Started | Jan 07 01:32:56 PM PST 24 |
| Finished | Jan 07 01:32:59 PM PST 24 |
| Peak memory | 197756 kb |
| Host | smart-e52c7960-b017-49a9-acfc-46b6a9f11ca7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072366435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.4072366435 |
| Directory | /workspace/32.gpio_full_random/latest |
| Test location | /workspace/coverage/default/32.gpio_intr_rand_pgm.1136219467 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 138913347 ps |
| CPU time | 0.82 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 196572 kb |
| Host | smart-ae928fc5-20c2-4f55-a387-3e79df2cec08 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136219467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1136219467 |
| Directory | /workspace/32.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3276917298 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 130270974 ps |
| CPU time | 2.62 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:07 PM PST 24 |
| Peak memory | 196476 kb |
| Host | smart-a906c124-5182-4c57-bb18-23e51f63df46 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276917298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3276917298 |
| Directory | /workspace/32.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/32.gpio_rand_intr_trigger.3886584004 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 258284723 ps |
| CPU time | 1.47 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:21 PM PST 24 |
| Peak memory | 196180 kb |
| Host | smart-9f8289cc-4d3f-4901-b247-8e6f08531b8f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886584004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger .3886584004 |
| Directory | /workspace/32.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/32.gpio_random_dout_din.3287028473 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 81697952 ps |
| CPU time | 0.89 seconds |
| Started | Jan 07 01:33:02 PM PST 24 |
| Finished | Jan 07 01:33:12 PM PST 24 |
| Peak memory | 196096 kb |
| Host | smart-bdb0c0b9-09c5-4555-ae1c-50c7b4891502 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287028473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3287028473 |
| Directory | /workspace/32.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1895576259 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 284789420 ps |
| CPU time | 1.25 seconds |
| Started | Jan 07 01:32:58 PM PST 24 |
| Finished | Jan 07 01:33:04 PM PST 24 |
| Peak memory | 198096 kb |
| Host | smart-ab1fb70c-4eb7-4b0b-a0b2-b8ac0a8e1160 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895576259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu p_pulldown.1895576259 |
| Directory | /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.4156907198 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 548687291 ps |
| CPU time | 6.05 seconds |
| Started | Jan 07 01:32:53 PM PST 24 |
| Finished | Jan 07 01:33:00 PM PST 24 |
| Peak memory | 197828 kb |
| Host | smart-ccf96484-e596-4aeb-930c-0dc2bf8003f5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156907198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra ndom_long_reg_writes_reg_reads.4156907198 |
| Directory | /workspace/32.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/32.gpio_smoke.3212988039 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 98989264 ps |
| CPU time | 1.01 seconds |
| Started | Jan 07 01:32:17 PM PST 24 |
| Finished | Jan 07 01:32:27 PM PST 24 |
| Peak memory | 196216 kb |
| Host | smart-c3ecd547-a542-420f-88d9-9774627f0ed1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3212988039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3212988039 |
| Directory | /workspace/32.gpio_smoke/latest |
| Test location | /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1135645550 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 29280666 ps |
| CPU time | 0.82 seconds |
| Started | Jan 07 01:32:17 PM PST 24 |
| Finished | Jan 07 01:32:27 PM PST 24 |
| Peak memory | 195484 kb |
| Host | smart-094bfb15-b04a-4f2e-9a46-86fcaea875dc |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135645550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1135645550 |
| Directory | /workspace/32.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/32.gpio_stress_all.3240150794 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 5014478984 ps |
| CPU time | 53.36 seconds |
| Started | Jan 07 01:32:17 PM PST 24 |
| Finished | Jan 07 01:33:19 PM PST 24 |
| Peak memory | 198304 kb |
| Host | smart-ccac044e-80a1-42d5-a7ca-e54ee4b5874c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240150794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. gpio_stress_all.3240150794 |
| Directory | /workspace/32.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.141265019 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 23155534304 ps |
| CPU time | 308.51 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:38:11 PM PST 24 |
| Peak memory | 197800 kb |
| Host | smart-46b846b9-0c4f-4085-bb99-02bd62ba000d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =141265019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.141265019 |
| Directory | /workspace/32.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.gpio_alert_test.3571437965 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 20502733 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 01:33:24 PM PST 24 |
| Peak memory | 194224 kb |
| Host | smart-a76e9e82-a38e-417e-a280-a23f5d376a52 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571437965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3571437965 |
| Directory | /workspace/33.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2243991653 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 29183785 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:32:56 PM PST 24 |
| Finished | Jan 07 01:33:00 PM PST 24 |
| Peak memory | 196596 kb |
| Host | smart-acb3bd3a-3bf6-463d-8f38-40ae2be7da97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2243991653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2243991653 |
| Directory | /workspace/33.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/33.gpio_filter_stress.3277905877 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 3038603906 ps |
| CPU time | 25.36 seconds |
| Started | Jan 07 01:33:08 PM PST 24 |
| Finished | Jan 07 01:33:43 PM PST 24 |
| Peak memory | 197072 kb |
| Host | smart-46d7abef-7f5e-4c37-85f7-1eb3ec3ff3dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277905877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre ss.3277905877 |
| Directory | /workspace/33.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/33.gpio_full_random.4188095826 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 35696703 ps |
| CPU time | 0.65 seconds |
| Started | Jan 07 01:33:13 PM PST 24 |
| Finished | Jan 07 01:33:22 PM PST 24 |
| Peak memory | 194424 kb |
| Host | smart-933f5bc1-18b8-4fe0-8bda-eca002799a0f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188095826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.4188095826 |
| Directory | /workspace/33.gpio_full_random/latest |
| Test location | /workspace/coverage/default/33.gpio_intr_rand_pgm.3588674619 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 412178629 ps |
| CPU time | 1.42 seconds |
| Started | Jan 07 01:32:58 PM PST 24 |
| Finished | Jan 07 01:33:04 PM PST 24 |
| Peak memory | 197156 kb |
| Host | smart-b6cc1a51-fa44-4ac9-b704-b5a5ebe0f5b6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588674619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3588674619 |
| Directory | /workspace/33.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2037581663 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 147569564 ps |
| CPU time | 1.73 seconds |
| Started | Jan 07 01:33:10 PM PST 24 |
| Finished | Jan 07 01:33:21 PM PST 24 |
| Peak memory | 196760 kb |
| Host | smart-8040fbb7-bff0-409a-9be7-8905ef1babc5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037581663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2037581663 |
| Directory | /workspace/33.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/33.gpio_rand_intr_trigger.891859277 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 141535337 ps |
| CPU time | 2.27 seconds |
| Started | Jan 07 01:32:57 PM PST 24 |
| Finished | Jan 07 01:33:03 PM PST 24 |
| Peak memory | 195964 kb |
| Host | smart-4e647d4f-8c5b-41bf-8310-a758cf2feecb |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891859277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger. 891859277 |
| Directory | /workspace/33.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/33.gpio_random_dout_din.340721725 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 42514791 ps |
| CPU time | 1.29 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:08 PM PST 24 |
| Peak memory | 196932 kb |
| Host | smart-0e431743-e7d6-4fdf-ae46-d9d3094371f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340721725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.340721725 |
| Directory | /workspace/33.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.20884106 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 24415278 ps |
| CPU time | 0.73 seconds |
| Started | Jan 07 01:33:07 PM PST 24 |
| Finished | Jan 07 01:33:18 PM PST 24 |
| Peak memory | 196112 kb |
| Host | smart-b7ec4361-ae94-4703-bb2c-f2debe526bc2 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20884106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup_ pulldown.20884106 |
| Directory | /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.662288072 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 259666030 ps |
| CPU time | 2.62 seconds |
| Started | Jan 07 01:33:06 PM PST 24 |
| Finished | Jan 07 01:33:19 PM PST 24 |
| Peak memory | 198024 kb |
| Host | smart-74438e5d-13c5-4c33-ae36-bb761a03f97c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662288072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran dom_long_reg_writes_reg_reads.662288072 |
| Directory | /workspace/33.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/33.gpio_smoke.1806064407 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 241145368 ps |
| CPU time | 0.77 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:33:05 PM PST 24 |
| Peak memory | 195980 kb |
| Host | smart-2fba4fef-2cfa-4a1d-9a00-e61997add4ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1806064407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1806064407 |
| Directory | /workspace/33.gpio_smoke/latest |
| Test location | /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2653753902 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 44079321 ps |
| CPU time | 0.96 seconds |
| Started | Jan 07 01:32:17 PM PST 24 |
| Finished | Jan 07 01:32:26 PM PST 24 |
| Peak memory | 195832 kb |
| Host | smart-997efa2f-eedb-45ad-b755-5bf3639707c7 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653753902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2653753902 |
| Directory | /workspace/33.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/33.gpio_stress_all.1774443738 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 132740776488 ps |
| CPU time | 218.83 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 01:37:03 PM PST 24 |
| Peak memory | 198192 kb |
| Host | smart-f5a2eec2-7c43-4479-951d-6145d70d3221 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774443738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. gpio_stress_all.1774443738 |
| Directory | /workspace/33.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2888995133 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 61086258744 ps |
| CPU time | 495.76 seconds |
| Started | Jan 07 01:33:07 PM PST 24 |
| Finished | Jan 07 01:41:34 PM PST 24 |
| Peak memory | 198404 kb |
| Host | smart-c52b7c16-d895-4827-aa81-a40549da0ec9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2888995133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2888995133 |
| Directory | /workspace/33.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.gpio_alert_test.3611335557 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 13896696 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:24 PM PST 24 |
| Peak memory | 194980 kb |
| Host | smart-ee244c9f-1fe7-4caf-99dc-3af75af7fd4c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611335557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3611335557 |
| Directory | /workspace/34.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3130116649 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 112886674 ps |
| CPU time | 0.86 seconds |
| Started | Jan 07 01:33:08 PM PST 24 |
| Finished | Jan 07 01:33:19 PM PST 24 |
| Peak memory | 195516 kb |
| Host | smart-58791f74-e4e6-4ea6-9480-b0f077fdb611 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130116649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3130116649 |
| Directory | /workspace/34.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/34.gpio_filter_stress.414509499 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 1565263136 ps |
| CPU time | 10.96 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 01:33:34 PM PST 24 |
| Peak memory | 196444 kb |
| Host | smart-e1c62038-5750-4e4f-a78c-a1b0a3125028 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414509499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres s.414509499 |
| Directory | /workspace/34.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/34.gpio_full_random.2667017579 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 61254007 ps |
| CPU time | 0.96 seconds |
| Started | Jan 07 01:33:45 PM PST 24 |
| Finished | Jan 07 01:33:48 PM PST 24 |
| Peak memory | 197772 kb |
| Host | smart-158ef9ca-513e-463f-8e8c-1ca533f748b1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667017579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2667017579 |
| Directory | /workspace/34.gpio_full_random/latest |
| Test location | /workspace/coverage/default/34.gpio_intr_rand_pgm.2676535089 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 23426409 ps |
| CPU time | 0.64 seconds |
| Started | Jan 07 01:33:18 PM PST 24 |
| Finished | Jan 07 01:33:26 PM PST 24 |
| Peak memory | 194304 kb |
| Host | smart-3bebdfc3-1889-4c2a-aa9d-4c9fe8535d98 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676535089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2676535089 |
| Directory | /workspace/34.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3088036781 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 89132619 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 01:33:46 PM PST 24 |
| Finished | Jan 07 01:33:49 PM PST 24 |
| Peak memory | 197096 kb |
| Host | smart-4066a529-1e05-4902-a254-5944b9303e29 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088036781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3088036781 |
| Directory | /workspace/34.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/34.gpio_rand_intr_trigger.336397263 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 144950894 ps |
| CPU time | 3.16 seconds |
| Started | Jan 07 01:33:14 PM PST 24 |
| Finished | Jan 07 01:33:26 PM PST 24 |
| Peak memory | 195992 kb |
| Host | smart-146ff8bc-7893-4619-acb1-44f3f76bc541 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336397263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger. 336397263 |
| Directory | /workspace/34.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/34.gpio_random_dout_din.1757951079 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 47888456 ps |
| CPU time | 0.99 seconds |
| Started | Jan 07 01:33:13 PM PST 24 |
| Finished | Jan 07 01:33:23 PM PST 24 |
| Peak memory | 196200 kb |
| Host | smart-f2b71159-984f-45c4-b8eb-3e9f7536177e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1757951079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1757951079 |
| Directory | /workspace/34.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1941785780 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 37274209 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 01:33:37 PM PST 24 |
| Finished | Jan 07 01:33:39 PM PST 24 |
| Peak memory | 198196 kb |
| Host | smart-2c6a4319-9a47-448e-b5a9-303f284cdb2f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941785780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu p_pulldown.1941785780 |
| Directory | /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.967725785 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 4220682887 ps |
| CPU time | 3.2 seconds |
| Started | Jan 07 01:33:16 PM PST 24 |
| Finished | Jan 07 01:33:27 PM PST 24 |
| Peak memory | 198060 kb |
| Host | smart-ab590b33-c0a5-4afc-aa2b-7447a8600ded |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967725785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran dom_long_reg_writes_reg_reads.967725785 |
| Directory | /workspace/34.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/34.gpio_smoke.3797485253 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 137848409 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 01:33:12 PM PST 24 |
| Finished | Jan 07 01:33:23 PM PST 24 |
| Peak memory | 198144 kb |
| Host | smart-a108f6bb-30f9-4afe-9df8-8e66f8b78959 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797485253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3797485253 |
| Directory | /workspace/34.gpio_smoke/latest |
| Test location | /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.902277435 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 183995553 ps |
| CPU time | 1.31 seconds |
| Started | Jan 07 01:33:12 PM PST 24 |
| Finished | Jan 07 01:33:23 PM PST 24 |
| Peak memory | 196768 kb |
| Host | smart-56d976ae-11b9-4cf1-ba71-94ee3156bbda |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902277435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.902277435 |
| Directory | /workspace/34.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/34.gpio_stress_all.2073872453 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 15117400710 ps |
| CPU time | 193.19 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 01:36:37 PM PST 24 |
| Peak memory | 198292 kb |
| Host | smart-7f9cac68-28f2-4b75-93c7-973f72199994 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073872453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. gpio_stress_all.2073872453 |
| Directory | /workspace/34.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1069692652 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 117161870544 ps |
| CPU time | 412.71 seconds |
| Started | Jan 07 01:32:53 PM PST 24 |
| Finished | Jan 07 01:39:47 PM PST 24 |
| Peak memory | 198288 kb |
| Host | smart-7bd55536-0d3c-4ccc-958b-3c40d68f6bb6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1069692652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1069692652 |
| Directory | /workspace/34.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.gpio_alert_test.264552294 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 17242099 ps |
| CPU time | 0.55 seconds |
| Started | Jan 07 01:32:56 PM PST 24 |
| Finished | Jan 07 01:33:00 PM PST 24 |
| Peak memory | 194760 kb |
| Host | smart-3ba0c5a5-52b7-4a06-a4ac-1e4a48ba7af3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264552294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.264552294 |
| Directory | /workspace/35.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.762964255 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 31300596 ps |
| CPU time | 0.94 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:25 PM PST 24 |
| Peak memory | 196844 kb |
| Host | smart-4eee8531-34e6-4002-8ad8-631b2d095e01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762964255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.762964255 |
| Directory | /workspace/35.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/35.gpio_filter_stress.1400311076 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 266803361 ps |
| CPU time | 13.72 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:32:33 PM PST 24 |
| Peak memory | 196848 kb |
| Host | smart-adfb65dd-be4a-4872-8e4b-388dd51ef98f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400311076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre ss.1400311076 |
| Directory | /workspace/35.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/35.gpio_full_random.4245567975 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 139825172 ps |
| CPU time | 0.69 seconds |
| Started | Jan 07 01:32:57 PM PST 24 |
| Finished | Jan 07 01:33:02 PM PST 24 |
| Peak memory | 194684 kb |
| Host | smart-69a690cc-4620-4e5f-934c-a0a4b28aeb14 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245567975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.4245567975 |
| Directory | /workspace/35.gpio_full_random/latest |
| Test location | /workspace/coverage/default/35.gpio_intr_rand_pgm.3069626052 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 91819378 ps |
| CPU time | 0.68 seconds |
| Started | Jan 07 01:32:17 PM PST 24 |
| Finished | Jan 07 01:32:26 PM PST 24 |
| Peak memory | 194324 kb |
| Host | smart-0e5cff1d-3078-4f6e-9c8e-71360b508e52 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069626052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3069626052 |
| Directory | /workspace/35.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3465102129 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 383248773 ps |
| CPU time | 3.88 seconds |
| Started | Jan 07 01:32:20 PM PST 24 |
| Finished | Jan 07 01:32:32 PM PST 24 |
| Peak memory | 198296 kb |
| Host | smart-4a02960b-12ec-4650-921f-e24b7ef7e1e3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465102129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3465102129 |
| Directory | /workspace/35.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/35.gpio_rand_intr_trigger.3385359543 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 355273549 ps |
| CPU time | 2.71 seconds |
| Started | Jan 07 01:32:33 PM PST 24 |
| Finished | Jan 07 01:32:39 PM PST 24 |
| Peak memory | 196888 kb |
| Host | smart-d0dd0383-3310-4f58-8962-524ccb1ea6e3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385359543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger .3385359543 |
| Directory | /workspace/35.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/35.gpio_random_dout_din.2657804232 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 56642724 ps |
| CPU time | 0.74 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:07 PM PST 24 |
| Peak memory | 195520 kb |
| Host | smart-7081034d-eb08-4fbc-8ea3-0c02f716d4d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2657804232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2657804232 |
| Directory | /workspace/35.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3740034006 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 114475182 ps |
| CPU time | 1.12 seconds |
| Started | Jan 07 01:32:36 PM PST 24 |
| Finished | Jan 07 01:32:41 PM PST 24 |
| Peak memory | 196836 kb |
| Host | smart-5063228b-6a2e-43ff-8653-793dcce88ae5 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740034006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu p_pulldown.3740034006 |
| Directory | /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.4128871609 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 379387307 ps |
| CPU time | 4.48 seconds |
| Started | Jan 07 01:32:13 PM PST 24 |
| Finished | Jan 07 01:32:24 PM PST 24 |
| Peak memory | 198080 kb |
| Host | smart-c165360f-f3c6-4545-94ac-79d5b13dfe32 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128871609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra ndom_long_reg_writes_reg_reads.4128871609 |
| Directory | /workspace/35.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/35.gpio_smoke.3041161779 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 37132533 ps |
| CPU time | 0.96 seconds |
| Started | Jan 07 01:32:36 PM PST 24 |
| Finished | Jan 07 01:32:41 PM PST 24 |
| Peak memory | 197188 kb |
| Host | smart-f505b330-e79f-4229-82fc-b204446198c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3041161779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3041161779 |
| Directory | /workspace/35.gpio_smoke/latest |
| Test location | /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2062708095 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 86286290 ps |
| CPU time | 1.39 seconds |
| Started | Jan 07 01:32:18 PM PST 24 |
| Finished | Jan 07 01:32:29 PM PST 24 |
| Peak memory | 195668 kb |
| Host | smart-9dddd66e-cd33-4c38-9b37-34a0e403a983 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062708095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2062708095 |
| Directory | /workspace/35.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/35.gpio_stress_all.1852450275 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 60902589340 ps |
| CPU time | 191.47 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:35:32 PM PST 24 |
| Peak memory | 198232 kb |
| Host | smart-315bbbc2-ce85-461d-9ebc-278617d43ae0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852450275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. gpio_stress_all.1852450275 |
| Directory | /workspace/35.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.4129521851 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 281505797109 ps |
| CPU time | 1460.78 seconds |
| Started | Jan 07 01:32:15 PM PST 24 |
| Finished | Jan 07 01:56:43 PM PST 24 |
| Peak memory | 198276 kb |
| Host | smart-ff82f99b-e9d0-459e-af4d-1b60b7e45be1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4129521851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.4129521851 |
| Directory | /workspace/35.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.gpio_alert_test.2737949134 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 16626454 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 01:33:01 PM PST 24 |
| Finished | Jan 07 01:33:17 PM PST 24 |
| Peak memory | 194996 kb |
| Host | smart-5dca5ece-1f51-41d1-b7a5-beb2a75133cd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737949134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2737949134 |
| Directory | /workspace/36.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.4132763903 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 99202424 ps |
| CPU time | 0.72 seconds |
| Started | Jan 07 01:32:15 PM PST 24 |
| Finished | Jan 07 01:32:23 PM PST 24 |
| Peak memory | 194084 kb |
| Host | smart-b396b4fd-4ba0-4011-9b49-1befdb961775 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4132763903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.4132763903 |
| Directory | /workspace/36.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/36.gpio_filter_stress.2214734240 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 1338792006 ps |
| CPU time | 14.68 seconds |
| Started | Jan 07 01:32:19 PM PST 24 |
| Finished | Jan 07 01:32:43 PM PST 24 |
| Peak memory | 198052 kb |
| Host | smart-45b63971-d548-44bf-adc1-61971ab197ef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214734240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre ss.2214734240 |
| Directory | /workspace/36.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/36.gpio_full_random.2371232341 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 223375640 ps |
| CPU time | 0.64 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:20 PM PST 24 |
| Peak memory | 194688 kb |
| Host | smart-e213bb41-5f73-415e-ad74-95b84216f1b3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371232341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2371232341 |
| Directory | /workspace/36.gpio_full_random/latest |
| Test location | /workspace/coverage/default/36.gpio_intr_rand_pgm.3857209298 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 61656728 ps |
| CPU time | 0.77 seconds |
| Started | Jan 07 01:32:34 PM PST 24 |
| Finished | Jan 07 01:32:37 PM PST 24 |
| Peak memory | 195440 kb |
| Host | smart-bc765591-fc38-475d-9e94-31e1ebc4ee13 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857209298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3857209298 |
| Directory | /workspace/36.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1294516517 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 183528121 ps |
| CPU time | 1.99 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:32:41 PM PST 24 |
| Peak memory | 198092 kb |
| Host | smart-69b6a61b-85d3-4713-9635-f6c5d64c5412 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294516517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1294516517 |
| Directory | /workspace/36.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/36.gpio_rand_intr_trigger.3457708808 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 90414465 ps |
| CPU time | 1.89 seconds |
| Started | Jan 07 01:32:18 PM PST 24 |
| Finished | Jan 07 01:32:29 PM PST 24 |
| Peak memory | 196788 kb |
| Host | smart-293ff22d-3df1-4e0e-9737-271ea7d11c30 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457708808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger .3457708808 |
| Directory | /workspace/36.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/36.gpio_random_dout_din.1367034134 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 91655804 ps |
| CPU time | 1.09 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:26 PM PST 24 |
| Peak memory | 196144 kb |
| Host | smart-3f4ac81f-3a8b-4af6-bcfd-4be738b31781 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1367034134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1367034134 |
| Directory | /workspace/36.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.741843281 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 246318913 ps |
| CPU time | 1.23 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:07 PM PST 24 |
| Peak memory | 197224 kb |
| Host | smart-2c9cfac1-311d-4ddb-9904-d2e141c0d967 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741843281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup _pulldown.741843281 |
| Directory | /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1349134860 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 73354734 ps |
| CPU time | 3.26 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:28 PM PST 24 |
| Peak memory | 197912 kb |
| Host | smart-51b2fec2-77c7-4c1b-8639-49c04f5830a8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349134860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra ndom_long_reg_writes_reg_reads.1349134860 |
| Directory | /workspace/36.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/36.gpio_smoke.3141235875 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 132089971 ps |
| CPU time | 0.94 seconds |
| Started | Jan 07 01:32:15 PM PST 24 |
| Finished | Jan 07 01:32:22 PM PST 24 |
| Peak memory | 195944 kb |
| Host | smart-bccc32e9-e9e9-4cea-8219-50065a1ed702 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3141235875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3141235875 |
| Directory | /workspace/36.gpio_smoke/latest |
| Test location | /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3028783466 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 255125186 ps |
| CPU time | 1.22 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:32:21 PM PST 24 |
| Peak memory | 196736 kb |
| Host | smart-950df6af-ea84-4b9d-8274-485a406bbd74 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028783466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3028783466 |
| Directory | /workspace/36.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/36.gpio_stress_all.580582025 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 44975173337 ps |
| CPU time | 125.86 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:34:29 PM PST 24 |
| Peak memory | 198084 kb |
| Host | smart-3977ffa1-e47c-49b4-870d-ea187d87995e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580582025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g pio_stress_all.580582025 |
| Directory | /workspace/36.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2289410898 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 59961507371 ps |
| CPU time | 489.07 seconds |
| Started | Jan 07 01:32:57 PM PST 24 |
| Finished | Jan 07 01:41:09 PM PST 24 |
| Peak memory | 198408 kb |
| Host | smart-193aa27f-a31e-4524-94ca-e3b9299d88a2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2289410898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2289410898 |
| Directory | /workspace/36.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.gpio_alert_test.319097346 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 22703059 ps |
| CPU time | 0.55 seconds |
| Started | Jan 07 01:32:18 PM PST 24 |
| Finished | Jan 07 01:32:27 PM PST 24 |
| Peak memory | 194100 kb |
| Host | smart-431ac470-6f0f-4a4a-bba4-2ce1e93585e7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319097346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.319097346 |
| Directory | /workspace/37.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1441341455 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 31038999 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 01:32:19 PM PST 24 |
| Finished | Jan 07 01:32:28 PM PST 24 |
| Peak memory | 193964 kb |
| Host | smart-03608554-cb21-48cf-814e-2d3f74d44e58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441341455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1441341455 |
| Directory | /workspace/37.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/37.gpio_filter_stress.732753879 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 8372205780 ps |
| CPU time | 23.41 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:33:27 PM PST 24 |
| Peak memory | 196828 kb |
| Host | smart-d7e836c6-2d30-4e47-a260-f30dfa2fcf65 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732753879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres s.732753879 |
| Directory | /workspace/37.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/37.gpio_full_random.1372651771 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 89766955 ps |
| CPU time | 0.64 seconds |
| Started | Jan 07 01:32:12 PM PST 24 |
| Finished | Jan 07 01:32:18 PM PST 24 |
| Peak memory | 194644 kb |
| Host | smart-533b1de7-382c-4c57-ac1f-4d29f6a4a7bb |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372651771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1372651771 |
| Directory | /workspace/37.gpio_full_random/latest |
| Test location | /workspace/coverage/default/37.gpio_intr_rand_pgm.3727403115 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 185030815 ps |
| CPU time | 1.37 seconds |
| Started | Jan 07 01:32:58 PM PST 24 |
| Finished | Jan 07 01:33:04 PM PST 24 |
| Peak memory | 196936 kb |
| Host | smart-94a923ce-ae4a-432d-82e6-4dac2095af68 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727403115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3727403115 |
| Directory | /workspace/37.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.837462014 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 79236888 ps |
| CPU time | 3.3 seconds |
| Started | Jan 07 01:33:01 PM PST 24 |
| Finished | Jan 07 01:33:13 PM PST 24 |
| Peak memory | 197080 kb |
| Host | smart-3cfc8f4a-d064-4a8d-9c11-fe4301397aed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837462014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 37.gpio_intr_with_filter_rand_intr_event.837462014 |
| Directory | /workspace/37.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/37.gpio_rand_intr_trigger.4248289434 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 221261764 ps |
| CPU time | 1.6 seconds |
| Started | Jan 07 01:32:36 PM PST 24 |
| Finished | Jan 07 01:32:41 PM PST 24 |
| Peak memory | 196964 kb |
| Host | smart-171ad2f3-bf1d-4c47-aa2a-3de47e82c3cd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248289434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger .4248289434 |
| Directory | /workspace/37.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/37.gpio_random_dout_din.2666080731 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 73893280 ps |
| CPU time | 0.85 seconds |
| Started | Jan 07 01:32:55 PM PST 24 |
| Finished | Jan 07 01:32:58 PM PST 24 |
| Peak memory | 196120 kb |
| Host | smart-71b69720-8c00-40d2-8307-7aa3fddcb625 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666080731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2666080731 |
| Directory | /workspace/37.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2059797407 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 88469242 ps |
| CPU time | 0.77 seconds |
| Started | Jan 07 01:32:19 PM PST 24 |
| Finished | Jan 07 01:32:28 PM PST 24 |
| Peak memory | 196236 kb |
| Host | smart-ada6fa52-d541-47d0-af22-d0bbeb1c2add |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059797407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu p_pulldown.2059797407 |
| Directory | /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3469446269 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 399605259 ps |
| CPU time | 4.09 seconds |
| Started | Jan 07 01:32:53 PM PST 24 |
| Finished | Jan 07 01:32:59 PM PST 24 |
| Peak memory | 197912 kb |
| Host | smart-a73d7fd7-c6eb-4767-a91d-dcb1edc77a0f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469446269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra ndom_long_reg_writes_reg_reads.3469446269 |
| Directory | /workspace/37.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/37.gpio_smoke.1551810829 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 252460094 ps |
| CPU time | 1.3 seconds |
| Started | Jan 07 01:32:15 PM PST 24 |
| Finished | Jan 07 01:32:22 PM PST 24 |
| Peak memory | 198004 kb |
| Host | smart-44e62975-a0b8-4787-b618-b71d9e1643d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551810829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1551810829 |
| Directory | /workspace/37.gpio_smoke/latest |
| Test location | /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1555851854 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 54816511 ps |
| CPU time | 0.96 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:25 PM PST 24 |
| Peak memory | 195832 kb |
| Host | smart-2daf5fa1-2b4d-49a2-9513-23a545f59a5d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555851854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1555851854 |
| Directory | /workspace/37.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/37.gpio_stress_all.931363462 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 3791473569 ps |
| CPU time | 86.67 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:34:29 PM PST 24 |
| Peak memory | 198248 kb |
| Host | smart-e9bdb235-811b-464f-b1ca-5369d84f0a0c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931363462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g pio_stress_all.931363462 |
| Directory | /workspace/37.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3008459454 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 100424124194 ps |
| CPU time | 1378.12 seconds |
| Started | Jan 07 01:32:20 PM PST 24 |
| Finished | Jan 07 01:55:27 PM PST 24 |
| Peak memory | 198172 kb |
| Host | smart-a3fa7bf1-f796-45ba-9313-c61722401be2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3008459454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3008459454 |
| Directory | /workspace/37.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.gpio_alert_test.3454741455 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 23030572 ps |
| CPU time | 0.6 seconds |
| Started | Jan 07 01:32:20 PM PST 24 |
| Finished | Jan 07 01:32:29 PM PST 24 |
| Peak memory | 194224 kb |
| Host | smart-4c6bfb10-8019-4025-aec3-18e6bdad836f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454741455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3454741455 |
| Directory | /workspace/38.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.596146087 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 375968425 ps |
| CPU time | 0.74 seconds |
| Started | Jan 07 01:33:01 PM PST 24 |
| Finished | Jan 07 01:33:09 PM PST 24 |
| Peak memory | 194064 kb |
| Host | smart-4e4484f6-f002-4f5c-a163-87f4bd631894 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596146087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.596146087 |
| Directory | /workspace/38.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/38.gpio_filter_stress.1545858306 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 599937933 ps |
| CPU time | 15.54 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:32:53 PM PST 24 |
| Peak memory | 198008 kb |
| Host | smart-7fc6e18f-1f1d-48c5-97a8-1ede83cb6e5a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545858306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre ss.1545858306 |
| Directory | /workspace/38.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/38.gpio_full_random.2079707974 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 96764665 ps |
| CPU time | 1.08 seconds |
| Started | Jan 07 01:33:36 PM PST 24 |
| Finished | Jan 07 01:33:38 PM PST 24 |
| Peak memory | 197776 kb |
| Host | smart-5945dbfd-c233-4a77-a0c5-ab030fcd6bd7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079707974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2079707974 |
| Directory | /workspace/38.gpio_full_random/latest |
| Test location | /workspace/coverage/default/38.gpio_intr_rand_pgm.2874571782 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 96242525 ps |
| CPU time | 1.43 seconds |
| Started | Jan 07 01:32:20 PM PST 24 |
| Finished | Jan 07 01:32:30 PM PST 24 |
| Peak memory | 197904 kb |
| Host | smart-493d546c-4c79-4fcd-8dd2-183791833222 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874571782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2874571782 |
| Directory | /workspace/38.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2152500555 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 184307389 ps |
| CPU time | 2.1 seconds |
| Started | Jan 07 01:32:19 PM PST 24 |
| Finished | Jan 07 01:32:30 PM PST 24 |
| Peak memory | 198136 kb |
| Host | smart-52f85e60-76ea-45f1-af6a-86798c3df88a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152500555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2152500555 |
| Directory | /workspace/38.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/38.gpio_rand_intr_trigger.4125620011 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 35762846 ps |
| CPU time | 1.23 seconds |
| Started | Jan 07 01:32:17 PM PST 24 |
| Finished | Jan 07 01:32:27 PM PST 24 |
| Peak memory | 196876 kb |
| Host | smart-f96bfd4a-f75f-402f-8ba7-fbfe5675aad4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125620011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger .4125620011 |
| Directory | /workspace/38.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/38.gpio_random_dout_din.1587516944 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 45373410 ps |
| CPU time | 0.93 seconds |
| Started | Jan 07 01:32:58 PM PST 24 |
| Finished | Jan 07 01:33:03 PM PST 24 |
| Peak memory | 196828 kb |
| Host | smart-11e7afe4-2303-4931-9e0b-605f259f69ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1587516944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1587516944 |
| Directory | /workspace/38.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3543874925 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 177815914 ps |
| CPU time | 0.99 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:25 PM PST 24 |
| Peak memory | 196060 kb |
| Host | smart-0b9ad8e9-b4da-459a-9b5e-36f4260af051 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543874925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu p_pulldown.3543874925 |
| Directory | /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2045395261 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 998186902 ps |
| CPU time | 4.25 seconds |
| Started | Jan 07 01:32:53 PM PST 24 |
| Finished | Jan 07 01:32:59 PM PST 24 |
| Peak memory | 198156 kb |
| Host | smart-0ace80d3-1ca8-4c4e-8cb8-331ea6317818 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045395261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra ndom_long_reg_writes_reg_reads.2045395261 |
| Directory | /workspace/38.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/38.gpio_smoke.40839023 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 41456349 ps |
| CPU time | 1.08 seconds |
| Started | Jan 07 01:32:56 PM PST 24 |
| Finished | Jan 07 01:33:01 PM PST 24 |
| Peak memory | 195940 kb |
| Host | smart-82ea175c-4f3f-4395-8a82-431635fd2f8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40839023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.40839023 |
| Directory | /workspace/38.gpio_smoke/latest |
| Test location | /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2129368773 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 94975401 ps |
| CPU time | 1.23 seconds |
| Started | Jan 07 01:32:18 PM PST 24 |
| Finished | Jan 07 01:32:28 PM PST 24 |
| Peak memory | 196840 kb |
| Host | smart-a93a50ef-aea5-4db7-b782-2aa87d1a515a |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129368773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2129368773 |
| Directory | /workspace/38.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/38.gpio_stress_all.3570106709 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 25230159422 ps |
| CPU time | 89.07 seconds |
| Started | Jan 07 01:32:18 PM PST 24 |
| Finished | Jan 07 01:33:56 PM PST 24 |
| Peak memory | 197912 kb |
| Host | smart-f6065ab0-2200-4da9-acb1-e0eabab34864 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570106709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. gpio_stress_all.3570106709 |
| Directory | /workspace/38.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1393285845 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 29608612457 ps |
| CPU time | 418.75 seconds |
| Started | Jan 07 01:32:14 PM PST 24 |
| Finished | Jan 07 01:39:19 PM PST 24 |
| Peak memory | 198444 kb |
| Host | smart-76473a0d-fd1e-4a35-866d-253b54a376d6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1393285845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1393285845 |
| Directory | /workspace/38.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.gpio_alert_test.1913549336 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 14300785 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 01:33:24 PM PST 24 |
| Peak memory | 194100 kb |
| Host | smart-b9a0f4c3-8baf-45ee-9a63-8f697d3023ab |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913549336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1913549336 |
| Directory | /workspace/39.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2947873689 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 266477382 ps |
| CPU time | 0.73 seconds |
| Started | Jan 07 01:32:57 PM PST 24 |
| Finished | Jan 07 01:33:02 PM PST 24 |
| Peak memory | 195288 kb |
| Host | smart-4ce25ab7-cfb5-457c-b076-9fcd37b97abd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947873689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2947873689 |
| Directory | /workspace/39.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/39.gpio_filter_stress.1396541271 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1042646129 ps |
| CPU time | 27.22 seconds |
| Started | Jan 07 01:33:07 PM PST 24 |
| Finished | Jan 07 01:33:44 PM PST 24 |
| Peak memory | 196628 kb |
| Host | smart-c8860de6-5159-4d12-90fb-26285e2bef2e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396541271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre ss.1396541271 |
| Directory | /workspace/39.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/39.gpio_full_random.2373919505 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 126859630 ps |
| CPU time | 0.75 seconds |
| Started | Jan 07 01:33:07 PM PST 24 |
| Finished | Jan 07 01:33:18 PM PST 24 |
| Peak memory | 196588 kb |
| Host | smart-1885438b-d805-4d43-af8b-edd995165c1d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373919505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2373919505 |
| Directory | /workspace/39.gpio_full_random/latest |
| Test location | /workspace/coverage/default/39.gpio_intr_rand_pgm.1106511261 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 40610972 ps |
| CPU time | 0.85 seconds |
| Started | Jan 07 01:33:01 PM PST 24 |
| Finished | Jan 07 01:33:09 PM PST 24 |
| Peak memory | 195584 kb |
| Host | smart-e811a85c-7f9e-4760-8e35-0d170a8201d6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106511261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1106511261 |
| Directory | /workspace/39.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.4190628677 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 28759164 ps |
| CPU time | 1.31 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:14 PM PST 24 |
| Peak memory | 197916 kb |
| Host | smart-9a30fbef-0e16-4121-9776-a69154da5720 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190628677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.gpio_intr_with_filter_rand_intr_event.4190628677 |
| Directory | /workspace/39.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/39.gpio_rand_intr_trigger.2656432090 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 322347418 ps |
| CPU time | 2.91 seconds |
| Started | Jan 07 01:32:41 PM PST 24 |
| Finished | Jan 07 01:32:46 PM PST 24 |
| Peak memory | 195956 kb |
| Host | smart-fc37fcbe-76e6-490a-9bc5-f0cd0f1c457c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656432090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger .2656432090 |
| Directory | /workspace/39.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/39.gpio_random_dout_din.3051204042 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 131310007 ps |
| CPU time | 1.28 seconds |
| Started | Jan 07 01:32:16 PM PST 24 |
| Finished | Jan 07 01:32:25 PM PST 24 |
| Peak memory | 198132 kb |
| Host | smart-236988d0-696d-48fb-a6b6-2fa952421e93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051204042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3051204042 |
| Directory | /workspace/39.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1298392283 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 15076089 ps |
| CPU time | 0.71 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:06 PM PST 24 |
| Peak memory | 195476 kb |
| Host | smart-97debf35-5b66-4c45-ab6b-7ac681d22ebf |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298392283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu p_pulldown.1298392283 |
| Directory | /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.483869994 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 213043203 ps |
| CPU time | 1.21 seconds |
| Started | Jan 07 01:33:07 PM PST 24 |
| Finished | Jan 07 01:33:18 PM PST 24 |
| Peak memory | 198028 kb |
| Host | smart-afaad232-99b9-4228-ad5e-d1bbfd2f5ebc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483869994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran dom_long_reg_writes_reg_reads.483869994 |
| Directory | /workspace/39.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/39.gpio_smoke.2671417937 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 50682784 ps |
| CPU time | 0.94 seconds |
| Started | Jan 07 01:32:18 PM PST 24 |
| Finished | Jan 07 01:32:28 PM PST 24 |
| Peak memory | 195792 kb |
| Host | smart-7bf817f1-2453-44f1-b51b-3f2470977177 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671417937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2671417937 |
| Directory | /workspace/39.gpio_smoke/latest |
| Test location | /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1118773842 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 167610061 ps |
| CPU time | 1.32 seconds |
| Started | Jan 07 01:32:55 PM PST 24 |
| Finished | Jan 07 01:32:58 PM PST 24 |
| Peak memory | 196744 kb |
| Host | smart-c24131b9-23f8-4451-8579-dfbf490d5a66 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118773842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1118773842 |
| Directory | /workspace/39.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/39.gpio_stress_all.3955368445 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 8009288600 ps |
| CPU time | 164.41 seconds |
| Started | Jan 07 01:33:06 PM PST 24 |
| Finished | Jan 07 01:36:01 PM PST 24 |
| Peak memory | 198156 kb |
| Host | smart-9429928b-4538-43d6-965f-b709de38d296 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955368445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. gpio_stress_all.3955368445 |
| Directory | /workspace/39.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.476525511 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 15627686741 ps |
| CPU time | 366.83 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 01:39:30 PM PST 24 |
| Peak memory | 198440 kb |
| Host | smart-aa03358f-ad84-4326-959e-2fae2afe4228 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =476525511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.476525511 |
| Directory | /workspace/39.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.gpio_alert_test.3866388820 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 23177301 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 194072 kb |
| Host | smart-ebccf43b-dafa-4a2f-8b26-e45b0fd6e288 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866388820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3866388820 |
| Directory | /workspace/4.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1457852784 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 37493079 ps |
| CPU time | 0.75 seconds |
| Started | Jan 07 01:31:12 PM PST 24 |
| Finished | Jan 07 01:31:25 PM PST 24 |
| Peak memory | 195028 kb |
| Host | smart-4ff52953-f079-4c4d-9365-6563f89bc3eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457852784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1457852784 |
| Directory | /workspace/4.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/4.gpio_filter_stress.3136126029 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 251349976 ps |
| CPU time | 8.87 seconds |
| Started | Jan 07 01:31:18 PM PST 24 |
| Finished | Jan 07 01:31:39 PM PST 24 |
| Peak memory | 198124 kb |
| Host | smart-03d42e80-a636-4b08-a11e-c18849878be7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136126029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres s.3136126029 |
| Directory | /workspace/4.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/4.gpio_full_random.2240794257 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 314348541 ps |
| CPU time | 1.06 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 196948 kb |
| Host | smart-391bd010-2215-420d-8092-8cf863113fc6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240794257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2240794257 |
| Directory | /workspace/4.gpio_full_random/latest |
| Test location | /workspace/coverage/default/4.gpio_intr_rand_pgm.3440135283 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 52232568 ps |
| CPU time | 1.02 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 196120 kb |
| Host | smart-e502254d-6d2d-4151-9a80-6de1f3ed80d9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440135283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3440135283 |
| Directory | /workspace/4.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3610671786 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 171701661 ps |
| CPU time | 1.92 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 196552 kb |
| Host | smart-77f98373-9632-4a1f-8655-f1d19fb2ec14 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610671786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3610671786 |
| Directory | /workspace/4.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/4.gpio_rand_intr_trigger.1353117434 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 437664847 ps |
| CPU time | 1.21 seconds |
| Started | Jan 07 01:31:18 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 196880 kb |
| Host | smart-79e9e0bb-5ccf-44d9-876a-ab13e47e563d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353117434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger. 1353117434 |
| Directory | /workspace/4.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/4.gpio_random_dout_din.1038652675 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 23747489 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 01:31:19 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 196128 kb |
| Host | smart-ac6d1517-b8a0-4de6-9b0e-419dfc069693 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1038652675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1038652675 |
| Directory | /workspace/4.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1839446302 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 18083927 ps |
| CPU time | 0.79 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 195528 kb |
| Host | smart-a971a270-2daf-4736-80e3-430d3db5d508 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839446302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup _pulldown.1839446302 |
| Directory | /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.370005206 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 404466383 ps |
| CPU time | 5.02 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 198116 kb |
| Host | smart-ce073ee1-0188-4347-bc36-78e55212bf62 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370005206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand om_long_reg_writes_reg_reads.370005206 |
| Directory | /workspace/4.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/4.gpio_smoke.1075192182 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 83118015 ps |
| CPU time | 0.77 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 195272 kb |
| Host | smart-1ddf8f69-5f6e-4dfa-967d-f0545cfa2144 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075192182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1075192182 |
| Directory | /workspace/4.gpio_smoke/latest |
| Test location | /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2264659132 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 309218942 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:34 PM PST 24 |
| Peak memory | 195696 kb |
| Host | smart-72a317f4-3ac3-45a8-a8e0-8726c31bf7f9 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264659132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2264659132 |
| Directory | /workspace/4.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/4.gpio_stress_all.1377656279 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 9879539439 ps |
| CPU time | 145.16 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:33:57 PM PST 24 |
| Peak memory | 198300 kb |
| Host | smart-c0891a25-f839-4295-9204-c0c9f5c6be8b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377656279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g pio_stress_all.1377656279 |
| Directory | /workspace/4.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1440598232 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 17542286030 ps |
| CPU time | 149.22 seconds |
| Started | Jan 07 01:31:18 PM PST 24 |
| Finished | Jan 07 01:34:00 PM PST 24 |
| Peak memory | 198300 kb |
| Host | smart-63f3dd40-1d32-4ba1-8f78-ce6332c6d154 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1440598232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1440598232 |
| Directory | /workspace/4.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.gpio_alert_test.414340517 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 13117706 ps |
| CPU time | 0.62 seconds |
| Started | Jan 07 01:32:33 PM PST 24 |
| Finished | Jan 07 01:32:36 PM PST 24 |
| Peak memory | 193948 kb |
| Host | smart-3d1ecb50-7e06-48dd-ab0e-a702e30dbaf1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414340517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.414340517 |
| Directory | /workspace/40.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1049719621 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 96772275 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:33:22 PM PST 24 |
| Finished | Jan 07 01:33:30 PM PST 24 |
| Peak memory | 196532 kb |
| Host | smart-6d7a68f9-e9e5-4ff2-8f36-5373164dd0a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1049719621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1049719621 |
| Directory | /workspace/40.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/40.gpio_filter_stress.819919471 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 630214395 ps |
| CPU time | 14.83 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:21 PM PST 24 |
| Peak memory | 196964 kb |
| Host | smart-71d091ba-e7ee-4fd0-8c54-7567da426075 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819919471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres s.819919471 |
| Directory | /workspace/40.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/40.gpio_full_random.3432258722 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 269761929 ps |
| CPU time | 0.73 seconds |
| Started | Jan 07 01:32:32 PM PST 24 |
| Finished | Jan 07 01:32:36 PM PST 24 |
| Peak memory | 194660 kb |
| Host | smart-77bced3b-637a-4a09-b8ab-a60b1dbecedd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432258722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3432258722 |
| Directory | /workspace/40.gpio_full_random/latest |
| Test location | /workspace/coverage/default/40.gpio_intr_rand_pgm.4112320067 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 82257854 ps |
| CPU time | 0.79 seconds |
| Started | Jan 07 01:32:33 PM PST 24 |
| Finished | Jan 07 01:32:37 PM PST 24 |
| Peak memory | 195536 kb |
| Host | smart-3c0058b8-8b44-4e99-ac86-d730f7a566be |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112320067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.4112320067 |
| Directory | /workspace/40.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3243515175 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 65088334 ps |
| CPU time | 2.02 seconds |
| Started | Jan 07 01:33:02 PM PST 24 |
| Finished | Jan 07 01:33:12 PM PST 24 |
| Peak memory | 198240 kb |
| Host | smart-f1037ff4-ba30-4aa3-9a4d-922b7eb6c69e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243515175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3243515175 |
| Directory | /workspace/40.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/40.gpio_rand_intr_trigger.2844332834 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 488325830 ps |
| CPU time | 3.68 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:32:42 PM PST 24 |
| Peak memory | 196628 kb |
| Host | smart-34c61066-f4bb-454a-9c67-076edf465c4b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844332834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger .2844332834 |
| Directory | /workspace/40.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/40.gpio_random_dout_din.2053503595 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1001552879 ps |
| CPU time | 1.37 seconds |
| Started | Jan 07 01:33:12 PM PST 24 |
| Finished | Jan 07 01:33:23 PM PST 24 |
| Peak memory | 197240 kb |
| Host | smart-cc876af4-ecdd-4a11-bc1f-ad5297b7997c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053503595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2053503595 |
| Directory | /workspace/40.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1640109024 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 123082480 ps |
| CPU time | 1.29 seconds |
| Started | Jan 07 01:33:13 PM PST 24 |
| Finished | Jan 07 01:33:23 PM PST 24 |
| Peak memory | 198168 kb |
| Host | smart-c1b59fcd-6832-4d10-91e5-53b5a76ff4fa |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640109024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu p_pulldown.1640109024 |
| Directory | /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.223101276 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 333426415 ps |
| CPU time | 4.32 seconds |
| Started | Jan 07 01:32:36 PM PST 24 |
| Finished | Jan 07 01:32:44 PM PST 24 |
| Peak memory | 197980 kb |
| Host | smart-7dd67831-e23c-4fd8-8e1e-37338e6dfb83 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223101276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran dom_long_reg_writes_reg_reads.223101276 |
| Directory | /workspace/40.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/40.gpio_smoke.4278102810 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 37485937 ps |
| CPU time | 0.86 seconds |
| Started | Jan 07 01:33:04 PM PST 24 |
| Finished | Jan 07 01:33:14 PM PST 24 |
| Peak memory | 195728 kb |
| Host | smart-4dcf0d1e-2301-49b3-b99b-5fea3b93ab83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278102810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.4278102810 |
| Directory | /workspace/40.gpio_smoke/latest |
| Test location | /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2576851346 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 111056045 ps |
| CPU time | 0.95 seconds |
| Started | Jan 07 01:33:20 PM PST 24 |
| Finished | Jan 07 01:33:29 PM PST 24 |
| Peak memory | 195692 kb |
| Host | smart-6b128fb9-beb6-4641-a831-2d6acddfe100 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576851346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2576851346 |
| Directory | /workspace/40.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/40.gpio_stress_all.1031800596 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 30443386570 ps |
| CPU time | 66.8 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:34:28 PM PST 24 |
| Peak memory | 198184 kb |
| Host | smart-e20c6278-e4d4-4652-88bd-cb0d521831dd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031800596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. gpio_stress_all.1031800596 |
| Directory | /workspace/40.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.846866527 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 199681661171 ps |
| CPU time | 1031.49 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:50:24 PM PST 24 |
| Peak memory | 196836 kb |
| Host | smart-d12abee1-1557-4e8c-99f3-eea41f6d6ea6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =846866527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.846866527 |
| Directory | /workspace/40.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.gpio_alert_test.2457040256 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 13544790 ps |
| CPU time | 0.59 seconds |
| Started | Jan 07 01:32:36 PM PST 24 |
| Finished | Jan 07 01:32:40 PM PST 24 |
| Peak memory | 192732 kb |
| Host | smart-7165043d-246e-4c66-88b9-26855d48cfb9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457040256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2457040256 |
| Directory | /workspace/41.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1088613795 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 85531296 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:33:01 PM PST 24 |
| Finished | Jan 07 01:33:08 PM PST 24 |
| Peak memory | 197264 kb |
| Host | smart-a39e6ac3-9650-45fa-8cba-9a15e8033034 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1088613795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1088613795 |
| Directory | /workspace/41.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/41.gpio_filter_stress.1671977374 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 365318775 ps |
| CPU time | 13.95 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:32:52 PM PST 24 |
| Peak memory | 196980 kb |
| Host | smart-063c8761-5e08-4b9e-84a6-c2fdb32bee3b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671977374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre ss.1671977374 |
| Directory | /workspace/41.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/41.gpio_full_random.2329532560 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 275557777 ps |
| CPU time | 0.84 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:06 PM PST 24 |
| Peak memory | 195980 kb |
| Host | smart-76c10de7-afde-4320-8849-17b799227da4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329532560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2329532560 |
| Directory | /workspace/41.gpio_full_random/latest |
| Test location | /workspace/coverage/default/41.gpio_intr_rand_pgm.3580565469 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 351509808 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:06 PM PST 24 |
| Peak memory | 197336 kb |
| Host | smart-3f98928b-bbfc-41d0-a069-6350523c06c6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580565469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3580565469 |
| Directory | /workspace/41.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.383133135 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 273188303 ps |
| CPU time | 2.75 seconds |
| Started | Jan 07 01:32:34 PM PST 24 |
| Finished | Jan 07 01:32:39 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-084aff64-9eeb-4807-bd18-c33f446cc76b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383133135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 41.gpio_intr_with_filter_rand_intr_event.383133135 |
| Directory | /workspace/41.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/41.gpio_rand_intr_trigger.2721255305 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 423094170 ps |
| CPU time | 3.03 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:15 PM PST 24 |
| Peak memory | 197036 kb |
| Host | smart-210c81d2-752f-4b83-a233-e4e8285b6f80 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721255305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger .2721255305 |
| Directory | /workspace/41.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/41.gpio_random_dout_din.1966975225 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 374082241 ps |
| CPU time | 1 seconds |
| Started | Jan 07 01:32:59 PM PST 24 |
| Finished | Jan 07 01:33:04 PM PST 24 |
| Peak memory | 195256 kb |
| Host | smart-221124d0-041b-4053-ac37-4e56a1ad069e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1966975225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1966975225 |
| Directory | /workspace/41.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2204632658 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 146057424 ps |
| CPU time | 0.91 seconds |
| Started | Jan 07 01:33:01 PM PST 24 |
| Finished | Jan 07 01:33:09 PM PST 24 |
| Peak memory | 195860 kb |
| Host | smart-d7c853bb-87f7-4e0b-adcc-99852ac45166 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204632658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu p_pulldown.2204632658 |
| Directory | /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.966628918 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 256673349 ps |
| CPU time | 4.16 seconds |
| Started | Jan 07 01:32:32 PM PST 24 |
| Finished | Jan 07 01:32:39 PM PST 24 |
| Peak memory | 197012 kb |
| Host | smart-dac7e93e-effd-486d-b23d-e8ec0f9611e0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966628918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran dom_long_reg_writes_reg_reads.966628918 |
| Directory | /workspace/41.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/41.gpio_smoke.3629422085 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 63976340 ps |
| CPU time | 1.18 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:06 PM PST 24 |
| Peak memory | 196768 kb |
| Host | smart-f8d370d0-153f-41cd-bccf-f208c6b00641 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629422085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3629422085 |
| Directory | /workspace/41.gpio_smoke/latest |
| Test location | /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1351829760 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 208147911 ps |
| CPU time | 1.2 seconds |
| Started | Jan 07 01:32:32 PM PST 24 |
| Finished | Jan 07 01:32:36 PM PST 24 |
| Peak memory | 196284 kb |
| Host | smart-0dd11a20-8393-497c-974f-a5cce76e10d7 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351829760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1351829760 |
| Directory | /workspace/41.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/41.gpio_stress_all.917377125 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 5085413983 ps |
| CPU time | 75.83 seconds |
| Started | Jan 07 01:33:01 PM PST 24 |
| Finished | Jan 07 01:34:23 PM PST 24 |
| Peak memory | 198168 kb |
| Host | smart-742a01d3-1827-4ac1-b01f-7d6e8f57a91a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917377125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g pio_stress_all.917377125 |
| Directory | /workspace/41.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.1666811432 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 398419727161 ps |
| CPU time | 1251.86 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:54:04 PM PST 24 |
| Peak memory | 196788 kb |
| Host | smart-34485dec-a835-42ad-9668-c20ea1e9ee72 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1666811432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.1666811432 |
| Directory | /workspace/41.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.gpio_alert_test.2857923024 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 24352271 ps |
| CPU time | 0.55 seconds |
| Started | Jan 07 01:32:33 PM PST 24 |
| Finished | Jan 07 01:32:36 PM PST 24 |
| Peak memory | 194260 kb |
| Host | smart-d3ace77b-8ff4-4d48-b649-668c1b26058a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857923024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2857923024 |
| Directory | /workspace/42.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.4084725944 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 44417281 ps |
| CPU time | 0.67 seconds |
| Started | Jan 07 01:32:33 PM PST 24 |
| Finished | Jan 07 01:32:37 PM PST 24 |
| Peak memory | 194168 kb |
| Host | smart-9d664352-218f-40dd-9321-4f8a1840f3cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084725944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.4084725944 |
| Directory | /workspace/42.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/42.gpio_filter_stress.4257782029 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1364322762 ps |
| CPU time | 18.65 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:25 PM PST 24 |
| Peak memory | 198064 kb |
| Host | smart-b711e8af-cb77-4931-af14-a062cc7a686d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257782029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre ss.4257782029 |
| Directory | /workspace/42.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/42.gpio_full_random.1872467809 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 107638806 ps |
| CPU time | 0.71 seconds |
| Started | Jan 07 01:32:33 PM PST 24 |
| Finished | Jan 07 01:32:37 PM PST 24 |
| Peak memory | 194748 kb |
| Host | smart-b468ff34-6f4d-4dc6-939c-8f83604bfaa7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872467809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1872467809 |
| Directory | /workspace/42.gpio_full_random/latest |
| Test location | /workspace/coverage/default/42.gpio_intr_rand_pgm.1305590758 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 185916840 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 01:33:02 PM PST 24 |
| Finished | Jan 07 01:33:12 PM PST 24 |
| Peak memory | 197492 kb |
| Host | smart-a505026f-132d-467f-9d7d-3159861daec3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305590758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1305590758 |
| Directory | /workspace/42.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3495511283 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 285383853 ps |
| CPU time | 2.89 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:10 PM PST 24 |
| Peak memory | 198180 kb |
| Host | smart-514b124d-c418-4f39-933d-7fdbd0a5aa10 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495511283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3495511283 |
| Directory | /workspace/42.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/42.gpio_rand_intr_trigger.3299155378 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 162190192 ps |
| CPU time | 2.5 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:09 PM PST 24 |
| Peak memory | 195860 kb |
| Host | smart-d8b3900b-b7e8-45eb-9842-22c03d4ec238 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299155378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger .3299155378 |
| Directory | /workspace/42.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/42.gpio_random_dout_din.1083691390 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 301335022 ps |
| CPU time | 0.7 seconds |
| Started | Jan 07 01:32:33 PM PST 24 |
| Finished | Jan 07 01:32:36 PM PST 24 |
| Peak memory | 196068 kb |
| Host | smart-f6a00233-2301-4d04-84b5-b0193bedeb7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083691390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1083691390 |
| Directory | /workspace/42.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1984324191 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 17500939 ps |
| CPU time | 0.73 seconds |
| Started | Jan 07 01:33:01 PM PST 24 |
| Finished | Jan 07 01:33:08 PM PST 24 |
| Peak memory | 196064 kb |
| Host | smart-e80acaaa-d3e8-4308-a686-e2bf5e2cd70d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984324191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu p_pulldown.1984324191 |
| Directory | /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.447275376 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 326294138 ps |
| CPU time | 5.08 seconds |
| Started | Jan 07 01:33:00 PM PST 24 |
| Finished | Jan 07 01:33:22 PM PST 24 |
| Peak memory | 198132 kb |
| Host | smart-a50318c5-2fe5-4d6b-99e9-1ae9c04c0334 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447275376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran dom_long_reg_writes_reg_reads.447275376 |
| Directory | /workspace/42.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/42.gpio_smoke.3682355406 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 485993842 ps |
| CPU time | 0.91 seconds |
| Started | Jan 07 01:32:31 PM PST 24 |
| Finished | Jan 07 01:32:35 PM PST 24 |
| Peak memory | 196540 kb |
| Host | smart-2868574f-a57b-4250-89f2-675151f2c976 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682355406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3682355406 |
| Directory | /workspace/42.gpio_smoke/latest |
| Test location | /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3245472920 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 50936920 ps |
| CPU time | 0.92 seconds |
| Started | Jan 07 01:32:32 PM PST 24 |
| Finished | Jan 07 01:32:36 PM PST 24 |
| Peak memory | 195292 kb |
| Host | smart-103877b4-737c-48da-8e87-e75fdaf86d14 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245472920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3245472920 |
| Directory | /workspace/42.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/42.gpio_stress_all.2305816557 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 5501727267 ps |
| CPU time | 36.49 seconds |
| Started | Jan 07 01:32:39 PM PST 24 |
| Finished | Jan 07 01:33:20 PM PST 24 |
| Peak memory | 198224 kb |
| Host | smart-5cd9a4e1-b5a3-4166-8456-8648321b9803 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305816557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. gpio_stress_all.2305816557 |
| Directory | /workspace/42.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3748864544 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 498643423236 ps |
| CPU time | 2031.68 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 02:06:30 PM PST 24 |
| Peak memory | 198376 kb |
| Host | smart-f5dfeba9-13ec-4666-90fe-217b33086fea |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3748864544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3748864544 |
| Directory | /workspace/42.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.gpio_alert_test.697822202 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 26199066 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 01:33:37 PM PST 24 |
| Finished | Jan 07 01:33:38 PM PST 24 |
| Peak memory | 194072 kb |
| Host | smart-fb727b9f-7aeb-4afd-9f19-89daf3b878dc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697822202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.697822202 |
| Directory | /workspace/43.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1540888003 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 103734908 ps |
| CPU time | 0.84 seconds |
| Started | Jan 07 01:33:05 PM PST 24 |
| Finished | Jan 07 01:33:15 PM PST 24 |
| Peak memory | 196592 kb |
| Host | smart-ebf72b5e-182f-49bb-a733-1e04f05e9508 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540888003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1540888003 |
| Directory | /workspace/43.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/43.gpio_filter_stress.2339460980 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1715294208 ps |
| CPU time | 19.75 seconds |
| Started | Jan 07 01:33:13 PM PST 24 |
| Finished | Jan 07 01:33:42 PM PST 24 |
| Peak memory | 195692 kb |
| Host | smart-9add7be0-80aa-4478-a38c-52c947e635f9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339460980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre ss.2339460980 |
| Directory | /workspace/43.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/43.gpio_full_random.1864788447 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 296583074 ps |
| CPU time | 1.07 seconds |
| Started | Jan 07 01:33:07 PM PST 24 |
| Finished | Jan 07 01:33:19 PM PST 24 |
| Peak memory | 198028 kb |
| Host | smart-eee4f1f8-c4c4-4a9d-a1d9-d9161873fb48 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864788447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1864788447 |
| Directory | /workspace/43.gpio_full_random/latest |
| Test location | /workspace/coverage/default/43.gpio_intr_rand_pgm.2255268335 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 98451473 ps |
| CPU time | 0.89 seconds |
| Started | Jan 07 01:33:41 PM PST 24 |
| Finished | Jan 07 01:33:43 PM PST 24 |
| Peak memory | 197508 kb |
| Host | smart-7d06542f-bdad-4044-b0df-342471c02747 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255268335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2255268335 |
| Directory | /workspace/43.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1488445164 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 99375787 ps |
| CPU time | 0.92 seconds |
| Started | Jan 07 01:33:43 PM PST 24 |
| Finished | Jan 07 01:33:46 PM PST 24 |
| Peak memory | 196052 kb |
| Host | smart-08528cec-594c-4857-acac-77ebba22f05c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488445164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1488445164 |
| Directory | /workspace/43.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/43.gpio_rand_intr_trigger.993919910 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 323153172 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 01:33:44 PM PST 24 |
| Finished | Jan 07 01:33:47 PM PST 24 |
| Peak memory | 195096 kb |
| Host | smart-629b1907-fefb-4b5e-bbca-64617a2df3b1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993919910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger. 993919910 |
| Directory | /workspace/43.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/43.gpio_random_dout_din.1716827014 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 148689960 ps |
| CPU time | 1.02 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:13 PM PST 24 |
| Peak memory | 196204 kb |
| Host | smart-da5fcca8-b16e-421e-bcee-3270e1209b03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1716827014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1716827014 |
| Directory | /workspace/43.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1244096815 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 144319500 ps |
| CPU time | 0.7 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:12 PM PST 24 |
| Peak memory | 195340 kb |
| Host | smart-2ce2c161-9295-41c6-9363-5be44220270b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244096815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu p_pulldown.1244096815 |
| Directory | /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2649100052 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2334857269 ps |
| CPU time | 5.71 seconds |
| Started | Jan 07 01:33:19 PM PST 24 |
| Finished | Jan 07 01:33:33 PM PST 24 |
| Peak memory | 198160 kb |
| Host | smart-b95cf88d-e537-42dd-ba73-d58ccc23a20f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649100052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra ndom_long_reg_writes_reg_reads.2649100052 |
| Directory | /workspace/43.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/43.gpio_smoke.2918177906 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 58734302 ps |
| CPU time | 1.06 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:13 PM PST 24 |
| Peak memory | 196356 kb |
| Host | smart-4f4c49fb-b1ac-43d3-8ee9-9139b11cb576 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918177906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2918177906 |
| Directory | /workspace/43.gpio_smoke/latest |
| Test location | /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2388502773 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 342568385 ps |
| CPU time | 1.37 seconds |
| Started | Jan 07 01:33:02 PM PST 24 |
| Finished | Jan 07 01:33:12 PM PST 24 |
| Peak memory | 196904 kb |
| Host | smart-c6aba0d4-78f1-4d66-9e82-fc89d6db1658 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388502773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2388502773 |
| Directory | /workspace/43.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/43.gpio_stress_all.905275341 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 14944938668 ps |
| CPU time | 166.64 seconds |
| Started | Jan 07 01:33:14 PM PST 24 |
| Finished | Jan 07 01:36:09 PM PST 24 |
| Peak memory | 198208 kb |
| Host | smart-b550cfdd-22f5-4632-ac02-514872932a61 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905275341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g pio_stress_all.905275341 |
| Directory | /workspace/43.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.427781210 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 128019645224 ps |
| CPU time | 1644.76 seconds |
| Started | Jan 07 01:33:17 PM PST 24 |
| Finished | Jan 07 02:00:50 PM PST 24 |
| Peak memory | 198300 kb |
| Host | smart-fe2ba1a0-39f2-4ef3-99dd-7b87d396b0c7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =427781210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.427781210 |
| Directory | /workspace/43.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.gpio_alert_test.3187763586 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 29559951 ps |
| CPU time | 0.54 seconds |
| Started | Jan 07 01:32:34 PM PST 24 |
| Finished | Jan 07 01:32:37 PM PST 24 |
| Peak memory | 193504 kb |
| Host | smart-baa88c6e-7520-43d6-8930-93bee8dee131 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187763586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3187763586 |
| Directory | /workspace/44.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3434688317 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 25957857 ps |
| CPU time | 0.81 seconds |
| Started | Jan 07 01:33:20 PM PST 24 |
| Finished | Jan 07 01:33:29 PM PST 24 |
| Peak memory | 195312 kb |
| Host | smart-aeb37f67-67c0-4247-910d-d7afda191aa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3434688317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3434688317 |
| Directory | /workspace/44.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/44.gpio_filter_stress.3243012041 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 352978213 ps |
| CPU time | 12.03 seconds |
| Started | Jan 07 01:33:18 PM PST 24 |
| Finished | Jan 07 01:33:37 PM PST 24 |
| Peak memory | 196824 kb |
| Host | smart-1582108b-32de-4d4b-af22-dae1a24313fe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243012041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre ss.3243012041 |
| Directory | /workspace/44.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/44.gpio_full_random.4278749875 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 83161705 ps |
| CPU time | 1.09 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:13 PM PST 24 |
| Peak memory | 197096 kb |
| Host | smart-06b0c962-127c-46b1-ac7b-97f7ce7cce2f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278749875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.4278749875 |
| Directory | /workspace/44.gpio_full_random/latest |
| Test location | /workspace/coverage/default/44.gpio_intr_rand_pgm.2061757951 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 59514028 ps |
| CPU time | 0.75 seconds |
| Started | Jan 07 01:33:53 PM PST 24 |
| Finished | Jan 07 01:33:55 PM PST 24 |
| Peak memory | 195460 kb |
| Host | smart-77abbf4e-db5b-487f-b21d-eec334c47a2c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061757951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2061757951 |
| Directory | /workspace/44.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2785717378 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 134955079 ps |
| CPU time | 0.92 seconds |
| Started | Jan 07 01:33:18 PM PST 24 |
| Finished | Jan 07 01:33:26 PM PST 24 |
| Peak memory | 196084 kb |
| Host | smart-d67c5a10-cd3d-42e9-a1c0-62504a4d65b6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785717378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2785717378 |
| Directory | /workspace/44.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/44.gpio_rand_intr_trigger.2677152261 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 119724934 ps |
| CPU time | 3.25 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 01:33:26 PM PST 24 |
| Peak memory | 197444 kb |
| Host | smart-20a80942-cd15-44bf-8cf8-2e9a4697a625 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677152261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger .2677152261 |
| Directory | /workspace/44.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/44.gpio_random_dout_din.1905073920 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 149881384 ps |
| CPU time | 1.3 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 01:33:25 PM PST 24 |
| Peak memory | 195956 kb |
| Host | smart-9e379a44-aaee-4dba-8dce-214193f1771f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1905073920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1905073920 |
| Directory | /workspace/44.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3952934596 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 200174828 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:33:38 PM PST 24 |
| Finished | Jan 07 01:33:40 PM PST 24 |
| Peak memory | 196944 kb |
| Host | smart-04227de4-e789-4e0f-9601-e32b57decd03 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952934596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu p_pulldown.3952934596 |
| Directory | /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2915209977 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 278195115 ps |
| CPU time | 1.64 seconds |
| Started | Jan 07 01:32:36 PM PST 24 |
| Finished | Jan 07 01:32:42 PM PST 24 |
| Peak memory | 198076 kb |
| Host | smart-c0e7f720-6988-4fbf-afc9-d2e5b7b439c3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915209977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra ndom_long_reg_writes_reg_reads.2915209977 |
| Directory | /workspace/44.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/44.gpio_smoke.3333152865 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 61863425 ps |
| CPU time | 0.79 seconds |
| Started | Jan 07 01:33:20 PM PST 24 |
| Finished | Jan 07 01:33:28 PM PST 24 |
| Peak memory | 195316 kb |
| Host | smart-3cfa1a64-6786-4b01-a864-9d9314877915 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3333152865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3333152865 |
| Directory | /workspace/44.gpio_smoke/latest |
| Test location | /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1825092847 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 69739022 ps |
| CPU time | 1.27 seconds |
| Started | Jan 07 01:33:19 PM PST 24 |
| Finished | Jan 07 01:33:29 PM PST 24 |
| Peak memory | 197040 kb |
| Host | smart-d8ca8202-27b1-4909-a4ea-648b34a5b8a6 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825092847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1825092847 |
| Directory | /workspace/44.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/44.gpio_stress_all.2202261639 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 14303424454 ps |
| CPU time | 205.88 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:36:39 PM PST 24 |
| Peak memory | 198296 kb |
| Host | smart-d19c482f-180e-4b4d-8914-61ab33c89b4d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202261639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. gpio_stress_all.2202261639 |
| Directory | /workspace/44.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2169023573 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 96854813082 ps |
| CPU time | 95.18 seconds |
| Started | Jan 07 01:32:34 PM PST 24 |
| Finished | Jan 07 01:34:12 PM PST 24 |
| Peak memory | 198304 kb |
| Host | smart-5ebbfef8-de3b-4167-8f5e-519ea7121ce7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2169023573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2169023573 |
| Directory | /workspace/44.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.gpio_alert_test.3590455677 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 94244597 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:12 PM PST 24 |
| Peak memory | 194776 kb |
| Host | smart-5d3797f9-77e0-4b8e-9b89-1956b4c5d1bb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590455677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3590455677 |
| Directory | /workspace/45.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.4020842588 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 17485325 ps |
| CPU time | 0.63 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:13 PM PST 24 |
| Peak memory | 194816 kb |
| Host | smart-46e503ec-69e3-4be4-8f6e-e7c30b868714 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020842588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.4020842588 |
| Directory | /workspace/45.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/45.gpio_filter_stress.1657585022 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1575206558 ps |
| CPU time | 9.68 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:32:48 PM PST 24 |
| Peak memory | 198048 kb |
| Host | smart-44c6b345-ac8f-409f-9b2e-9a9fe777ba7f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657585022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre ss.1657585022 |
| Directory | /workspace/45.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/45.gpio_full_random.3631840151 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 44129454 ps |
| CPU time | 0.89 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:32:38 PM PST 24 |
| Peak memory | 197728 kb |
| Host | smart-a619e5ce-b0f7-4a92-bbe1-babede8267a0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631840151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3631840151 |
| Directory | /workspace/45.gpio_full_random/latest |
| Test location | /workspace/coverage/default/45.gpio_intr_rand_pgm.3249607489 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 35842785 ps |
| CPU time | 0.98 seconds |
| Started | Jan 07 01:33:02 PM PST 24 |
| Finished | Jan 07 01:33:11 PM PST 24 |
| Peak memory | 196744 kb |
| Host | smart-d1dd7075-ac86-4b79-ad2e-1a47d93675a4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249607489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3249607489 |
| Directory | /workspace/45.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.628284926 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 165198494 ps |
| CPU time | 3.32 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:15 PM PST 24 |
| Peak memory | 196380 kb |
| Host | smart-2bc4c0f1-bff7-49b2-b46d-812f190c4c4b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628284926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 45.gpio_intr_with_filter_rand_intr_event.628284926 |
| Directory | /workspace/45.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/45.gpio_rand_intr_trigger.2932358632 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 546332522 ps |
| CPU time | 3.12 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:15 PM PST 24 |
| Peak memory | 198164 kb |
| Host | smart-30524f80-210a-4c5e-8be6-93843f596543 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932358632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger .2932358632 |
| Directory | /workspace/45.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/45.gpio_random_dout_din.2749389654 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 252752745 ps |
| CPU time | 1.11 seconds |
| Started | Jan 07 01:32:37 PM PST 24 |
| Finished | Jan 07 01:32:43 PM PST 24 |
| Peak memory | 195940 kb |
| Host | smart-f5ab9dba-b2ac-4b45-9482-d2eee1ece64c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2749389654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2749389654 |
| Directory | /workspace/45.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.4174319784 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 56690536 ps |
| CPU time | 0.65 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:13 PM PST 24 |
| Peak memory | 194968 kb |
| Host | smart-d18cef82-3ac3-4ace-9c81-0fffc1ba97b3 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174319784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu p_pulldown.4174319784 |
| Directory | /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1412610172 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1084916304 ps |
| CPU time | 3.08 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:32:41 PM PST 24 |
| Peak memory | 198008 kb |
| Host | smart-4c34a10d-77ea-47bc-a1e8-bbd89bb5a6db |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412610172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra ndom_long_reg_writes_reg_reads.1412610172 |
| Directory | /workspace/45.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/45.gpio_smoke.1070246342 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 167548621 ps |
| CPU time | 1.32 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:14 PM PST 24 |
| Peak memory | 196948 kb |
| Host | smart-2ddddab1-ef01-473c-91eb-7d32273816df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1070246342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1070246342 |
| Directory | /workspace/45.gpio_smoke/latest |
| Test location | /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2446648795 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 41666375 ps |
| CPU time | 1.25 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:19 PM PST 24 |
| Peak memory | 196956 kb |
| Host | smart-0ee4469c-eab3-4091-a3a6-db9654557d8c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446648795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2446648795 |
| Directory | /workspace/45.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/45.gpio_stress_all.1783269099 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 11114108808 ps |
| CPU time | 158.61 seconds |
| Started | Jan 07 01:32:34 PM PST 24 |
| Finished | Jan 07 01:35:15 PM PST 24 |
| Peak memory | 198220 kb |
| Host | smart-086bfb6a-4453-4883-b9d9-5c57f0726305 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783269099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. gpio_stress_all.1783269099 |
| Directory | /workspace/45.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.311176001 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 69220445926 ps |
| CPU time | 87.82 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:34:40 PM PST 24 |
| Peak memory | 198348 kb |
| Host | smart-a8fea53b-77a1-4c90-b805-051f764ba656 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =311176001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.311176001 |
| Directory | /workspace/45.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.gpio_alert_test.3035268830 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 29451159 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 01:33:04 PM PST 24 |
| Finished | Jan 07 01:33:13 PM PST 24 |
| Peak memory | 194320 kb |
| Host | smart-a1429be7-8858-4ef2-bdcb-6402b664ad7f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035268830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3035268830 |
| Directory | /workspace/46.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.414468719 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 33657045 ps |
| CPU time | 0.71 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:12 PM PST 24 |
| Peak memory | 194052 kb |
| Host | smart-cc84956c-cd7b-4cc9-af07-7b3b89c645c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414468719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.414468719 |
| Directory | /workspace/46.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/46.gpio_filter_stress.1538645212 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 1737439362 ps |
| CPU time | 22.61 seconds |
| Started | Jan 07 01:32:34 PM PST 24 |
| Finished | Jan 07 01:32:59 PM PST 24 |
| Peak memory | 196804 kb |
| Host | smart-73940761-c264-40a0-967f-7b501aaf8e0a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538645212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre ss.1538645212 |
| Directory | /workspace/46.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/46.gpio_full_random.1466747542 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 256249306 ps |
| CPU time | 0.91 seconds |
| Started | Jan 07 01:33:04 PM PST 24 |
| Finished | Jan 07 01:33:14 PM PST 24 |
| Peak memory | 197576 kb |
| Host | smart-1b49c977-32d9-464e-b1df-c7305f202271 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466747542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1466747542 |
| Directory | /workspace/46.gpio_full_random/latest |
| Test location | /workspace/coverage/default/46.gpio_intr_rand_pgm.1189033288 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 49748619 ps |
| CPU time | 0.86 seconds |
| Started | Jan 07 01:33:01 PM PST 24 |
| Finished | Jan 07 01:33:11 PM PST 24 |
| Peak memory | 196628 kb |
| Host | smart-ba74677a-dd8c-456b-836c-9c6580774d06 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189033288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1189033288 |
| Directory | /workspace/46.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.816930559 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 122071556 ps |
| CPU time | 1.48 seconds |
| Started | Jan 07 01:32:38 PM PST 24 |
| Finished | Jan 07 01:32:44 PM PST 24 |
| Peak memory | 198148 kb |
| Host | smart-01bac400-7c45-4fa7-a169-9ce00ab2698a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816930559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 46.gpio_intr_with_filter_rand_intr_event.816930559 |
| Directory | /workspace/46.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/46.gpio_rand_intr_trigger.2052756258 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 114457714 ps |
| CPU time | 3.45 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:32:42 PM PST 24 |
| Peak memory | 198192 kb |
| Host | smart-10ae3018-3021-47c0-8afa-d8939760cb66 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052756258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger .2052756258 |
| Directory | /workspace/46.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/46.gpio_random_dout_din.3839074091 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 71226606 ps |
| CPU time | 0.68 seconds |
| Started | Jan 07 01:33:02 PM PST 24 |
| Finished | Jan 07 01:33:12 PM PST 24 |
| Peak memory | 194964 kb |
| Host | smart-3d0f1779-53da-46f4-a05a-eae1fd5a13c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839074091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3839074091 |
| Directory | /workspace/46.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.446098540 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 91011558 ps |
| CPU time | 1.06 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:13 PM PST 24 |
| Peak memory | 196780 kb |
| Host | smart-c3bf52bd-e19c-42e3-8762-10f96005f04a |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446098540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup _pulldown.446098540 |
| Directory | /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.583734669 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 295379051 ps |
| CPU time | 5 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:17 PM PST 24 |
| Peak memory | 197840 kb |
| Host | smart-90d2a209-90a6-4f31-996b-1c93310d639f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583734669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran dom_long_reg_writes_reg_reads.583734669 |
| Directory | /workspace/46.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/46.gpio_smoke.509686066 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 54064887 ps |
| CPU time | 0.86 seconds |
| Started | Jan 07 01:33:04 PM PST 24 |
| Finished | Jan 07 01:33:15 PM PST 24 |
| Peak memory | 196316 kb |
| Host | smart-59944c6d-505f-47a6-b473-aa40e2114b89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=509686066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.509686066 |
| Directory | /workspace/46.gpio_smoke/latest |
| Test location | /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1733514317 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 41097332 ps |
| CPU time | 0.8 seconds |
| Started | Jan 07 01:33:01 PM PST 24 |
| Finished | Jan 07 01:33:11 PM PST 24 |
| Peak memory | 195208 kb |
| Host | smart-b71e37e2-1601-4b0a-b174-ca05bc667494 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733514317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1733514317 |
| Directory | /workspace/46.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/46.gpio_stress_all.3059678838 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 10734341085 ps |
| CPU time | 135.67 seconds |
| Started | Jan 07 01:33:02 PM PST 24 |
| Finished | Jan 07 01:35:26 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-d0edd04e-851f-424b-9314-eaa22ee942c4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059678838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. gpio_stress_all.3059678838 |
| Directory | /workspace/46.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.379714343 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 427715498027 ps |
| CPU time | 790.86 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:45:49 PM PST 24 |
| Peak memory | 206620 kb |
| Host | smart-ab830e9c-0328-411a-b435-d2b160ddd285 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =379714343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.379714343 |
| Directory | /workspace/46.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.gpio_alert_test.2895860364 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14584245 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 01:33:13 PM PST 24 |
| Finished | Jan 07 01:33:22 PM PST 24 |
| Peak memory | 194088 kb |
| Host | smart-0b2b8951-5b3a-4d36-a186-a24e98dc1c5c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895860364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2895860364 |
| Directory | /workspace/47.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2202040669 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 61886666 ps |
| CPU time | 0.64 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:32:38 PM PST 24 |
| Peak memory | 194116 kb |
| Host | smart-2c017ca2-5fdd-4d32-808e-6aeded4dc893 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202040669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2202040669 |
| Directory | /workspace/47.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/47.gpio_filter_stress.890898643 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 553998540 ps |
| CPU time | 26.16 seconds |
| Started | Jan 07 01:33:04 PM PST 24 |
| Finished | Jan 07 01:33:41 PM PST 24 |
| Peak memory | 197256 kb |
| Host | smart-28eb6a4a-7b96-4a64-8b24-35dc83f434e8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890898643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres s.890898643 |
| Directory | /workspace/47.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/47.gpio_full_random.1656792677 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 169054971 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 01:32:39 PM PST 24 |
| Finished | Jan 07 01:32:44 PM PST 24 |
| Peak memory | 195380 kb |
| Host | smart-d917e22f-09df-4a66-8110-1214df87a7d9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656792677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1656792677 |
| Directory | /workspace/47.gpio_full_random/latest |
| Test location | /workspace/coverage/default/47.gpio_intr_rand_pgm.3622816515 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 84729370 ps |
| CPU time | 0.92 seconds |
| Started | Jan 07 01:33:05 PM PST 24 |
| Finished | Jan 07 01:33:20 PM PST 24 |
| Peak memory | 197556 kb |
| Host | smart-d8f6b0cf-3ea8-421d-ba84-48741ee63938 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622816515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3622816515 |
| Directory | /workspace/47.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1014433817 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 28881614 ps |
| CPU time | 1.07 seconds |
| Started | Jan 07 01:33:04 PM PST 24 |
| Finished | Jan 07 01:33:16 PM PST 24 |
| Peak memory | 197148 kb |
| Host | smart-a5a84726-4f5e-4107-ba08-d742ce6ab4ac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014433817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1014433817 |
| Directory | /workspace/47.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/47.gpio_rand_intr_trigger.2753488782 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1384497495 ps |
| CPU time | 2.99 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:32:40 PM PST 24 |
| Peak memory | 198188 kb |
| Host | smart-8e96ffff-b51e-4d9b-9fea-a70ec88fa72f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753488782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger .2753488782 |
| Directory | /workspace/47.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/47.gpio_random_dout_din.233390024 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 122329979 ps |
| CPU time | 1.2 seconds |
| Started | Jan 07 01:33:03 PM PST 24 |
| Finished | Jan 07 01:33:13 PM PST 24 |
| Peak memory | 195940 kb |
| Host | smart-0a0881bd-1ea3-41ba-8b46-26dff144e690 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233390024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.233390024 |
| Directory | /workspace/47.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2314716933 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 66653022 ps |
| CPU time | 0.73 seconds |
| Started | Jan 07 01:32:38 PM PST 24 |
| Finished | Jan 07 01:32:43 PM PST 24 |
| Peak memory | 195244 kb |
| Host | smart-8bd9843a-2b55-4c32-97e7-644f7b267047 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314716933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu p_pulldown.2314716933 |
| Directory | /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3104454526 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 362709669 ps |
| CPU time | 4.48 seconds |
| Started | Jan 07 01:33:05 PM PST 24 |
| Finished | Jan 07 01:33:20 PM PST 24 |
| Peak memory | 198128 kb |
| Host | smart-b87f01bf-4597-4343-b614-4afabcccf4c1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104454526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra ndom_long_reg_writes_reg_reads.3104454526 |
| Directory | /workspace/47.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/47.gpio_smoke.3679093968 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 141669580 ps |
| CPU time | 1.19 seconds |
| Started | Jan 07 01:32:35 PM PST 24 |
| Finished | Jan 07 01:32:39 PM PST 24 |
| Peak memory | 196984 kb |
| Host | smart-cc23d0e7-4a6c-4edf-baa5-d0a31195728e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679093968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3679093968 |
| Directory | /workspace/47.gpio_smoke/latest |
| Test location | /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.4116125436 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 85915112 ps |
| CPU time | 0.9 seconds |
| Started | Jan 07 01:33:04 PM PST 24 |
| Finished | Jan 07 01:33:14 PM PST 24 |
| Peak memory | 195344 kb |
| Host | smart-de5492d6-bdf3-4fee-8d44-0dca6ec8030d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116125436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.4116125436 |
| Directory | /workspace/47.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/47.gpio_stress_all.3244434091 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 8369283820 ps |
| CPU time | 89.44 seconds |
| Started | Jan 07 01:33:05 PM PST 24 |
| Finished | Jan 07 01:34:45 PM PST 24 |
| Peak memory | 198240 kb |
| Host | smart-1f1d1992-5694-4a25-8e52-f110d69295c6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244434091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. gpio_stress_all.3244434091 |
| Directory | /workspace/47.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.912965553 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 165448637422 ps |
| CPU time | 600.25 seconds |
| Started | Jan 07 01:33:14 PM PST 24 |
| Finished | Jan 07 01:43:23 PM PST 24 |
| Peak memory | 198348 kb |
| Host | smart-a98c5e92-88e5-4a55-bd27-c7cf63eaf20e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =912965553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.912965553 |
| Directory | /workspace/47.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.gpio_alert_test.3112421564 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 15117562 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 01:33:18 PM PST 24 |
| Finished | Jan 07 01:33:26 PM PST 24 |
| Peak memory | 194804 kb |
| Host | smart-11d3aeaf-de7a-493c-af15-11277e8dd3bf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112421564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3112421564 |
| Directory | /workspace/48.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.681699730 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 28059007 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 01:33:23 PM PST 24 |
| Finished | Jan 07 01:33:30 PM PST 24 |
| Peak memory | 193868 kb |
| Host | smart-6d2355f6-d4df-481b-9e3e-4ae44f11ce37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=681699730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.681699730 |
| Directory | /workspace/48.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/48.gpio_filter_stress.3225318842 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 693727620 ps |
| CPU time | 9.95 seconds |
| Started | Jan 07 01:33:17 PM PST 24 |
| Finished | Jan 07 01:33:34 PM PST 24 |
| Peak memory | 196860 kb |
| Host | smart-eb151289-6a76-465c-8c27-bf1ffa9f916c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225318842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre ss.3225318842 |
| Directory | /workspace/48.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/48.gpio_full_random.347160500 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 87438031 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 01:33:25 PM PST 24 |
| Peak memory | 197820 kb |
| Host | smart-9539ed04-009c-40af-8602-9fb8658bbcc5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347160500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.347160500 |
| Directory | /workspace/48.gpio_full_random/latest |
| Test location | /workspace/coverage/default/48.gpio_intr_rand_pgm.3957437522 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 25577532 ps |
| CPU time | 0.85 seconds |
| Started | Jan 07 01:33:14 PM PST 24 |
| Finished | Jan 07 01:33:23 PM PST 24 |
| Peak memory | 197176 kb |
| Host | smart-925b216a-8fe6-4451-9d20-3474a00d7f4e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957437522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3957437522 |
| Directory | /workspace/48.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1537327623 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 36040084 ps |
| CPU time | 1.45 seconds |
| Started | Jan 07 01:33:11 PM PST 24 |
| Finished | Jan 07 01:33:22 PM PST 24 |
| Peak memory | 196956 kb |
| Host | smart-0aa57fac-802e-48f1-9eb5-8a1839578d74 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537327623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1537327623 |
| Directory | /workspace/48.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/48.gpio_rand_intr_trigger.1317537679 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 210173900 ps |
| CPU time | 1.41 seconds |
| Started | Jan 07 01:33:27 PM PST 24 |
| Finished | Jan 07 01:33:36 PM PST 24 |
| Peak memory | 196772 kb |
| Host | smart-65bc9c6f-2cbf-4ed6-9786-dd71723c75bc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317537679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger .1317537679 |
| Directory | /workspace/48.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/48.gpio_random_dout_din.3622777149 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 155669997 ps |
| CPU time | 0.82 seconds |
| Started | Jan 07 01:33:42 PM PST 24 |
| Finished | Jan 07 01:33:44 PM PST 24 |
| Peak memory | 196520 kb |
| Host | smart-b7e475c3-45c8-43a1-8a82-9bf8e1d1c7d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622777149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3622777149 |
| Directory | /workspace/48.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3397917777 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 199597153 ps |
| CPU time | 1.06 seconds |
| Started | Jan 07 01:33:46 PM PST 24 |
| Finished | Jan 07 01:33:49 PM PST 24 |
| Peak memory | 195960 kb |
| Host | smart-ced3aff8-01be-4d34-9e95-5db8e4e7582a |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397917777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu p_pulldown.3397917777 |
| Directory | /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2355727465 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 320468766 ps |
| CPU time | 4.53 seconds |
| Started | Jan 07 01:33:42 PM PST 24 |
| Finished | Jan 07 01:33:47 PM PST 24 |
| Peak memory | 198168 kb |
| Host | smart-b1b098a5-6391-4c35-9e38-53fa1a1d4e37 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355727465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra ndom_long_reg_writes_reg_reads.2355727465 |
| Directory | /workspace/48.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/48.gpio_smoke.3349067908 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 52703040 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 01:33:25 PM PST 24 |
| Finished | Jan 07 01:33:32 PM PST 24 |
| Peak memory | 196092 kb |
| Host | smart-f9cc35cd-346d-4171-b330-efad5ed21ffe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3349067908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3349067908 |
| Directory | /workspace/48.gpio_smoke/latest |
| Test location | /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3070495712 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 22473231 ps |
| CPU time | 0.77 seconds |
| Started | Jan 07 01:33:13 PM PST 24 |
| Finished | Jan 07 01:33:23 PM PST 24 |
| Peak memory | 195264 kb |
| Host | smart-bd475292-9bce-4329-a388-f5de3829f7f7 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070495712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3070495712 |
| Directory | /workspace/48.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/48.gpio_stress_all.3315362432 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 6765554895 ps |
| CPU time | 94.69 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 01:34:58 PM PST 24 |
| Peak memory | 198292 kb |
| Host | smart-ad9eb8f0-d4b7-4d07-b3e6-c352340099b1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315362432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. gpio_stress_all.3315362432 |
| Directory | /workspace/48.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.4252846024 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 531477705360 ps |
| CPU time | 2527.49 seconds |
| Started | Jan 07 01:33:15 PM PST 24 |
| Finished | Jan 07 02:15:31 PM PST 24 |
| Peak memory | 198444 kb |
| Host | smart-9fb62be8-93b7-4813-b653-160d06f25e1b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4252846024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.4252846024 |
| Directory | /workspace/48.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.gpio_alert_test.3832263552 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 18351886 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 01:33:20 PM PST 24 |
| Finished | Jan 07 01:33:28 PM PST 24 |
| Peak memory | 194796 kb |
| Host | smart-42b1f988-d725-4bfa-a3dc-24eeb54e8b3c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832263552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3832263552 |
| Directory | /workspace/49.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1228478960 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 47979894 ps |
| CPU time | 0.71 seconds |
| Started | Jan 07 01:33:19 PM PST 24 |
| Finished | Jan 07 01:33:28 PM PST 24 |
| Peak memory | 195964 kb |
| Host | smart-cb9ba27a-e058-4e84-a676-bad825e53565 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1228478960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1228478960 |
| Directory | /workspace/49.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/49.gpio_filter_stress.1328315411 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 1601686375 ps |
| CPU time | 19.96 seconds |
| Started | Jan 07 01:33:18 PM PST 24 |
| Finished | Jan 07 01:33:46 PM PST 24 |
| Peak memory | 195604 kb |
| Host | smart-850ef49b-d660-4306-ab61-dd343500efae |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328315411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre ss.1328315411 |
| Directory | /workspace/49.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/49.gpio_full_random.3008052595 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 200330186 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 01:33:24 PM PST 24 |
| Finished | Jan 07 01:33:31 PM PST 24 |
| Peak memory | 195880 kb |
| Host | smart-5021eb7b-937a-4a56-99c5-8664508b01de |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008052595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3008052595 |
| Directory | /workspace/49.gpio_full_random/latest |
| Test location | /workspace/coverage/default/49.gpio_intr_rand_pgm.333386600 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 284903863 ps |
| CPU time | 1.24 seconds |
| Started | Jan 07 01:33:45 PM PST 24 |
| Finished | Jan 07 01:33:48 PM PST 24 |
| Peak memory | 196992 kb |
| Host | smart-33655b4f-bcfc-484c-89f3-871a3b468127 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333386600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.333386600 |
| Directory | /workspace/49.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3326893706 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 52864272 ps |
| CPU time | 2.15 seconds |
| Started | Jan 07 01:33:16 PM PST 24 |
| Finished | Jan 07 01:33:26 PM PST 24 |
| Peak memory | 198056 kb |
| Host | smart-98ea0622-517f-408c-8ff7-b361dff7e3b4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326893706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3326893706 |
| Directory | /workspace/49.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/49.gpio_rand_intr_trigger.1570599937 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 133335973 ps |
| CPU time | 1.65 seconds |
| Started | Jan 07 01:33:47 PM PST 24 |
| Finished | Jan 07 01:33:50 PM PST 24 |
| Peak memory | 195988 kb |
| Host | smart-f5d7eed2-9347-4121-9820-021ec3a02e62 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570599937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger .1570599937 |
| Directory | /workspace/49.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/49.gpio_random_dout_din.4057477933 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 29997773 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 01:33:26 PM PST 24 |
| Finished | Jan 07 01:33:32 PM PST 24 |
| Peak memory | 196168 kb |
| Host | smart-b0d8c632-1560-4268-b6f9-fc88fa9f7228 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4057477933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.4057477933 |
| Directory | /workspace/49.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3297409970 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 103440358 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 01:33:14 PM PST 24 |
| Finished | Jan 07 01:33:24 PM PST 24 |
| Peak memory | 195996 kb |
| Host | smart-5ee8b041-0049-4c52-a11c-9ff79c7cc2f1 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297409970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu p_pulldown.3297409970 |
| Directory | /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1438477376 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 322981045 ps |
| CPU time | 4.05 seconds |
| Started | Jan 07 01:33:52 PM PST 24 |
| Finished | Jan 07 01:33:57 PM PST 24 |
| Peak memory | 198044 kb |
| Host | smart-c50cde84-b3c3-434b-b021-fb3e94d30b8e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438477376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra ndom_long_reg_writes_reg_reads.1438477376 |
| Directory | /workspace/49.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/49.gpio_smoke.2595291675 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 240146418 ps |
| CPU time | 1.28 seconds |
| Started | Jan 07 01:33:52 PM PST 24 |
| Finished | Jan 07 01:33:55 PM PST 24 |
| Peak memory | 195524 kb |
| Host | smart-f1141d1e-6221-4fed-b45f-37e3e26bd8fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2595291675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2595291675 |
| Directory | /workspace/49.gpio_smoke/latest |
| Test location | /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2518819548 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 72861776 ps |
| CPU time | 1.19 seconds |
| Started | Jan 07 01:33:17 PM PST 24 |
| Finished | Jan 07 01:33:26 PM PST 24 |
| Peak memory | 195668 kb |
| Host | smart-d105c1f5-e095-499a-afbb-8e30c5b6b876 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518819548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2518819548 |
| Directory | /workspace/49.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/49.gpio_stress_all.3390267679 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 90104913078 ps |
| CPU time | 108.39 seconds |
| Started | Jan 07 01:33:24 PM PST 24 |
| Finished | Jan 07 01:35:19 PM PST 24 |
| Peak memory | 198148 kb |
| Host | smart-bc66be02-8429-4a5d-936e-276e99b37fec |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390267679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. gpio_stress_all.3390267679 |
| Directory | /workspace/49.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3593695863 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 662567728007 ps |
| CPU time | 600.67 seconds |
| Started | Jan 07 01:33:55 PM PST 24 |
| Finished | Jan 07 01:43:56 PM PST 24 |
| Peak memory | 206500 kb |
| Host | smart-a654102d-94b2-4399-92ca-22762dd5a64c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3593695863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3593695863 |
| Directory | /workspace/49.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.gpio_alert_test.3978973662 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 36075655 ps |
| CPU time | 0.57 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:35 PM PST 24 |
| Peak memory | 194924 kb |
| Host | smart-f8bc0f2b-e175-46e8-85b0-0cc486ea87bf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978973662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3978973662 |
| Directory | /workspace/5.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1393200753 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 87112531 ps |
| CPU time | 0.72 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 195380 kb |
| Host | smart-c675f9a4-f0e8-47e0-9457-2f2c8348b2dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1393200753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1393200753 |
| Directory | /workspace/5.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/5.gpio_filter_stress.3074658569 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 274862150 ps |
| CPU time | 3.26 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 195560 kb |
| Host | smart-49e6ad27-fc44-48e7-9cad-1e607e563dc4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074658569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres s.3074658569 |
| Directory | /workspace/5.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/5.gpio_full_random.3051744100 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 21950964 ps |
| CPU time | 0.66 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 195224 kb |
| Host | smart-0829cce7-3541-48c4-acf2-4e84e8f9e76f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051744100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3051744100 |
| Directory | /workspace/5.gpio_full_random/latest |
| Test location | /workspace/coverage/default/5.gpio_intr_rand_pgm.2806704959 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 65252824 ps |
| CPU time | 0.69 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:31:38 PM PST 24 |
| Peak memory | 195220 kb |
| Host | smart-ee49d42b-782c-4b19-98d2-9c8f55af4efe |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806704959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2806704959 |
| Directory | /workspace/5.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4041197042 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 165548647 ps |
| CPU time | 3.3 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:39 PM PST 24 |
| Peak memory | 198096 kb |
| Host | smart-12e4b1c0-c6d7-44c9-ba7a-7b3bd4166c69 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041197042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.gpio_intr_with_filter_rand_intr_event.4041197042 |
| Directory | /workspace/5.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/5.gpio_rand_intr_trigger.2549506975 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 659914456 ps |
| CPU time | 2.92 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:38 PM PST 24 |
| Peak memory | 197288 kb |
| Host | smart-ea958f11-b501-4602-b54c-527d466d35f2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549506975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger. 2549506975 |
| Directory | /workspace/5.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/5.gpio_random_dout_din.2736126721 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 401514026 ps |
| CPU time | 1.31 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:34 PM PST 24 |
| Peak memory | 198220 kb |
| Host | smart-cbac2a47-9156-4b6c-b1d7-49ae8b25f088 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2736126721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2736126721 |
| Directory | /workspace/5.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2182501013 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 90018201 ps |
| CPU time | 0.97 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 196652 kb |
| Host | smart-00849aed-e129-461d-908b-01ae52343fdd |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182501013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup _pulldown.2182501013 |
| Directory | /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2596801526 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 345875438 ps |
| CPU time | 5.65 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:41 PM PST 24 |
| Peak memory | 198052 kb |
| Host | smart-4bfffda3-724a-4cb4-8355-db6467fb7be9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596801526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran dom_long_reg_writes_reg_reads.2596801526 |
| Directory | /workspace/5.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/5.gpio_smoke.2230726848 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 324436399 ps |
| CPU time | 0.85 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 195296 kb |
| Host | smart-221f26ad-477c-407e-9411-24b566420dd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2230726848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2230726848 |
| Directory | /workspace/5.gpio_smoke/latest |
| Test location | /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1596406349 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 30208764 ps |
| CPU time | 0.98 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 195740 kb |
| Host | smart-e2075d78-a209-4d05-a5bc-c84ea4eb9e37 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596406349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1596406349 |
| Directory | /workspace/5.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/5.gpio_stress_all.2098211115 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2938869345 ps |
| CPU time | 40.05 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:32:14 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-c37266fc-d4ea-4173-81a0-a00d9b01dba7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098211115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g pio_stress_all.2098211115 |
| Directory | /workspace/5.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2330381428 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 90880611016 ps |
| CPU time | 1949.68 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 02:04:02 PM PST 24 |
| Peak memory | 198312 kb |
| Host | smart-30849d10-3557-472e-a712-1f4279f20541 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2330381428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2330381428 |
| Directory | /workspace/5.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.gpio_alert_test.3332623592 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 61370124 ps |
| CPU time | 0.58 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 194108 kb |
| Host | smart-a36f9418-1529-48b9-aa33-760cbce8c001 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332623592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3332623592 |
| Directory | /workspace/6.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.293300004 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 38996830 ps |
| CPU time | 0.85 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 196252 kb |
| Host | smart-dd79a3a9-64ef-4316-8f00-b0121cdf062d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=293300004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.293300004 |
| Directory | /workspace/6.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/6.gpio_filter_stress.1412356099 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 424555952 ps |
| CPU time | 14.83 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:31:51 PM PST 24 |
| Peak memory | 197020 kb |
| Host | smart-a16ddf3d-2199-46f0-9b35-1b040b61f5f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412356099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres s.1412356099 |
| Directory | /workspace/6.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/6.gpio_full_random.3834416375 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 245034695 ps |
| CPU time | 0.81 seconds |
| Started | Jan 07 01:31:26 PM PST 24 |
| Finished | Jan 07 01:31:44 PM PST 24 |
| Peak memory | 195760 kb |
| Host | smart-1f582c51-3d9f-4983-b934-39620d82a556 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834416375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3834416375 |
| Directory | /workspace/6.gpio_full_random/latest |
| Test location | /workspace/coverage/default/6.gpio_intr_rand_pgm.2354947163 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 90675705 ps |
| CPU time | 0.71 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:35 PM PST 24 |
| Peak memory | 195412 kb |
| Host | smart-5db9098a-d676-4dd7-b85a-1265fb614925 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354947163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2354947163 |
| Directory | /workspace/6.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2988511235 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 76785275 ps |
| CPU time | 1.8 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 198320 kb |
| Host | smart-721e88a0-8784-40cc-bfad-da518ae9d531 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988511235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2988511235 |
| Directory | /workspace/6.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/6.gpio_rand_intr_trigger.1178224051 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 93434867 ps |
| CPU time | 1.05 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 195696 kb |
| Host | smart-eb2c68e7-949b-4ef9-863e-3b3ac0c56b52 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178224051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger. 1178224051 |
| Directory | /workspace/6.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/6.gpio_random_dout_din.2485522460 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 118067263 ps |
| CPU time | 1.15 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:31:39 PM PST 24 |
| Peak memory | 195948 kb |
| Host | smart-d34bf4ac-88a4-4067-b9fd-bcd194b905ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2485522460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2485522460 |
| Directory | /workspace/6.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1851931416 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 43143255 ps |
| CPU time | 1.04 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:38 PM PST 24 |
| Peak memory | 196044 kb |
| Host | smart-d6a28d74-b32b-45e6-bbb1-914b8df5ce24 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851931416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup _pulldown.1851931416 |
| Directory | /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2605520002 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 248765676 ps |
| CPU time | 2.97 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:31:40 PM PST 24 |
| Peak memory | 198120 kb |
| Host | smart-be489c55-ac38-4295-865f-113550991c26 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605520002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran dom_long_reg_writes_reg_reads.2605520002 |
| Directory | /workspace/6.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/6.gpio_smoke.1999548545 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 43896774 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:31:37 PM PST 24 |
| Finished | Jan 07 01:31:52 PM PST 24 |
| Peak memory | 195824 kb |
| Host | smart-17f6f033-6934-4a83-be98-a2b6becdf1d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999548545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1999548545 |
| Directory | /workspace/6.gpio_smoke/latest |
| Test location | /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3978357846 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 529827432 ps |
| CPU time | 1.33 seconds |
| Started | Jan 07 01:31:20 PM PST 24 |
| Finished | Jan 07 01:31:34 PM PST 24 |
| Peak memory | 196732 kb |
| Host | smart-9c52fe07-71c0-40d2-8106-727863fdaf15 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978357846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3978357846 |
| Directory | /workspace/6.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/6.gpio_stress_all.3014786346 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 53574651072 ps |
| CPU time | 152.35 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:34:08 PM PST 24 |
| Peak memory | 198252 kb |
| Host | smart-bd7c7670-91e6-41bb-a4a9-18129069aee9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014786346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g pio_stress_all.3014786346 |
| Directory | /workspace/6.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.952108459 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 80128359285 ps |
| CPU time | 949.9 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:47:25 PM PST 24 |
| Peak memory | 198360 kb |
| Host | smart-269cecce-a1da-42cb-87c2-d78f032c81a3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =952108459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.952108459 |
| Directory | /workspace/6.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.gpio_alert_test.3824879542 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 31162783 ps |
| CPU time | 0.61 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:31:40 PM PST 24 |
| Peak memory | 194084 kb |
| Host | smart-314e072a-cb1f-4ca3-894a-c1133fd9f69b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824879542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3824879542 |
| Directory | /workspace/7.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2366237262 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 35896878 ps |
| CPU time | 0.85 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 196536 kb |
| Host | smart-ddf1ece9-34f1-4684-ad05-6fd5a4aeb827 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2366237262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2366237262 |
| Directory | /workspace/7.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/7.gpio_filter_stress.130871124 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 4980164596 ps |
| CPU time | 29.09 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:32:04 PM PST 24 |
| Peak memory | 196868 kb |
| Host | smart-9aec95df-b8a7-4324-a59b-07aafe2d3611 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130871124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress .130871124 |
| Directory | /workspace/7.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/7.gpio_full_random.1407086075 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 25714784 ps |
| CPU time | 0.69 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:35 PM PST 24 |
| Peak memory | 194740 kb |
| Host | smart-729b1b4d-6b50-48ac-9aa5-2eaa334eb6f9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407086075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1407086075 |
| Directory | /workspace/7.gpio_full_random/latest |
| Test location | /workspace/coverage/default/7.gpio_intr_rand_pgm.2718133833 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 15469600 ps |
| CPU time | 0.7 seconds |
| Started | Jan 07 01:31:25 PM PST 24 |
| Finished | Jan 07 01:31:42 PM PST 24 |
| Peak memory | 194280 kb |
| Host | smart-767ddef3-e0e2-451b-b988-f0c3ebadade9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718133833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2718133833 |
| Directory | /workspace/7.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1524242910 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1098633546 ps |
| CPU time | 2.91 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:31:41 PM PST 24 |
| Peak memory | 198292 kb |
| Host | smart-c84e1232-ce48-4ae6-bfea-94a37ddc8195 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524242910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1524242910 |
| Directory | /workspace/7.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/7.gpio_rand_intr_trigger.1890821320 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 369450158 ps |
| CPU time | 3.1 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:38 PM PST 24 |
| Peak memory | 198096 kb |
| Host | smart-a8db4b2e-b017-4e9a-9f9e-bd77d1aa6424 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890821320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger. 1890821320 |
| Directory | /workspace/7.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/7.gpio_random_dout_din.2211119943 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 103810163 ps |
| CPU time | 0.74 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 194828 kb |
| Host | smart-672638a7-d1e3-48f2-bbb5-2f036133f968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2211119943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2211119943 |
| Directory | /workspace/7.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.759172551 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 104754015 ps |
| CPU time | 1.01 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:35 PM PST 24 |
| Peak memory | 196720 kb |
| Host | smart-47d71ba5-b733-45e1-bca9-74e50c9c0a20 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759172551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_ pulldown.759172551 |
| Directory | /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1943440841 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 154686125 ps |
| CPU time | 2.5 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 198132 kb |
| Host | smart-01040990-ecfc-4101-8154-ddebbe4bd417 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943440841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran dom_long_reg_writes_reg_reads.1943440841 |
| Directory | /workspace/7.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/7.gpio_smoke.2348768918 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 161623578 ps |
| CPU time | 1.08 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:34 PM PST 24 |
| Peak memory | 195760 kb |
| Host | smart-a45e18fa-6ea4-417b-b595-4e66c8c69b51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348768918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2348768918 |
| Directory | /workspace/7.gpio_smoke/latest |
| Test location | /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2107812124 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 155782179 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:31:25 PM PST 24 |
| Finished | Jan 07 01:31:42 PM PST 24 |
| Peak memory | 195972 kb |
| Host | smart-64b6c7b9-c373-4d5a-be18-b6ad0504bb1a |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107812124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2107812124 |
| Directory | /workspace/7.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/7.gpio_stress_all.3854899106 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 4931532186 ps |
| CPU time | 117.53 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:33:33 PM PST 24 |
| Peak memory | 198204 kb |
| Host | smart-4f8b78b6-472d-41cd-a15d-653ad096dde0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854899106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g pio_stress_all.3854899106 |
| Directory | /workspace/7.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.4112954661 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 31909876890 ps |
| CPU time | 932.31 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:47:08 PM PST 24 |
| Peak memory | 198300 kb |
| Host | smart-3bd63fae-7c8e-46e4-9c62-5d0180ae627a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4112954661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.4112954661 |
| Directory | /workspace/7.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.gpio_alert_test.2108336580 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 113266444 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 01:31:29 PM PST 24 |
| Finished | Jan 07 01:31:48 PM PST 24 |
| Peak memory | 194228 kb |
| Host | smart-5f9dad7e-176d-4fb9-ab49-34bd569a4586 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108336580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2108336580 |
| Directory | /workspace/8.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.537872286 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 88833800 ps |
| CPU time | 0.7 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 195920 kb |
| Host | smart-6d5f65a7-85b4-4fc0-9dc2-5fd9f31951d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537872286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.537872286 |
| Directory | /workspace/8.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/8.gpio_filter_stress.3168310038 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 250777018 ps |
| CPU time | 7.74 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:43 PM PST 24 |
| Peak memory | 196896 kb |
| Host | smart-4b19b679-fb23-4dcd-a2dc-b710f590be94 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168310038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres s.3168310038 |
| Directory | /workspace/8.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/8.gpio_full_random.2299177014 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 302288421 ps |
| CPU time | 1.01 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 198172 kb |
| Host | smart-d114334d-f4ad-4ad5-bf68-5f1f453b2689 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299177014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2299177014 |
| Directory | /workspace/8.gpio_full_random/latest |
| Test location | /workspace/coverage/default/8.gpio_intr_rand_pgm.2417620220 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 77952723 ps |
| CPU time | 1.14 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 196292 kb |
| Host | smart-301cb788-4b72-4b32-9dd7-e7d32b11a000 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417620220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2417620220 |
| Directory | /workspace/8.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3156721375 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 336196052 ps |
| CPU time | 3.22 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:38 PM PST 24 |
| Peak memory | 196436 kb |
| Host | smart-b09ea015-51f0-4f64-83a5-1bc3adf78705 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156721375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3156721375 |
| Directory | /workspace/8.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/8.gpio_rand_intr_trigger.4089303608 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 85469488 ps |
| CPU time | 1.92 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 196264 kb |
| Host | smart-4ebb76df-e086-41a9-b581-43f61eadeb0b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089303608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger. 4089303608 |
| Directory | /workspace/8.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/8.gpio_random_dout_din.1271220195 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 25245304 ps |
| CPU time | 0.96 seconds |
| Started | Jan 07 01:31:25 PM PST 24 |
| Finished | Jan 07 01:31:42 PM PST 24 |
| Peak memory | 196152 kb |
| Host | smart-e4ebb9c5-1821-4034-8cd9-dbac0c50c8a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1271220195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1271220195 |
| Directory | /workspace/8.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2446776523 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 36875958 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 01:31:30 PM PST 24 |
| Finished | Jan 07 01:31:49 PM PST 24 |
| Peak memory | 196304 kb |
| Host | smart-45794092-d7ee-47e3-89d2-28e3e8a94a5f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446776523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup _pulldown.2446776523 |
| Directory | /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3428117379 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 335643101 ps |
| CPU time | 1.62 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 197676 kb |
| Host | smart-09e112d3-6342-4be1-a2d0-40b65899a47e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428117379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran dom_long_reg_writes_reg_reads.3428117379 |
| Directory | /workspace/8.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/8.gpio_smoke.4278582037 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 100205610 ps |
| CPU time | 0.95 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 195720 kb |
| Host | smart-29abbb7d-7605-4b43-bcee-ac9c57d916b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278582037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.4278582037 |
| Directory | /workspace/8.gpio_smoke/latest |
| Test location | /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2530550999 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1272648506 ps |
| CPU time | 1.36 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 198100 kb |
| Host | smart-78559368-49d5-4241-9b50-6ea5ae69b5b5 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530550999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2530550999 |
| Directory | /workspace/8.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/8.gpio_stress_all.352984690 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 377992852828 ps |
| CPU time | 212.6 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:35:08 PM PST 24 |
| Peak memory | 198276 kb |
| Host | smart-2681cd93-89e2-499d-b845-9dc023cb747d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352984690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp io_stress_all.352984690 |
| Directory | /workspace/8.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1092622673 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 120218761092 ps |
| CPU time | 858.26 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:45:56 PM PST 24 |
| Peak memory | 198444 kb |
| Host | smart-67d60e0d-fe9a-4952-aba1-9b237f64704f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1092622673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.1092622673 |
| Directory | /workspace/8.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.gpio_alert_test.3987404658 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 14763095 ps |
| CPU time | 0.56 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 194088 kb |
| Host | smart-979dd051-b31c-4173-a3b8-d762617de06c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987404658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3987404658 |
| Directory | /workspace/9.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2865303248 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 163615865 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 196076 kb |
| Host | smart-d53a9593-586b-4083-ad68-9bcd71ef9efe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865303248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2865303248 |
| Directory | /workspace/9.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/9.gpio_filter_stress.2036907930 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 521064842 ps |
| CPU time | 27.68 seconds |
| Started | Jan 07 01:31:24 PM PST 24 |
| Finished | Jan 07 01:32:05 PM PST 24 |
| Peak memory | 196952 kb |
| Host | smart-066fe5a1-aada-4459-8079-8e391c28ce0f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036907930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres s.2036907930 |
| Directory | /workspace/9.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/9.gpio_full_random.3576318973 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 246096365 ps |
| CPU time | 0.89 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:35 PM PST 24 |
| Peak memory | 196092 kb |
| Host | smart-482ea050-3829-46b5-8afa-f425bd3a848a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576318973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3576318973 |
| Directory | /workspace/9.gpio_full_random/latest |
| Test location | /workspace/coverage/default/9.gpio_intr_rand_pgm.2704748168 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 323674925 ps |
| CPU time | 1.15 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 196120 kb |
| Host | smart-fdb0e9e1-a524-4715-afba-e8222961c95a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704748168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2704748168 |
| Directory | /workspace/9.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.865321621 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 64671388 ps |
| CPU time | 2.4 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:38 PM PST 24 |
| Peak memory | 198184 kb |
| Host | smart-3e142164-7755-40e6-9d3d-b40c7127e3aa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865321621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.gpio_intr_with_filter_rand_intr_event.865321621 |
| Directory | /workspace/9.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/9.gpio_rand_intr_trigger.3972632328 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 57157281 ps |
| CPU time | 1.93 seconds |
| Started | Jan 07 01:31:25 PM PST 24 |
| Finished | Jan 07 01:31:42 PM PST 24 |
| Peak memory | 197052 kb |
| Host | smart-81492c6d-1f6e-42e3-92af-76c4e2f1120e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972632328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger. 3972632328 |
| Directory | /workspace/9.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/9.gpio_random_dout_din.3506392572 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 64084365 ps |
| CPU time | 1.21 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:37 PM PST 24 |
| Peak memory | 197052 kb |
| Host | smart-5648a2a4-259d-4785-98eb-764ac29944ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3506392572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3506392572 |
| Directory | /workspace/9.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1517973463 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 16192585 ps |
| CPU time | 0.67 seconds |
| Started | Jan 07 01:31:21 PM PST 24 |
| Finished | Jan 07 01:31:33 PM PST 24 |
| Peak memory | 195048 kb |
| Host | smart-59914bc5-dd75-4531-8bcf-512af777b6f3 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517973463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup _pulldown.1517973463 |
| Directory | /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2930471407 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 276631543 ps |
| CPU time | 4.63 seconds |
| Started | Jan 07 01:31:22 PM PST 24 |
| Finished | Jan 07 01:31:39 PM PST 24 |
| Peak memory | 198020 kb |
| Host | smart-6743a258-11ff-4881-af9b-c249e05c7096 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930471407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran dom_long_reg_writes_reg_reads.2930471407 |
| Directory | /workspace/9.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/9.gpio_smoke.4246218670 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 58785983 ps |
| CPU time | 1.23 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:31:36 PM PST 24 |
| Peak memory | 198000 kb |
| Host | smart-0c689d75-4bd7-460a-9b15-96f4b63c18de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4246218670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.4246218670 |
| Directory | /workspace/9.gpio_smoke/latest |
| Test location | /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1335894711 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 55629433 ps |
| CPU time | 0.91 seconds |
| Started | Jan 07 01:31:25 PM PST 24 |
| Finished | Jan 07 01:31:41 PM PST 24 |
| Peak memory | 195404 kb |
| Host | smart-86610186-1e8a-45c4-8e02-1c3a540b5e8c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335894711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1335894711 |
| Directory | /workspace/9.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/9.gpio_stress_all.1089827687 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 29864416220 ps |
| CPU time | 177.19 seconds |
| Started | Jan 07 01:31:23 PM PST 24 |
| Finished | Jan 07 01:34:32 PM PST 24 |
| Peak memory | 198260 kb |
| Host | smart-60858e2d-af55-4c58-b5d2-01aaa9788a0e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089827687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g pio_stress_all.1089827687 |
| Directory | /workspace/9.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2874111737 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 336226191163 ps |
| CPU time | 1142.07 seconds |
| Started | Jan 07 01:31:29 PM PST 24 |
| Finished | Jan 07 01:50:50 PM PST 24 |
| Peak memory | 198368 kb |
| Host | smart-ae87f6eb-8868-4c5d-a205-a29b0e16c8b6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2874111737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2874111737 |
| Directory | /workspace/9.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1005458128 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 120615708 ps |
| CPU time | 1 seconds |
| Started | Jan 07 12:37:00 PM PST 24 |
| Finished | Jan 07 12:38:15 PM PST 24 |
| Peak memory | 195312 kb |
| Host | smart-20142011-f954-4223-a90a-420a83a6d03e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1005458128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1005458128 |
| Directory | /workspace/0.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.795283020 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 172033118 ps |
| CPU time | 1.29 seconds |
| Started | Jan 07 12:37:41 PM PST 24 |
| Finished | Jan 07 12:38:53 PM PST 24 |
| Peak memory | 195460 kb |
| Host | smart-58478d2f-3640-4d65-b0e2-dfe0c2cca32a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795283020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e n_cdc_prim.795283020 |
| Directory | /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.962140869 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 91071882 ps |
| CPU time | 0.93 seconds |
| Started | Jan 07 12:37:52 PM PST 24 |
| Finished | Jan 07 12:38:57 PM PST 24 |
| Peak memory | 196108 kb |
| Host | smart-187c3758-4505-4740-bc00-5163baf75c7a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=962140869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.962140869 |
| Directory | /workspace/1.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3241674955 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 269492829 ps |
| CPU time | 1.03 seconds |
| Started | Jan 07 12:37:51 PM PST 24 |
| Finished | Jan 07 12:39:06 PM PST 24 |
| Peak memory | 195448 kb |
| Host | smart-9f23ade3-f4d2-4d5f-b148-da623483c47b |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241674955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.3241674955 |
| Directory | /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3885629605 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 76751910 ps |
| CPU time | 0.71 seconds |
| Started | Jan 07 12:38:29 PM PST 24 |
| Finished | Jan 07 12:39:36 PM PST 24 |
| Peak memory | 194092 kb |
| Host | smart-d59b4918-d6eb-4183-8179-7fd35963f223 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3885629605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3885629605 |
| Directory | /workspace/10.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1123358323 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 460570125 ps |
| CPU time | 0.85 seconds |
| Started | Jan 07 12:38:04 PM PST 24 |
| Finished | Jan 07 12:39:38 PM PST 24 |
| Peak memory | 196008 kb |
| Host | smart-5e8609dc-9f2f-44fc-a50e-c364056e5f9c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123358323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1123358323 |
| Directory | /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4224869051 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 36408676 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 12:38:32 PM PST 24 |
| Finished | Jan 07 12:39:47 PM PST 24 |
| Peak memory | 195184 kb |
| Host | smart-d4e62553-3437-4e6f-88a6-44956d240ef9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4224869051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.4224869051 |
| Directory | /workspace/11.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2939683028 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 69773794 ps |
| CPU time | 1.15 seconds |
| Started | Jan 07 12:38:18 PM PST 24 |
| Finished | Jan 07 12:39:25 PM PST 24 |
| Peak memory | 196176 kb |
| Host | smart-9ca00668-cda9-4185-90ab-fd6a7569c46a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2939683028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2939683028 |
| Directory | /workspace/12.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.415144335 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 52536438 ps |
| CPU time | 0.8 seconds |
| Started | Jan 07 12:38:42 PM PST 24 |
| Finished | Jan 07 12:40:00 PM PST 24 |
| Peak memory | 195216 kb |
| Host | smart-4a904da7-780f-4805-909a-16c813c20e3c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415144335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.415144335 |
| Directory | /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2145716248 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 56642670 ps |
| CPU time | 1.11 seconds |
| Started | Jan 07 12:37:49 PM PST 24 |
| Finished | Jan 07 12:39:15 PM PST 24 |
| Peak memory | 196208 kb |
| Host | smart-2f0b45a8-59eb-4471-89ab-c54ea1d19f79 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2145716248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2145716248 |
| Directory | /workspace/13.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2201050968 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 957014143 ps |
| CPU time | 1.39 seconds |
| Started | Jan 07 12:38:13 PM PST 24 |
| Finished | Jan 07 12:39:23 PM PST 24 |
| Peak memory | 196436 kb |
| Host | smart-eec65bc1-3dde-4834-996a-da815b6d5216 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201050968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2201050968 |
| Directory | /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2639503873 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 50043969 ps |
| CPU time | 1.03 seconds |
| Started | Jan 07 12:38:46 PM PST 24 |
| Finished | Jan 07 12:39:55 PM PST 24 |
| Peak memory | 196308 kb |
| Host | smart-0603ad00-9c43-4176-b568-668dfbb5f564 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2639503873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2639503873 |
| Directory | /workspace/14.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.273802082 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 216266348 ps |
| CPU time | 1.15 seconds |
| Started | Jan 07 12:37:49 PM PST 24 |
| Finished | Jan 07 12:39:37 PM PST 24 |
| Peak memory | 195432 kb |
| Host | smart-a37a7d09-b1eb-49f6-8604-5593c992f70a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273802082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.273802082 |
| Directory | /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2673206667 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 34860102 ps |
| CPU time | 0.98 seconds |
| Started | Jan 07 12:38:04 PM PST 24 |
| Finished | Jan 07 12:39:36 PM PST 24 |
| Peak memory | 195324 kb |
| Host | smart-a69e942d-b2bc-4e4b-8b52-7121b87d12ca |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2673206667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2673206667 |
| Directory | /workspace/15.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1184191963 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 80296785 ps |
| CPU time | 0.88 seconds |
| Started | Jan 07 12:37:59 PM PST 24 |
| Finished | Jan 07 12:39:16 PM PST 24 |
| Peak memory | 196364 kb |
| Host | smart-fe04d3fa-5207-4166-96df-1dc5ff4fe750 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184191963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1184191963 |
| Directory | /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3907699467 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 237544031 ps |
| CPU time | 1.14 seconds |
| Started | Jan 07 12:38:12 PM PST 24 |
| Finished | Jan 07 12:39:39 PM PST 24 |
| Peak memory | 197688 kb |
| Host | smart-b037b74a-707e-48f4-8b9b-1ad97cc28d42 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3907699467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3907699467 |
| Directory | /workspace/16.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3073169677 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 95441859 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 12:38:29 PM PST 24 |
| Finished | Jan 07 12:39:46 PM PST 24 |
| Peak memory | 195156 kb |
| Host | smart-247ae5d2-fc4c-4480-9f6e-cb12d6ffc415 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073169677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3073169677 |
| Directory | /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2028947790 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 146069385 ps |
| CPU time | 1.07 seconds |
| Started | Jan 07 12:37:41 PM PST 24 |
| Finished | Jan 07 12:38:57 PM PST 24 |
| Peak memory | 195564 kb |
| Host | smart-1cc04764-87b4-458b-a9b1-a910e802e2e1 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2028947790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2028947790 |
| Directory | /workspace/17.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1231799615 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 66207537 ps |
| CPU time | 1.22 seconds |
| Started | Jan 07 12:37:43 PM PST 24 |
| Finished | Jan 07 12:39:02 PM PST 24 |
| Peak memory | 196148 kb |
| Host | smart-69926b31-4ab4-46fd-8910-22cfabc89ae8 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231799615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1231799615 |
| Directory | /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2825242066 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 297781850 ps |
| CPU time | 1.43 seconds |
| Started | Jan 07 12:38:19 PM PST 24 |
| Finished | Jan 07 12:39:53 PM PST 24 |
| Peak memory | 196392 kb |
| Host | smart-b36d6fbb-1e17-44ca-bdf9-420443172aa0 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2825242066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2825242066 |
| Directory | /workspace/18.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.310270337 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 87042424 ps |
| CPU time | 0.96 seconds |
| Started | Jan 07 12:37:50 PM PST 24 |
| Finished | Jan 07 12:39:02 PM PST 24 |
| Peak memory | 196264 kb |
| Host | smart-44b63e88-ecc7-460d-b2f6-bd57a43e15dd |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310270337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.310270337 |
| Directory | /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.793851068 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 705011413 ps |
| CPU time | 1.17 seconds |
| Started | Jan 07 12:38:04 PM PST 24 |
| Finished | Jan 07 12:39:19 PM PST 24 |
| Peak memory | 196188 kb |
| Host | smart-59ae2c08-5552-420c-ae43-8d69f9c265ed |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=793851068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.793851068 |
| Directory | /workspace/2.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.498340599 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 120419317 ps |
| CPU time | 0.72 seconds |
| Started | Jan 07 12:38:18 PM PST 24 |
| Finished | Jan 07 12:39:23 PM PST 24 |
| Peak memory | 194064 kb |
| Host | smart-deb91c96-92b8-43c9-bd05-10937b3eee4a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498340599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e n_cdc_prim.498340599 |
| Directory | /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3485208001 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 36997043 ps |
| CPU time | 1.05 seconds |
| Started | Jan 07 12:37:49 PM PST 24 |
| Finished | Jan 07 12:39:10 PM PST 24 |
| Peak memory | 196180 kb |
| Host | smart-57367026-5625-4fd2-8a11-2e5b94ace6f0 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3485208001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3485208001 |
| Directory | /workspace/20.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.906222082 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 546599514 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 12:37:56 PM PST 24 |
| Finished | Jan 07 12:39:12 PM PST 24 |
| Peak memory | 196220 kb |
| Host | smart-44a6cfb3-14d2-4169-ac0a-99f6cc35a660 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906222082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.906222082 |
| Directory | /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.259112901 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 145188001 ps |
| CPU time | 1.12 seconds |
| Started | Jan 07 12:37:53 PM PST 24 |
| Finished | Jan 07 12:39:01 PM PST 24 |
| Peak memory | 195516 kb |
| Host | smart-7a35c043-6c9d-4784-8d1e-408d547017c6 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=259112901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.259112901 |
| Directory | /workspace/21.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.12913956 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 59004375 ps |
| CPU time | 0.89 seconds |
| Started | Jan 07 12:38:27 PM PST 24 |
| Finished | Jan 07 12:39:56 PM PST 24 |
| Peak memory | 196072 kb |
| Host | smart-b463a0a6-37c0-4a8e-9608-65484e1d8a7e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=12913956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.12913956 |
| Directory | /workspace/22.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1122957719 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 136155568 ps |
| CPU time | 1.17 seconds |
| Started | Jan 07 12:37:50 PM PST 24 |
| Finished | Jan 07 12:39:12 PM PST 24 |
| Peak memory | 196348 kb |
| Host | smart-fabe00fc-bbc5-4e24-beea-6c7e4b9b382e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1122957719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1122957719 |
| Directory | /workspace/23.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1529904427 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 155045753 ps |
| CPU time | 0.89 seconds |
| Started | Jan 07 12:37:35 PM PST 24 |
| Finished | Jan 07 12:38:51 PM PST 24 |
| Peak memory | 195356 kb |
| Host | smart-10710163-75d7-4fae-85d5-6221e3b0ffad |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529904427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1529904427 |
| Directory | /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.708292485 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 115616452 ps |
| CPU time | 0.8 seconds |
| Started | Jan 07 12:38:13 PM PST 24 |
| Finished | Jan 07 12:39:23 PM PST 24 |
| Peak memory | 195688 kb |
| Host | smart-fd877108-d6bd-4d2a-a4a1-7dbbfb441c10 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=708292485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.708292485 |
| Directory | /workspace/24.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2338481431 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 32930516 ps |
| CPU time | 0.9 seconds |
| Started | Jan 07 12:37:48 PM PST 24 |
| Finished | Jan 07 12:39:06 PM PST 24 |
| Peak memory | 196068 kb |
| Host | smart-aebf0ccb-47b8-48e0-a3d0-1748b6b7e9fb |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338481431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2338481431 |
| Directory | /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4426581 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 147681111 ps |
| CPU time | 0.84 seconds |
| Started | Jan 07 12:38:09 PM PST 24 |
| Finished | Jan 07 12:39:31 PM PST 24 |
| Peak memory | 194972 kb |
| Host | smart-5ef5c8ef-9eff-46e8-9cf8-2dc9c29db6f5 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4426581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.4426581 |
| Directory | /workspace/25.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.318484056 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 86988634 ps |
| CPU time | 1.27 seconds |
| Started | Jan 07 12:37:33 PM PST 24 |
| Finished | Jan 07 12:38:51 PM PST 24 |
| Peak memory | 196520 kb |
| Host | smart-22d10fe7-4707-47d9-8439-716dc2f1032f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318484056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.318484056 |
| Directory | /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2305655174 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 76693269 ps |
| CPU time | 0.78 seconds |
| Started | Jan 07 12:37:51 PM PST 24 |
| Finished | Jan 07 12:39:13 PM PST 24 |
| Peak memory | 195032 kb |
| Host | smart-8d27adf7-cf11-45d6-bcd2-fe4fe8ced2f9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2305655174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2305655174 |
| Directory | /workspace/26.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3458906925 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 134255986 ps |
| CPU time | 1.05 seconds |
| Started | Jan 07 12:37:55 PM PST 24 |
| Finished | Jan 07 12:39:07 PM PST 24 |
| Peak memory | 195540 kb |
| Host | smart-31196ca7-a1b2-4d20-85d4-8827d8de7180 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458906925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3458906925 |
| Directory | /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4074020644 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 51523008 ps |
| CPU time | 1.22 seconds |
| Started | Jan 07 12:38:22 PM PST 24 |
| Finished | Jan 07 12:39:37 PM PST 24 |
| Peak memory | 196472 kb |
| Host | smart-6330a280-111f-4f28-bd83-c1de424cdd74 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4074020644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.4074020644 |
| Directory | /workspace/27.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.254755068 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 286458897 ps |
| CPU time | 1.18 seconds |
| Started | Jan 07 12:37:31 PM PST 24 |
| Finished | Jan 07 12:39:07 PM PST 24 |
| Peak memory | 195336 kb |
| Host | smart-c3fe9e39-9df4-4923-8103-dca57d640e89 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254755068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.254755068 |
| Directory | /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1072977707 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 155408788 ps |
| CPU time | 0.89 seconds |
| Started | Jan 07 12:38:05 PM PST 24 |
| Finished | Jan 07 12:39:18 PM PST 24 |
| Peak memory | 196044 kb |
| Host | smart-03006d58-f9a1-4e0d-bb2f-bab7785f4ea4 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1072977707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1072977707 |
| Directory | /workspace/28.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3125642889 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 252058909 ps |
| CPU time | 1.04 seconds |
| Started | Jan 07 12:38:15 PM PST 24 |
| Finished | Jan 07 12:39:36 PM PST 24 |
| Peak memory | 195152 kb |
| Host | smart-2061c63d-e675-4484-9be3-1b9b3feedff6 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125642889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3125642889 |
| Directory | /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3939374994 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 209431261 ps |
| CPU time | 1.08 seconds |
| Started | Jan 07 12:38:28 PM PST 24 |
| Finished | Jan 07 12:39:35 PM PST 24 |
| Peak memory | 196148 kb |
| Host | smart-a57b26ee-15b7-44a5-aa5f-9630118dbbf0 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3939374994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3939374994 |
| Directory | /workspace/29.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2593291001 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 121684831 ps |
| CPU time | 1.05 seconds |
| Started | Jan 07 12:38:26 PM PST 24 |
| Finished | Jan 07 12:39:28 PM PST 24 |
| Peak memory | 196080 kb |
| Host | smart-efe111c7-2d66-4b04-b307-f934417bc9b5 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593291001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2593291001 |
| Directory | /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2801996270 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 61707622 ps |
| CPU time | 1 seconds |
| Started | Jan 07 12:37:48 PM PST 24 |
| Finished | Jan 07 12:39:26 PM PST 24 |
| Peak memory | 195612 kb |
| Host | smart-e4722f19-4439-439e-8381-ec8fa2ee1be7 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2801996270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2801996270 |
| Directory | /workspace/3.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3781469854 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 78824140 ps |
| CPU time | 0.87 seconds |
| Started | Jan 07 12:37:33 PM PST 24 |
| Finished | Jan 07 12:39:06 PM PST 24 |
| Peak memory | 196824 kb |
| Host | smart-7eda718b-0ec9-44ab-a61d-df10d2f0102a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781469854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.3781469854 |
| Directory | /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1220369435 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 47984926 ps |
| CPU time | 1.2 seconds |
| Started | Jan 07 12:38:07 PM PST 24 |
| Finished | Jan 07 12:39:21 PM PST 24 |
| Peak memory | 195128 kb |
| Host | smart-2aa262fa-f90e-4585-8c45-bb05cd1527de |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220369435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1220369435 |
| Directory | /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1886571267 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 351211968 ps |
| CPU time | 1.11 seconds |
| Started | Jan 07 12:38:13 PM PST 24 |
| Finished | Jan 07 12:39:26 PM PST 24 |
| Peak memory | 196380 kb |
| Host | smart-54d7f6a1-f59a-45de-a308-8c33e5b650a9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1886571267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1886571267 |
| Directory | /workspace/31.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1113911148 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 78688067 ps |
| CPU time | 0.67 seconds |
| Started | Jan 07 12:37:42 PM PST 24 |
| Finished | Jan 07 12:39:01 PM PST 24 |
| Peak memory | 194052 kb |
| Host | smart-573518c9-d9aa-4550-9efe-c8532ea54edd |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113911148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1113911148 |
| Directory | /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2016462489 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 182793091 ps |
| CPU time | 0.94 seconds |
| Started | Jan 07 12:38:03 PM PST 24 |
| Finished | Jan 07 12:39:04 PM PST 24 |
| Peak memory | 195276 kb |
| Host | smart-970975b1-a1ab-4cf8-9601-f3d0a3bf14fd |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2016462489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2016462489 |
| Directory | /workspace/32.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2144995929 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 27377949 ps |
| CPU time | 0.72 seconds |
| Started | Jan 07 12:38:39 PM PST 24 |
| Finished | Jan 07 12:40:15 PM PST 24 |
| Peak memory | 195012 kb |
| Host | smart-77700fad-debc-4ecd-a71b-2f151b385985 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144995929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2144995929 |
| Directory | /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.4253665139 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 283900518 ps |
| CPU time | 1.23 seconds |
| Started | Jan 07 12:38:34 PM PST 24 |
| Finished | Jan 07 12:39:52 PM PST 24 |
| Peak memory | 196520 kb |
| Host | smart-bb9c816d-c860-4d1c-b315-85f001fded69 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4253665139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.4253665139 |
| Directory | /workspace/33.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2590230309 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 122773390 ps |
| CPU time | 0.94 seconds |
| Started | Jan 07 12:37:56 PM PST 24 |
| Finished | Jan 07 12:39:07 PM PST 24 |
| Peak memory | 196104 kb |
| Host | smart-40733ce4-f0ef-40d0-87ce-ed80883b3cf0 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590230309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2590230309 |
| Directory | /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2655750893 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 48295226 ps |
| CPU time | 1.14 seconds |
| Started | Jan 07 12:38:04 PM PST 24 |
| Finished | Jan 07 12:39:28 PM PST 24 |
| Peak memory | 196404 kb |
| Host | smart-73544dd8-9625-48cd-b0cb-6682b353c12d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2655750893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2655750893 |
| Directory | /workspace/34.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3307535014 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 118015895 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 12:38:11 PM PST 24 |
| Finished | Jan 07 12:39:17 PM PST 24 |
| Peak memory | 196240 kb |
| Host | smart-3ff19fdd-15ec-4921-a8d3-a59d6f246f38 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307535014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3307535014 |
| Directory | /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3308263862 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 77835222 ps |
| CPU time | 1.32 seconds |
| Started | Jan 07 12:38:30 PM PST 24 |
| Finished | Jan 07 12:39:37 PM PST 24 |
| Peak memory | 197096 kb |
| Host | smart-a784c5d2-109c-46ab-9dfc-24b3ab984f14 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3308263862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3308263862 |
| Directory | /workspace/35.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3907412685 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 156714246 ps |
| CPU time | 1.07 seconds |
| Started | Jan 07 12:38:35 PM PST 24 |
| Finished | Jan 07 12:39:55 PM PST 24 |
| Peak memory | 196352 kb |
| Host | smart-a4d2b54a-9699-4124-ba16-0489f3fc76da |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907412685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3907412685 |
| Directory | /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.423695453 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 55479503 ps |
| CPU time | 1.07 seconds |
| Started | Jan 07 12:37:54 PM PST 24 |
| Finished | Jan 07 12:38:58 PM PST 24 |
| Peak memory | 197672 kb |
| Host | smart-07688876-c5e4-4f54-8ed8-c012dfff854a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423695453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.423695453 |
| Directory | /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1724973091 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 38876850 ps |
| CPU time | 1.12 seconds |
| Started | Jan 07 12:38:03 PM PST 24 |
| Finished | Jan 07 12:39:10 PM PST 24 |
| Peak memory | 196668 kb |
| Host | smart-06fd0041-a14e-4f70-b8c3-c28b0ad90c86 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1724973091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1724973091 |
| Directory | /workspace/37.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.231824611 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 31844029 ps |
| CPU time | 0.93 seconds |
| Started | Jan 07 12:38:10 PM PST 24 |
| Finished | Jan 07 12:39:50 PM PST 24 |
| Peak memory | 197700 kb |
| Host | smart-14f4c5dd-2eeb-48b6-b730-702f378dbfea |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231824611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.231824611 |
| Directory | /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2860207607 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 68594836 ps |
| CPU time | 0.98 seconds |
| Started | Jan 07 12:38:31 PM PST 24 |
| Finished | Jan 07 12:39:53 PM PST 24 |
| Peak memory | 196276 kb |
| Host | smart-86d25e1a-3dc4-4325-bab5-130656903883 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2860207607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2860207607 |
| Directory | /workspace/38.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2341933922 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 96713188 ps |
| CPU time | 1.04 seconds |
| Started | Jan 07 12:38:28 PM PST 24 |
| Finished | Jan 07 12:39:44 PM PST 24 |
| Peak memory | 196244 kb |
| Host | smart-e11f3512-9521-46ed-900e-96dd101d865d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341933922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2341933922 |
| Directory | /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.505863750 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 445469372 ps |
| CPU time | 1.36 seconds |
| Started | Jan 07 12:38:02 PM PST 24 |
| Finished | Jan 07 12:39:10 PM PST 24 |
| Peak memory | 197084 kb |
| Host | smart-df5ea848-6ad3-4b35-adaa-74646a1b82e5 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=505863750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.505863750 |
| Directory | /workspace/39.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3966019368 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 48559494 ps |
| CPU time | 0.97 seconds |
| Started | Jan 07 12:38:42 PM PST 24 |
| Finished | Jan 07 12:40:38 PM PST 24 |
| Peak memory | 195520 kb |
| Host | smart-6a8c790b-e2b5-4008-9abc-d3993d74c9e6 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966019368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3966019368 |
| Directory | /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2554350395 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 97480037 ps |
| CPU time | 0.79 seconds |
| Started | Jan 07 12:38:07 PM PST 24 |
| Finished | Jan 07 12:39:17 PM PST 24 |
| Peak memory | 194932 kb |
| Host | smart-91dfbf62-9361-4a00-a470-3bb064ca2b48 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2554350395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2554350395 |
| Directory | /workspace/4.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2812370809 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 96284100 ps |
| CPU time | 1.04 seconds |
| Started | Jan 07 12:38:40 PM PST 24 |
| Finished | Jan 07 12:39:50 PM PST 24 |
| Peak memory | 196244 kb |
| Host | smart-c7b56022-3208-4a9d-9922-ac8089ed5985 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812370809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.2812370809 |
| Directory | /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4202119871 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 133641959 ps |
| CPU time | 0.94 seconds |
| Started | Jan 07 12:38:24 PM PST 24 |
| Finished | Jan 07 12:39:30 PM PST 24 |
| Peak memory | 196268 kb |
| Host | smart-294d6d01-d561-409e-9b63-ce8da7a87dfe |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4202119871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.4202119871 |
| Directory | /workspace/40.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2422815929 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 63274762 ps |
| CPU time | 1.01 seconds |
| Started | Jan 07 12:38:32 PM PST 24 |
| Finished | Jan 07 12:39:47 PM PST 24 |
| Peak memory | 196172 kb |
| Host | smart-59a231f7-f738-4c0d-8ea9-246eee30fed4 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422815929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2422815929 |
| Directory | /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2720847516 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 78425240 ps |
| CPU time | 0.99 seconds |
| Started | Jan 07 12:38:27 PM PST 24 |
| Finished | Jan 07 12:39:34 PM PST 24 |
| Peak memory | 196264 kb |
| Host | smart-fc4561ad-5942-4e1a-8cf2-b7eb45693635 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2720847516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2720847516 |
| Directory | /workspace/42.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1708760578 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 152951486 ps |
| CPU time | 0.99 seconds |
| Started | Jan 07 12:37:37 PM PST 24 |
| Finished | Jan 07 12:39:19 PM PST 24 |
| Peak memory | 196128 kb |
| Host | smart-d41754ad-74a7-45bb-a1a7-6e976ca1129f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708760578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1708760578 |
| Directory | /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3292853175 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 156134818 ps |
| CPU time | 1.06 seconds |
| Started | Jan 07 12:38:02 PM PST 24 |
| Finished | Jan 07 12:39:11 PM PST 24 |
| Peak memory | 196164 kb |
| Host | smart-0de6cea1-f3bf-401f-a03e-97e46740762e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3292853175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3292853175 |
| Directory | /workspace/43.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3935053774 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 52961126 ps |
| CPU time | 1.24 seconds |
| Started | Jan 07 12:38:31 PM PST 24 |
| Finished | Jan 07 12:39:54 PM PST 24 |
| Peak memory | 195344 kb |
| Host | smart-83cf9a41-b2a7-4983-abfb-2aa4093e435a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935053774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3935053774 |
| Directory | /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3157824545 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 243446740 ps |
| CPU time | 1.17 seconds |
| Started | Jan 07 12:38:13 PM PST 24 |
| Finished | Jan 07 12:39:48 PM PST 24 |
| Peak memory | 196604 kb |
| Host | smart-c4dae425-74f0-46ab-bcf6-c29bb9c1e253 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3157824545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3157824545 |
| Directory | /workspace/44.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3879195381 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 150374671 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 12:38:01 PM PST 24 |
| Finished | Jan 07 12:39:15 PM PST 24 |
| Peak memory | 196020 kb |
| Host | smart-f0d041a7-efc7-4d58-bed5-0179235ba2be |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879195381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3879195381 |
| Directory | /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3486762139 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 77112537 ps |
| CPU time | 1.18 seconds |
| Started | Jan 07 12:38:14 PM PST 24 |
| Finished | Jan 07 12:39:19 PM PST 24 |
| Peak memory | 195352 kb |
| Host | smart-fab7b83b-5bde-4436-8743-1402a1e35af9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3486762139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3486762139 |
| Directory | /workspace/45.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1520607560 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 55209428 ps |
| CPU time | 1.01 seconds |
| Started | Jan 07 12:37:52 PM PST 24 |
| Finished | Jan 07 12:39:07 PM PST 24 |
| Peak memory | 196364 kb |
| Host | smart-f740371f-cf18-4ffd-9cd6-30f0be2166c9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520607560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1520607560 |
| Directory | /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2103800840 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 146276116 ps |
| CPU time | 1.01 seconds |
| Started | Jan 07 12:38:29 PM PST 24 |
| Finished | Jan 07 12:39:34 PM PST 24 |
| Peak memory | 196312 kb |
| Host | smart-f97bd212-ffe9-4c5e-8977-41f7bc881ce6 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2103800840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2103800840 |
| Directory | /workspace/46.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3818877213 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 71871660 ps |
| CPU time | 0.99 seconds |
| Started | Jan 07 12:38:36 PM PST 24 |
| Finished | Jan 07 12:39:42 PM PST 24 |
| Peak memory | 196316 kb |
| Host | smart-f7085e79-a280-4a85-9213-90f322a4a0ae |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818877213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3818877213 |
| Directory | /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.346004414 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 36773974 ps |
| CPU time | 0.97 seconds |
| Started | Jan 07 12:38:01 PM PST 24 |
| Finished | Jan 07 12:39:02 PM PST 24 |
| Peak memory | 195280 kb |
| Host | smart-00b9080b-45c2-4660-93dd-4b2fb50fc971 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346004414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.346004414 |
| Directory | /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3693242628 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 102004855 ps |
| CPU time | 1.03 seconds |
| Started | Jan 07 12:37:49 PM PST 24 |
| Finished | Jan 07 12:39:06 PM PST 24 |
| Peak memory | 197636 kb |
| Host | smart-86998ef0-3882-4a11-9300-a03ae9039654 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3693242628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3693242628 |
| Directory | /workspace/48.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3416558146 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 111965607 ps |
| CPU time | 0.76 seconds |
| Started | Jan 07 12:38:14 PM PST 24 |
| Finished | Jan 07 12:39:28 PM PST 24 |
| Peak memory | 195032 kb |
| Host | smart-e2f028a9-60f2-450e-8067-00aaf1f55162 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416558146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3416558146 |
| Directory | /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3131850094 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 242816067 ps |
| CPU time | 1.01 seconds |
| Started | Jan 07 12:37:49 PM PST 24 |
| Finished | Jan 07 12:38:54 PM PST 24 |
| Peak memory | 197520 kb |
| Host | smart-d9436d16-a538-40c6-96ca-1d3b57197726 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3131850094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3131850094 |
| Directory | /workspace/49.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.279442258 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 184806899 ps |
| CPU time | 0.99 seconds |
| Started | Jan 07 12:38:24 PM PST 24 |
| Finished | Jan 07 12:39:25 PM PST 24 |
| Peak memory | 197616 kb |
| Host | smart-d271aea8-d28d-471f-93db-f9ee5c5299a9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279442258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.279442258 |
| Directory | /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.140661364 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 75944156 ps |
| CPU time | 1.28 seconds |
| Started | Jan 07 12:37:46 PM PST 24 |
| Finished | Jan 07 12:38:59 PM PST 24 |
| Peak memory | 196832 kb |
| Host | smart-a56c7e36-8222-451f-b6d0-62b4946bd44f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=140661364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.140661364 |
| Directory | /workspace/5.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3279569534 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 98011778 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 12:38:09 PM PST 24 |
| Finished | Jan 07 12:39:23 PM PST 24 |
| Peak memory | 196376 kb |
| Host | smart-59a8d35d-d679-4a92-895f-dff955bfb3bd |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279569534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.3279569534 |
| Directory | /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1266310184 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 60489752 ps |
| CPU time | 1 seconds |
| Started | Jan 07 12:38:23 PM PST 24 |
| Finished | Jan 07 12:39:44 PM PST 24 |
| Peak memory | 195436 kb |
| Host | smart-62154834-78f0-4b81-b1d0-db792e128949 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1266310184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1266310184 |
| Directory | /workspace/7.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2789270753 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 46765628 ps |
| CPU time | 1.13 seconds |
| Started | Jan 07 12:37:47 PM PST 24 |
| Finished | Jan 07 12:38:51 PM PST 24 |
| Peak memory | 197592 kb |
| Host | smart-798a2eed-9d64-4b35-8169-1fd5cfcc86cf |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789270753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.2789270753 |
| Directory | /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2711973091 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 40724130 ps |
| CPU time | 0.82 seconds |
| Started | Jan 07 12:38:23 PM PST 24 |
| Finished | Jan 07 12:39:29 PM PST 24 |
| Peak memory | 195100 kb |
| Host | smart-483d619e-3f12-4c9a-929c-e94dfe28a83d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2711973091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2711973091 |
| Directory | /workspace/8.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.89783336 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 197231442 ps |
| CPU time | 1 seconds |
| Started | Jan 07 12:38:30 PM PST 24 |
| Finished | Jan 07 12:39:34 PM PST 24 |
| Peak memory | 195452 kb |
| Host | smart-fae308cc-60dd-4c02-a24f-204c32500941 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89783336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_en _cdc_prim.89783336 |
| Directory | /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2328753146 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 324036594 ps |
| CPU time | 0.98 seconds |
| Started | Jan 07 12:38:29 PM PST 24 |
| Finished | Jan 07 12:39:42 PM PST 24 |
| Peak memory | 196176 kb |
| Host | smart-5d02cb70-570b-4e8c-88f0-e56f67766937 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2328753146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2328753146 |
| Directory | /workspace/9.gpio_smoke_en_cdc_prim/latest |
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