Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	20848094	1			T1	3		T11	5		T2	7
all_values[1]	20848094	1			T1	3		T11	5		T2	7
all_values[2]	20848094	1			T1	3		T11	5		T2	7
all_values[3]	20848094	1			T1	3		T11	5		T2	7
all_values[4]	20848094	1			T1	3		T11	5		T2	7
all_values[5]	20848094	1			T1	3		T11	5		T2	7
all_values[6]	20848094	1			T1	3		T11	5		T2	7
all_values[7]	20848094	1			T1	3		T11	5		T2	7
all_values[8]	20848094	1			T1	3		T11	5		T2	7
all_values[9]	20848094	1			T1	3		T11	5		T2	7
all_values[10]	20848094	1			T1	3		T11	5		T2	7
all_values[11]	20848094	1			T1	3		T11	5		T2	7
all_values[12]	20848094	1			T1	3		T11	5		T2	7
all_values[13]	20848094	1			T1	3		T11	5		T2	7
all_values[14]	20848094	1			T1	3		T11	5		T2	7
all_values[15]	20848094	1			T1	3		T11	5		T2	7
all_values[16]	20848094	1			T1	3		T11	5		T2	7
all_values[17]	20848094	1			T1	3		T11	5		T2	7
all_values[18]	20848094	1			T1	3		T11	5		T2	7
all_values[19]	20848094	1			T1	3		T11	5		T2	7
all_values[20]	20848094	1			T1	3		T11	5		T2	7
all_values[21]	20848094	1			T1	3		T11	5		T2	7
all_values[22]	20848094	1			T1	3		T11	5		T2	7
all_values[23]	20848094	1			T1	3		T11	5		T2	7
all_values[24]	20848094	1			T1	3		T11	5		T2	7
all_values[25]	20848094	1			T1	3		T11	5		T2	7
all_values[26]	20848094	1			T1	3		T11	5		T2	7
all_values[27]	20848094	1			T1	3		T11	5		T2	7
all_values[28]	20848094	1			T1	3		T11	5		T2	7
all_values[29]	20848094	1			T1	3		T11	5		T2	7
all_values[30]	20848094	1			T1	3		T11	5		T2	7
all_values[31]	20848094	1			T1	3		T11	5		T2	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

373210223

1

T1

74

T11

160

T2

213

auto[1]

293928785

1

T1

22

T2

11

T14

38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132700795

1

T1

78

T11

136

T2

177

auto[1]

534438213

1

T1

18

T11

24

T2

47

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3296323	1			T1	2		T11	4		T2	5
all_values[0]	auto[0]	auto[1]	8345849	1			T1	1		T11	1		T2	1
all_values[0]	auto[1]	auto[0]	844531	1			T20	5		T73	1		T4	9
all_values[0]	auto[1]	auto[1]	8361391	1			T2	1		T14	2		T20	3
all_values[1]	auto[0]	auto[0]	3299895	1			T1	2		T11	4		T2	6
all_values[1]	auto[0]	auto[1]	8398625	1			T11	1		T2	1		T12	1
all_values[1]	auto[1]	auto[0]	848098	1			T15	1		T20	3		T19	3
all_values[1]	auto[1]	auto[1]	8301476	1			T1	1		T14	2		T15	2
all_values[2]	auto[0]	auto[0]	3298761	1			T1	2		T11	5		T2	5
all_values[2]	auto[0]	auto[1]	8370657	1			T2	1		T12	2		T20	11
all_values[2]	auto[1]	auto[0]	848961	1			T14	2		T15	3		T20	2
all_values[2]	auto[1]	auto[1]	8329715	1			T1	1		T2	1		T19	3
all_values[3]	auto[0]	auto[0]	3298502	1			T1	2		T11	4		T2	5
all_values[3]	auto[0]	auto[1]	8333339	1			T11	1		T2	2		T12	1
all_values[3]	auto[1]	auto[0]	852566	1			T1	1		T15	2		T20	1
all_values[3]	auto[1]	auto[1]	8363687	1			T15	1		T20	5		T3	3
all_values[4]	auto[0]	auto[0]	3295739	1			T1	3		T11	4		T2	6
all_values[4]	auto[0]	auto[1]	8371792	1			T11	1		T12	1		T20	3
all_values[4]	auto[1]	auto[0]	858067	1			T15	3		T20	7		T73	1
all_values[4]	auto[1]	auto[1]	8322496	1			T2	1		T14	2		T20	8
all_values[5]	auto[0]	auto[0]	3302773	1			T1	2		T11	4		T2	6
all_values[5]	auto[0]	auto[1]	8339772	1			T11	1		T2	1		T12	2
all_values[5]	auto[1]	auto[0]	858737	1			T20	2		T19	3		T4	5
all_values[5]	auto[1]	auto[1]	8346812	1			T1	1		T14	2		T20	6
all_values[6]	auto[0]	auto[0]	3302849	1			T1	2		T11	4		T2	4
all_values[6]	auto[0]	auto[1]	8340507	1			T11	1		T2	2		T20	5
all_values[6]	auto[1]	auto[0]	852983	1			T1	1		T2	1		T15	3
all_values[6]	auto[1]	auto[1]	8351755	1			T14	2		T20	4		T19	3
all_values[7]	auto[0]	auto[0]	3300419	1			T1	2		T11	5		T2	4
all_values[7]	auto[0]	auto[1]	8380230	1			T2	3		T12	1		T15	1
all_values[7]	auto[1]	auto[0]	841581	1			T1	1		T20	3		T73	1
all_values[7]	auto[1]	auto[1]	8325864	1			T14	2		T20	5		T4	4
all_values[8]	auto[0]	auto[0]	3309776	1			T1	2		T11	4		T2	7
all_values[8]	auto[0]	auto[1]	8334158	1			T11	1		T14	2		T20	8
all_values[8]	auto[1]	auto[0]	853211	1			T1	1		T15	3		T19	3
all_values[8]	auto[1]	auto[1]	8350949	1			T3	3		T4	8		T77	13
all_values[9]	auto[0]	auto[0]	3293254	1			T1	2		T11	5		T2	6
all_values[9]	auto[0]	auto[1]	8355030	1			T2	1		T12	1		T14	2
all_values[9]	auto[1]	auto[0]	852990	1			T20	2		T19	3		T4	4
all_values[9]	auto[1]	auto[1]	8346820	1			T1	1		T73	1		T4	4
all_values[10]	auto[0]	auto[0]	3292096	1			T1	2		T11	5		T2	5
all_values[10]	auto[0]	auto[1]	8391954	1			T2	2		T14	1		T20	1
all_values[10]	auto[1]	auto[0]	857563	1			T20	11		T73	1		T4	7
all_values[10]	auto[1]	auto[1]	8306481	1			T1	1		T14	2		T15	3
all_values[11]	auto[0]	auto[0]	3307333	1			T1	2		T11	3		T2	6
all_values[11]	auto[0]	auto[1]	8347057	1			T1	1		T11	2		T12	1
all_values[11]	auto[1]	auto[0]	854138	1			T2	1		T20	2		T4	8
all_values[11]	auto[1]	auto[1]	8339566	1			T19	3		T3	3		T4	3
all_values[12]	auto[0]	auto[0]	3298288	1			T1	2		T11	5		T2	6
all_values[12]	auto[0]	auto[1]	8367355	1			T12	2		T20	5		T3	3
all_values[12]	auto[1]	auto[0]	842295	1			T1	1		T20	5		T4	3
all_values[12]	auto[1]	auto[1]	8340156	1			T2	1		T20	6		T19	3
all_values[13]	auto[0]	auto[0]	3298091	1			T1	2		T11	4		T2	5
all_values[13]	auto[0]	auto[1]	8354009	1			T11	1		T2	2		T14	1
all_values[13]	auto[1]	auto[0]	838982	1			T20	5		T4	8		T5	6
all_values[13]	auto[1]	auto[1]	8357012	1			T1	1		T14	2		T15	3
all_values[14]	auto[0]	auto[0]	3296486	1			T1	3		T11	5		T2	5
all_values[14]	auto[0]	auto[1]	8375034	1			T2	2		T12	2		T20	3
all_values[14]	auto[1]	auto[0]	844113	1			T15	2		T19	1		T4	5
all_values[14]	auto[1]	auto[1]	8332461	1			T14	2		T15	1		T19	2
all_values[15]	auto[0]	auto[0]	3294924	1			T1	2		T11	4		T2	5
all_values[15]	auto[0]	auto[1]	8387543	1			T11	1		T2	2		T12	1
all_values[15]	auto[1]	auto[0]	850151	1			T1	1		T20	9		T4	8
all_values[15]	auto[1]	auto[1]	8315476	1			T14	2		T20	5		T19	3
all_values[16]	auto[0]	auto[0]	3297458	1			T1	2		T11	5		T2	5
all_values[16]	auto[0]	auto[1]	8366792	1			T2	1		T12	1		T14	1
all_values[16]	auto[1]	auto[0]	855862	1			T2	1		T20	3		T3	5
all_values[16]	auto[1]	auto[1]	8327982	1			T1	1		T14	2		T15	3
all_values[17]	auto[0]	auto[0]	3293068	1			T1	2		T11	4		T2	6
all_values[17]	auto[0]	auto[1]	8379882	1			T11	1		T14	3		T15	3
all_values[17]	auto[1]	auto[0]	846926	1			T2	1		T20	3		T19	3
all_values[17]	auto[1]	auto[1]	8328218	1			T1	1		T20	7		T3	3
all_values[18]	auto[0]	auto[0]	3296786	1			T1	2		T11	3		T2	5
all_values[18]	auto[0]	auto[1]	8377573	1			T11	2		T2	2		T20	12
all_values[18]	auto[1]	auto[0]	841086	1			T1	1		T20	1		T19	3
all_values[18]	auto[1]	auto[1]	8332649	1			T14	2		T15	3		T3	2
all_values[19]	auto[0]	auto[0]	3306904	1			T1	3		T11	5		T2	5
all_values[19]	auto[0]	auto[1]	8374646	1			T2	2		T12	1		T20	1
all_values[19]	auto[1]	auto[0]	854777	1			T14	2		T20	3		T3	3
all_values[19]	auto[1]	auto[1]	8311767	1			T15	3		T20	4		T3	2
all_values[20]	auto[0]	auto[0]	3299490	1			T1	2		T11	5		T2	5
all_values[20]	auto[0]	auto[1]	8386004	1			T2	1		T14	1		T20	2
all_values[20]	auto[1]	auto[0]	850400	1			T2	1		T15	3		T20	8
all_values[20]	auto[1]	auto[1]	8312200	1			T1	1		T3	1		T4	7
all_values[21]	auto[0]	auto[0]	3300660	1			T1	2		T11	3		T2	4
all_values[21]	auto[0]	auto[1]	8363963	1			T11	2		T2	3		T14	1
all_values[21]	auto[1]	auto[0]	850422	1			T20	3		T19	3		T4	8
all_values[21]	auto[1]	auto[1]	8333049	1			T1	1		T14	2		T20	2
all_values[22]	auto[0]	auto[0]	3290449	1			T1	3		T11	5		T2	5
all_values[22]	auto[0]	auto[1]	8370030	1			T2	2		T12	1		T15	3
all_values[22]	auto[1]	auto[0]	851677	1			T14	2		T20	7		T3	1
all_values[22]	auto[1]	auto[1]	8335938	1			T20	10		T19	3		T73	1
all_values[23]	auto[0]	auto[0]	3299095	1			T1	2		T11	4		T2	5
all_values[23]	auto[0]	auto[1]	8386007	1			T1	1		T11	1		T2	2
all_values[23]	auto[1]	auto[0]	831914	1			T20	1		T19	1		T4	7
all_values[23]	auto[1]	auto[1]	8331078	1			T15	3		T20	1		T19	2
all_values[24]	auto[0]	auto[0]	3304143	1			T1	2		T11	3		T2	6
all_values[24]	auto[0]	auto[1]	8350485	1			T11	2		T2	1		T12	1
all_values[24]	auto[1]	auto[0]	839467	1			T1	1		T20	8		T19	3
all_values[24]	auto[1]	auto[1]	8353999	1			T20	3		T4	6		T77	13
all_values[25]	auto[0]	auto[0]	3299920	1			T1	2		T11	5		T2	6
all_values[25]	auto[0]	auto[1]	8360223	1			T2	1		T12	1		T20	5
all_values[25]	auto[1]	auto[0]	853296	1			T14	1		T20	6		T4	5
all_values[25]	auto[1]	auto[1]	8334655	1			T1	1		T14	1		T15	3
all_values[26]	auto[0]	auto[0]	3297808	1			T1	2		T11	4		T2	6
all_values[26]	auto[0]	auto[1]	8353047	1			T1	1		T11	1		T2	1
all_values[26]	auto[1]	auto[0]	846022	1			T20	7		T3	1		T4	6
all_values[26]	auto[1]	auto[1]	8351217	1			T14	2		T15	3		T20	4
all_values[27]	auto[0]	auto[0]	3303209	1			T1	2		T11	4		T2	6
all_values[27]	auto[0]	auto[1]	8363218	1			T1	1		T11	1		T2	1
all_values[27]	auto[1]	auto[0]	837906	1			T15	3		T20	7		T4	7
all_values[27]	auto[1]	auto[1]	8343761	1			T20	3		T3	2		T4	3
all_values[28]	auto[0]	auto[0]	3295532	1			T1	2		T11	4		T2	5
all_values[28]	auto[0]	auto[1]	8313361	1			T11	1		T2	2		T12	1
all_values[28]	auto[1]	auto[0]	850009	1			T1	1		T15	3		T20	3
all_values[28]	auto[1]	auto[1]	8389192	1			T14	2		T3	3		T4	2
all_values[29]	auto[0]	auto[0]	3284513	1			T1	2		T11	4		T2	5
all_values[29]	auto[0]	auto[1]	8380068	1			T11	1		T2	1		T14	1
all_values[29]	auto[1]	auto[0]	840976	1			T20	3		T4	5		T77	8
all_values[29]	auto[1]	auto[1]	8342537	1			T1	1		T2	1		T20	6
all_values[30]	auto[0]	auto[0]	3296120	1			T1	2		T11	4		T2	5
all_values[30]	auto[0]	auto[1]	8392235	1			T11	1		T2	1		T14	3
all_values[30]	auto[1]	auto[0]	848455	1			T1	1		T15	3		T20	2
all_values[30]	auto[1]	auto[1]	8311284	1			T2	1		T20	13		T3	2
all_values[31]	auto[0]	auto[0]	3296359	1			T1	2		T11	5		T2	7
all_values[31]	auto[0]	auto[1]	8352755	1			T1	1		T12	1		T20	8
all_values[31]	auto[1]	auto[0]	855610	1			T20	2		T3	2		T4	9
all_values[31]	auto[1]	auto[1]	8343370	1			T15	3		T20	1		T77	22