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Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3121999 1 T40 172 T41 180 T42 30
auto[1] 2734828 1 T40 156 T41 220 T42 36


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3688859 1 T40 186 T41 229 T42 27
auto[1] 2167968 1 T40 142 T41 171 T42 39


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2032348 1 T40 106 T41 105 T42 14
auto[0] auto[1] 1089651 1 T40 66 T41 75 T42 16
auto[1] auto[0] 1656511 1 T40 80 T41 124 T42 13
auto[1] auto[1] 1078317 1 T40 76 T41 96 T42 23


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3124716 1 T40 158 T41 212 T42 38
auto[1] 2732111 1 T40 170 T41 188 T42 28


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3683579 1 T40 157 T41 196 T42 19
auto[1] 2173248 1 T40 171 T41 204 T42 47


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2031452 1 T40 74 T41 108 T42 10
auto[0] auto[1] 1093264 1 T40 84 T41 104 T42 28
auto[1] auto[0] 1652127 1 T40 83 T41 88 T42 9
auto[1] auto[1] 1079984 1 T40 87 T41 100 T42 19


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3127289 1 T40 162 T41 194 T42 20
auto[1] 2729538 1 T40 166 T41 206 T42 46


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3691700 1 T40 150 T41 202 T42 36
auto[1] 2165127 1 T40 178 T41 198 T42 30


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2036357 1 T40 76 T41 101 T42 9
auto[0] auto[1] 1090932 1 T40 86 T41 93 T42 11
auto[1] auto[0] 1655343 1 T40 74 T41 101 T42 27
auto[1] auto[1] 1074195 1 T40 92 T41 105 T42 19


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3125432 1 T40 162 T41 178 T42 38
auto[1] 2731395 1 T40 166 T41 222 T42 28


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3691168 1 T40 169 T41 184 T42 30
auto[1] 2165659 1 T40 159 T41 216 T42 36


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2033993 1 T40 83 T41 92 T42 21
auto[0] auto[1] 1091439 1 T40 79 T41 86 T42 17
auto[1] auto[0] 1657175 1 T40 86 T41 92 T42 9
auto[1] auto[1] 1074220 1 T40 80 T41 130 T42 19


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3119302 1 T40 174 T41 188 T42 46
auto[1] 2737525 1 T40 154 T41 212 T42 20


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3687363 1 T40 173 T41 200 T42 32
auto[1] 2169464 1 T40 155 T41 200 T42 34


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2027802 1 T40 84 T41 88 T42 22
auto[0] auto[1] 1091500 1 T40 90 T41 100 T42 24
auto[1] auto[0] 1659561 1 T40 89 T41 112 T42 10
auto[1] auto[1] 1077964 1 T40 65 T41 100 T42 10


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3128181 1 T40 168 T41 190 T42 32
auto[1] 2728646 1 T40 160 T41 210 T42 34


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3687884 1 T40 153 T41 185 T42 32
auto[1] 2168943 1 T40 175 T41 215 T42 34


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2035175 1 T40 77 T41 87 T42 17
auto[0] auto[1] 1093006 1 T40 91 T41 103 T42 15
auto[1] auto[0] 1652709 1 T40 76 T41 98 T42 15
auto[1] auto[1] 1075937 1 T40 84 T41 112 T42 19


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3125547 1 T40 164 T41 198 T42 24
auto[1] 2731280 1 T40 164 T41 202 T42 42


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3687488 1 T40 173 T41 180 T42 27
auto[1] 2169339 1 T40 155 T41 220 T42 39


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2033230 1 T40 78 T41 84 T42 11
auto[0] auto[1] 1092317 1 T40 86 T41 114 T42 13
auto[1] auto[0] 1654258 1 T40 95 T41 96 T42 16
auto[1] auto[1] 1077022 1 T40 69 T41 106 T42 26


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3122178 1 T40 168 T41 194 T42 30
auto[1] 2734649 1 T40 160 T41 206 T42 36


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3690663 1 T40 168 T41 185 T42 40
auto[1] 2166164 1 T40 160 T41 215 T42 26


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2032281 1 T40 87 T41 95 T42 20
auto[0] auto[1] 1089897 1 T40 81 T41 99 T42 10
auto[1] auto[0] 1658382 1 T40 81 T41 90 T42 20
auto[1] auto[1] 1076267 1 T40 79 T41 116 T42 16


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3119958 1 T40 172 T41 208 T42 44
auto[1] 2736869 1 T40 156 T41 192 T42 22


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3700033 1 T40 149 T41 224 T42 38
auto[1] 2156794 1 T40 179 T41 176 T42 28


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2035663 1 T40 82 T41 116 T42 28
auto[0] auto[1] 1084295 1 T40 90 T41 92 T42 16
auto[1] auto[0] 1664370 1 T40 67 T41 108 T42 10
auto[1] auto[1] 1072499 1 T40 89 T41 84 T42 12


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3122260 1 T40 172 T41 196 T42 30
auto[1] 2734567 1 T40 156 T41 204 T42 36


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3698778 1 T40 166 T41 217 T42 31
auto[1] 2158049 1 T40 162 T41 183 T42 35


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2036190 1 T40 83 T41 110 T42 14
auto[0] auto[1] 1086070 1 T40 89 T41 86 T42 16
auto[1] auto[0] 1662588 1 T40 83 T41 107 T42 17
auto[1] auto[1] 1071979 1 T40 73 T41 97 T42 19


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3123735 1 T40 162 T41 182 T42 38
auto[1] 2733092 1 T40 166 T41 218 T42 28


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3699377 1 T40 180 T41 167 T42 30
auto[1] 2157450 1 T40 148 T41 233 T42 36


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2037708 1 T40 95 T41 74 T42 17
auto[0] auto[1] 1086027 1 T40 67 T41 108 T42 21
auto[1] auto[0] 1661669 1 T40 85 T41 93 T42 13
auto[1] auto[1] 1071423 1 T40 81 T41 125 T42 15


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3123476 1 T40 140 T41 188 T42 30
auto[1] 2733351 1 T40 188 T41 212 T42 36


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3696504 1 T40 172 T41 218 T42 37
auto[1] 2160323 1 T40 156 T41 182 T42 29


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2036095 1 T40 79 T41 102 T42 17
auto[0] auto[1] 1087381 1 T40 61 T41 86 T42 13
auto[1] auto[0] 1660409 1 T40 93 T41 116 T42 20
auto[1] auto[1] 1072942 1 T40 95 T41 96 T42 16


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3123397 1 T40 160 T41 198 T42 38
auto[1] 2733430 1 T40 168 T41 202 T42 28


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3688873 1 T40 168 T41 186 T42 38
auto[1] 2167954 1 T40 160 T41 214 T42 28


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2033573 1 T40 76 T41 97 T42 20
auto[0] auto[1] 1089824 1 T40 84 T41 101 T42 18
auto[1] auto[0] 1655300 1 T40 92 T41 89 T42 18
auto[1] auto[1] 1078130 1 T40 76 T41 113 T42 10


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3122081 1 T40 146 T41 206 T42 34
auto[1] 2734746 1 T40 182 T41 194 T42 32


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3700740 1 T40 183 T41 198 T42 24
auto[1] 2156087 1 T40 145 T41 202 T42 42


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2037317 1 T40 87 T41 96 T42 16
auto[0] auto[1] 1084764 1 T40 59 T41 110 T42 18
auto[1] auto[0] 1663423 1 T40 96 T41 102 T42 8
auto[1] auto[1] 1071323 1 T40 86 T41 92 T42 24


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3128134 1 T40 172 T41 188 T42 32
auto[1] 2728693 1 T40 156 T41 212 T42 34


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3701068 1 T40 151 T41 198 T42 36
auto[1] 2155759 1 T40 177 T41 202 T42 30


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2041516 1 T40 81 T41 89 T42 16
auto[0] auto[1] 1086618 1 T40 91 T41 99 T42 16
auto[1] auto[0] 1659552 1 T40 70 T41 109 T42 20
auto[1] auto[1] 1069141 1 T40 86 T41 103 T42 14


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3121634 1 T40 154 T41 202 T42 28
auto[1] 2735193 1 T40 174 T41 198 T42 38


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3700254 1 T40 174 T41 202 T42 37
auto[1] 2156573 1 T40 154 T41 198 T42 29


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2036002 1 T40 84 T41 110 T42 17
auto[0] auto[1] 1085632 1 T40 70 T41 92 T42 11
auto[1] auto[0] 1664252 1 T40 90 T41 92 T42 20
auto[1] auto[1] 1070941 1 T40 84 T41 106 T42 18


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3124835 1 T40 156 T41 200 T42 32
auto[1] 2731992 1 T40 172 T41 200 T42 34


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3697658 1 T40 171 T41 212 T42 43
auto[1] 2159169 1 T40 157 T41 188 T42 23


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2037031 1 T40 78 T41 106 T42 21
auto[0] auto[1] 1087804 1 T40 78 T41 94 T42 11
auto[1] auto[0] 1660627 1 T40 93 T41 106 T42 22
auto[1] auto[1] 1071365 1 T40 79 T41 94 T42 12


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3120856 1 T40 178 T41 182 T42 34
auto[1] 2735971 1 T40 150 T41 218 T42 32


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3698824 1 T40 182 T41 208 T42 34
auto[1] 2158003 1 T40 146 T41 192 T42 32


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2036521 1 T40 103 T41 95 T42 19
auto[0] auto[1] 1084335 1 T40 75 T41 87 T42 15
auto[1] auto[0] 1662303 1 T40 79 T41 113 T42 15
auto[1] auto[1] 1073668 1 T40 71 T41 105 T42 17


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3123393 1 T40 146 T41 208 T42 40
auto[1] 2733434 1 T40 182 T41 192 T42 26


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3697196 1 T40 168 T41 195 T42 39
auto[1] 2159631 1 T40 160 T41 205 T42 27


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2034116 1 T40 69 T41 95 T42 23
auto[0] auto[1] 1089277 1 T40 77 T41 113 T42 17
auto[1] auto[0] 1663080 1 T40 99 T41 100 T42 16
auto[1] auto[1] 1070354 1 T40 83 T41 92 T42 10


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3125665 1 T40 154 T41 204 T42 36
auto[1] 2731162 1 T40 174 T41 196 T42 30


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3697902 1 T40 164 T41 203 T42 36
auto[1] 2158925 1 T40 164 T41 197 T42 30


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2037520 1 T40 81 T41 99 T42 19
auto[0] auto[1] 1088145 1 T40 73 T41 105 T42 17
auto[1] auto[0] 1660382 1 T40 83 T41 104 T42 17
auto[1] auto[1] 1070780 1 T40 91 T41 92 T42 13


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3122089 1 T40 164 T41 192 T42 36
auto[1] 2734738 1 T40 164 T41 208 T42 30


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3699161 1 T40 158 T41 203 T42 38
auto[1] 2157666 1 T40 170 T41 197 T42 28


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2035809 1 T40 76 T41 94 T42 21
auto[0] auto[1] 1086280 1 T40 88 T41 98 T42 15
auto[1] auto[0] 1663352 1 T40 82 T41 109 T42 17
auto[1] auto[1] 1071386 1 T40 82 T41 99 T42 13


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3129221 1 T40 166 T41 180 T42 30
auto[1] 2727606 1 T40 162 T41 220 T42 36


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3701515 1 T40 171 T41 230 T42 39
auto[1] 2155312 1 T40 157 T41 170 T42 27


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2041203 1 T40 88 T41 106 T42 20
auto[0] auto[1] 1088018 1 T40 78 T41 74 T42 10
auto[1] auto[0] 1660312 1 T40 83 T41 124 T42 19
auto[1] auto[1] 1067294 1 T40 79 T41 96 T42 17


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3129492 1 T40 156 T41 190 T42 36
auto[1] 2727335 1 T40 172 T41 210 T42 30


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3699449 1 T40 152 T41 186 T42 41
auto[1] 2157378 1 T40 176 T41 214 T42 25


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2040812 1 T40 68 T41 84 T42 25
auto[0] auto[1] 1088680 1 T40 88 T41 106 T42 11
auto[1] auto[0] 1658637 1 T40 84 T41 102 T42 16
auto[1] auto[1] 1068698 1 T40 88 T41 108 T42 14


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3121159 1 T40 158 T41 202 T42 26
auto[1] 2735668 1 T40 170 T41 198 T42 40


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3693545 1 T40 142 T41 195 T42 25
auto[1] 2163282 1 T40 186 T41 205 T42 41


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2031711 1 T40 75 T41 105 T42 13
auto[0] auto[1] 1089448 1 T40 83 T41 97 T42 13
auto[1] auto[0] 1661834 1 T40 67 T41 90 T42 12
auto[1] auto[1] 1073834 1 T40 103 T41 108 T42 28


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3121077 1 T40 146 T41 196 T42 26
auto[1] 2735750 1 T40 182 T41 204 T42 40


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3700569 1 T40 153 T41 204 T42 37
auto[1] 2156258 1 T40 175 T41 196 T42 29


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2036006 1 T40 76 T41 103 T42 15
auto[0] auto[1] 1085071 1 T40 70 T41 93 T42 11
auto[1] auto[0] 1664563 1 T40 77 T41 101 T42 22
auto[1] auto[1] 1071187 1 T40 105 T41 103 T42 18


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3120753 1 T40 178 T41 184 T42 32
auto[1] 2736074 1 T40 150 T41 216 T42 34


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3702118 1 T40 160 T41 205 T42 42
auto[1] 2154709 1 T40 168 T41 195 T42 24

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