Unified Coverage Report :: Group Instance : masked_out_lower_mask_data_cov_obj

Group Instance : masked_out_lower_mask_data_cov_obj_pin3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin3

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_lower_mask_data_cov_obj_pin4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_lower_mask_data_cov_obj_pin5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin5

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_lower_mask_data_cov_obj_pin6

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin6

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin6

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin6

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_lower_mask_data_cov_obj_pin7

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin7

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin7

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin7

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_lower_mask_data_cov_obj_pin8

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin8

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin8

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin8

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_lower_mask_data_cov_obj_pin9

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin9

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin9

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin9

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin0

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin1

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin10

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin10

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin10

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin10

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin11

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin11

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin11

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin11

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin12

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin12

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin12

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin12

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin13

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin13

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin13

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin13

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin14

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin14

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin14

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin14

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin15

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin15

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin15

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin15

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin2

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin3

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316041

T32

6568

T43

T51

auto[1]

316363

T32

6547

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316121

T32

6606

T51

T44

auto[1]

316283

T32

6509

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158268

T32

3314

T51

T70

4545

auto[0]

auto[1]

157773

T32

3254

T43

T51

auto[1]

auto[0]

157853

T32

3292

T51

T44

auto[1]

158510

T32

3255

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316014

T32

6511

T43

T51

auto[1]

316390

T32

6604

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316057

T32

6569

T43

T51

auto[1]

316347

T32

6546

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158297

T32

3248

T51

T70

4662

auto[0]

auto[1]

157717

T32

3263

T43

T51

auto[1]

auto[0]

157760

T32

3321

T43

T51

auto[1]

158630

T32

3283

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316189

T32

6543

T43

T51

auto[1]

316215

T32

6572

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316188

T32

6617

T43

T51

auto[1]

316216

T32

6498

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

157907

T32

3313

T43

T51

auto[0]

auto[1]

158282

T32

3230

T51

T44

auto[1]

auto[0]

158281

T32

3304

T43

T51

auto[1]

157934

T32

3268

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316115

T32

6557

T43

T51

auto[1]

316289

T32

6558

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316383

T32

6575

T51

T44

auto[1]

316021

T32

6540

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158159

T32

3276

T51

T44

auto[0]

auto[1]

157956

T32

3281

T43

T51

auto[1]

auto[0]

158224

T32

3299

T51

T44

auto[1]

158065

T32

3259

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316393

T32

6519

T43

T51

auto[1]

316011

T32

6596

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316011

T32

6490

T43

T51

auto[1]

316393

T32

6625

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158080

T32

3216

T51

T70

4602

auto[0]

auto[1]

158313

T32

3303

T43

T51

auto[1]

auto[0]

157931

T32

3274

T43

T51

auto[1]

158080

T32

3322

T51

T44

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316345

T32

6539

T43

T51

auto[1]

316059

T32

6576

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316405

T32

6566

T43

T51

auto[1]

315999

T32

6549

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158647

T32

3312

T43

T51

auto[0]

auto[1]

157698

T32

3227

T43

T51

auto[1]

auto[0]

157758

T32

3254

T43

T51

auto[1]

158301

T32

3322

T51

T44

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

315918

T32

6601

T43

T51

auto[1]

316486

T32

6514

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316033

T32

6598

T43

T51

auto[1]

316371

T32

6517

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

157816

T32

3299

T51

T44

auto[0]

auto[1]

158102

T32

3302

T43

T51

auto[1]

auto[0]

158217

T32

3299

T43

T51

auto[1]

158269

T32

3215

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316671

T32

6453

T43

T51

auto[1]

315918

T32

6434

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316328

T32

6479

T43

T51

auto[1]

316261

T32

6408

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158339

T32

3288

T43

T51

auto[0]

auto[1]

158332

T32

3165

T43

T51

auto[1]

auto[0]

157989

T32

3191

T51

T44

auto[1]

157929

T32

3243

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316535

T32

6409

T43

T51

auto[1]

316054

T32

6478

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316435

T32

6368

T43

T51

auto[1]

316154

T32

6519

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158632

T32

3147

T51

T44

auto[0]

auto[1]

157903

T32

3262

T43

T51

auto[1]

auto[0]

157803

T32

3221

T43

T51

auto[1]

158251

T32

3257

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316261

T32

6413

T43

T51

auto[1]

316328

T32

6474

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316074

T32

6479

T43

T51

auto[1]

316515

T32

6408

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158074

T32

3213

T43

T51

auto[0]

auto[1]

158187

T32

3200

T43

T51

auto[1]

auto[0]

158000

T32

3266

T51

T44

auto[1]

158328

T32

3208

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316467

T32

6567

T43

T51

auto[1]

316122

T32

6320

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316824

T32

6526

T43

T51

auto[1]

315765

T32

6361

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158462

T32

3322

T43

T51

auto[0]

auto[1]

158005

T32

3245

T43

T51

auto[1]

auto[0]

158362

T32

3204

T43

T51

auto[1]

157760

T32

3116

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316803

T32

6378

T43

T51

auto[1]

315786

T32

6509

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316250

T32

6474

T43

T51

auto[1]

316339

T32

6413

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158332

T32

3252

T43

T51

auto[0]

auto[1]

158471

T32

3126

T43

T51

auto[1]

auto[0]

157918

T32

3222

T43

T51

auto[1]

157868

T32

3287

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316325

T32

6419

T43

T51

auto[1]

316264

T32

6468

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316572

T32

6414

T43

T51

auto[1]

316017

T32

6473

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158025

T32

3167

T43

T51

auto[0]

auto[1]

158300

T32

3252

T43

T51

auto[1]

auto[0]

158547

T32

3247

T43

T51

auto[1]

157717

T32

3221

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

315612

T32

6345

T43

T51

auto[1]

316977

T32

6542

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316256

T32

6501

T43

T51

auto[1]

316333

T32

6386

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

157655

T32

3194

T43

T51

auto[0]

auto[1]

157957

T32

3151

T43

T51

auto[1]

auto[0]

158601

T32

3307

T51

T70

4633

auto[1]

158376

T32

3235

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316148

T32

6464

T43

T51

auto[1]

316441

T32

6423

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

315766

T32

6341

T43

T51

auto[1]

316823

T32

6546

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158250

T32

3158

T43

T51

auto[0]

auto[1]

157898

T32

3306

T43

T51

auto[1]

auto[0]

157516

T32

3183

T43

T51

auto[1]

158925

T32

3240

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316402

T32

6583

T43

T51

auto[1]

316187

T32

6304

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316428

T32

6500

T43

T51

auto[1]

316161

T32

6387

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158599

T32

3314

T43

T51

auto[0]

auto[1]

157803

T32

3269

T43

T51

auto[1]

auto[0]

157829

T32

3186

T43

T51

auto[1]

158358

T32

3118

T51

T70

4751

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316525

T32

6443

T43

T51

auto[1]

316064

T32

6444

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316611

T32

6530

T43

T51

auto[1]

315978

T32

6357

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158419

T32

3250

T43

T51

auto[0]

auto[1]

158106

T32

3193

T43

T51

auto[1]

auto[0]

158192

T32

3280

T43

T51

auto[1]

157872

T32

3164

T43

T51

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316243

T32

6554

T43

T51

auto[1]

316346

T32

6333

T43

T51

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

315788

T32

6350

T43

T51

auto[1]

316801

T32

6537

T43

T51

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

157783

T32

3198

T43

T51

auto[0]

auto[1]

158460

T32

3356

T43

T51

auto[1]

auto[0]

158005

T32

3152

T43

T51

auto[1]

158341

T32

3181

T43

T51