Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6079488	1			T1	4		T11	9		T2	7
all_pins[1]	6079488	1			T1	4		T11	9		T2	7
all_pins[2]	6079488	1			T1	4		T11	9		T2	7
all_pins[3]	6079488	1			T1	4		T11	9		T2	7
all_pins[4]	6079488	1			T1	4		T11	9		T2	7
all_pins[5]	6079488	1			T1	4		T11	9		T2	7
all_pins[6]	6079488	1			T1	4		T11	9		T2	7
all_pins[7]	6079488	1			T1	4		T11	9		T2	7
all_pins[8]	6079488	1			T1	4		T11	9		T2	7
all_pins[9]	6079488	1			T1	4		T11	9		T2	7
all_pins[10]	6079488	1			T1	4		T11	9		T2	7
all_pins[11]	6079488	1			T1	4		T11	9		T2	7
all_pins[12]	6079488	1			T1	4		T11	9		T2	7
all_pins[13]	6079488	1			T1	4		T11	9		T2	7
all_pins[14]	6079488	1			T1	4		T11	9		T2	7
all_pins[15]	6079488	1			T1	4		T11	9		T2	7
all_pins[16]	6079488	1			T1	4		T11	9		T2	7
all_pins[17]	6079488	1			T1	4		T11	9		T2	7
all_pins[18]	6079488	1			T1	4		T11	9		T2	7
all_pins[19]	6079488	1			T1	4		T11	9		T2	7
all_pins[20]	6079488	1			T1	4		T11	9		T2	7
all_pins[21]	6079488	1			T1	4		T11	9		T2	7
all_pins[22]	6079488	1			T1	4		T11	9		T2	7
all_pins[23]	6079488	1			T1	4		T11	9		T2	7
all_pins[24]	6079488	1			T1	4		T11	9		T2	7
all_pins[25]	6079488	1			T1	4		T11	9		T2	7
all_pins[26]	6079488	1			T1	4		T11	9		T2	7
all_pins[27]	6079488	1			T1	4		T11	9		T2	7
all_pins[28]	6079488	1			T1	4		T11	9		T2	7
all_pins[29]	6079488	1			T1	4		T11	9		T2	7
all_pins[30]	6079488	1			T1	4		T11	9		T2	7
all_pins[31]	6079488	1			T1	4		T11	9		T2	7

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	120623030	1			T1	106		T11	250		T2	206
values[0x1]	73920586	1			T1	22		T11	38		T2	18
transitions[0x0=>0x1]	44240262	1			T1	15		T11	30		T2	13
transitions[0x1=>0x0]	44240107	1			T1	15		T11	30		T2	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3770278	1			T1	4		T11	5		T2	5
all_pins[0]	values[0x1]	2309210	1			T11	4		T2	2		T12	2
all_pins[0]	transitions[0x0=>0x1]	1426177	1			T11	4		T2	2		T12	2
all_pins[0]	transitions[0x1=>0x0]	1422094	1			T12	1		T13	1		T15	3
all_pins[1]	values[0x0]	3765847	1			T1	2		T11	9		T2	7
all_pins[1]	values[0x1]	2313641	1			T1	2		T13	1		T14	3
all_pins[1]	transitions[0x0=>0x1]	1382189	1			T1	2		T13	1		T14	1
all_pins[1]	transitions[0x1=>0x0]	1377758	1			T11	4		T2	2		T12	2
all_pins[2]	values[0x0]	3776555	1			T1	2		T11	9		T2	6
all_pins[2]	values[0x1]	2302933	1			T1	2		T2	1		T12	2
all_pins[2]	transitions[0x0=>0x1]	1375265	1			T2	1		T12	2		T13	1
all_pins[2]	transitions[0x1=>0x0]	1385973	1			T13	1		T14	3		T15	1
all_pins[3]	values[0x0]	3772965	1			T1	4		T11	7		T2	7
all_pins[3]	values[0x1]	2306523	1			T11	2		T12	2		T13	1
all_pins[3]	transitions[0x0=>0x1]	1381827	1			T11	2		T12	2		T13	1
all_pins[3]	transitions[0x1=>0x0]	1378237	1			T1	2		T2	1		T12	2
all_pins[4]	values[0x0]	3767910	1			T1	4		T11	8		T2	6
all_pins[4]	values[0x1]	2311578	1			T11	1		T2	1		T12	5
all_pins[4]	transitions[0x0=>0x1]	1385067	1			T2	1		T12	3		T13	1
all_pins[4]	transitions[0x1=>0x0]	1380012	1			T11	1		T13	1		T14	1
all_pins[5]	values[0x0]	3767490	1			T1	2		T11	6		T2	7
all_pins[5]	values[0x1]	2311998	1			T1	2		T11	3		T12	3
all_pins[5]	transitions[0x0=>0x1]	1381580	1			T1	2		T11	3		T13	1
all_pins[5]	transitions[0x1=>0x0]	1381160	1			T11	1		T2	1		T12	2
all_pins[6]	values[0x0]	3772922	1			T1	4		T11	7		T2	6
all_pins[6]	values[0x1]	2306566	1			T11	2		T2	1		T13	1
all_pins[6]	transitions[0x0=>0x1]	1376002	1			T11	2		T2	1		T13	1
all_pins[6]	transitions[0x1=>0x0]	1381434	1			T1	2		T11	3		T12	3
all_pins[7]	values[0x0]	3770008	1			T1	4		T11	9		T2	6
all_pins[7]	values[0x1]	2309480	1			T2	1		T13	1		T14	3
all_pins[7]	transitions[0x0=>0x1]	1381176	1			T13	1		T14	1		T20	3
all_pins[7]	transitions[0x1=>0x0]	1378262	1			T11	2		T13	1		T15	2
all_pins[8]	values[0x0]	3766894	1			T1	4		T11	7		T2	7
all_pins[8]	values[0x1]	2312594	1			T11	2		T13	1		T19	2
all_pins[8]	transitions[0x0=>0x1]	1384897	1			T11	2		T13	1		T19	2
all_pins[8]	transitions[0x1=>0x0]	1381783	1			T2	1		T13	1		T14	3
all_pins[9]	values[0x0]	3765618	1			T1	2		T11	8		T2	7
all_pins[9]	values[0x1]	2313870	1			T1	2		T11	1		T13	1
all_pins[9]	transitions[0x0=>0x1]	1382982	1			T1	2		T13	1		T15	1
all_pins[9]	transitions[0x1=>0x0]	1381706	1			T11	1		T13	1		T73	5
all_pins[10]	values[0x0]	3768113	1			T1	3		T11	8		T2	6
all_pins[10]	values[0x1]	2311375	1			T1	1		T11	1		T2	1
all_pins[10]	transitions[0x0=>0x1]	1378915	1			T2	1		T13	1		T14	3
all_pins[10]	transitions[0x1=>0x0]	1381410	1			T1	1		T13	1		T15	1
all_pins[11]	values[0x0]	3769434	1			T1	4		T11	9		T2	7
all_pins[11]	values[0x1]	2310054	1			T12	1		T13	1		T19	3
all_pins[11]	transitions[0x0=>0x1]	1379713	1			T12	1		T13	1		T19	2
all_pins[11]	transitions[0x1=>0x0]	1381034	1			T1	1		T11	1		T2	1
all_pins[12]	values[0x0]	3765831	1			T1	4		T11	9		T2	4
all_pins[12]	values[0x1]	2313657	1			T2	3		T12	1		T13	1
all_pins[12]	transitions[0x0=>0x1]	1384739	1			T2	3		T12	1		T13	1
all_pins[12]	transitions[0x1=>0x0]	1381136	1			T12	1		T13	1		T19	1
all_pins[13]	values[0x0]	3769664	1			T1	2		T11	9		T2	6
all_pins[13]	values[0x1]	2309824	1			T1	2		T2	1		T13	1
all_pins[13]	transitions[0x0=>0x1]	1377492	1			T1	2		T13	1		T14	3
all_pins[13]	transitions[0x1=>0x0]	1381325	1			T2	2		T12	1		T13	1
all_pins[14]	values[0x0]	3771875	1			T1	4		T11	9		T2	7
all_pins[14]	values[0x1]	2307613	1			T12	5		T13	1		T14	1
all_pins[14]	transitions[0x0=>0x1]	1378383	1			T12	5		T13	1		T73	3
all_pins[14]	transitions[0x1=>0x0]	1380594	1			T1	2		T2	1		T13	1
all_pins[15]	values[0x0]	3770322	1			T1	4		T11	9		T2	7
all_pins[15]	values[0x1]	2309166	1			T12	2		T13	1		T14	3
all_pins[15]	transitions[0x0=>0x1]	1380180	1			T13	1		T14	2		T15	2
all_pins[15]	transitions[0x1=>0x0]	1378627	1			T12	3		T13	1		T73	4
all_pins[16]	values[0x0]	3765932	1			T1	2		T11	8		T2	7
all_pins[16]	values[0x1]	2313556	1			T1	2		T11	1		T12	2
all_pins[16]	transitions[0x0=>0x1]	1386408	1			T1	2		T11	1		T13	1
all_pins[16]	transitions[0x1=>0x0]	1382018	1			T13	1		T15	1		T20	5
all_pins[17]	values[0x0]	3775137	1			T1	2		T11	8		T2	7
all_pins[17]	values[0x1]	2304351	1			T1	2		T11	1		T13	1
all_pins[17]	transitions[0x0=>0x1]	1376023	1			T13	1		T20	4		T19	1
all_pins[17]	transitions[0x1=>0x0]	1385228	1			T12	2		T13	1		T14	2
all_pins[18]	values[0x0]	3769456	1			T1	4		T11	6		T2	7
all_pins[18]	values[0x1]	2310032	1			T11	3		T13	1		T14	1
all_pins[18]	transitions[0x0=>0x1]	1384380	1			T11	3		T13	1		T14	1
all_pins[18]	transitions[0x1=>0x0]	1378699	1			T1	2		T11	1		T13	1
all_pins[19]	values[0x0]	3773629	1			T1	4		T11	8		T2	6
all_pins[19]	values[0x1]	2305859	1			T11	1		T2	1		T12	3
all_pins[19]	transitions[0x0=>0x1]	1377414	1			T11	1		T2	1		T12	3
all_pins[19]	transitions[0x1=>0x0]	1381587	1			T11	3		T13	1		T14	1
all_pins[20]	values[0x0]	3774893	1			T1	2		T11	7		T2	6
all_pins[20]	values[0x1]	2304595	1			T1	2		T11	2		T2	1
all_pins[20]	transitions[0x0=>0x1]	1378952	1			T1	2		T11	2		T13	1
all_pins[20]	transitions[0x1=>0x0]	1380216	1			T11	1		T12	3		T13	1
all_pins[21]	values[0x0]	3764861	1			T1	2		T11	5		T2	7
all_pins[21]	values[0x1]	2314627	1			T1	2		T11	4		T13	1
all_pins[21]	transitions[0x0=>0x1]	1391489	1			T11	2		T13	1		T14	2
all_pins[21]	transitions[0x1=>0x0]	1381457	1			T2	1		T13	1		T15	2
all_pins[22]	values[0x0]	3769267	1			T1	4		T11	9		T2	7
all_pins[22]	values[0x1]	2310221	1			T13	1		T15	1		T20	9
all_pins[22]	transitions[0x0=>0x1]	1380347	1			T13	1		T15	1		T20	8
all_pins[22]	transitions[0x1=>0x0]	1384753	1			T1	2		T11	4		T13	1
all_pins[23]	values[0x0]	3770173	1			T1	4		T11	8		T2	7
all_pins[23]	values[0x1]	2309315	1			T11	1		T13	1		T15	3
all_pins[23]	transitions[0x0=>0x1]	1381064	1			T11	1		T13	1		T15	3
all_pins[23]	transitions[0x1=>0x0]	1381970	1			T13	1		T15	1		T20	8
all_pins[24]	values[0x0]	3772897	1			T1	4		T11	8		T2	6
all_pins[24]	values[0x1]	2306591	1			T11	1		T2	1		T12	2
all_pins[24]	transitions[0x0=>0x1]	1378985	1			T2	1		T12	2		T13	1
all_pins[24]	transitions[0x1=>0x0]	1381709	1			T13	1		T15	3		T73	3
all_pins[25]	values[0x0]	3763738	1			T1	3		T11	7		T2	7
all_pins[25]	values[0x1]	2315750	1			T1	1		T11	2		T12	2
all_pins[25]	transitions[0x0=>0x1]	1387786	1			T1	1		T11	2		T12	2
all_pins[25]	transitions[0x1=>0x0]	1378627	1			T11	1		T2	1		T12	2
all_pins[26]	values[0x0]	3766449	1			T1	4		T11	9		T2	7
all_pins[26]	values[0x1]	2313039	1			T12	2		T13	1		T14	2
all_pins[26]	transitions[0x0=>0x1]	1380460	1			T13	1		T15	2		T20	1
all_pins[26]	transitions[0x1=>0x0]	1383171	1			T1	1		T11	2		T13	1
all_pins[27]	values[0x0]	3771001	1			T1	4		T11	6		T2	7
all_pins[27]	values[0x1]	2308487	1			T11	3		T12	2		T13	1
all_pins[27]	transitions[0x0=>0x1]	1377000	1			T11	3		T13	1		T20	1
all_pins[27]	transitions[0x1=>0x0]	1381552	1			T13	1		T14	2		T15	1
all_pins[28]	values[0x0]	3760631	1			T1	4		T11	7		T2	7
all_pins[28]	values[0x1]	2318857	1			T11	2		T12	4		T13	1
all_pins[28]	transitions[0x0=>0x1]	1387358	1			T11	1		T12	2		T13	1
all_pins[28]	transitions[0x1=>0x0]	1376988	1			T11	2		T13	1		T20	3
all_pins[29]	values[0x0]	3764702	1			T1	2		T11	9		T2	5
all_pins[29]	values[0x1]	2314786	1			T1	2		T2	2		T13	1
all_pins[29]	transitions[0x0=>0x1]	1378629	1			T1	2		T2	2		T13	1
all_pins[29]	transitions[0x1=>0x0]	1382700	1			T11	2		T12	4		T13	1
all_pins[30]	values[0x0]	3774332	1			T1	4		T11	8		T2	5
all_pins[30]	values[0x1]	2305156	1			T11	1		T2	2		T12	2
all_pins[30]	transitions[0x0=>0x1]	1377910	1			T11	1		T12	2		T13	1
all_pins[30]	transitions[0x1=>0x0]	1387540	1			T1	2		T13	1		T73	2
all_pins[31]	values[0x0]	3774206	1			T1	4		T11	9		T2	7
all_pins[31]	values[0x1]	2305282	1			T12	1		T13	1		T15	4
all_pins[31]	transitions[0x0=>0x1]	1379473	1			T13	1		T15	2		T20	1
all_pins[31]	transitions[0x1=>0x0]	1379347	1			T11	1		T2	2		T12	1