Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	20848094	1			T1	3		T11	5		T2	7
all_values[1]	20848094	1			T1	3		T11	5		T2	7
all_values[2]	20848094	1			T1	3		T11	5		T2	7
all_values[3]	20848094	1			T1	3		T11	5		T2	7
all_values[4]	20848094	1			T1	3		T11	5		T2	7
all_values[5]	20848094	1			T1	3		T11	5		T2	7
all_values[6]	20848094	1			T1	3		T11	5		T2	7
all_values[7]	20848094	1			T1	3		T11	5		T2	7
all_values[8]	20848094	1			T1	3		T11	5		T2	7
all_values[9]	20848094	1			T1	3		T11	5		T2	7
all_values[10]	20848094	1			T1	3		T11	5		T2	7
all_values[11]	20848094	1			T1	3		T11	5		T2	7
all_values[12]	20848094	1			T1	3		T11	5		T2	7
all_values[13]	20848094	1			T1	3		T11	5		T2	7
all_values[14]	20848094	1			T1	3		T11	5		T2	7
all_values[15]	20848094	1			T1	3		T11	5		T2	7
all_values[16]	20848094	1			T1	3		T11	5		T2	7
all_values[17]	20848094	1			T1	3		T11	5		T2	7
all_values[18]	20848094	1			T1	3		T11	5		T2	7
all_values[19]	20848094	1			T1	3		T11	5		T2	7
all_values[20]	20848094	1			T1	3		T11	5		T2	7
all_values[21]	20848094	1			T1	3		T11	5		T2	7
all_values[22]	20848094	1			T1	3		T11	5		T2	7
all_values[23]	20848094	1			T1	3		T11	5		T2	7
all_values[24]	20848094	1			T1	3		T11	5		T2	7
all_values[25]	20848094	1			T1	3		T11	5		T2	7
all_values[26]	20848094	1			T1	3		T11	5		T2	7
all_values[27]	20848094	1			T1	3		T11	5		T2	7
all_values[28]	20848094	1			T1	3		T11	5		T2	7
all_values[29]	20848094	1			T1	3		T11	5		T2	7
all_values[30]	20848094	1			T1	3		T11	5		T2	7
all_values[31]	20848094	1			T1	3		T11	5		T2	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

373210223

1

T1

74

T11

160

T2

213

auto[1]

293928785

1

T1

22

T2

11

T14

38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132700795

1

T1

78

T11

136

T2

177

auto[1]

534438213

1

T1

18

T11

24

T2

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659629843

1

T1

96

T11

160

T2

224

auto[1]

7509165

1

T20

96

T21

88

T103

41

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3296323	1			T1	2		T11	4		T2	5
all_values[0]	auto[0]	auto[0]	auto[1]	8228381	1			T1	1		T11	1		T2	1
all_values[0]	auto[0]	auto[1]	auto[0]	844531	1			T20	5		T73	1		T4	9
all_values[0]	auto[0]	auto[1]	auto[1]	8244395	1			T2	1		T14	2		T20	1
all_values[0]	auto[1]	auto[0]	auto[1]	117468	1			T21	2		T103	1		T104	3
all_values[0]	auto[1]	auto[1]	auto[1]	116996	1			T20	2		T21	2		T105	2
all_values[1]	auto[0]	auto[0]	auto[0]	3299895	1			T1	2		T11	4		T2	6
all_values[1]	auto[0]	auto[0]	auto[1]	8281370	1			T11	1		T2	1		T12	1
all_values[1]	auto[0]	auto[1]	auto[0]	848098	1			T15	1		T20	3		T19	3
all_values[1]	auto[0]	auto[1]	auto[1]	8184080	1			T1	1		T14	2		T15	2
all_values[1]	auto[1]	auto[0]	auto[1]	117255	1			T20	1		T21	1		T103	1
all_values[1]	auto[1]	auto[1]	auto[1]	117396	1			T20	2		T21	2		T103	1
all_values[2]	auto[0]	auto[0]	auto[0]	3298761	1			T1	2		T11	5		T2	5
all_values[2]	auto[0]	auto[0]	auto[1]	8252412	1			T2	1		T12	2		T20	9
all_values[2]	auto[0]	auto[1]	auto[0]	848961	1			T14	2		T15	3		T20	2
all_values[2]	auto[0]	auto[1]	auto[1]	8213288	1			T1	1		T2	1		T19	3
all_values[2]	auto[1]	auto[0]	auto[1]	118245	1			T20	2		T21	1		T103	1
all_values[2]	auto[1]	auto[1]	auto[1]	116427	1			T21	2		T105	2		T104	3
all_values[3]	auto[0]	auto[0]	auto[0]	3298502	1			T1	2		T11	4		T2	5
all_values[3]	auto[0]	auto[0]	auto[1]	8216212	1			T11	1		T2	2		T12	1
all_values[3]	auto[0]	auto[1]	auto[0]	852566	1			T1	1		T15	2		T20	1
all_values[3]	auto[0]	auto[1]	auto[1]	8246321	1			T15	1		T20	4		T3	3
all_values[3]	auto[1]	auto[0]	auto[1]	117127	1			T20	2		T21	1		T103	1
all_values[3]	auto[1]	auto[1]	auto[1]	117366	1			T20	1		T21	2		T105	2
all_values[4]	auto[0]	auto[0]	auto[0]	3295739	1			T1	3		T11	4		T2	6
all_values[4]	auto[0]	auto[0]	auto[1]	8253757	1			T11	1		T12	1		T20	1
all_values[4]	auto[0]	auto[1]	auto[0]	858067	1			T15	3		T20	7		T73	1
all_values[4]	auto[0]	auto[1]	auto[1]	8205534	1			T2	1		T14	2		T20	5
all_values[4]	auto[1]	auto[0]	auto[1]	118035	1			T20	2		T21	3		T105	4
all_values[4]	auto[1]	auto[1]	auto[1]	116962	1			T20	3		T21	2		T105	3
all_values[5]	auto[0]	auto[0]	auto[0]	3302773	1			T1	2		T11	4		T2	6
all_values[5]	auto[0]	auto[0]	auto[1]	8221834	1			T11	1		T2	1		T12	2
all_values[5]	auto[0]	auto[1]	auto[0]	858737	1			T20	2		T19	3		T4	5
all_values[5]	auto[0]	auto[1]	auto[1]	8229755	1			T1	1		T14	2		T20	5
all_values[5]	auto[1]	auto[0]	auto[1]	117938	1			T20	1		T21	2		T103	3
all_values[5]	auto[1]	auto[1]	auto[1]	117057	1			T20	1		T21	3		T105	4
all_values[6]	auto[0]	auto[0]	auto[0]	3302849	1			T1	2		T11	4		T2	4
all_values[6]	auto[0]	auto[0]	auto[1]	8222529	1			T11	1		T2	2		T20	3
all_values[6]	auto[0]	auto[1]	auto[0]	852983	1			T1	1		T2	1		T15	3
all_values[6]	auto[0]	auto[1]	auto[1]	8235607	1			T14	2		T20	3		T19	3
all_values[6]	auto[1]	auto[0]	auto[1]	117978	1			T20	2		T103	1		T105	4
all_values[6]	auto[1]	auto[1]	auto[1]	116148	1			T20	1		T21	3		T105	3
all_values[7]	auto[0]	auto[0]	auto[0]	3300419	1			T1	2		T11	5		T2	4
all_values[7]	auto[0]	auto[0]	auto[1]	8262084	1			T2	3		T12	1		T15	1
all_values[7]	auto[0]	auto[1]	auto[0]	841581	1			T1	1		T20	3		T73	1
all_values[7]	auto[0]	auto[1]	auto[1]	8209233	1			T14	2		T20	4		T4	4
all_values[7]	auto[1]	auto[0]	auto[1]	118146	1			T20	3		T21	3		T103	1
all_values[7]	auto[1]	auto[1]	auto[1]	116631	1			T20	1		T21	1		T105	1
all_values[8]	auto[0]	auto[0]	auto[0]	3309776	1			T1	2		T11	4		T2	7
all_values[8]	auto[0]	auto[0]	auto[1]	8216910	1			T11	1		T14	2		T20	6
all_values[8]	auto[0]	auto[1]	auto[0]	853211	1			T1	1		T15	3		T19	3
all_values[8]	auto[0]	auto[1]	auto[1]	8233391	1			T3	3		T4	8		T77	13
all_values[8]	auto[1]	auto[0]	auto[1]	117248	1			T20	2		T103	2		T105	2
all_values[8]	auto[1]	auto[1]	auto[1]	117558	1			T21	1		T105	4		T104	1
all_values[9]	auto[0]	auto[0]	auto[0]	3293254	1			T1	2		T11	5		T2	6
all_values[9]	auto[0]	auto[0]	auto[1]	8237187	1			T2	1		T12	1		T14	2
all_values[9]	auto[0]	auto[1]	auto[0]	852990	1			T20	2		T19	3		T4	4
all_values[9]	auto[0]	auto[1]	auto[1]	8229973	1			T1	1		T73	1		T4	4
all_values[9]	auto[1]	auto[0]	auto[1]	117843	1			T20	2		T103	2		T105	3
all_values[9]	auto[1]	auto[1]	auto[1]	116847	1			T21	2		T105	3		T104	1
all_values[10]	auto[0]	auto[0]	auto[0]	3292096	1			T1	2		T11	5		T2	5
all_values[10]	auto[0]	auto[0]	auto[1]	8274562	1			T2	2		T14	1		T3	5
all_values[10]	auto[0]	auto[1]	auto[0]	857563	1			T20	11		T73	1		T4	7
all_values[10]	auto[0]	auto[1]	auto[1]	8189148	1			T1	1		T14	2		T15	3
all_values[10]	auto[1]	auto[0]	auto[1]	117392	1			T20	1		T21	1		T105	2
all_values[10]	auto[1]	auto[1]	auto[1]	117333	1			T20	3		T105	4		T104	2
all_values[11]	auto[0]	auto[0]	auto[0]	3307333	1			T1	2		T11	3		T2	6
all_values[11]	auto[0]	auto[0]	auto[1]	8229656	1			T1	1		T11	2		T12	1
all_values[11]	auto[0]	auto[1]	auto[0]	854138	1			T2	1		T20	2		T4	8
all_values[11]	auto[0]	auto[1]	auto[1]	8222116	1			T19	3		T3	3		T4	3
all_values[11]	auto[1]	auto[0]	auto[1]	117401	1			T21	2		T105	1		T104	3
all_values[11]	auto[1]	auto[1]	auto[1]	117450	1			T21	1		T105	3		T104	1
all_values[12]	auto[0]	auto[0]	auto[0]	3298288	1			T1	2		T11	5		T2	6
all_values[12]	auto[0]	auto[0]	auto[1]	8250394	1			T12	2		T20	3		T3	3
all_values[12]	auto[0]	auto[1]	auto[0]	842295	1			T1	1		T20	5		T4	3
all_values[12]	auto[0]	auto[1]	auto[1]	8222588	1			T2	1		T20	4		T19	3
all_values[12]	auto[1]	auto[0]	auto[1]	116961	1			T20	2		T21	2		T103	1
all_values[12]	auto[1]	auto[1]	auto[1]	117568	1			T20	2		T21	1		T105	3
all_values[13]	auto[0]	auto[0]	auto[0]	3298091	1			T1	2		T11	4		T2	5
all_values[13]	auto[0]	auto[0]	auto[1]	8236482	1			T11	1		T2	2		T14	1
all_values[13]	auto[0]	auto[1]	auto[0]	838982	1			T20	5		T4	8		T5	6
all_values[13]	auto[0]	auto[1]	auto[1]	8239928	1			T1	1		T14	2		T15	3
all_values[13]	auto[1]	auto[0]	auto[1]	117527	1			T20	2		T21	2		T103	1
all_values[13]	auto[1]	auto[1]	auto[1]	117084	1			T21	1		T103	1		T105	4
all_values[14]	auto[0]	auto[0]	auto[0]	3296486	1			T1	3		T11	5		T2	5
all_values[14]	auto[0]	auto[0]	auto[1]	8257706	1			T2	2		T12	2		T20	1
all_values[14]	auto[0]	auto[1]	auto[0]	844113	1			T15	2		T19	1		T4	5
all_values[14]	auto[0]	auto[1]	auto[1]	8215286	1			T14	2		T15	1		T19	2
all_values[14]	auto[1]	auto[0]	auto[1]	117328	1			T20	2		T21	1		T103	2
all_values[14]	auto[1]	auto[1]	auto[1]	117175	1			T21	1		T105	5		T104	2
all_values[15]	auto[0]	auto[0]	auto[0]	3294924	1			T1	2		T11	4		T2	5
all_values[15]	auto[0]	auto[0]	auto[1]	8270035	1			T11	1		T2	2		T12	1
all_values[15]	auto[0]	auto[1]	auto[0]	850151	1			T1	1		T20	9		T4	8
all_values[15]	auto[0]	auto[1]	auto[1]	8198021	1			T14	2		T20	4		T19	3
all_values[15]	auto[1]	auto[0]	auto[1]	117508	1			T21	1		T103	1		T105	3
all_values[15]	auto[1]	auto[1]	auto[1]	117455	1			T20	1		T103	1		T105	2
all_values[16]	auto[0]	auto[0]	auto[0]	3297458	1			T1	2		T11	5		T2	5
all_values[16]	auto[0]	auto[0]	auto[1]	8248733	1			T2	1		T12	1		T14	1
all_values[16]	auto[0]	auto[1]	auto[0]	855862	1			T2	1		T20	3		T3	5
all_values[16]	auto[0]	auto[1]	auto[1]	8210724	1			T1	1		T14	2		T15	3
all_values[16]	auto[1]	auto[0]	auto[1]	118059	1			T20	3		T105	3		T104	4
all_values[16]	auto[1]	auto[1]	auto[1]	117258	1			T20	1		T21	3		T105	1
all_values[17]	auto[0]	auto[0]	auto[0]	3293068	1			T1	2		T11	4		T2	6
all_values[17]	auto[0]	auto[0]	auto[1]	8262046	1			T11	1		T14	3		T15	3
all_values[17]	auto[0]	auto[1]	auto[0]	846926	1			T2	1		T20	3		T19	3
all_values[17]	auto[0]	auto[1]	auto[1]	8211401	1			T1	1		T20	5		T3	3
all_values[17]	auto[1]	auto[0]	auto[1]	117836	1			T20	3		T103	1		T105	3
all_values[17]	auto[1]	auto[1]	auto[1]	116817	1			T20	2		T21	1		T105	4
all_values[18]	auto[0]	auto[0]	auto[0]	3296786	1			T1	2		T11	3		T2	5
all_values[18]	auto[0]	auto[0]	auto[1]	8260454	1			T11	2		T2	2		T20	9
all_values[18]	auto[0]	auto[1]	auto[0]	841086	1			T1	1		T20	1		T19	3
all_values[18]	auto[0]	auto[1]	auto[1]	8215190	1			T14	2		T15	3		T3	2
all_values[18]	auto[1]	auto[0]	auto[1]	117119	1			T20	3		T21	3		T105	1
all_values[18]	auto[1]	auto[1]	auto[1]	117459	1			T103	1		T105	5		T104	2
all_values[19]	auto[0]	auto[0]	auto[0]	3306904	1			T1	3		T11	5		T2	5
all_values[19]	auto[0]	auto[0]	auto[1]	8257053	1			T2	2		T12	1		T19	3
all_values[19]	auto[0]	auto[1]	auto[0]	854777	1			T14	2		T20	3		T3	3
all_values[19]	auto[0]	auto[1]	auto[1]	8194570	1			T15	3		T20	2		T3	2
all_values[19]	auto[1]	auto[0]	auto[1]	117593	1			T20	1		T21	1		T105	3
all_values[19]	auto[1]	auto[1]	auto[1]	117197	1			T20	2		T103	1		T105	3
all_values[20]	auto[0]	auto[0]	auto[0]	3299490	1			T1	2		T11	5		T2	5
all_values[20]	auto[0]	auto[0]	auto[1]	8268829	1			T2	1		T14	1		T20	1
all_values[20]	auto[0]	auto[1]	auto[0]	850400	1			T2	1		T15	3		T20	8
all_values[20]	auto[0]	auto[1]	auto[1]	8194752	1			T1	1		T3	1		T4	7
all_values[20]	auto[1]	auto[0]	auto[1]	117175	1			T20	1		T103	1		T105	2
all_values[20]	auto[1]	auto[1]	auto[1]	117448	1			T21	2		T103	1		T105	4
all_values[21]	auto[0]	auto[0]	auto[0]	3300660	1			T1	2		T11	3		T2	4
all_values[21]	auto[0]	auto[0]	auto[1]	8246687	1			T11	2		T2	3		T14	1
all_values[21]	auto[0]	auto[1]	auto[0]	850422	1			T20	3		T19	3		T4	8
all_values[21]	auto[0]	auto[1]	auto[1]	8215618	1			T1	1		T14	2		T20	1
all_values[21]	auto[1]	auto[0]	auto[1]	117276	1			T20	3		T21	2		T105	5
all_values[21]	auto[1]	auto[1]	auto[1]	117431	1			T20	1		T21	2		T103	1
all_values[22]	auto[0]	auto[0]	auto[0]	3290449	1			T1	3		T11	5		T2	5
all_values[22]	auto[0]	auto[0]	auto[1]	8252429	1			T2	2		T12	1		T15	3
all_values[22]	auto[0]	auto[1]	auto[0]	851677	1			T14	2		T20	7		T3	1
all_values[22]	auto[0]	auto[1]	auto[1]	8219029	1			T20	7		T19	3		T73	1
all_values[22]	auto[1]	auto[0]	auto[1]	117601	1			T20	1		T21	2		T103	1
all_values[22]	auto[1]	auto[1]	auto[1]	116909	1			T20	3		T21	2		T105	5
all_values[23]	auto[0]	auto[0]	auto[0]	3299095	1			T1	2		T11	4		T2	5
all_values[23]	auto[0]	auto[0]	auto[1]	8268219	1			T1	1		T11	1		T2	2
all_values[23]	auto[0]	auto[1]	auto[0]	831914	1			T20	1		T19	1		T4	7
all_values[23]	auto[0]	auto[1]	auto[1]	8213991	1			T15	3		T20	1		T19	2
all_values[23]	auto[1]	auto[0]	auto[1]	117788	1			T20	4		T21	2		T103	1
all_values[23]	auto[1]	auto[1]	auto[1]	117087	1			T21	1		T103	1		T105	1
all_values[24]	auto[0]	auto[0]	auto[0]	3304143	1			T1	2		T11	3		T2	6
all_values[24]	auto[0]	auto[0]	auto[1]	8232759	1			T11	2		T2	1		T12	1
all_values[24]	auto[0]	auto[1]	auto[0]	839467	1			T1	1		T20	8		T19	3
all_values[24]	auto[0]	auto[1]	auto[1]	8237375	1			T20	2		T4	6		T77	13
all_values[24]	auto[1]	auto[0]	auto[1]	117726	1			T20	1		T21	1		T105	2
all_values[24]	auto[1]	auto[1]	auto[1]	116624	1			T20	1		T21	3		T105	4
all_values[25]	auto[0]	auto[0]	auto[0]	3299920	1			T1	2		T11	5		T2	6
all_values[25]	auto[0]	auto[0]	auto[1]	8243448	1			T2	1		T12	1		T20	3
all_values[25]	auto[0]	auto[1]	auto[0]	853296	1			T14	1		T20	6		T4	5
all_values[25]	auto[0]	auto[1]	auto[1]	8217004	1			T1	1		T14	1		T15	3
all_values[25]	auto[1]	auto[0]	auto[1]	116775	1			T20	2		T21	1		T103	2
all_values[25]	auto[1]	auto[1]	auto[1]	117651	1			T20	2		T21	2		T103	1
all_values[26]	auto[0]	auto[0]	auto[0]	3297808	1			T1	2		T11	4		T2	6
all_values[26]	auto[0]	auto[0]	auto[1]	8235318	1			T1	1		T11	1		T2	1
all_values[26]	auto[0]	auto[1]	auto[0]	846022	1			T20	7		T3	1		T4	6
all_values[26]	auto[0]	auto[1]	auto[1]	8234470	1			T14	2		T15	3		T20	3
all_values[26]	auto[1]	auto[0]	auto[1]	117729	1			T20	1		T106	1		T107	3
all_values[26]	auto[1]	auto[1]	auto[1]	116747	1			T20	1		T21	2		T105	3
all_values[27]	auto[0]	auto[0]	auto[0]	3303209	1			T1	2		T11	4		T2	6
all_values[27]	auto[0]	auto[0]	auto[1]	8245598	1			T1	1		T11	1		T2	1
all_values[27]	auto[0]	auto[1]	auto[0]	837906	1			T15	3		T20	7		T4	7
all_values[27]	auto[0]	auto[1]	auto[1]	8226114	1			T20	1		T3	2		T4	3
all_values[27]	auto[1]	auto[0]	auto[1]	117620	1			T20	2		T21	1		T105	1
all_values[27]	auto[1]	auto[1]	auto[1]	117647	1			T20	2		T21	1		T103	2
all_values[28]	auto[0]	auto[0]	auto[0]	3295532	1			T1	2		T11	4		T2	5
all_values[28]	auto[0]	auto[0]	auto[1]	8195793	1			T11	1		T2	2		T12	1
all_values[28]	auto[0]	auto[1]	auto[0]	850009	1			T1	1		T15	3		T20	3
all_values[28]	auto[0]	auto[1]	auto[1]	8272514	1			T14	2		T3	3		T4	2
all_values[28]	auto[1]	auto[0]	auto[1]	117568	1			T20	3		T21	2		T105	5
all_values[28]	auto[1]	auto[1]	auto[1]	116678	1			T21	1		T103	1		T105	1
all_values[29]	auto[0]	auto[0]	auto[0]	3284513	1			T1	2		T11	4		T2	5
all_values[29]	auto[0]	auto[0]	auto[1]	8262271	1			T11	1		T2	1		T14	1
all_values[29]	auto[0]	auto[1]	auto[0]	840976	1			T20	3		T4	5		T77	8
all_values[29]	auto[0]	auto[1]	auto[1]	8225556	1			T1	1		T2	1		T20	5
all_values[29]	auto[1]	auto[0]	auto[1]	117797	1			T20	2		T105	2		T104	1
all_values[29]	auto[1]	auto[1]	auto[1]	116981	1			T20	1		T21	1		T103	1
all_values[30]	auto[0]	auto[0]	auto[0]	3296120	1			T1	2		T11	4		T2	5
all_values[30]	auto[0]	auto[0]	auto[1]	8274377	1			T11	1		T2	1		T14	3
all_values[30]	auto[0]	auto[1]	auto[0]	848455	1			T1	1		T15	3		T20	2
all_values[30]	auto[0]	auto[1]	auto[1]	8194715	1			T2	1		T20	10		T3	2
all_values[30]	auto[1]	auto[0]	auto[1]	117858	1			T20	2		T21	1		T105	2
all_values[30]	auto[1]	auto[1]	auto[1]	116569	1			T20	3		T21	2		T103	2
all_values[31]	auto[0]	auto[0]	auto[0]	3296359	1			T1	2		T11	5		T2	7
all_values[31]	auto[0]	auto[0]	auto[1]	8235372	1			T1	1		T12	1		T20	4
all_values[31]	auto[0]	auto[1]	auto[0]	855610	1			T20	2		T3	2		T4	9
all_values[31]	auto[0]	auto[1]	auto[1]	8226464	1			T15	3		T20	1		T77	22
all_values[31]	auto[1]	auto[0]	auto[1]	117383	1			T20	4		T103	1		T105	2
all_values[31]	auto[1]	auto[1]	auto[1]	116906	1			T21	3		T103	1		T105	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal