Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[1]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[2]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[3]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[4]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[5]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[6]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[7]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[8]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[9]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[10]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[11]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[12]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[13]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[14]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[15]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[16]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[17]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[18]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[19]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[20]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[21]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[22]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[23]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[24]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[25]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[26]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[27]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[28]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[29]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[30]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[31]	20637368	1			T1	3		T11	6		T2	7

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

408343714

1

T1

96

T11

192

T2

224

auto[1]

252052062

1

T40

6646

T41

20691

T42

3742

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

526367754

1

T1

96

T11

192

T2

224

auto[1]

134028022

1

T40

10383

T41

12824

T42

1985

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

486481669

1

T1

96

T11

192

T2

224

auto[1]

173914107

1

T40

10648

T41

13135

T42

2160

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	7790532	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	5305151	1			T40	43		T41	258		T42	78
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	2103827	1			T40	132		T41	150		T42	32
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2866463	1			T40	159		T42	26		T52	112
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	478793	1			T41	248		T55	109		T58	81
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	2092602	1			T40	152		T41	191		T42	45
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	7770004	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	5323951	1			T40	46		T41	252		T42	96
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	2110775	1			T40	167		T41	208		T42	56
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2860293	1			T40	166		T42	18		T52	83
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	476715	1			T41	176		T55	123		T58	54
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	2095630	1			T40	174		T41	200		T42	37
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	7781303	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	5316963	1			T40	32		T41	224		T42	84
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	2104054	1			T40	168		T41	202		T42	36
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2866892	1			T40	183		T42	36		T52	90
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	475664	1			T41	178		T55	92		T58	86
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	2092492	1			T40	152		T41	226		T42	20
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	7770092	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	5322960	1			T40	33		T41	255		T42	81
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	2103463	1			T40	166		T41	194		T42	26
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2877303	1			T40	133		T42	24		T52	94
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	479067	1			T41	180		T55	120		T58	80
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	2084483	1			T40	206		T41	215		T42	55
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	7786246	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	5309582	1			T40	39		T41	215		T42	89
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	2106330	1			T40	154		T41	268		T42	29
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2872358	1			T40	194		T42	24		T52	72
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	477706	1			T41	191		T55	124		T58	74
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	2085146	1			T40	154		T41	168		T42	40
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	7784517	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	5318871	1			T40	45		T41	247		T42	84
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	2107654	1			T40	181		T41	190		T42	23
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2867289	1			T40	160		T42	58		T52	86
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	476556	1			T41	200		T55	142		T58	73
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	2082481	1			T40	168		T41	203		T42	30
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	7793544	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	5303482	1			T40	40		T41	211		T42	89
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	2110392	1			T40	178		T41	196		T42	18
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2867503	1			T40	118		T42	32		T52	125
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	476947	1			T41	183		T55	118		T58	69
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	2085500	1			T40	174		T41	256		T42	43
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	7772674	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	5320346	1			T40	41		T41	217		T42	78
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	2111544	1			T40	148		T41	206		T42	15
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2861197	1			T40	182		T42	58		T52	76
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	481631	1			T41	192		T55	110		T58	91
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	2089976	1			T40	181		T41	223		T42	26
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	7770130	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	5315626	1			T40	48		T41	255		T42	88
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	2106289	1			T40	112		T41	186		T42	23
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2875290	1			T40	198		T42	50		T52	100
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	476902	1			T41	198		T55	120		T58	80
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	2093131	1			T40	145		T41	202		T42	22
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	7791129	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	5312345	1			T40	55		T41	265		T42	81
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	2108626	1			T40	144		T41	166		T42	34
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2864388	1			T40	162		T42	41		T52	100
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	479011	1			T41	218		T55	82		T58	76
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	2081869	1			T40	185		T41	194		T42	38
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	7785676	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	5317625	1			T40	45		T41	247		T42	84
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	2106349	1			T40	172		T41	186		T42	22
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2866866	1			T40	147		T42	53		T52	100
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	475875	1			T41	202		T55	120		T58	71
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	2084977	1			T40	184		T41	210		T42	38
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	7783081	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	5314567	1			T40	40		T41	224		T42	86
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	2107405	1			T40	158		T41	172		T42	34
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2868735	1			T40	172		T42	18		T52	63
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	478772	1			T41	183		T55	108		T58	77
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	2084808	1			T40	159		T41	260		T42	38
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	7774058	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	5311560	1			T40	36		T41	223		T42	94
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	2107264	1			T40	179		T41	200		T42	48
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2872980	1			T40	178		T42	19		T52	82
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	479655	1			T41	224		T55	90		T58	120
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	2091851	1			T40	130		T41	200		T42	20
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	7794017	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	5306243	1			T40	46		T41	218		T42	87
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	2110487	1			T40	181		T41	206		T42	30
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2860059	1			T40	152		T42	30		T52	110
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	478320	1			T41	196		T55	136		T58	89
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	2088242	1			T40	168		T41	223		T42	38
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	7787820	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	5309273	1			T40	44		T41	206		T42	70
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	2108645	1			T40	172		T41	228		T42	26
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2863337	1			T40	190		T42	32		T52	70
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	477829	1			T41	192		T55	136		T58	83
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	2090464	1			T40	137		T41	212		T42	51
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	7777123	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	5317248	1			T40	29		T41	230		T42	67
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	2104255	1			T40	162		T41	197		T42	20
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2871802	1			T40	162		T42	39		T52	100
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	478046	1			T41	180		T55	87		T58	74
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	2088894	1			T40	158		T41	232		T42	32
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	7784600	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	5313881	1			T40	41		T41	265		T42	86
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	2095550	1			T40	179		T41	184		T42	32
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2878392	1			T40	134		T42	20		T52	72
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	480778	1			T41	216		T55	114		T58	72
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	2084167	1			T40	178		T41	168		T42	24
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	7780795	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	5319005	1			T40	40		T41	269		T42	91
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	2099601	1			T40	178		T41	172		T42	31
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2877867	1			T40	166		T42	34		T52	80
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	477512	1			T41	214		T55	99		T58	84
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	2082588	1			T40	146		T41	193		T42	38
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	7793153	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	5309041	1			T40	42		T41	187		T42	84
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	2099704	1			T40	134		T41	216		T42	42
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2873341	1			T40	169		T42	26		T52	88
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	480331	1			T41	186		T55	116		T58	89
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	2081798	1			T40	162		T41	249		T42	30
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	7786005	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	5313322	1			T40	37		T41	244		T42	93
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	2102220	1			T40	122		T41	172		T42	25
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2874431	1			T40	185		T42	40		T52	98
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	476771	1			T41	232		T55	143		T58	76
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	2084619	1			T40	190		T41	192		T42	32
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	7801635	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	5300484	1			T40	40		T41	236		T42	80
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	2096882	1			T40	118		T41	220		T42	36
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2875405	1			T40	192		T42	16		T52	90
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	481332	1			T41	204		T55	102		T58	85
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	2081630	1			T40	171		T41	184		T42	48
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	7787703	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	5322720	1			T40	44		T41	214		T42	73
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	2100875	1			T40	182		T41	198		T42	32
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2869747	1			T40	140		T42	39		T52	100
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	478555	1			T41	218		T55	90		T58	72
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	2077768	1			T40	171		T41	206		T42	28
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	7783561	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	5314687	1			T40	38		T41	258		T42	70
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	2098554	1			T40	140		T41	184		T42	21
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2879158	1			T40	179		T42	40		T52	108
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	480392	1			T41	183		T55	82		T58	76
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	2081016	1			T40	168		T41	212		T42	36
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	7791413	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	5309933	1			T40	43		T41	249		T42	75
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	2102606	1			T40	155		T41	188		T42	21
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2875037	1			T40	186		T42	44		T52	94
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	476673	1			T41	211		T55	90		T58	77
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	2081706	1			T40	158		T41	188		T42	24
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	7785280	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	5314297	1			T40	42		T41	237		T42	95
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	2096073	1			T40	150		T41	174		T42	30
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2874228	1			T40	158		T42	29		T52	98
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	481071	1			T41	225		T55	89		T58	92
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	2086419	1			T40	142		T41	210		T42	34
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	7786375	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	5307691	1			T40	43		T41	222		T42	91
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	2105623	1			T40	154		T41	225		T42	34
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2880025	1			T40	198		T42	32		T52	76
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	477688	1			T41	200		T55	128		T58	62
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	2079966	1			T40	166		T41	184		T42	19
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	7797796	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	5304269	1			T40	47		T41	238		T42	73
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	2103560	1			T40	146		T41	209		T42	34
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2873205	1			T40	166		T42	34		T52	90
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	477888	1			T41	208		T55	125		T58	71
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	2080650	1			T40	182		T41	184		T42	26
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	7792641	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	5307090	1			T40	46		T41	232		T42	82
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	2099430	1			T40	176		T41	196		T42	30
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2876260	1			T40	163		T42	33		T52	86
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	479818	1			T41	218		T55	121		T58	84
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	2082129	1			T40	164		T41	197		T42	26
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	7796212	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	5313617	1			T40	37		T41	254		T42	87
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	2102995	1			T40	155		T41	148		T42	20
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2869032	1			T40	166		T42	38		T52	79
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	481370	1			T41	248		T55	118		T58	82
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	2074142	1			T40	158		T41	192		T42	33
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	7791363	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	5317676	1			T40	32		T41	217		T42	84
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	2104407	1			T40	176		T41	212		T42	22
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2870977	1			T40	168		T42	32		T52	94
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	476294	1			T41	203		T55	134		T58	89
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	2076651	1			T40	176		T41	216		T42	27
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	7779119	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	5319981	1			T40	49		T41	249		T42	88
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	2097313	1			T40	140		T41	186		T42	21
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2880176	1			T40	154		T42	44		T52	90
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	479193	1			T41	201		T55	113		T58	76
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	2081586	1			T40	209		T41	206		T42	36
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	7787761	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	5314844	1			T40	49		T41	238		T42	92
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	2093228	1			T40	190		T41	176		T42	20
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2880340	1			T40	154		T42	39		T52	96
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	478534	1			T41	218		T55	114		T58	84
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	2082661	1			T40	146		T41	213		T42	28

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal