Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[1]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[2]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[3]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[4]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[5]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[6]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[7]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[8]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[9]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[10]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[11]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[12]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[13]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[14]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[15]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[16]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[17]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[18]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[19]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[20]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[21]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[22]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[23]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[24]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[25]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[26]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[27]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[28]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[29]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[30]	20637368	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[31]	20637368	1			T1	3		T11	6		T2	7

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

408343714

1

T1

96

T11

192

T2

224

auto[1]

252052062

1

T40

6646

T41

20691

T42

3742

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

408333575

1

T1

87

T11

175

T2

195

auto[1]

252062201

1

T1

9

T11

17

T2

29

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	12386747	1			T1	2		T11	5		T2	6
bins_for_gpio_bits[0]	auto[0]	auto[1]	373758	1			T40	44		T41	42		T42	9
bins_for_gpio_bits[0]	auto[1]	auto[0]	374075	1			T1	1		T11	1		T2	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	7502788	1			T40	151		T41	655		T42	114
bins_for_gpio_bits[1]	auto[0]	auto[0]	12366270	1			T1	3		T11	5		T2	7
bins_for_gpio_bits[1]	auto[0]	auto[1]	374515	1			T40	46		T41	57		T42	8
bins_for_gpio_bits[1]	auto[1]	auto[0]	374802	1			T11	1		T15	1		T3	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	7521781	1			T40	174		T41	571		T42	125
bins_for_gpio_bits[2]	auto[0]	auto[0]	12377381	1			T1	3		T11	6		T2	6
bins_for_gpio_bits[2]	auto[0]	auto[1]	374550	1			T40	40		T41	52		T42	8
bins_for_gpio_bits[2]	auto[1]	auto[0]	374868	1			T2	1		T12	1		T3	3
bins_for_gpio_bits[2]	auto[1]	auto[1]	7510569	1			T40	144		T41	576		T42	96
bins_for_gpio_bits[3]	auto[0]	auto[0]	12376296	1			T1	3		T11	6		T2	5
bins_for_gpio_bits[3]	auto[0]	auto[1]	374244	1			T40	43		T41	48		T42	7
bins_for_gpio_bits[3]	auto[1]	auto[0]	374562	1			T2	2		T14	3		T15	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	7512266	1			T40	196		T41	602		T42	129
bins_for_gpio_bits[4]	auto[0]	auto[0]	12391052	1			T1	2		T11	6		T2	6
bins_for_gpio_bits[4]	auto[0]	auto[1]	373521	1			T40	41		T41	49		T42	9
bins_for_gpio_bits[4]	auto[1]	auto[0]	373882	1			T1	1		T2	1		T12	2
bins_for_gpio_bits[4]	auto[1]	auto[1]	7498913	1			T40	152		T41	525		T42	120
bins_for_gpio_bits[5]	auto[0]	auto[0]	12385555	1			T1	3		T11	5		T2	6
bins_for_gpio_bits[5]	auto[0]	auto[1]	373606	1			T40	47		T41	50		T42	8
bins_for_gpio_bits[5]	auto[1]	auto[0]	373905	1			T11	1		T2	1		T12	2
bins_for_gpio_bits[5]	auto[1]	auto[1]	7504302	1			T40	166		T41	600		T42	106
bins_for_gpio_bits[6]	auto[0]	auto[0]	12396695	1			T1	3		T11	5		T2	6
bins_for_gpio_bits[6]	auto[0]	auto[1]	374436	1			T40	41		T41	45		T42	5
bins_for_gpio_bits[6]	auto[1]	auto[0]	374744	1			T11	1		T2	1		T14	3
bins_for_gpio_bits[6]	auto[1]	auto[1]	7491493	1			T40	173		T41	605		T42	127
bins_for_gpio_bits[7]	auto[0]	auto[0]	12371416	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[7]	auto[0]	auto[1]	373655	1			T40	45		T41	48		T42	7
bins_for_gpio_bits[7]	auto[1]	auto[0]	373999	1			T14	3		T15	1		T19	2
bins_for_gpio_bits[7]	auto[1]	auto[1]	7518298	1			T40	177		T41	584		T42	97
bins_for_gpio_bits[8]	auto[0]	auto[0]	12376439	1			T1	3		T11	5		T2	7
bins_for_gpio_bits[8]	auto[0]	auto[1]	374964	1			T40	38		T41	47		T42	9
bins_for_gpio_bits[8]	auto[1]	auto[0]	375270	1			T11	1		T14	1		T3	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	7510695	1			T40	155		T41	608		T42	101
bins_for_gpio_bits[9]	auto[0]	auto[0]	12390364	1			T1	3		T11	6		T2	6
bins_for_gpio_bits[9]	auto[0]	auto[1]	373453	1			T40	48		T41	45		T42	11
bins_for_gpio_bits[9]	auto[1]	auto[0]	373779	1			T2	1		T14	1		T15	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	7499772	1			T40	192		T41	632		T42	108
bins_for_gpio_bits[10]	auto[0]	auto[0]	12385371	1			T1	2		T11	6		T2	7
bins_for_gpio_bits[10]	auto[0]	auto[1]	373188	1			T40	45		T41	47		T42	10
bins_for_gpio_bits[10]	auto[1]	auto[0]	373520	1			T1	1		T14	1		T15	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	7505289	1			T40	184		T41	612		T42	112
bins_for_gpio_bits[11]	auto[0]	auto[0]	12385054	1			T1	3		T11	5		T2	5
bins_for_gpio_bits[11]	auto[0]	auto[1]	373824	1			T40	41		T41	51		T42	8
bins_for_gpio_bits[11]	auto[1]	auto[0]	374167	1			T11	1		T2	2		T12	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	7504323	1			T40	158		T41	616		T42	116
bins_for_gpio_bits[12]	auto[0]	auto[0]	12379458	1			T1	3		T11	6		T2	5
bins_for_gpio_bits[12]	auto[0]	auto[1]	374528	1			T40	34		T41	53		T42	7
bins_for_gpio_bits[12]	auto[1]	auto[0]	374844	1			T2	2		T12	2		T14	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	7508538	1			T40	132		T41	594		T42	107
bins_for_gpio_bits[13]	auto[0]	auto[0]	12390317	1			T1	3		T11	6		T2	5
bins_for_gpio_bits[13]	auto[0]	auto[1]	373934	1			T40	46		T41	53		T42	10
bins_for_gpio_bits[13]	auto[1]	auto[0]	374246	1			T2	2		T3	2		T4	8
bins_for_gpio_bits[13]	auto[1]	auto[1]	7498871	1			T40	168		T41	584		T42	115
bins_for_gpio_bits[14]	auto[0]	auto[0]	12384853	1			T1	3		T11	5		T2	6
bins_for_gpio_bits[14]	auto[0]	auto[1]	374625	1			T40	37		T41	47		T42	10
bins_for_gpio_bits[14]	auto[1]	auto[0]	374949	1			T11	1		T2	1		T12	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	7502941	1			T40	144		T41	563		T42	111
bins_for_gpio_bits[15]	auto[0]	auto[0]	12378255	1			T1	3		T11	5		T2	5
bins_for_gpio_bits[15]	auto[0]	auto[1]	374565	1			T40	39		T41	54		T42	8
bins_for_gpio_bits[15]	auto[1]	auto[0]	374925	1			T11	1		T2	2		T3	3
bins_for_gpio_bits[15]	auto[1]	auto[1]	7509623	1			T40	148		T41	588		T42	91
bins_for_gpio_bits[16]	auto[0]	auto[0]	12384341	1			T1	3		T11	5		T2	6
bins_for_gpio_bits[16]	auto[0]	auto[1]	373841	1			T40	42		T41	51		T42	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	374201	1			T11	1		T2	1		T14	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	7504985	1			T40	177		T41	598		T42	103
bins_for_gpio_bits[17]	auto[0]	auto[0]	12383511	1			T1	2		T11	5		T2	7
bins_for_gpio_bits[17]	auto[0]	auto[1]	374456	1			T40	39		T41	42		T42	11
bins_for_gpio_bits[17]	auto[1]	auto[0]	374752	1			T1	1		T11	1		T14	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	7504649	1			T40	147		T41	634		T42	118
bins_for_gpio_bits[18]	auto[0]	auto[0]	12392127	1			T1	3		T11	4		T2	6
bins_for_gpio_bits[18]	auto[0]	auto[1]	373770	1			T40	37		T41	48		T42	10
bins_for_gpio_bits[18]	auto[1]	auto[0]	374071	1			T11	2		T2	1		T14	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	7497400	1			T40	167		T41	574		T42	104
bins_for_gpio_bits[19]	auto[0]	auto[0]	12387651	1			T1	2		T11	6		T2	7
bins_for_gpio_bits[19]	auto[0]	auto[1]	374695	1			T40	46		T41	43		T42	10
bins_for_gpio_bits[19]	auto[1]	auto[0]	375005	1			T1	1		T12	1		T4	7
bins_for_gpio_bits[19]	auto[1]	auto[1]	7500017	1			T40	181		T41	625		T42	115
bins_for_gpio_bits[20]	auto[0]	auto[0]	12399878	1			T1	2		T11	6		T2	6
bins_for_gpio_bits[20]	auto[0]	auto[1]	373718	1			T40	40		T41	56		T42	9
bins_for_gpio_bits[20]	auto[1]	auto[0]	374044	1			T1	1		T2	1		T12	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	7489728	1			T40	171		T41	568		T42	119
bins_for_gpio_bits[21]	auto[0]	auto[0]	12384493	1			T1	3		T11	5		T2	6
bins_for_gpio_bits[21]	auto[0]	auto[1]	373557	1			T40	42		T41	49		T42	9
bins_for_gpio_bits[21]	auto[1]	auto[0]	373832	1			T11	1		T2	1		T15	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	7505486	1			T40	173		T41	589		T42	92
bins_for_gpio_bits[22]	auto[0]	auto[0]	12386753	1			T1	3		T11	6		T2	6
bins_for_gpio_bits[22]	auto[0]	auto[1]	374203	1			T40	41		T41	49		T42	9
bins_for_gpio_bits[22]	auto[1]	auto[0]	374520	1			T2	1		T14	1		T15	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	7501892	1			T40	165		T41	604		T42	97
bins_for_gpio_bits[23]	auto[0]	auto[0]	12394099	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[23]	auto[0]	auto[1]	374624	1			T40	42		T41	55		T42	6
bins_for_gpio_bits[23]	auto[1]	auto[0]	374957	1			T12	1		T15	3		T19	2
bins_for_gpio_bits[23]	auto[1]	auto[1]	7493688	1			T40	159		T41	593		T42	93
bins_for_gpio_bits[24]	auto[0]	auto[0]	12380674	1			T1	3		T11	5		T2	6
bins_for_gpio_bits[24]	auto[0]	auto[1]	374603	1			T40	29		T41	42		T42	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	374907	1			T11	1		T2	1		T12	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	7507184	1			T40	155		T41	630		T42	119
bins_for_gpio_bits[25]	auto[0]	auto[0]	12397572	1			T1	2		T11	6		T2	5
bins_for_gpio_bits[25]	auto[0]	auto[1]	374166	1			T40	38		T41	49		T42	4
bins_for_gpio_bits[25]	auto[1]	auto[0]	374451	1			T1	1		T2	2		T14	3
bins_for_gpio_bits[25]	auto[1]	auto[1]	7491179	1			T40	171		T41	557		T42	106
bins_for_gpio_bits[26]	auto[0]	auto[0]	12399339	1			T1	2		T11	5		T2	7
bins_for_gpio_bits[26]	auto[0]	auto[1]	374941	1			T40	44		T41	53		T42	8
bins_for_gpio_bits[26]	auto[1]	auto[0]	375222	1			T1	1		T11	1		T12	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	7487866	1			T40	185		T41	577		T42	91
bins_for_gpio_bits[27]	auto[0]	auto[0]	12393551	1			T1	2		T11	6		T2	6
bins_for_gpio_bits[27]	auto[0]	auto[1]	374472	1			T40	42		T41	46		T42	7
bins_for_gpio_bits[27]	auto[1]	auto[0]	374780	1			T1	1		T2	1		T15	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	7494565	1			T40	168		T41	601		T42	101
bins_for_gpio_bits[28]	auto[0]	auto[0]	12394205	1			T1	3		T11	6		T2	7
bins_for_gpio_bits[28]	auto[0]	auto[1]	373730	1			T40	34		T41	42		T42	4
bins_for_gpio_bits[28]	auto[1]	auto[0]	374034	1			T12	1		T14	1		T3	1
bins_for_gpio_bits[28]	auto[1]	auto[1]	7495399	1			T40	161		T41	652		T42	116
bins_for_gpio_bits[29]	auto[0]	auto[0]	12392856	1			T1	3		T11	5		T2	6
bins_for_gpio_bits[29]	auto[0]	auto[1]	373556	1			T40	46		T41	46		T42	6
bins_for_gpio_bits[29]	auto[1]	auto[0]	373891	1			T11	1		T2	1		T14	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	7497065	1			T40	162		T41	590		T42	105
bins_for_gpio_bits[30]	auto[0]	auto[0]	12382663	1			T1	3		T11	5		T2	7
bins_for_gpio_bits[30]	auto[0]	auto[1]	373622	1			T40	38		T41	47		T42	11
bins_for_gpio_bits[30]	auto[1]	auto[0]	373945	1			T11	1		T14	2		T15	3
bins_for_gpio_bits[30]	auto[1]	auto[1]	7507138	1			T40	220		T41	609		T42	113
bins_for_gpio_bits[31]	auto[0]	auto[0]	12386389	1			T1	3		T11	6		T2	5
bins_for_gpio_bits[31]	auto[0]	auto[1]	374630	1			T40	39		T41	39		T42	9
bins_for_gpio_bits[31]	auto[1]	auto[0]	374940	1			T2	2		T12	1		T15	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	7501409	1			T40	156		T41	630		T42	111