Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11642172 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
6 |
| auto[1] |
9205922 |
1 |
|
|
T2 |
1 |
|
T14 |
2 |
|
T20 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19652012 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1196082 |
1 |
|
|
T14 |
1 |
|
T7 |
1 |
|
T32 |
27818 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11625675 |
1 |
|
|
T1 |
3 |
|
T11 |
4 |
|
T2 |
6 |
| auto[1] |
9222419 |
1 |
|
|
T11 |
1 |
|
T2 |
1 |
|
T12 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4016437 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T3 |
3 |
| auto[1] |
auto[0] |
auto[1] |
598770 |
1 |
|
|
T32 |
14207 |
|
T70 |
16715 |
|
T108 |
84 |
| auto[1] |
auto[1] |
auto[0] |
4009900 |
1 |
|
|
T2 |
1 |
|
T14 |
1 |
|
T4 |
3 |
| auto[1] |
auto[1] |
auto[1] |
597312 |
1 |
|
|
T14 |
1 |
|
T7 |
1 |
|
T32 |
13611 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11698520 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9149574 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19664074 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1184020 |
1 |
|
|
T3 |
1 |
|
T77 |
5 |
|
T94 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11683487 |
1 |
|
|
T1 |
2 |
|
T11 |
4 |
|
T2 |
6 |
| auto[1] |
9164607 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4006203 |
1 |
|
|
T11 |
1 |
|
T2 |
1 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
594241 |
1 |
|
|
T94 |
4 |
|
T32 |
14264 |
|
T43 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3974384 |
1 |
|
|
T1 |
1 |
|
T19 |
3 |
|
T3 |
4 |
| auto[1] |
auto[1] |
auto[1] |
589779 |
1 |
|
|
T3 |
1 |
|
T77 |
5 |
|
T94 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11684050 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9164044 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19661638 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1186456 |
1 |
|
|
T3 |
1 |
|
T7 |
1 |
|
T94 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11675884 |
1 |
|
|
T1 |
2 |
|
T11 |
4 |
|
T2 |
6 |
| auto[1] |
9172210 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4009048 |
1 |
|
|
T11 |
1 |
|
T2 |
1 |
|
T12 |
1 |
| auto[1] |
auto[0] |
auto[1] |
596538 |
1 |
|
|
T3 |
1 |
|
T7 |
1 |
|
T94 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3976706 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T4 |
5 |
| auto[1] |
auto[1] |
auto[1] |
589918 |
1 |
|
|
T32 |
12631 |
|
T43 |
1 |
|
T100 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11654390 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
6 |
| auto[1] |
9193704 |
1 |
|
|
T2 |
1 |
|
T20 |
2 |
|
T19 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19664819 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1183275 |
1 |
|
|
T77 |
3 |
|
T92 |
1 |
|
T94 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11705932 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
5 |
| auto[1] |
9142162 |
1 |
|
|
T2 |
2 |
|
T12 |
2 |
|
T14 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3973861 |
1 |
|
|
T2 |
1 |
|
T12 |
2 |
|
T14 |
2 |
| auto[1] |
auto[0] |
auto[1] |
591011 |
1 |
|
|
T32 |
14490 |
|
T100 |
4 |
|
T70 |
16642 |
| auto[1] |
auto[1] |
auto[0] |
3985026 |
1 |
|
|
T2 |
1 |
|
T19 |
3 |
|
T3 |
2 |
| auto[1] |
auto[1] |
auto[1] |
592264 |
1 |
|
|
T77 |
3 |
|
T92 |
1 |
|
T94 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11665643 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
6 |
| auto[1] |
9182451 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T20 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19660406 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1187688 |
1 |
|
|
T19 |
1 |
|
T77 |
5 |
|
T78 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11675572 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
6 |
| auto[1] |
9172522 |
1 |
|
|
T2 |
1 |
|
T12 |
1 |
|
T19 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3992318 |
1 |
|
|
T12 |
1 |
|
T3 |
2 |
|
T4 |
6 |
| auto[1] |
auto[0] |
auto[1] |
594028 |
1 |
|
|
T77 |
2 |
|
T32 |
13673 |
|
T100 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3992516 |
1 |
|
|
T2 |
1 |
|
T19 |
2 |
|
T4 |
5 |
| auto[1] |
auto[1] |
auto[1] |
593660 |
1 |
|
|
T19 |
1 |
|
T77 |
3 |
|
T78 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11652100 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9195994 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19654557 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1193537 |
1 |
|
|
T77 |
4 |
|
T94 |
2 |
|
T95 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11621915 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
6 |
| auto[1] |
9226179 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T12 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4031222 |
1 |
|
|
T2 |
1 |
|
T12 |
1 |
|
T4 |
5 |
| auto[1] |
auto[0] |
auto[1] |
599154 |
1 |
|
|
T77 |
4 |
|
T32 |
14025 |
|
T43 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4001420 |
1 |
|
|
T1 |
1 |
|
T15 |
3 |
|
T4 |
5 |
| auto[1] |
auto[1] |
auto[1] |
594383 |
1 |
|
|
T94 |
2 |
|
T95 |
3 |
|
T32 |
12838 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11671520 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9176574 |
1 |
|
|
T14 |
2 |
|
T15 |
3 |
|
T19 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19658203 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1189891 |
1 |
|
|
T19 |
1 |
|
T3 |
1 |
|
T94 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11657685 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
6 |
| auto[1] |
9190409 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4011123 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
| auto[1] |
auto[0] |
auto[1] |
596717 |
1 |
|
|
T3 |
1 |
|
T94 |
1 |
|
T32 |
13028 |
| auto[1] |
auto[1] |
auto[0] |
3989395 |
1 |
|
|
T14 |
2 |
|
T15 |
3 |
|
T19 |
2 |
| auto[1] |
auto[1] |
auto[1] |
593174 |
1 |
|
|
T19 |
1 |
|
T32 |
13162 |
|
T100 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11682467 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9165627 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T20 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19659326 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1188768 |
1 |
|
|
T77 |
3 |
|
T94 |
3 |
|
T32 |
27515 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11661675 |
1 |
|
|
T1 |
2 |
|
T11 |
4 |
|
T2 |
6 |
| auto[1] |
9186419 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4010055 |
1 |
|
|
T11 |
1 |
|
T2 |
1 |
|
T12 |
1 |
| auto[1] |
auto[0] |
auto[1] |
596194 |
1 |
|
|
T77 |
1 |
|
T94 |
3 |
|
T32 |
14176 |
| auto[1] |
auto[1] |
auto[0] |
3987596 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T19 |
3 |
| auto[1] |
auto[1] |
auto[1] |
592574 |
1 |
|
|
T77 |
2 |
|
T32 |
13339 |
|
T70 |
16252 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11664250 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
6 |
| auto[1] |
9183844 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19658350 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1189744 |
1 |
|
|
T95 |
3 |
|
T32 |
27923 |
|
T43 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11657652 |
1 |
|
|
T1 |
3 |
|
T11 |
4 |
|
T2 |
6 |
| auto[1] |
9190442 |
1 |
|
|
T11 |
1 |
|
T2 |
1 |
|
T14 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4009479 |
1 |
|
|
T11 |
1 |
|
T4 |
7 |
|
T22 |
5 |
| auto[1] |
auto[0] |
auto[1] |
597028 |
1 |
|
|
T95 |
1 |
|
T32 |
14375 |
|
T43 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3991219 |
1 |
|
|
T2 |
1 |
|
T14 |
2 |
|
T15 |
3 |
| auto[1] |
auto[1] |
auto[1] |
592716 |
1 |
|
|
T95 |
2 |
|
T32 |
13548 |
|
T44 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11672950 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
6 |
| auto[1] |
9175144 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T20 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19654075 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1194019 |
1 |
|
|
T94 |
2 |
|
T32 |
27962 |
|
T100 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11634355 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
5 |
| auto[1] |
9213739 |
1 |
|
|
T2 |
2 |
|
T12 |
2 |
|
T14 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4012657 |
1 |
|
|
T2 |
1 |
|
T12 |
2 |
|
T14 |
2 |
| auto[1] |
auto[0] |
auto[1] |
596947 |
1 |
|
|
T94 |
2 |
|
T32 |
13682 |
|
T100 |
4 |
| auto[1] |
auto[1] |
auto[0] |
4007063 |
1 |
|
|
T2 |
1 |
|
T19 |
3 |
|
T4 |
2 |
| auto[1] |
auto[1] |
auto[1] |
597072 |
1 |
|
|
T32 |
14280 |
|
T100 |
3 |
|
T70 |
17107 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11674359 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9173735 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19662829 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1185265 |
1 |
|
|
T3 |
1 |
|
T94 |
4 |
|
T32 |
26380 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11681045 |
1 |
|
|
T1 |
3 |
|
T11 |
4 |
|
T2 |
7 |
| auto[1] |
9167049 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T14 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3997206 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T3 |
1 |
| auto[1] |
auto[0] |
auto[1] |
593539 |
1 |
|
|
T3 |
1 |
|
T32 |
13259 |
|
T100 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3984578 |
1 |
|
|
T14 |
2 |
|
T4 |
5 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[1] |
591726 |
1 |
|
|
T94 |
4 |
|
T32 |
13121 |
|
T100 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11681550 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9166544 |
1 |
|
|
T14 |
2 |
|
T15 |
3 |
|
T20 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19665742 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1182352 |
1 |
|
|
T94 |
3 |
|
T32 |
26112 |
|
T100 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11699699 |
1 |
|
|
T1 |
2 |
|
T11 |
4 |
|
T2 |
6 |
| auto[1] |
9148395 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3989940 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T2 |
1 |
| auto[1] |
auto[0] |
auto[1] |
593084 |
1 |
|
|
T94 |
3 |
|
T32 |
13305 |
|
T100 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3976103 |
1 |
|
|
T14 |
2 |
|
T15 |
3 |
|
T3 |
5 |
| auto[1] |
auto[1] |
auto[1] |
589268 |
1 |
|
|
T32 |
12807 |
|
T100 |
1 |
|
T70 |
17895 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669418 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
6 |
| auto[1] |
9178676 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19663383 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1184711 |
1 |
|
|
T32 |
26325 |
|
T43 |
1 |
|
T100 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11690367 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9157727 |
1 |
|
|
T12 |
1 |
|
T19 |
3 |
|
T3 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3992996 |
1 |
|
|
T12 |
1 |
|
T3 |
3 |
|
T4 |
9 |
| auto[1] |
auto[0] |
auto[1] |
593556 |
1 |
|
|
T32 |
13388 |
|
T43 |
1 |
|
T70 |
17003 |
| auto[1] |
auto[1] |
auto[0] |
3980020 |
1 |
|
|
T19 |
3 |
|
T4 |
3 |
|
T78 |
3 |
| auto[1] |
auto[1] |
auto[1] |
591155 |
1 |
|
|
T32 |
12937 |
|
T100 |
2 |
|
T44 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11685494 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
6 |
| auto[1] |
9162600 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19656844 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1191250 |
1 |
|
|
T3 |
1 |
|
T94 |
4 |
|
T95 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11653513 |
1 |
|
|
T1 |
2 |
|
T11 |
4 |
|
T2 |
6 |
| auto[1] |
9194581 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4008999 |
1 |
|
|
T11 |
1 |
|
T2 |
1 |
|
T12 |
1 |
| auto[1] |
auto[0] |
auto[1] |
596555 |
1 |
|
|
T32 |
13899 |
|
T44 |
1 |
|
T70 |
16829 |
| auto[1] |
auto[1] |
auto[0] |
3994332 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
5 |
| auto[1] |
auto[1] |
auto[1] |
594695 |
1 |
|
|
T3 |
1 |
|
T94 |
4 |
|
T95 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11664623 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9183471 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T20 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19656942 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1191152 |
1 |
|
|
T3 |
1 |
|
T32 |
27684 |
|
T43 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11646440 |
1 |
|
|
T1 |
2 |
|
T11 |
4 |
|
T2 |
7 |
| auto[1] |
9201654 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T12 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4005027 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T15 |
3 |
| auto[1] |
auto[0] |
auto[1] |
594468 |
1 |
|
|
T3 |
1 |
|
T32 |
14348 |
|
T43 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4005475 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T19 |
3 |
| auto[1] |
auto[1] |
auto[1] |
596684 |
1 |
|
|
T32 |
13336 |
|
T70 |
18092 |
|
T108 |
99 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11660479 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9187615 |
1 |
|
|
T14 |
2 |
|
T20 |
17 |
|
T19 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19659765 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1188329 |
1 |
|
|
T15 |
1 |
|
T3 |
1 |
|
T79 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11655593 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
6 |
| auto[1] |
9192501 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T12 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4015789 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
597221 |
1 |
|
|
T15 |
1 |
|
T32 |
14741 |
|
T43 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3988383 |
1 |
|
|
T19 |
3 |
|
T3 |
1 |
|
T4 |
3 |
| auto[1] |
auto[1] |
auto[1] |
591108 |
1 |
|
|
T3 |
1 |
|
T79 |
1 |
|
T32 |
12669 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11685102 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9162992 |
1 |
|
|
T15 |
3 |
|
T20 |
2 |
|
T19 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19664535 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1183559 |
1 |
|
|
T19 |
1 |
|
T77 |
6 |
|
T94 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11679562 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
5 |
| auto[1] |
9168532 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T12 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4033008 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
598871 |
1 |
|
|
T77 |
6 |
|
T32 |
14327 |
|
T100 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3951965 |
1 |
|
|
T15 |
3 |
|
T19 |
2 |
|
T4 |
2 |
| auto[1] |
auto[1] |
auto[1] |
584688 |
1 |
|
|
T19 |
1 |
|
T94 |
3 |
|
T32 |
13690 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11654628 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9193466 |
1 |
|
|
T1 |
1 |
|
T20 |
11 |
|
T19 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19662074 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1186020 |
1 |
|
|
T3 |
1 |
|
T77 |
4 |
|
T94 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11680343 |
1 |
|
|
T1 |
2 |
|
T11 |
4 |
|
T2 |
6 |
| auto[1] |
9167751 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3981024 |
1 |
|
|
T11 |
1 |
|
T2 |
1 |
|
T12 |
1 |
| auto[1] |
auto[0] |
auto[1] |
590043 |
1 |
|
|
T3 |
1 |
|
T77 |
1 |
|
T32 |
13263 |
| auto[1] |
auto[1] |
auto[0] |
4000707 |
1 |
|
|
T1 |
1 |
|
T4 |
5 |
|
T77 |
10 |
| auto[1] |
auto[1] |
auto[1] |
595977 |
1 |
|
|
T77 |
3 |
|
T94 |
2 |
|
T32 |
13827 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11660143 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9187951 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19658039 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1190055 |
1 |
|
|
T32 |
26616 |
|
T43 |
1 |
|
T100 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11638643 |
1 |
|
|
T1 |
2 |
|
T11 |
4 |
|
T2 |
5 |
| auto[1] |
9209451 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T2 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4021637 |
1 |
|
|
T11 |
1 |
|
T2 |
2 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
597666 |
1 |
|
|
T32 |
12425 |
|
T43 |
1 |
|
T100 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3997759 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
4 |
| auto[1] |
auto[1] |
auto[1] |
592389 |
1 |
|
|
T32 |
14191 |
|
T100 |
1 |
|
T70 |
16595 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |