Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11680649 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
7 |
auto[1] |
9167445 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T20 |
8 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
19658428 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
auto[1] |
1189666 |
1 |
|
|
T77 |
6 |
|
T94 |
1 |
|
T95 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11650939 |
1 |
|
|
T1 |
2 |
|
T11 |
4 |
|
T2 |
6 |
auto[1] |
9197155 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4008611 |
1 |
|
|
T11 |
1 |
|
T2 |
1 |
|
T19 |
3 |
auto[1] |
auto[0] |
auto[1] |
595298 |
1 |
|
|
T94 |
1 |
|
T95 |
2 |
|
T32 |
14079 |
auto[1] |
auto[1] |
auto[0] |
3998878 |
1 |
|
|
T1 |
1 |
|
T4 |
5 |
|
T77 |
28 |
auto[1] |
auto[1] |
auto[1] |
594368 |
1 |
|
|
T77 |
6 |
|
T32 |
14254 |
|
T100 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |