Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11631841 |
1 |
|
|
T1 |
2 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
9216253 |
1 |
|
|
T1 |
1 |
|
T15 |
3 |
|
T20 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19660989 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
7 |
| auto[1] |
1187105 |
1 |
|
|
T32 |
26028 |
|
T100 |
4 |
|
T70 |
34677 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11674782 |
1 |
|
|
T1 |
3 |
|
T11 |
5 |
|
T2 |
6 |
| auto[1] |
9173312 |
1 |
|
|
T2 |
1 |
|
T12 |
1 |
|
T15 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3978700 |
1 |
|
|
T2 |
1 |
|
T12 |
1 |
|
T19 |
3 |
| auto[1] |
auto[0] |
auto[1] |
591778 |
1 |
|
|
T32 |
14216 |
|
T100 |
2 |
|
T70 |
17176 |
| auto[1] |
auto[1] |
auto[0] |
4007507 |
1 |
|
|
T15 |
3 |
|
T3 |
2 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[1] |
595327 |
1 |
|
|
T32 |
11812 |
|
T100 |
2 |
|
T70 |
17501 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |