| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.61 | 99.06 | 99.10 | 100.00 | 99.80 | 99.68 | 100.00 |
| T774 | /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2306771212 | Jan 10 01:12:27 PM PST 24 | Jan 10 01:13:51 PM PST 24 | 330486584 ps | ||
| T775 | /workspace/coverage/default/42.gpio_smoke.3340059883 | Jan 10 01:13:53 PM PST 24 | Jan 10 01:15:06 PM PST 24 | 52256212 ps | ||
| T776 | /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.719474764 | Jan 10 01:12:50 PM PST 24 | Jan 10 01:14:18 PM PST 24 | 54682234 ps | ||
| T777 | /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.82640089 | Jan 10 01:11:48 PM PST 24 | Jan 10 01:13:13 PM PST 24 | 225731977 ps | ||
| T778 | /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1367607195 | Jan 10 01:12:53 PM PST 24 | Jan 10 01:14:21 PM PST 24 | 40266664 ps | ||
| T779 | /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.900058069 | Jan 10 01:12:40 PM PST 24 | Jan 10 01:14:06 PM PST 24 | 127946825 ps | ||
| T780 | /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3309023297 | Jan 10 01:15:23 PM PST 24 | Jan 10 01:59:18 PM PST 24 | 876530677055 ps | ||
| T781 | /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2199184798 | Jan 10 01:12:34 PM PST 24 | Jan 10 01:13:54 PM PST 24 | 21203676 ps | ||
| T782 | /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3936974322 | Jan 10 01:13:01 PM PST 24 | Jan 10 01:14:29 PM PST 24 | 365528598 ps | ||
| T783 | /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1299743126 | Jan 10 01:12:30 PM PST 24 | Jan 10 01:13:55 PM PST 24 | 162157995 ps | ||
| T784 | /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1244154388 | Jan 10 01:11:48 PM PST 24 | Jan 10 01:13:02 PM PST 24 | 50211724 ps | ||
| T785 | /workspace/coverage/default/32.gpio_filter_stress.2922525760 | Jan 10 01:12:46 PM PST 24 | Jan 10 01:14:16 PM PST 24 | 675565573 ps | ||
| T786 | /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.4222717060 | Jan 10 01:13:27 PM PST 24 | Jan 10 01:14:58 PM PST 24 | 34309159 ps | ||
| T787 | /workspace/coverage/default/46.gpio_random_dout_din.419208067 | Jan 10 01:13:22 PM PST 24 | Jan 10 01:14:48 PM PST 24 | 168927273 ps | ||
| T788 | /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1127196816 | Jan 10 01:13:26 PM PST 24 | Jan 10 01:14:51 PM PST 24 | 221252404 ps | ||
| T789 | /workspace/coverage/default/10.gpio_filter_stress.3517081715 | Jan 10 01:12:09 PM PST 24 | Jan 10 01:13:48 PM PST 24 | 2086702970 ps | ||
| T790 | /workspace/coverage/default/4.gpio_alert_test.1740644999 | Jan 10 01:12:08 PM PST 24 | Jan 10 01:13:24 PM PST 24 | 45048274 ps | ||
| T791 | /workspace/coverage/default/43.gpio_alert_test.2043973786 | Jan 10 01:13:04 PM PST 24 | Jan 10 01:14:29 PM PST 24 | 37092911 ps | ||
| T792 | /workspace/coverage/default/43.gpio_stress_all.3022995972 | Jan 10 01:13:47 PM PST 24 | Jan 10 01:15:25 PM PST 24 | 4360789706 ps | ||
| T793 | /workspace/coverage/default/29.gpio_smoke.4275208073 | Jan 10 01:12:41 PM PST 24 | Jan 10 01:14:09 PM PST 24 | 34262716 ps | ||
| T794 | /workspace/coverage/default/26.gpio_alert_test.3870800685 | Jan 10 01:12:57 PM PST 24 | Jan 10 01:14:22 PM PST 24 | 79364045 ps | ||
| T795 | /workspace/coverage/default/37.gpio_stress_all.2066627094 | Jan 10 01:13:09 PM PST 24 | Jan 10 01:18:13 PM PST 24 | 21180004713 ps | ||
| T796 | /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2885212444 | Jan 10 01:12:00 PM PST 24 | Jan 10 01:13:18 PM PST 24 | 447762071 ps | ||
| T797 | /workspace/coverage/default/36.gpio_stress_all.954139197 | Jan 10 01:12:57 PM PST 24 | Jan 10 01:16:04 PM PST 24 | 18317883108 ps | ||
| T798 | /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.291349310 | Jan 10 01:12:56 PM PST 24 | Jan 10 01:34:46 PM PST 24 | 960891962828 ps | ||
| T799 | /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.476486657 | Jan 10 01:13:54 PM PST 24 | Jan 10 01:15:06 PM PST 24 | 52483029 ps | ||
| T800 | /workspace/coverage/default/31.gpio_intr_rand_pgm.3431157411 | Jan 10 01:12:49 PM PST 24 | Jan 10 01:14:13 PM PST 24 | 105683809 ps | ||
| T801 | /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2050044799 | Jan 10 01:13:30 PM PST 24 | Jan 10 01:14:55 PM PST 24 | 87918654 ps | ||
| T802 | /workspace/coverage/default/37.gpio_rand_intr_trigger.2149576980 | Jan 10 01:13:15 PM PST 24 | Jan 10 01:14:44 PM PST 24 | 92890621 ps | ||
| T803 | /workspace/coverage/default/3.gpio_full_random.608683989 | Jan 10 01:12:16 PM PST 24 | Jan 10 01:13:38 PM PST 24 | 305653088 ps | ||
| T804 | /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1115306599 | Jan 10 01:12:08 PM PST 24 | Jan 10 01:13:23 PM PST 24 | 157504767 ps | ||
| T805 | /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1369786205 | Jan 10 01:13:17 PM PST 24 | Jan 10 01:14:44 PM PST 24 | 23259071 ps | ||
| T806 | /workspace/coverage/default/30.gpio_stress_all.3105985211 | Jan 10 01:12:54 PM PST 24 | Jan 10 01:17:19 PM PST 24 | 74008628209 ps | ||
| T807 | /workspace/coverage/default/10.gpio_random_dout_din.2031645949 | Jan 10 01:12:14 PM PST 24 | Jan 10 01:13:56 PM PST 24 | 19189836 ps | ||
| T808 | /workspace/coverage/default/15.gpio_intr_rand_pgm.71989929 | Jan 10 01:12:18 PM PST 24 | Jan 10 01:13:41 PM PST 24 | 41200625 ps | ||
| T809 | /workspace/coverage/default/41.gpio_random_dout_din.3536137783 | Jan 10 01:13:05 PM PST 24 | Jan 10 01:14:36 PM PST 24 | 44537327 ps | ||
| T810 | /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.743639163 | Jan 10 01:12:22 PM PST 24 | Jan 10 01:13:44 PM PST 24 | 35275899 ps | ||
| T811 | /workspace/coverage/default/43.gpio_smoke.3428469188 | Jan 10 01:13:06 PM PST 24 | Jan 10 01:14:34 PM PST 24 | 269700552 ps | ||
| T812 | /workspace/coverage/default/34.gpio_rand_intr_trigger.3146223720 | Jan 10 01:13:24 PM PST 24 | Jan 10 01:15:03 PM PST 24 | 34909064 ps | ||
| T813 | /workspace/coverage/default/14.gpio_full_random.1337037867 | Jan 10 01:12:29 PM PST 24 | Jan 10 01:13:54 PM PST 24 | 47470763 ps | ||
| T814 | /workspace/coverage/default/46.gpio_filter_stress.4263827082 | Jan 10 01:13:20 PM PST 24 | Jan 10 01:15:11 PM PST 24 | 2017764796 ps | ||
| T815 | /workspace/coverage/default/18.gpio_stress_all.3201124121 | Jan 10 01:12:23 PM PST 24 | Jan 10 01:15:30 PM PST 24 | 7911503170 ps | ||
| T816 | /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1424702293 | Jan 10 01:12:53 PM PST 24 | Jan 10 01:14:21 PM PST 24 | 52130979 ps | ||
| T817 | /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1101701735 | Jan 10 01:11:47 PM PST 24 | Jan 10 01:13:13 PM PST 24 | 134516792 ps | ||
| T818 | /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1722560828 | Jan 10 01:13:13 PM PST 24 | Jan 10 01:14:58 PM PST 24 | 324550530 ps | ||
| T819 | /workspace/coverage/default/38.gpio_alert_test.1423242954 | Jan 10 01:12:59 PM PST 24 | Jan 10 01:14:28 PM PST 24 | 12121538 ps | ||
| T820 | /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1479800187 | Jan 10 01:13:02 PM PST 24 | Jan 10 01:14:34 PM PST 24 | 325679082 ps | ||
| T821 | /workspace/coverage/default/45.gpio_stress_all.1477221623 | Jan 10 01:13:19 PM PST 24 | Jan 10 01:16:13 PM PST 24 | 26109879145 ps | ||
| T822 | /workspace/coverage/default/1.gpio_stress_all.1557487510 | Jan 10 01:11:47 PM PST 24 | Jan 10 01:16:01 PM PST 24 | 6384807176 ps | ||
| T823 | /workspace/coverage/default/42.gpio_stress_all.1269761293 | Jan 10 01:13:10 PM PST 24 | Jan 10 01:15:03 PM PST 24 | 2163594476 ps | ||
| T824 | /workspace/coverage/default/6.gpio_stress_all.2485091674 | Jan 10 01:12:04 PM PST 24 | Jan 10 01:15:09 PM PST 24 | 9027257313 ps | ||
| T825 | /workspace/coverage/default/2.gpio_filter_stress.4088664961 | Jan 10 01:11:48 PM PST 24 | Jan 10 01:13:31 PM PST 24 | 3037905302 ps | ||
| T826 | /workspace/coverage/default/19.gpio_stress_all.977778357 | Jan 10 01:12:21 PM PST 24 | Jan 10 01:15:51 PM PST 24 | 10639263609 ps | ||
| T827 | /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1781042225 | Jan 10 01:11:49 PM PST 24 | Jan 10 01:13:05 PM PST 24 | 43154793 ps | ||
| T828 | /workspace/coverage/default/12.gpio_full_random.3460087724 | Jan 10 01:12:22 PM PST 24 | Jan 10 01:13:53 PM PST 24 | 42579069 ps | ||
| T829 | /workspace/coverage/default/5.gpio_filter_stress.3003092067 | Jan 10 01:12:04 PM PST 24 | Jan 10 01:13:20 PM PST 24 | 360990767 ps | ||
| T830 | /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2061970172 | Jan 10 01:12:08 PM PST 24 | Jan 10 01:13:27 PM PST 24 | 56868669 ps | ||
| T831 | /workspace/coverage/default/22.gpio_intr_rand_pgm.974194050 | Jan 10 01:12:25 PM PST 24 | Jan 10 01:13:48 PM PST 24 | 161699480 ps | ||
| T832 | /workspace/coverage/default/34.gpio_stress_all.819412871 | Jan 10 01:12:57 PM PST 24 | Jan 10 01:16:49 PM PST 24 | 12318000468 ps | ||
| T81 | /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1557705617 | Jan 10 01:12:12 PM PST 24 | Jan 10 01:25:14 PM PST 24 | 56467023108 ps | ||
| T833 | /workspace/coverage/default/26.gpio_smoke.873018316 | Jan 10 01:12:25 PM PST 24 | Jan 10 01:13:43 PM PST 24 | 229358896 ps | ||
| T834 | /workspace/coverage/default/1.gpio_alert_test.3229865277 | Jan 10 01:11:48 PM PST 24 | Jan 10 01:13:06 PM PST 24 | 24846348 ps | ||
| T835 | /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.291745741 | Jan 10 01:13:00 PM PST 24 | Jan 10 01:31:53 PM PST 24 | 281128864908 ps | ||
| T836 | /workspace/coverage/default/26.gpio_random_dout_din.673487945 | Jan 10 01:12:42 PM PST 24 | Jan 10 01:14:09 PM PST 24 | 51660997 ps | ||
| T837 | /workspace/coverage/default/47.gpio_random_dout_din.74528670 | Jan 10 01:13:16 PM PST 24 | Jan 10 01:14:58 PM PST 24 | 63913377 ps | ||
| T838 | /workspace/coverage/default/24.gpio_intr_rand_pgm.956804031 | Jan 10 01:12:25 PM PST 24 | Jan 10 01:13:54 PM PST 24 | 16461898 ps | ||
| T839 | /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3341798613 | Jan 10 01:12:32 PM PST 24 | Jan 10 01:28:31 PM PST 24 | 322221081772 ps | ||
| T840 | /workspace/coverage/default/33.gpio_random_dout_din.1255962172 | Jan 10 01:12:58 PM PST 24 | Jan 10 01:14:24 PM PST 24 | 37978756 ps | ||
| T841 | /workspace/coverage/default/27.gpio_rand_intr_trigger.606498114 | Jan 10 01:12:59 PM PST 24 | Jan 10 01:14:33 PM PST 24 | 80075754 ps | ||
| T842 | /workspace/coverage/default/28.gpio_rand_intr_trigger.1732310882 | Jan 10 01:12:46 PM PST 24 | Jan 10 01:14:15 PM PST 24 | 403714712 ps | ||
| T843 | /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.4125896927 | Jan 10 01:12:30 PM PST 24 | Jan 10 01:13:50 PM PST 24 | 50550667 ps | ||
| T60 | /workspace/coverage/default/0.gpio_sec_cm.2679215772 | Jan 10 01:11:56 PM PST 24 | Jan 10 01:13:13 PM PST 24 | 36715558 ps | ||
| T844 | /workspace/coverage/default/41.gpio_filter_stress.3986909206 | Jan 10 01:13:19 PM PST 24 | Jan 10 01:14:56 PM PST 24 | 280776648 ps | ||
| T845 | /workspace/coverage/default/9.gpio_random_dout_din.1764322553 | Jan 10 01:12:17 PM PST 24 | Jan 10 01:13:36 PM PST 24 | 58523457 ps | ||
| T846 | /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3715039190 | Jan 10 01:12:48 PM PST 24 | Jan 10 01:19:00 PM PST 24 | 46278582370 ps | ||
| T847 | /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.324516331 | Jan 10 01:12:45 PM PST 24 | Jan 10 01:14:13 PM PST 24 | 108543966 ps | ||
| T848 | /workspace/coverage/default/39.gpio_alert_test.3899884492 | Jan 10 01:13:03 PM PST 24 | Jan 10 01:14:29 PM PST 24 | 20065005 ps | ||
| T849 | /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1147993537 | Jan 10 01:12:36 PM PST 24 | Jan 10 01:13:59 PM PST 24 | 141999343 ps | ||
| T850 | /workspace/coverage/default/39.gpio_filter_stress.2114777794 | Jan 10 01:13:00 PM PST 24 | Jan 10 01:14:41 PM PST 24 | 1196078989 ps | ||
| T851 | /workspace/coverage/default/27.gpio_intr_rand_pgm.1387686519 | Jan 10 01:12:56 PM PST 24 | Jan 10 01:14:35 PM PST 24 | 46147450 ps | ||
| T852 | /workspace/coverage/default/47.gpio_smoke.1150421671 | Jan 10 01:13:19 PM PST 24 | Jan 10 01:14:46 PM PST 24 | 234196734 ps | ||
| T853 | /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1883049191 | Jan 10 01:15:29 PM PST 24 | Jan 10 01:15:40 PM PST 24 | 132637259 ps | ||
| T854 | /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2943204539 | Jan 10 01:12:27 PM PST 24 | Jan 10 01:13:45 PM PST 24 | 101058452 ps | ||
| T855 | /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2133583461 | Jan 10 01:12:39 PM PST 24 | Jan 10 01:14:05 PM PST 24 | 381288645 ps | ||
| T856 | /workspace/coverage/default/2.gpio_alert_test.2043753674 | Jan 10 01:11:48 PM PST 24 | Jan 10 01:13:06 PM PST 24 | 14884743 ps | ||
| T857 | /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2113673647 | Jan 10 01:13:12 PM PST 24 | Jan 10 01:14:43 PM PST 24 | 646573792 ps | ||
| T858 | /workspace/coverage/default/47.gpio_rand_intr_trigger.282077458 | Jan 10 01:13:19 PM PST 24 | Jan 10 01:14:49 PM PST 24 | 67709466 ps | ||
| T859 | /workspace/coverage/default/39.gpio_rand_intr_trigger.4166312274 | Jan 10 01:13:07 PM PST 24 | Jan 10 01:14:36 PM PST 24 | 48790828 ps | ||
| T860 | /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.452901947 | Jan 10 01:12:17 PM PST 24 | Jan 10 01:13:38 PM PST 24 | 477654665 ps | ||
| T861 | /workspace/coverage/default/49.gpio_full_random.1757496005 | Jan 10 01:15:23 PM PST 24 | Jan 10 01:15:28 PM PST 24 | 137642938 ps | ||
| T862 | /workspace/coverage/default/2.gpio_rand_intr_trigger.2562254135 | Jan 10 01:11:48 PM PST 24 | Jan 10 01:13:03 PM PST 24 | 73780732 ps | ||
| T863 | /workspace/coverage/default/30.gpio_filter_stress.3583338305 | Jan 10 01:12:52 PM PST 24 | Jan 10 01:14:25 PM PST 24 | 1496258448 ps | ||
| T864 | /workspace/coverage/default/49.gpio_smoke.160524367 | Jan 10 01:13:32 PM PST 24 | Jan 10 01:14:55 PM PST 24 | 51673488 ps | ||
| T865 | /workspace/coverage/default/29.gpio_alert_test.3080122247 | Jan 10 01:12:46 PM PST 24 | Jan 10 01:14:19 PM PST 24 | 39820385 ps | ||
| T866 | /workspace/coverage/default/16.gpio_stress_all.3290638763 | Jan 10 01:12:25 PM PST 24 | Jan 10 01:16:45 PM PST 24 | 30765693617 ps | ||
| T867 | /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.961637269 | Jan 10 01:13:01 PM PST 24 | Jan 10 01:14:29 PM PST 24 | 303086394 ps | ||
| T868 | /workspace/coverage/default/43.gpio_random_dout_din.2432050599 | Jan 10 01:13:08 PM PST 24 | Jan 10 01:14:35 PM PST 24 | 66204421 ps | ||
| T869 | /workspace/coverage/default/27.gpio_filter_stress.2994614684 | Jan 10 01:12:36 PM PST 24 | Jan 10 01:14:18 PM PST 24 | 973691187 ps | ||
| T870 | /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3070138077 | Jan 10 01:12:49 PM PST 24 | Jan 10 01:14:28 PM PST 24 | 16209748 ps | ||
| T82 | /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1430620482 | Jan 10 01:10:03 PM PST 24 | Jan 10 01:11:12 PM PST 24 | 77353242 ps | ||
| T28 | /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4008776259 | Jan 10 01:10:11 PM PST 24 | Jan 10 01:11:25 PM PST 24 | 418062040 ps | ||
| T871 | /workspace/coverage/cover_reg_top/39.gpio_intr_test.1887387107 | Jan 10 01:10:18 PM PST 24 | Jan 10 01:11:33 PM PST 24 | 24599464 ps | ||
| T101 | /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1971185099 | Jan 10 01:10:12 PM PST 24 | Jan 10 01:11:26 PM PST 24 | 1423524704 ps | ||
| T29 | /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2323880350 | Jan 10 01:10:03 PM PST 24 | Jan 10 01:11:12 PM PST 24 | 229930498 ps | ||
| T872 | /workspace/coverage/cover_reg_top/47.gpio_intr_test.1343316094 | Jan 10 01:10:10 PM PST 24 | Jan 10 01:11:22 PM PST 24 | 11388465 ps | ||
| T873 | /workspace/coverage/cover_reg_top/33.gpio_intr_test.3388330326 | Jan 10 01:10:23 PM PST 24 | Jan 10 01:11:40 PM PST 24 | 140279279 ps | ||
| T96 | /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.844797265 | Jan 10 01:10:12 PM PST 24 | Jan 10 01:11:25 PM PST 24 | 83256857 ps | ||
| T85 | /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4185214889 | Jan 10 01:10:07 PM PST 24 | Jan 10 01:11:17 PM PST 24 | 37363049 ps | ||
| T36 | /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2812730174 | Jan 10 01:10:12 PM PST 24 | Jan 10 01:11:25 PM PST 24 | 173124008 ps | ||
| T874 | /workspace/coverage/cover_reg_top/37.gpio_intr_test.3897441641 | Jan 10 01:10:18 PM PST 24 | Jan 10 01:11:33 PM PST 24 | 158906886 ps | ||
| T83 | /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4266667967 | Jan 10 01:09:53 PM PST 24 | Jan 10 01:10:59 PM PST 24 | 18906260 ps | ||
| T875 | /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4163126941 | Jan 10 01:10:10 PM PST 24 | Jan 10 01:11:23 PM PST 24 | 36288199 ps | ||
| T876 | /workspace/coverage/cover_reg_top/31.gpio_intr_test.2450155724 | Jan 10 01:10:24 PM PST 24 | Jan 10 01:11:41 PM PST 24 | 35039450 ps | ||
| T97 | /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.304712895 | Jan 10 01:09:59 PM PST 24 | Jan 10 01:11:08 PM PST 24 | 142250365 ps | ||
| T877 | /workspace/coverage/cover_reg_top/41.gpio_intr_test.3652384955 | Jan 10 01:10:17 PM PST 24 | Jan 10 01:11:36 PM PST 24 | 41060161 ps | ||
| T878 | /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3663433179 | Jan 10 01:09:56 PM PST 24 | Jan 10 01:11:03 PM PST 24 | 102415848 ps | ||
| T879 | /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2830225186 | Jan 10 01:10:04 PM PST 24 | Jan 10 01:11:14 PM PST 24 | 31920494 ps | ||
| T880 | /workspace/coverage/cover_reg_top/16.gpio_intr_test.3594947477 | Jan 10 01:09:48 PM PST 24 | Jan 10 01:10:55 PM PST 24 | 76705666 ps | ||
| T881 | /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2947196480 | Jan 10 01:10:06 PM PST 24 | Jan 10 01:11:17 PM PST 24 | 26684603 ps | ||
| T882 | /workspace/coverage/cover_reg_top/7.gpio_intr_test.1430992127 | Jan 10 01:10:08 PM PST 24 | Jan 10 01:11:18 PM PST 24 | 10421541 ps | ||
| T883 | /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2089744995 | Jan 10 01:09:48 PM PST 24 | Jan 10 01:10:55 PM PST 24 | 32591110 ps | ||
| T884 | /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2290912286 | Jan 10 01:10:09 PM PST 24 | Jan 10 01:11:21 PM PST 24 | 37498002 ps | ||
| T885 | /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.298092701 | Jan 10 01:10:08 PM PST 24 | Jan 10 01:11:19 PM PST 24 | 22351955 ps | ||
| T886 | /workspace/coverage/cover_reg_top/12.gpio_tl_errors.632386674 | Jan 10 01:09:55 PM PST 24 | Jan 10 01:11:03 PM PST 24 | 212333777 ps | ||
| T887 | /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3288614579 | Jan 10 01:10:13 PM PST 24 | Jan 10 01:11:32 PM PST 24 | 285913864 ps | ||
| T888 | /workspace/coverage/cover_reg_top/36.gpio_intr_test.3561318181 | Jan 10 01:10:13 PM PST 24 | Jan 10 01:11:26 PM PST 24 | 25753982 ps | ||
| T889 | /workspace/coverage/cover_reg_top/13.gpio_tl_errors.605964401 | Jan 10 01:10:00 PM PST 24 | Jan 10 01:11:11 PM PST 24 | 55669309 ps | ||
| T30 | /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3732562494 | Jan 10 01:10:14 PM PST 24 | Jan 10 01:11:28 PM PST 24 | 246667518 ps | ||
| T98 | /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2940236647 | Jan 10 01:10:10 PM PST 24 | Jan 10 01:11:23 PM PST 24 | 32879230 ps | ||
| T33 | /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.232379869 | Jan 10 01:10:05 PM PST 24 | Jan 10 01:11:16 PM PST 24 | 393396962 ps | ||
| T890 | /workspace/coverage/cover_reg_top/7.gpio_tl_errors.582702494 | Jan 10 01:09:56 PM PST 24 | Jan 10 01:11:04 PM PST 24 | 267927998 ps | ||
| T891 | /workspace/coverage/cover_reg_top/14.gpio_intr_test.3280700994 | Jan 10 01:10:15 PM PST 24 | Jan 10 01:11:29 PM PST 24 | 17789987 ps | ||
| T892 | /workspace/coverage/cover_reg_top/49.gpio_intr_test.2080928667 | Jan 10 01:10:14 PM PST 24 | Jan 10 01:11:27 PM PST 24 | 14416644 ps | ||
| T37 | /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3512728152 | Jan 10 01:10:05 PM PST 24 | Jan 10 01:11:16 PM PST 24 | 121222405 ps | ||
| T893 | /workspace/coverage/cover_reg_top/35.gpio_intr_test.2129513709 | Jan 10 01:10:19 PM PST 24 | Jan 10 01:11:34 PM PST 24 | 40535980 ps | ||
| T102 | /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.558285527 | Jan 10 01:10:02 PM PST 24 | Jan 10 01:11:10 PM PST 24 | 194323290 ps | ||
| T894 | /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.617198919 | Jan 10 01:10:14 PM PST 24 | Jan 10 01:11:33 PM PST 24 | 78919352 ps | ||
| T895 | /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.971192747 | Jan 10 01:10:08 PM PST 24 | Jan 10 01:11:21 PM PST 24 | 473137436 ps | ||
| T896 | /workspace/coverage/cover_reg_top/15.gpio_intr_test.2470622477 | Jan 10 01:10:12 PM PST 24 | Jan 10 01:11:25 PM PST 24 | 84261879 ps | ||
| T99 | /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1794635467 | Jan 10 01:10:01 PM PST 24 | Jan 10 01:11:10 PM PST 24 | 180378012 ps | ||
| T897 | /workspace/coverage/cover_reg_top/10.gpio_intr_test.1195638685 | Jan 10 01:09:51 PM PST 24 | Jan 10 01:10:58 PM PST 24 | 19932514 ps | ||
| T898 | /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3609180400 | Jan 10 01:10:09 PM PST 24 | Jan 10 01:11:22 PM PST 24 | 98741764 ps | ||
| T899 | /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.179213836 | Jan 10 01:10:03 PM PST 24 | Jan 10 01:11:13 PM PST 24 | 13068113 ps | ||
| T900 | /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3232289591 | Jan 10 01:10:13 PM PST 24 | Jan 10 01:11:32 PM PST 24 | 16236873 ps | ||
| T901 | /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1913198587 | Jan 10 01:10:09 PM PST 24 | Jan 10 01:11:22 PM PST 24 | 35029215 ps | ||
| T902 | /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2547920099 | Jan 10 01:09:59 PM PST 24 | Jan 10 01:11:08 PM PST 24 | 42454970 ps | ||
| T903 | /workspace/coverage/cover_reg_top/23.gpio_intr_test.3311360254 | Jan 10 01:10:12 PM PST 24 | Jan 10 01:11:25 PM PST 24 | 12124035 ps | ||
| T84 | /workspace/coverage/cover_reg_top/13.gpio_csr_rw.984102912 | Jan 10 01:09:58 PM PST 24 | Jan 10 01:11:06 PM PST 24 | 33491025 ps | ||
| T904 | /workspace/coverage/cover_reg_top/4.gpio_tl_errors.93913955 | Jan 10 01:10:04 PM PST 24 | Jan 10 01:11:15 PM PST 24 | 186812409 ps | ||
| T905 | /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1595431434 | Jan 10 01:10:03 PM PST 24 | Jan 10 01:11:13 PM PST 24 | 308062509 ps | ||
| T906 | /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2536070342 | Jan 10 01:09:49 PM PST 24 | Jan 10 01:10:56 PM PST 24 | 108264634 ps | ||
| T907 | /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1582313849 | Jan 10 01:10:01 PM PST 24 | Jan 10 01:11:10 PM PST 24 | 96655753 ps | ||
| T908 | /workspace/coverage/cover_reg_top/46.gpio_intr_test.3412537178 | Jan 10 01:10:10 PM PST 24 | Jan 10 01:11:23 PM PST 24 | 12564057 ps | ||
| T909 | /workspace/coverage/cover_reg_top/9.gpio_csr_rw.936592658 | Jan 10 01:10:13 PM PST 24 | Jan 10 01:11:27 PM PST 24 | 89809238 ps | ||
| T910 | /workspace/coverage/cover_reg_top/45.gpio_intr_test.1061878763 | Jan 10 01:10:14 PM PST 24 | Jan 10 01:11:36 PM PST 24 | 24129025 ps | ||
| T911 | /workspace/coverage/cover_reg_top/11.gpio_intr_test.2227627309 | Jan 10 01:09:53 PM PST 24 | Jan 10 01:10:59 PM PST 24 | 21410708 ps | ||
| T912 | /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3501717347 | Jan 10 01:09:56 PM PST 24 | Jan 10 01:11:03 PM PST 24 | 19808214 ps | ||
| T913 | /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3830076163 | Jan 10 01:09:52 PM PST 24 | Jan 10 01:10:59 PM PST 24 | 21035756 ps | ||
| T914 | /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3165710912 | Jan 10 01:10:08 PM PST 24 | Jan 10 01:11:19 PM PST 24 | 19481645 ps | ||
| T915 | /workspace/coverage/cover_reg_top/13.gpio_intr_test.1485520393 | Jan 10 01:10:10 PM PST 24 | Jan 10 01:11:22 PM PST 24 | 18188424 ps | ||
| T916 | /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1359287368 | Jan 10 01:10:15 PM PST 24 | Jan 10 01:11:30 PM PST 24 | 108170283 ps | ||
| T917 | /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1774336652 | Jan 10 01:10:00 PM PST 24 | Jan 10 01:11:10 PM PST 24 | 240238148 ps | ||
| T918 | /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4106696917 | Jan 10 01:10:05 PM PST 24 | Jan 10 01:11:15 PM PST 24 | 19749891 ps | ||
| T919 | /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1666210252 | Jan 10 01:10:00 PM PST 24 | Jan 10 01:11:09 PM PST 24 | 117041177 ps | ||
| T920 | /workspace/coverage/cover_reg_top/19.gpio_tl_errors.492902276 | Jan 10 01:10:23 PM PST 24 | Jan 10 01:11:41 PM PST 24 | 240710580 ps | ||
| T921 | /workspace/coverage/cover_reg_top/9.gpio_intr_test.2270433173 | Jan 10 01:10:10 PM PST 24 | Jan 10 01:11:23 PM PST 24 | 16035981 ps | ||
| T922 | /workspace/coverage/cover_reg_top/5.gpio_intr_test.422227248 | Jan 10 01:10:01 PM PST 24 | Jan 10 01:11:10 PM PST 24 | 34440176 ps | ||
| T923 | /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3275350964 | Jan 10 01:10:07 PM PST 24 | Jan 10 01:11:18 PM PST 24 | 209979946 ps | ||
| T924 | /workspace/coverage/cover_reg_top/16.gpio_tl_errors.913999913 | Jan 10 01:10:02 PM PST 24 | Jan 10 01:11:12 PM PST 24 | 215183341 ps | ||
| T925 | /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1588269146 | Jan 10 01:10:12 PM PST 24 | Jan 10 01:11:26 PM PST 24 | 32913652 ps | ||
| T926 | /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1268903766 | Jan 10 01:10:06 PM PST 24 | Jan 10 01:11:16 PM PST 24 | 49432050 ps | ||
| T34 | /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.140404627 | Jan 10 01:10:00 PM PST 24 | Jan 10 01:11:10 PM PST 24 | 506122881 ps | ||
| T927 | /workspace/coverage/cover_reg_top/27.gpio_intr_test.3291548918 | Jan 10 01:10:21 PM PST 24 | Jan 10 01:11:37 PM PST 24 | 17904315 ps | ||
| T928 | /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2907821722 | Jan 10 01:10:13 PM PST 24 | Jan 10 01:11:28 PM PST 24 | 312866528 ps | ||
| T929 | /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3417371349 | Jan 10 01:10:00 PM PST 24 | Jan 10 01:11:08 PM PST 24 | 11933312 ps | ||
| T930 | /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.183594821 | Jan 10 01:09:54 PM PST 24 | Jan 10 01:11:00 PM PST 24 | 20018731 ps | ||
| T931 | /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.408124277 | Jan 10 01:09:58 PM PST 24 | Jan 10 01:11:06 PM PST 24 | 31816778 ps | ||
| T932 | /workspace/coverage/cover_reg_top/30.gpio_intr_test.4126137437 | Jan 10 01:10:13 PM PST 24 | Jan 10 01:11:32 PM PST 24 | 12254686 ps | ||
| T933 | /workspace/coverage/cover_reg_top/15.gpio_csr_rw.119352417 | Jan 10 01:10:25 PM PST 24 | Jan 10 01:11:43 PM PST 24 | 53215544 ps | ||
| T934 | /workspace/coverage/cover_reg_top/0.gpio_intr_test.2699019864 | Jan 10 01:09:53 PM PST 24 | Jan 10 01:11:00 PM PST 24 | 18547333 ps | ||
| T935 | /workspace/coverage/cover_reg_top/20.gpio_intr_test.2965062023 | Jan 10 01:10:16 PM PST 24 | Jan 10 01:11:43 PM PST 24 | 15357469 ps | ||
| T936 | /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3529183753 | Jan 10 01:09:59 PM PST 24 | Jan 10 01:11:08 PM PST 24 | 22711278 ps | ||
| T937 | /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1104289359 | Jan 10 01:09:59 PM PST 24 | Jan 10 01:11:08 PM PST 24 | 55156177 ps | ||
| T938 | /workspace/coverage/cover_reg_top/21.gpio_intr_test.351420713 | Jan 10 01:10:09 PM PST 24 | Jan 10 01:11:22 PM PST 24 | 62433549 ps | ||
| T939 | /workspace/coverage/cover_reg_top/19.gpio_intr_test.1130213619 | Jan 10 01:10:16 PM PST 24 | Jan 10 01:11:35 PM PST 24 | 64027210 ps | ||
| T940 | /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2658039623 | Jan 10 01:09:55 PM PST 24 | Jan 10 01:11:02 PM PST 24 | 71890764 ps | ||
| T941 | /workspace/coverage/cover_reg_top/22.gpio_intr_test.1397357943 | Jan 10 01:10:15 PM PST 24 | Jan 10 01:11:28 PM PST 24 | 11799027 ps | ||
| T942 | /workspace/coverage/cover_reg_top/44.gpio_intr_test.1978869890 | Jan 10 01:10:15 PM PST 24 | Jan 10 01:11:29 PM PST 24 | 50762782 ps | ||
| T943 | /workspace/coverage/cover_reg_top/26.gpio_intr_test.2210840681 | Jan 10 01:10:11 PM PST 24 | Jan 10 01:11:23 PM PST 24 | 43160513 ps | ||
| T944 | /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1472561472 | Jan 10 01:10:09 PM PST 24 | Jan 10 01:11:21 PM PST 24 | 14956097 ps | ||
| T945 | /workspace/coverage/cover_reg_top/28.gpio_intr_test.2588072605 | Jan 10 01:10:16 PM PST 24 | Jan 10 01:11:29 PM PST 24 | 22617679 ps | ||
| T946 | /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2346107016 | Jan 10 01:10:04 PM PST 24 | Jan 10 01:11:14 PM PST 24 | 25805120 ps | ||
| T947 | /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1892033702 | Jan 10 01:10:15 PM PST 24 | Jan 10 01:11:28 PM PST 24 | 22299808 ps | ||
| T948 | /workspace/coverage/cover_reg_top/17.gpio_tl_errors.882520527 | Jan 10 01:10:07 PM PST 24 | Jan 10 01:11:19 PM PST 24 | 39175134 ps | ||
| T949 | /workspace/coverage/cover_reg_top/2.gpio_intr_test.2459356877 | Jan 10 01:10:13 PM PST 24 | Jan 10 01:11:26 PM PST 24 | 31313449 ps | ||
| T950 | /workspace/coverage/cover_reg_top/42.gpio_intr_test.2388469154 | Jan 10 01:10:20 PM PST 24 | Jan 10 01:11:39 PM PST 24 | 14128713 ps | ||
| T86 | /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.644891206 | Jan 10 01:10:12 PM PST 24 | Jan 10 01:11:24 PM PST 24 | 13673369 ps | ||
| T951 | /workspace/coverage/cover_reg_top/24.gpio_intr_test.1952059917 | Jan 10 01:10:16 PM PST 24 | Jan 10 01:11:30 PM PST 24 | 42972049 ps | ||
| T952 | /workspace/coverage/cover_reg_top/8.gpio_intr_test.1132729057 | Jan 10 01:09:48 PM PST 24 | Jan 10 01:10:55 PM PST 24 | 36366049 ps | ||
| T93 | /workspace/coverage/cover_reg_top/14.gpio_csr_rw.729133138 | Jan 10 01:09:58 PM PST 24 | Jan 10 01:11:06 PM PST 24 | 76328096 ps | ||
| T953 | /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.735894313 | Jan 10 01:09:48 PM PST 24 | Jan 10 01:10:55 PM PST 24 | 18197229 ps | ||
| T87 | /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1044175722 | Jan 10 01:09:52 PM PST 24 | Jan 10 01:10:58 PM PST 24 | 37410427 ps | ||
| T954 | /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1650498125 | Jan 10 01:10:22 PM PST 24 | Jan 10 01:11:38 PM PST 24 | 15014013 ps | ||
| T955 | /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1205634085 | Jan 10 01:09:57 PM PST 24 | Jan 10 01:11:04 PM PST 24 | 330644590 ps | ||
| T88 | /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1723340817 | Jan 10 01:10:12 PM PST 24 | Jan 10 01:11:25 PM PST 24 | 285171833 ps | ||
| T956 | /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.4116759588 | Jan 10 01:10:16 PM PST 24 | Jan 10 01:11:30 PM PST 24 | 85602463 ps | ||
| T957 | /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2066326539 | Jan 10 01:10:02 PM PST 24 | Jan 10 01:11:13 PM PST 24 | 51427383 ps |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1330315537 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 29856187 ps |
| CPU time | 1.56 seconds |
| Started | Jan 10 01:09:53 PM PST 24 |
| Finished | Jan 10 01:11:00 PM PST 24 |
| Peak memory | 198436 kb |
| Host | smart-739212ee-3f14-4ccb-9583-c43420b360b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330315537 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1330315537 |
| Directory | /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.714113099 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 271294255 ps |
| CPU time | 1.13 seconds |
| Started | Jan 10 12:57:48 PM PST 24 |
| Finished | Jan 10 12:59:08 PM PST 24 |
| Peak memory | 197672 kb |
| Host | smart-0f475ca6-91da-4fd2-8e25-9fbe5377d91d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=714113099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.714113099 |
| Directory | /workspace/23.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3883995769 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 69302013 ps |
| CPU time | 2.53 seconds |
| Started | Jan 10 01:12:09 PM PST 24 |
| Finished | Jan 10 01:13:35 PM PST 24 |
| Peak memory | 198264 kb |
| Host | smart-dba58033-579c-4c7b-92b2-723c43c33ed2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883995769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3883995769 |
| Directory | /workspace/12.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.791255211 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1234349363 ps |
| CPU time | 1.43 seconds |
| Started | Jan 10 01:10:09 PM PST 24 |
| Finished | Jan 10 01:11:21 PM PST 24 |
| Peak memory | 198392 kb |
| Host | smart-0009bd8d-dd3e-4741-a3d5-2968de39e836 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791255211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.gpio_tl_intg_err.791255211 |
| Directory | /workspace/16.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3281201795 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 288999964613 ps |
| CPU time | 1220.55 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:33:59 PM PST 24 |
| Peak memory | 198272 kb |
| Host | smart-f84091b4-a59d-42fe-92ec-42ddc3e63523 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3281201795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3281201795 |
| Directory | /workspace/15.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3518137230 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 34827608 ps |
| CPU time | 0.84 seconds |
| Started | Jan 10 01:10:09 PM PST 24 |
| Finished | Jan 10 01:11:21 PM PST 24 |
| Peak memory | 196632 kb |
| Host | smart-0379332f-3fd9-4d13-b618-8df54aae0347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518137230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_aliasing.3518137230 |
| Directory | /workspace/3.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/32.gpio_intr_test.1859331686 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 69779838 ps |
| CPU time | 0.61 seconds |
| Started | Jan 10 01:10:09 PM PST 24 |
| Finished | Jan 10 01:11:21 PM PST 24 |
| Peak memory | 194768 kb |
| Host | smart-670f6d6e-6710-40ec-b583-190f88a49c42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859331686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1859331686 |
| Directory | /workspace/32.gpio_intr_test/latest |
| Test location | /workspace/coverage/default/2.gpio_sec_cm.1383570757 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 59755655 ps |
| CPU time | 0.85 seconds |
| Started | Jan 10 01:11:49 PM PST 24 |
| Finished | Jan 10 01:13:05 PM PST 24 |
| Peak memory | 213404 kb |
| Host | smart-6b9a6622-6096-4e6a-89f7-97515af67c62 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383570757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1383570757 |
| Directory | /workspace/2.gpio_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1723340817 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 285171833 ps |
| CPU time | 1.54 seconds |
| Started | Jan 10 01:10:12 PM PST 24 |
| Finished | Jan 10 01:11:25 PM PST 24 |
| Peak memory | 197548 kb |
| Host | smart-170328b8-d0fa-4ad9-b0cd-e0355d40f944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723340817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1723340817 |
| Directory | /workspace/0.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2071123876 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 208313213 ps |
| CPU time | 1.4 seconds |
| Started | Jan 10 01:10:12 PM PST 24 |
| Finished | Jan 10 01:11:26 PM PST 24 |
| Peak memory | 196592 kb |
| Host | smart-73b34b1b-7abc-499d-83f7-3bdf1d6d928a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071123876 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.gpio_tl_intg_err.2071123876 |
| Directory | /workspace/2.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3956309517 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 209535124 ps |
| CPU time | 0.93 seconds |
| Started | Jan 10 12:57:37 PM PST 24 |
| Finished | Jan 10 12:58:55 PM PST 24 |
| Peak memory | 196372 kb |
| Host | smart-8ece414e-1196-4425-abd4-e8ec7fbb9199 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956309517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.3956309517 |
| Directory | /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.4286562707 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 90888789 ps |
| CPU time | 0.89 seconds |
| Started | Jan 10 01:10:05 PM PST 24 |
| Finished | Jan 10 01:11:19 PM PST 24 |
| Peak memory | 197936 kb |
| Host | smart-4e582c0f-ef7d-43a7-a2b3-b1e4cf1ad158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286562707 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 15.gpio_same_csr_outstanding.4286562707 |
| Directory | /workspace/15.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/15.gpio_alert_test.3802647229 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 38859305 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:12:17 PM PST 24 |
| Finished | Jan 10 01:13:36 PM PST 24 |
| Peak memory | 193996 kb |
| Host | smart-bf3a8189-dbd2-4720-80a8-da36f0242005 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802647229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3802647229 |
| Directory | /workspace/15.gpio_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_intr_test.1676146504 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 17254080 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:09:55 PM PST 24 |
| Finished | Jan 10 01:11:01 PM PST 24 |
| Peak memory | 194132 kb |
| Host | smart-32e4866d-d68e-463e-aa24-9a3b58224c38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676146504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1676146504 |
| Directory | /workspace/12.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.323815975 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 380709552 ps |
| CPU time | 1.33 seconds |
| Started | Jan 10 01:10:01 PM PST 24 |
| Finished | Jan 10 01:11:10 PM PST 24 |
| Peak memory | 198376 kb |
| Host | smart-a83a9f8d-b6ee-432f-bd32-249764d93d4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323815975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.gpio_tl_intg_err.323815975 |
| Directory | /workspace/9.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2046810101 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 29247189 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 01:10:09 PM PST 24 |
| Finished | Jan 10 01:11:22 PM PST 24 |
| Peak memory | 196128 kb |
| Host | smart-b340b9a5-d959-4d04-b8d7-08fd13305773 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046810101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_aliasing.2046810101 |
| Directory | /workspace/0.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2948537673 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 32182521 ps |
| CPU time | 0.63 seconds |
| Started | Jan 10 01:10:09 PM PST 24 |
| Finished | Jan 10 01:11:21 PM PST 24 |
| Peak memory | 194812 kb |
| Host | smart-ec5a2263-09e4-4efb-94d2-f3154914d5b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948537673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2948537673 |
| Directory | /workspace/0.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.298092701 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 22351955 ps |
| CPU time | 1.09 seconds |
| Started | Jan 10 01:10:08 PM PST 24 |
| Finished | Jan 10 01:11:19 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-0ec44a5c-3f11-4906-8199-1d75b39459e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298092701 -asser t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.298092701 |
| Directory | /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1582313849 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 96655753 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:10:01 PM PST 24 |
| Finished | Jan 10 01:11:10 PM PST 24 |
| Peak memory | 194812 kb |
| Host | smart-84d5193f-6741-423d-b32b-0ce854b6ab78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582313849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio _csr_rw.1582313849 |
| Directory | /workspace/0.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_intr_test.2699019864 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 18547333 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:09:53 PM PST 24 |
| Finished | Jan 10 01:11:00 PM PST 24 |
| Peak memory | 194092 kb |
| Host | smart-b597cc94-58a5-4ce3-a4e6-125d6455164e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699019864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2699019864 |
| Directory | /workspace/0.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3501717347 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 19808214 ps |
| CPU time | 0.67 seconds |
| Started | Jan 10 01:09:56 PM PST 24 |
| Finished | Jan 10 01:11:03 PM PST 24 |
| Peak memory | 195808 kb |
| Host | smart-dc1956ee-ff3a-4f12-9837-6b43aadf1561 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501717347 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.gpio_same_csr_outstanding.3501717347 |
| Directory | /workspace/0.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2438805702 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 94551638 ps |
| CPU time | 2.46 seconds |
| Started | Jan 10 01:10:00 PM PST 24 |
| Finished | Jan 10 01:11:11 PM PST 24 |
| Peak memory | 198436 kb |
| Host | smart-ccafab6a-3f6e-4c75-b56d-0f7f34008717 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438805702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2438805702 |
| Directory | /workspace/0.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4008776259 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 418062040 ps |
| CPU time | 1.48 seconds |
| Started | Jan 10 01:10:11 PM PST 24 |
| Finished | Jan 10 01:11:25 PM PST 24 |
| Peak memory | 198196 kb |
| Host | smart-3feaf5aa-0e5b-4120-8ac7-09c98270fbc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008776259 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.gpio_tl_intg_err.4008776259 |
| Directory | /workspace/0.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.4275017879 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 24712284 ps |
| CPU time | 0.64 seconds |
| Started | Jan 10 01:10:07 PM PST 24 |
| Finished | Jan 10 01:11:18 PM PST 24 |
| Peak memory | 194876 kb |
| Host | smart-2fc5ed5d-e681-42c7-b1ee-c72569177902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275017879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_aliasing.4275017879 |
| Directory | /workspace/1.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2407524329 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 525461494 ps |
| CPU time | 3.42 seconds |
| Started | Jan 10 01:10:17 PM PST 24 |
| Finished | Jan 10 01:11:38 PM PST 24 |
| Peak memory | 198176 kb |
| Host | smart-db707dc4-c5b4-4b40-abed-4d051a585899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407524329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2407524329 |
| Directory | /workspace/1.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.309839286 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 18248549 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:10:06 PM PST 24 |
| Finished | Jan 10 01:11:17 PM PST 24 |
| Peak memory | 195260 kb |
| Host | smart-714ef8f5-dccd-4489-8f04-969de0289372 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309839286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.309839286 |
| Directory | /workspace/1.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4254089924 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 29803793 ps |
| CPU time | 0.91 seconds |
| Started | Jan 10 01:10:07 PM PST 24 |
| Finished | Jan 10 01:11:18 PM PST 24 |
| Peak memory | 198200 kb |
| Host | smart-eba88117-a8d3-4aaf-984c-5c07078e5ec4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254089924 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.4254089924 |
| Directory | /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3232289591 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 16236873 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:10:13 PM PST 24 |
| Finished | Jan 10 01:11:32 PM PST 24 |
| Peak memory | 195020 kb |
| Host | smart-fe0ecf0d-fdfb-45f7-a494-0a55f640d3a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232289591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio _csr_rw.3232289591 |
| Directory | /workspace/1.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_intr_test.2550128148 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 14690104 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:09:59 PM PST 24 |
| Finished | Jan 10 01:11:07 PM PST 24 |
| Peak memory | 194776 kb |
| Host | smart-8f8b6fa9-5d03-4414-b64c-217ff1b5f4b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550128148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2550128148 |
| Directory | /workspace/1.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1676908988 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 28023519 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 01:10:18 PM PST 24 |
| Finished | Jan 10 01:11:33 PM PST 24 |
| Peak memory | 196252 kb |
| Host | smart-9cf1f490-474a-4911-94e1-7a399c3225cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676908988 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.gpio_same_csr_outstanding.1676908988 |
| Directory | /workspace/1.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3288614579 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 285913864 ps |
| CPU time | 1.51 seconds |
| Started | Jan 10 01:10:13 PM PST 24 |
| Finished | Jan 10 01:11:32 PM PST 24 |
| Peak memory | 198352 kb |
| Host | smart-30b60f1f-c746-4bed-a6f4-a07115cd4035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288614579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3288614579 |
| Directory | /workspace/1.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1971185099 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1423524704 ps |
| CPU time | 1.28 seconds |
| Started | Jan 10 01:10:12 PM PST 24 |
| Finished | Jan 10 01:11:26 PM PST 24 |
| Peak memory | 198424 kb |
| Host | smart-8bfb0954-4ecb-4c09-a08a-6437a52a87b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971185099 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 1.gpio_tl_intg_err.1971185099 |
| Directory | /workspace/1.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.4027544217 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 55208553 ps |
| CPU time | 0.66 seconds |
| Started | Jan 10 01:10:04 PM PST 24 |
| Finished | Jan 10 01:11:15 PM PST 24 |
| Peak memory | 197584 kb |
| Host | smart-040235dd-76f5-439d-9e1c-9e3b1e0ed6d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027544217 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.4027544217 |
| Directory | /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2536070342 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 108264634 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:09:49 PM PST 24 |
| Finished | Jan 10 01:10:56 PM PST 24 |
| Peak memory | 194864 kb |
| Host | smart-72e73ca2-346f-435d-8e60-23acf03ca6e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536070342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi o_csr_rw.2536070342 |
| Directory | /workspace/10.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_intr_test.1195638685 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 19932514 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:09:51 PM PST 24 |
| Finished | Jan 10 01:10:58 PM PST 24 |
| Peak memory | 194696 kb |
| Host | smart-ca4733f6-601c-43fc-9748-b5c2a4037f46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195638685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1195638685 |
| Directory | /workspace/10.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1892033702 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 22299808 ps |
| CPU time | 0.64 seconds |
| Started | Jan 10 01:10:15 PM PST 24 |
| Finished | Jan 10 01:11:28 PM PST 24 |
| Peak memory | 195028 kb |
| Host | smart-6ae0f5bf-24fa-4ff3-bbf9-992062fa1b30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892033702 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 10.gpio_same_csr_outstanding.1892033702 |
| Directory | /workspace/10.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3350359626 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 200168824 ps |
| CPU time | 3.14 seconds |
| Started | Jan 10 01:10:02 PM PST 24 |
| Finished | Jan 10 01:11:14 PM PST 24 |
| Peak memory | 198504 kb |
| Host | smart-9e2ea7c0-0306-40bf-bffd-06d4cc598874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350359626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3350359626 |
| Directory | /workspace/10.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2598514669 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 91848673 ps |
| CPU time | 1.13 seconds |
| Started | Jan 10 01:10:15 PM PST 24 |
| Finished | Jan 10 01:11:29 PM PST 24 |
| Peak memory | 198280 kb |
| Host | smart-5d6e9019-61b1-4ff1-9043-0168ad604d00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598514669 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 10.gpio_tl_intg_err.2598514669 |
| Directory | /workspace/10.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.483830659 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 54534732 ps |
| CPU time | 0.8 seconds |
| Started | Jan 10 01:09:48 PM PST 24 |
| Finished | Jan 10 01:10:55 PM PST 24 |
| Peak memory | 198260 kb |
| Host | smart-cf5f4e8a-af27-447e-805c-47071fa2b294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483830659 -asser t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.483830659 |
| Directory | /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3417371349 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 11933312 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:10:00 PM PST 24 |
| Finished | Jan 10 01:11:08 PM PST 24 |
| Peak memory | 195664 kb |
| Host | smart-e6945072-9420-4bf3-868b-0391adc2c22e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417371349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi o_csr_rw.3417371349 |
| Directory | /workspace/11.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_intr_test.2227627309 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 21410708 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:09:53 PM PST 24 |
| Finished | Jan 10 01:10:59 PM PST 24 |
| Peak memory | 194104 kb |
| Host | smart-c936fa19-56c3-4049-a95c-83289f9f0c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227627309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2227627309 |
| Directory | /workspace/11.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3830076163 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 21035756 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:09:52 PM PST 24 |
| Finished | Jan 10 01:10:59 PM PST 24 |
| Peak memory | 196572 kb |
| Host | smart-49a4bb7f-f22b-463d-b1a8-dc479d52b9dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830076163 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 11.gpio_same_csr_outstanding.3830076163 |
| Directory | /workspace/11.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2066326539 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 51427383 ps |
| CPU time | 2.38 seconds |
| Started | Jan 10 01:10:02 PM PST 24 |
| Finished | Jan 10 01:11:13 PM PST 24 |
| Peak memory | 198432 kb |
| Host | smart-dedd16f2-d724-492e-9a6b-6a6cd2f78c9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066326539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2066326539 |
| Directory | /workspace/11.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1359287368 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 108170283 ps |
| CPU time | 1.39 seconds |
| Started | Jan 10 01:10:15 PM PST 24 |
| Finished | Jan 10 01:11:30 PM PST 24 |
| Peak memory | 198312 kb |
| Host | smart-c9b69172-ead0-471f-b784-a56f703eeace |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359287368 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 11.gpio_tl_intg_err.1359287368 |
| Directory | /workspace/11.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1268903766 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 49432050 ps |
| CPU time | 0.65 seconds |
| Started | Jan 10 01:10:06 PM PST 24 |
| Finished | Jan 10 01:11:16 PM PST 24 |
| Peak memory | 197964 kb |
| Host | smart-84c902c6-e671-42f6-9dba-557c0ef09a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268903766 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1268903766 |
| Directory | /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4106696917 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 19749891 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:10:05 PM PST 24 |
| Finished | Jan 10 01:11:15 PM PST 24 |
| Peak memory | 194672 kb |
| Host | smart-84785de2-92e5-4fa7-9a9a-1f5d65dd05a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106696917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi o_csr_rw.4106696917 |
| Directory | /workspace/12.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.778911658 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 368678974 ps |
| CPU time | 0.76 seconds |
| Started | Jan 10 01:10:00 PM PST 24 |
| Finished | Jan 10 01:11:08 PM PST 24 |
| Peak memory | 196244 kb |
| Host | smart-18589237-5208-4f97-873a-9b2cddbb91ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778911658 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 12.gpio_same_csr_outstanding.778911658 |
| Directory | /workspace/12.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_tl_errors.632386674 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 212333777 ps |
| CPU time | 3.06 seconds |
| Started | Jan 10 01:09:55 PM PST 24 |
| Finished | Jan 10 01:11:03 PM PST 24 |
| Peak memory | 198444 kb |
| Host | smart-2893dda6-98f8-4705-83cb-5d7147a36b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632386674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.632386674 |
| Directory | /workspace/12.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2323880350 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 229930498 ps |
| CPU time | 0.85 seconds |
| Started | Jan 10 01:10:03 PM PST 24 |
| Finished | Jan 10 01:11:12 PM PST 24 |
| Peak memory | 197164 kb |
| Host | smart-2cb29c1f-be56-4eb9-9f86-85950dd3c6ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323880350 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 12.gpio_tl_intg_err.2323880350 |
| Directory | /workspace/12.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3128149041 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 74531386 ps |
| CPU time | 1.22 seconds |
| Started | Jan 10 01:09:53 PM PST 24 |
| Finished | Jan 10 01:11:00 PM PST 24 |
| Peak memory | 198356 kb |
| Host | smart-27e5d472-4d72-44a4-9386-f10d977ee0ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128149041 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3128149041 |
| Directory | /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_csr_rw.984102912 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 33491025 ps |
| CPU time | 0.64 seconds |
| Started | Jan 10 01:09:58 PM PST 24 |
| Finished | Jan 10 01:11:06 PM PST 24 |
| Peak memory | 195844 kb |
| Host | smart-ab30caa1-10af-4443-839b-b74036b385c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984102912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio _csr_rw.984102912 |
| Directory | /workspace/13.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_intr_test.1485520393 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 18188424 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:10:10 PM PST 24 |
| Finished | Jan 10 01:11:22 PM PST 24 |
| Peak memory | 194676 kb |
| Host | smart-51f01936-2161-4663-a531-7a51c36c42ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485520393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1485520393 |
| Directory | /workspace/13.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.59980463 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 214522270 ps |
| CPU time | 0.74 seconds |
| Started | Jan 10 01:09:46 PM PST 24 |
| Finished | Jan 10 01:10:53 PM PST 24 |
| Peak memory | 196096 kb |
| Host | smart-876a44bc-9d74-4c5d-ac1b-7e6dbd410d0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59980463 -assert nopostproc +UVM_TESTNAME=gpio_base _test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_same_csr_outstanding.59980463 |
| Directory | /workspace/13.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_tl_errors.605964401 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 55669309 ps |
| CPU time | 2.6 seconds |
| Started | Jan 10 01:10:00 PM PST 24 |
| Finished | Jan 10 01:11:11 PM PST 24 |
| Peak memory | 198448 kb |
| Host | smart-a0e2082d-1ae2-497e-8e52-1408fbe8ffda |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605964401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.605964401 |
| Directory | /workspace/13.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1595431434 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 308062509 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:10:03 PM PST 24 |
| Finished | Jan 10 01:11:13 PM PST 24 |
| Peak memory | 197092 kb |
| Host | smart-4b37c5e4-014e-471f-ae7d-22761bf85bf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595431434 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 13.gpio_tl_intg_err.1595431434 |
| Directory | /workspace/13.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3663433179 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 102415848 ps |
| CPU time | 0.98 seconds |
| Started | Jan 10 01:09:56 PM PST 24 |
| Finished | Jan 10 01:11:03 PM PST 24 |
| Peak memory | 198252 kb |
| Host | smart-c3f04dcb-9a78-4a9c-af60-190414a535a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663433179 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3663433179 |
| Directory | /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_csr_rw.729133138 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 76328096 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:09:58 PM PST 24 |
| Finished | Jan 10 01:11:06 PM PST 24 |
| Peak memory | 193964 kb |
| Host | smart-c3ac49cd-ea6a-479b-bf5a-5fa943ae077a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729133138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio _csr_rw.729133138 |
| Directory | /workspace/14.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_intr_test.3280700994 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 17789987 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:10:15 PM PST 24 |
| Finished | Jan 10 01:11:29 PM PST 24 |
| Peak memory | 194144 kb |
| Host | smart-2b5f700f-d5e9-4618-8724-091a156d2975 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280700994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3280700994 |
| Directory | /workspace/14.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.183594821 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 20018731 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:09:54 PM PST 24 |
| Finished | Jan 10 01:11:00 PM PST 24 |
| Peak memory | 197420 kb |
| Host | smart-c7a488b6-5b15-4fea-9282-ec342b1c3767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183594821 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 14.gpio_same_csr_outstanding.183594821 |
| Directory | /workspace/14.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1274020758 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 740419738 ps |
| CPU time | 3.25 seconds |
| Started | Jan 10 01:10:21 PM PST 24 |
| Finished | Jan 10 01:11:39 PM PST 24 |
| Peak memory | 198504 kb |
| Host | smart-37ce0e33-df14-4ade-a6b1-bb4f2fdf1a65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274020758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1274020758 |
| Directory | /workspace/14.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2676844046 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 61837610 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:09:57 PM PST 24 |
| Finished | Jan 10 01:11:05 PM PST 24 |
| Peak memory | 197512 kb |
| Host | smart-7e6328dd-02f4-40d9-b175-a01d86ad260d |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676844046 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 14.gpio_tl_intg_err.2676844046 |
| Directory | /workspace/14.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1205634085 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 330644590 ps |
| CPU time | 0.77 seconds |
| Started | Jan 10 01:09:57 PM PST 24 |
| Finished | Jan 10 01:11:04 PM PST 24 |
| Peak memory | 198280 kb |
| Host | smart-f1302987-e659-46a8-a7ac-fbe390eb8460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205634085 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1205634085 |
| Directory | /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_csr_rw.119352417 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 53215544 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:10:25 PM PST 24 |
| Finished | Jan 10 01:11:43 PM PST 24 |
| Peak memory | 193564 kb |
| Host | smart-7d879f21-5c7a-4060-be13-daf5f722c74c |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119352417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio _csr_rw.119352417 |
| Directory | /workspace/15.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_intr_test.2470622477 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 84261879 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:10:12 PM PST 24 |
| Finished | Jan 10 01:11:25 PM PST 24 |
| Peak memory | 193888 kb |
| Host | smart-73f02fa9-e8e2-47e2-b3a0-b6f7b08b07a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470622477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2470622477 |
| Directory | /workspace/15.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3275350964 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 209979946 ps |
| CPU time | 1.28 seconds |
| Started | Jan 10 01:10:07 PM PST 24 |
| Finished | Jan 10 01:11:18 PM PST 24 |
| Peak memory | 198500 kb |
| Host | smart-f2e75e38-6e8f-44eb-96a6-9159a7d2a334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275350964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3275350964 |
| Directory | /workspace/15.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3512728152 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 121222405 ps |
| CPU time | 1.44 seconds |
| Started | Jan 10 01:10:05 PM PST 24 |
| Finished | Jan 10 01:11:16 PM PST 24 |
| Peak memory | 198376 kb |
| Host | smart-fd74bdf2-2836-4e75-8f2f-2aa6e147cd5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512728152 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 15.gpio_tl_intg_err.3512728152 |
| Directory | /workspace/15.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2711022394 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 25464747 ps |
| CPU time | 0.85 seconds |
| Started | Jan 10 01:10:09 PM PST 24 |
| Finished | Jan 10 01:11:21 PM PST 24 |
| Peak memory | 198236 kb |
| Host | smart-94c4d43b-fc48-40e8-afce-6cde15f42d2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711022394 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2711022394 |
| Directory | /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2346107016 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 25805120 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:10:04 PM PST 24 |
| Finished | Jan 10 01:11:14 PM PST 24 |
| Peak memory | 193464 kb |
| Host | smart-e7da06b9-3801-45a6-8d98-48e4c592ec2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346107016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi o_csr_rw.2346107016 |
| Directory | /workspace/16.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_intr_test.3594947477 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 76705666 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:09:48 PM PST 24 |
| Finished | Jan 10 01:10:55 PM PST 24 |
| Peak memory | 194160 kb |
| Host | smart-dcacd2b9-06cb-416b-a553-c86bffa6b71f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594947477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3594947477 |
| Directory | /workspace/16.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3529183753 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 22711278 ps |
| CPU time | 0.67 seconds |
| Started | Jan 10 01:09:59 PM PST 24 |
| Finished | Jan 10 01:11:08 PM PST 24 |
| Peak memory | 194804 kb |
| Host | smart-38ebf760-ab49-4fb4-831b-e3a65a7c03be |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529183753 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 16.gpio_same_csr_outstanding.3529183753 |
| Directory | /workspace/16.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_tl_errors.913999913 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 215183341 ps |
| CPU time | 1.32 seconds |
| Started | Jan 10 01:10:02 PM PST 24 |
| Finished | Jan 10 01:11:12 PM PST 24 |
| Peak memory | 198400 kb |
| Host | smart-7853e007-01b3-4474-b7b5-0d3ba09b8f80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913999913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.913999913 |
| Directory | /workspace/16.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1588269146 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 32913652 ps |
| CPU time | 1.58 seconds |
| Started | Jan 10 01:10:12 PM PST 24 |
| Finished | Jan 10 01:11:26 PM PST 24 |
| Peak memory | 196868 kb |
| Host | smart-65be462d-ee4c-4482-821d-8853c1997640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588269146 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1588269146 |
| Directory | /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3137128852 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 41837393 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:10:20 PM PST 24 |
| Finished | Jan 10 01:11:39 PM PST 24 |
| Peak memory | 194876 kb |
| Host | smart-ae3fe8cd-cff6-4c35-8075-9f2bfade8916 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137128852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi o_csr_rw.3137128852 |
| Directory | /workspace/17.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_intr_test.694424366 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 19787536 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:10:24 PM PST 24 |
| Finished | Jan 10 01:11:41 PM PST 24 |
| Peak memory | 194648 kb |
| Host | smart-7fd67ce9-b367-4ecb-ab45-2e5f3ef562e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694424366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.694424366 |
| Directory | /workspace/17.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2658039623 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 71890764 ps |
| CPU time | 0.62 seconds |
| Started | Jan 10 01:09:55 PM PST 24 |
| Finished | Jan 10 01:11:02 PM PST 24 |
| Peak memory | 194904 kb |
| Host | smart-986fa6f8-157b-42da-b49b-c977b7103a50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658039623 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 17.gpio_same_csr_outstanding.2658039623 |
| Directory | /workspace/17.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_tl_errors.882520527 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 39175134 ps |
| CPU time | 1.04 seconds |
| Started | Jan 10 01:10:07 PM PST 24 |
| Finished | Jan 10 01:11:19 PM PST 24 |
| Peak memory | 198044 kb |
| Host | smart-72fb662d-3356-46a5-810d-a1c1909c7545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882520527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.882520527 |
| Directory | /workspace/17.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.140404627 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 506122881 ps |
| CPU time | 1.39 seconds |
| Started | Jan 10 01:10:00 PM PST 24 |
| Finished | Jan 10 01:11:10 PM PST 24 |
| Peak memory | 198356 kb |
| Host | smart-d17521de-d539-4ec6-abfb-55f05b48e9df |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140404627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.gpio_tl_intg_err.140404627 |
| Directory | /workspace/17.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2088900427 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 166488521 ps |
| CPU time | 0.72 seconds |
| Started | Jan 10 01:10:01 PM PST 24 |
| Finished | Jan 10 01:11:10 PM PST 24 |
| Peak memory | 198268 kb |
| Host | smart-cdc6e83c-acc7-4ebc-8be4-b8a8f4a876af |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088900427 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2088900427 |
| Directory | /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2429424902 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13661791 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:10:19 PM PST 24 |
| Finished | Jan 10 01:11:35 PM PST 24 |
| Peak memory | 194872 kb |
| Host | smart-44029951-44e4-4d82-bcf6-9de99086dac8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429424902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi o_csr_rw.2429424902 |
| Directory | /workspace/18.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_intr_test.1599266713 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 58186481 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:10:12 PM PST 24 |
| Finished | Jan 10 01:11:25 PM PST 24 |
| Peak memory | 194076 kb |
| Host | smart-d8809649-859c-4116-b6a4-9b2e2761c33c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599266713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1599266713 |
| Directory | /workspace/18.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.844797265 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 83256857 ps |
| CPU time | 0.63 seconds |
| Started | Jan 10 01:10:12 PM PST 24 |
| Finished | Jan 10 01:11:25 PM PST 24 |
| Peak memory | 195060 kb |
| Host | smart-5b9fabf7-7872-4247-b6e6-1df60123cb67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844797265 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 18.gpio_same_csr_outstanding.844797265 |
| Directory | /workspace/18.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_tl_errors.761312536 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 39591404 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:09:58 PM PST 24 |
| Finished | Jan 10 01:11:06 PM PST 24 |
| Peak memory | 198248 kb |
| Host | smart-c378dfd6-3e4d-4ac4-8e32-978d03da2b7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761312536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.761312536 |
| Directory | /workspace/18.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2812730174 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 173124008 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:10:12 PM PST 24 |
| Finished | Jan 10 01:11:25 PM PST 24 |
| Peak memory | 197840 kb |
| Host | smart-2fd299ca-00d5-42ef-a907-305fa6cf5766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812730174 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 18.gpio_tl_intg_err.2812730174 |
| Directory | /workspace/18.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.408124277 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 31816778 ps |
| CPU time | 1.4 seconds |
| Started | Jan 10 01:09:58 PM PST 24 |
| Finished | Jan 10 01:11:06 PM PST 24 |
| Peak memory | 198492 kb |
| Host | smart-8514f19f-4dbd-4cf5-ac2e-ea9d092f4f09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408124277 -asser t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.408124277 |
| Directory | /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2290912286 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 37498002 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:10:09 PM PST 24 |
| Finished | Jan 10 01:11:21 PM PST 24 |
| Peak memory | 194320 kb |
| Host | smart-ec31457c-e94c-4d10-a57d-60a0198e9ef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290912286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi o_csr_rw.2290912286 |
| Directory | /workspace/19.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_intr_test.1130213619 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 64027210 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:10:16 PM PST 24 |
| Finished | Jan 10 01:11:35 PM PST 24 |
| Peak memory | 194128 kb |
| Host | smart-33493d12-0c40-4279-bcd4-6598d9059332 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130213619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1130213619 |
| Directory | /workspace/19.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.200272867 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 326788089 ps |
| CPU time | 0.9 seconds |
| Started | Jan 10 01:10:10 PM PST 24 |
| Finished | Jan 10 01:11:22 PM PST 24 |
| Peak memory | 197588 kb |
| Host | smart-b5d2c2ea-41f4-41fb-8b60-011d50ca8170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200272867 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 19.gpio_same_csr_outstanding.200272867 |
| Directory | /workspace/19.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_tl_errors.492902276 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 240710580 ps |
| CPU time | 2.65 seconds |
| Started | Jan 10 01:10:23 PM PST 24 |
| Finished | Jan 10 01:11:41 PM PST 24 |
| Peak memory | 198308 kb |
| Host | smart-487095e4-b889-4fe7-942c-7ef1575655e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492902276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.492902276 |
| Directory | /workspace/19.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3732562494 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 246667518 ps |
| CPU time | 0.86 seconds |
| Started | Jan 10 01:10:14 PM PST 24 |
| Finished | Jan 10 01:11:28 PM PST 24 |
| Peak memory | 197320 kb |
| Host | smart-fc0025c6-bc39-4d9c-9882-0698cf386f30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732562494 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 19.gpio_tl_intg_err.3732562494 |
| Directory | /workspace/19.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2794681757 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 128112111 ps |
| CPU time | 0.74 seconds |
| Started | Jan 10 01:10:10 PM PST 24 |
| Finished | Jan 10 01:11:22 PM PST 24 |
| Peak memory | 195948 kb |
| Host | smart-ffa277cb-4e15-4e79-acd4-501a8e6771d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794681757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_aliasing.2794681757 |
| Directory | /workspace/2.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4137793090 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 58229214 ps |
| CPU time | 2.08 seconds |
| Started | Jan 10 01:10:08 PM PST 24 |
| Finished | Jan 10 01:11:20 PM PST 24 |
| Peak memory | 197008 kb |
| Host | smart-c135b232-459c-4d8c-8c61-3690909ccb3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137793090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.4137793090 |
| Directory | /workspace/2.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.179213836 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 13068113 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:10:03 PM PST 24 |
| Finished | Jan 10 01:11:13 PM PST 24 |
| Peak memory | 194672 kb |
| Host | smart-a16be512-6816-48f8-8f4e-b703499a36f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179213836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.179213836 |
| Directory | /workspace/2.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1666210252 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 117041177 ps |
| CPU time | 0.84 seconds |
| Started | Jan 10 01:10:00 PM PST 24 |
| Finished | Jan 10 01:11:09 PM PST 24 |
| Peak memory | 198260 kb |
| Host | smart-a6d9e8a4-7b57-48ca-a48d-f264158322ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666210252 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1666210252 |
| Directory | /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2830225186 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 31920494 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:10:04 PM PST 24 |
| Finished | Jan 10 01:11:14 PM PST 24 |
| Peak memory | 195368 kb |
| Host | smart-120f7055-33ab-4ae6-a19d-83bf37e4ed47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830225186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio _csr_rw.2830225186 |
| Directory | /workspace/2.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_intr_test.2459356877 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 31313449 ps |
| CPU time | 0.67 seconds |
| Started | Jan 10 01:10:13 PM PST 24 |
| Finished | Jan 10 01:11:26 PM PST 24 |
| Peak memory | 194132 kb |
| Host | smart-4f1a1dbb-9f12-4a5f-ba60-5d7957075692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459356877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2459356877 |
| Directory | /workspace/2.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.304712895 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 142250365 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 01:09:59 PM PST 24 |
| Finished | Jan 10 01:11:08 PM PST 24 |
| Peak memory | 196548 kb |
| Host | smart-3321bc65-b16e-486b-81bf-c62f56997846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304712895 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.gpio_same_csr_outstanding.304712895 |
| Directory | /workspace/2.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4163126941 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 36288199 ps |
| CPU time | 1.65 seconds |
| Started | Jan 10 01:10:10 PM PST 24 |
| Finished | Jan 10 01:11:23 PM PST 24 |
| Peak memory | 198412 kb |
| Host | smart-7d34226d-9640-4601-8def-5ffc1f5c314e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163126941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.4163126941 |
| Directory | /workspace/2.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.gpio_intr_test.2965062023 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 15357469 ps |
| CPU time | 0.61 seconds |
| Started | Jan 10 01:10:16 PM PST 24 |
| Finished | Jan 10 01:11:43 PM PST 24 |
| Peak memory | 194632 kb |
| Host | smart-30bc96cc-888c-4528-840d-3d05a8e1bdbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965062023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2965062023 |
| Directory | /workspace/20.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.gpio_intr_test.351420713 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 62433549 ps |
| CPU time | 0.67 seconds |
| Started | Jan 10 01:10:09 PM PST 24 |
| Finished | Jan 10 01:11:22 PM PST 24 |
| Peak memory | 194840 kb |
| Host | smart-7cae4a96-5ea5-4033-9bb2-8c3119cd7704 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351420713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.351420713 |
| Directory | /workspace/21.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.gpio_intr_test.1397357943 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 11799027 ps |
| CPU time | 0.62 seconds |
| Started | Jan 10 01:10:15 PM PST 24 |
| Finished | Jan 10 01:11:28 PM PST 24 |
| Peak memory | 194776 kb |
| Host | smart-99538f44-5d17-4715-8c0e-f27b365dfc95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397357943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1397357943 |
| Directory | /workspace/22.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.gpio_intr_test.3311360254 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 12124035 ps |
| CPU time | 0.64 seconds |
| Started | Jan 10 01:10:12 PM PST 24 |
| Finished | Jan 10 01:11:25 PM PST 24 |
| Peak memory | 194808 kb |
| Host | smart-bf6c17ce-aa41-4c60-8968-1769e28680a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311360254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3311360254 |
| Directory | /workspace/23.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.gpio_intr_test.1952059917 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 42972049 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:10:16 PM PST 24 |
| Finished | Jan 10 01:11:30 PM PST 24 |
| Peak memory | 194684 kb |
| Host | smart-7183a1ed-a64a-40fc-9ea5-1fc7304ba34d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952059917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1952059917 |
| Directory | /workspace/24.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.gpio_intr_test.3504270720 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 16052299 ps |
| CPU time | 0.61 seconds |
| Started | Jan 10 01:10:03 PM PST 24 |
| Finished | Jan 10 01:11:12 PM PST 24 |
| Peak memory | 194764 kb |
| Host | smart-57b56696-4110-4bcf-a064-728750b9cdbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504270720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3504270720 |
| Directory | /workspace/25.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.gpio_intr_test.2210840681 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 43160513 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:10:11 PM PST 24 |
| Finished | Jan 10 01:11:23 PM PST 24 |
| Peak memory | 194020 kb |
| Host | smart-cf032ae3-a67b-40e8-825c-93df50492096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210840681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2210840681 |
| Directory | /workspace/26.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.gpio_intr_test.3291548918 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 17904315 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:10:21 PM PST 24 |
| Finished | Jan 10 01:11:37 PM PST 24 |
| Peak memory | 194744 kb |
| Host | smart-71def1b0-7847-4bc8-8153-3906329c668c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291548918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3291548918 |
| Directory | /workspace/27.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.gpio_intr_test.2588072605 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 22617679 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:10:16 PM PST 24 |
| Finished | Jan 10 01:11:29 PM PST 24 |
| Peak memory | 194712 kb |
| Host | smart-c828c8d1-3675-4072-be98-3a9024e2059d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588072605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2588072605 |
| Directory | /workspace/28.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.gpio_intr_test.798289509 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 15477076 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:10:15 PM PST 24 |
| Finished | Jan 10 01:11:29 PM PST 24 |
| Peak memory | 194800 kb |
| Host | smart-2c7f45e3-bfc8-4fec-ac2c-04bc0ebb0850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798289509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.798289509 |
| Directory | /workspace/29.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2306167493 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1566876329 ps |
| CPU time | 1.53 seconds |
| Started | Jan 10 01:10:01 PM PST 24 |
| Finished | Jan 10 01:11:11 PM PST 24 |
| Peak memory | 198216 kb |
| Host | smart-b3ba49f7-214b-4da3-9c00-6791564eea12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306167493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2306167493 |
| Directory | /workspace/3.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3165710912 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 19481645 ps |
| CPU time | 0.63 seconds |
| Started | Jan 10 01:10:08 PM PST 24 |
| Finished | Jan 10 01:11:19 PM PST 24 |
| Peak memory | 194900 kb |
| Host | smart-f252e89c-6978-4e9b-8783-762eececac90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165710912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3165710912 |
| Directory | /workspace/3.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1829367140 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 88728562 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 01:10:06 PM PST 24 |
| Finished | Jan 10 01:11:16 PM PST 24 |
| Peak memory | 198132 kb |
| Host | smart-526d4834-460b-413f-9718-f6507b9133f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829367140 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1829367140 |
| Directory | /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1430620482 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 77353242 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:10:03 PM PST 24 |
| Finished | Jan 10 01:11:12 PM PST 24 |
| Peak memory | 193552 kb |
| Host | smart-078765fd-157d-43f7-96b7-343d3df76d48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430620482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio _csr_rw.1430620482 |
| Directory | /workspace/3.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_intr_test.3677972803 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 14336469 ps |
| CPU time | 0.68 seconds |
| Started | Jan 10 01:10:14 PM PST 24 |
| Finished | Jan 10 01:11:27 PM PST 24 |
| Peak memory | 194168 kb |
| Host | smart-f3335ee1-c335-4156-80dd-0f49b9e2c0a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677972803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3677972803 |
| Directory | /workspace/3.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2940236647 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 32879230 ps |
| CPU time | 0.77 seconds |
| Started | Jan 10 01:10:10 PM PST 24 |
| Finished | Jan 10 01:11:23 PM PST 24 |
| Peak memory | 197232 kb |
| Host | smart-05214b14-dbda-4b04-9351-08de4661b1d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940236647 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.gpio_same_csr_outstanding.2940236647 |
| Directory | /workspace/3.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2947196480 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 26684603 ps |
| CPU time | 1.16 seconds |
| Started | Jan 10 01:10:06 PM PST 24 |
| Finished | Jan 10 01:11:17 PM PST 24 |
| Peak memory | 198332 kb |
| Host | smart-9338be72-16b0-493e-abed-28e1cbc9c75e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947196480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2947196480 |
| Directory | /workspace/3.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.558285527 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 194323290 ps |
| CPU time | 0.89 seconds |
| Started | Jan 10 01:10:02 PM PST 24 |
| Finished | Jan 10 01:11:10 PM PST 24 |
| Peak memory | 197600 kb |
| Host | smart-bc630d58-9641-4dac-a576-b65cd97818dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558285527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.gpio_tl_intg_err.558285527 |
| Directory | /workspace/3.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.gpio_intr_test.4126137437 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 12254686 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:10:13 PM PST 24 |
| Finished | Jan 10 01:11:32 PM PST 24 |
| Peak memory | 193988 kb |
| Host | smart-539403a2-efe8-4f1d-9280-9cf555eb45e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126137437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.4126137437 |
| Directory | /workspace/30.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.gpio_intr_test.2450155724 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 35039450 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:10:24 PM PST 24 |
| Finished | Jan 10 01:11:41 PM PST 24 |
| Peak memory | 194052 kb |
| Host | smart-a2169128-5f7f-468d-ac07-ea2bcbea986f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450155724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2450155724 |
| Directory | /workspace/31.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.gpio_intr_test.3388330326 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 140279279 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:10:23 PM PST 24 |
| Finished | Jan 10 01:11:40 PM PST 24 |
| Peak memory | 194128 kb |
| Host | smart-72268545-9c6a-4e27-b2a5-0ef1ae32d40d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388330326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3388330326 |
| Directory | /workspace/33.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.gpio_intr_test.2663349592 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 48877525 ps |
| CPU time | 0.62 seconds |
| Started | Jan 10 01:10:15 PM PST 24 |
| Finished | Jan 10 01:11:29 PM PST 24 |
| Peak memory | 194804 kb |
| Host | smart-cd29343e-b1d3-478e-a64e-4f956a2e9aec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663349592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2663349592 |
| Directory | /workspace/34.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.gpio_intr_test.2129513709 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 40535980 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:10:19 PM PST 24 |
| Finished | Jan 10 01:11:34 PM PST 24 |
| Peak memory | 193936 kb |
| Host | smart-8d6ded92-c495-4cb1-a5b5-02c040f20e31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129513709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2129513709 |
| Directory | /workspace/35.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.gpio_intr_test.3561318181 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 25753982 ps |
| CPU time | 0.61 seconds |
| Started | Jan 10 01:10:13 PM PST 24 |
| Finished | Jan 10 01:11:26 PM PST 24 |
| Peak memory | 194128 kb |
| Host | smart-ffeb36f6-596b-4abc-bebb-2548a0e351b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561318181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3561318181 |
| Directory | /workspace/36.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.gpio_intr_test.3897441641 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 158906886 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:10:18 PM PST 24 |
| Finished | Jan 10 01:11:33 PM PST 24 |
| Peak memory | 194104 kb |
| Host | smart-92866a26-0987-4598-a3af-a084d69b07a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897441641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3897441641 |
| Directory | /workspace/37.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.gpio_intr_test.2546554567 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 45074026 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:10:01 PM PST 24 |
| Finished | Jan 10 01:11:10 PM PST 24 |
| Peak memory | 194100 kb |
| Host | smart-150e22da-31e7-47c4-9225-e08e123b4a17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546554567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2546554567 |
| Directory | /workspace/38.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.gpio_intr_test.1887387107 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 24599464 ps |
| CPU time | 0.62 seconds |
| Started | Jan 10 01:10:18 PM PST 24 |
| Finished | Jan 10 01:11:33 PM PST 24 |
| Peak memory | 194812 kb |
| Host | smart-293991d4-3f8c-4291-af6c-ad992ab17702 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887387107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1887387107 |
| Directory | /workspace/39.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.644891206 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 13673369 ps |
| CPU time | 0.64 seconds |
| Started | Jan 10 01:10:12 PM PST 24 |
| Finished | Jan 10 01:11:24 PM PST 24 |
| Peak memory | 195584 kb |
| Host | smart-580604fe-1b0e-48a5-a9fe-248daa171393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644891206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4 .gpio_csr_aliasing.644891206 |
| Directory | /workspace/4.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2907821722 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 312866528 ps |
| CPU time | 2.13 seconds |
| Started | Jan 10 01:10:13 PM PST 24 |
| Finished | Jan 10 01:11:28 PM PST 24 |
| Peak memory | 197212 kb |
| Host | smart-7a5bae84-6205-454b-8c99-ff9b270b190e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907821722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2907821722 |
| Directory | /workspace/4.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4185214889 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 37363049 ps |
| CPU time | 0.65 seconds |
| Started | Jan 10 01:10:07 PM PST 24 |
| Finished | Jan 10 01:11:17 PM PST 24 |
| Peak memory | 194960 kb |
| Host | smart-307cddfb-5bee-46a4-abaf-ff9341675ba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185214889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.4185214889 |
| Directory | /workspace/4.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3673148543 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 122292926 ps |
| CPU time | 0.93 seconds |
| Started | Jan 10 01:10:05 PM PST 24 |
| Finished | Jan 10 01:11:16 PM PST 24 |
| Peak memory | 198280 kb |
| Host | smart-3ed2d808-1d1f-4ae6-812d-edcd4d5223dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673148543 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3673148543 |
| Directory | /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3992439474 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 13518342 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:10:05 PM PST 24 |
| Finished | Jan 10 01:11:15 PM PST 24 |
| Peak memory | 194592 kb |
| Host | smart-a2762c42-0260-47e9-a80b-3b1243c3c41d |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992439474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio _csr_rw.3992439474 |
| Directory | /workspace/4.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_intr_test.3030673887 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 18248754 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:10:02 PM PST 24 |
| Finished | Jan 10 01:11:11 PM PST 24 |
| Peak memory | 193956 kb |
| Host | smart-bd97c35b-20f5-487a-b0bb-4960af06a6f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030673887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3030673887 |
| Directory | /workspace/4.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1472561472 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 14956097 ps |
| CPU time | 0.63 seconds |
| Started | Jan 10 01:10:09 PM PST 24 |
| Finished | Jan 10 01:11:21 PM PST 24 |
| Peak memory | 194852 kb |
| Host | smart-f49702be-4296-4218-b9c8-3b383f69b3f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472561472 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.gpio_same_csr_outstanding.1472561472 |
| Directory | /workspace/4.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_tl_errors.93913955 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 186812409 ps |
| CPU time | 2.05 seconds |
| Started | Jan 10 01:10:04 PM PST 24 |
| Finished | Jan 10 01:11:15 PM PST 24 |
| Peak memory | 198292 kb |
| Host | smart-659fb7cd-fcd1-47b8-a188-0ee41dd24967 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93913955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.93913955 |
| Directory | /workspace/4.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.4116759588 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 85602463 ps |
| CPU time | 1.19 seconds |
| Started | Jan 10 01:10:16 PM PST 24 |
| Finished | Jan 10 01:11:30 PM PST 24 |
| Peak memory | 198384 kb |
| Host | smart-34462cb6-1daa-4842-98d5-5722103c1bb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116759588 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.gpio_tl_intg_err.4116759588 |
| Directory | /workspace/4.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.gpio_intr_test.1994893185 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 11753297 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:10:16 PM PST 24 |
| Finished | Jan 10 01:11:30 PM PST 24 |
| Peak memory | 194000 kb |
| Host | smart-bfaa9dde-b7c0-43e5-a6b9-882fc3cdb4eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994893185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1994893185 |
| Directory | /workspace/40.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.gpio_intr_test.3652384955 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 41060161 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:10:17 PM PST 24 |
| Finished | Jan 10 01:11:36 PM PST 24 |
| Peak memory | 194092 kb |
| Host | smart-b12a2f10-6940-434e-a9c3-a4038d6c9e23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652384955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3652384955 |
| Directory | /workspace/41.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.gpio_intr_test.2388469154 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 14128713 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:10:20 PM PST 24 |
| Finished | Jan 10 01:11:39 PM PST 24 |
| Peak memory | 193952 kb |
| Host | smart-cb20fa48-a710-4e28-8fcf-7e0c373853e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388469154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2388469154 |
| Directory | /workspace/42.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.gpio_intr_test.1838401629 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 34895281 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:10:15 PM PST 24 |
| Finished | Jan 10 01:11:28 PM PST 24 |
| Peak memory | 194744 kb |
| Host | smart-e2f44c0b-b465-4644-bde5-806244e55b42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838401629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1838401629 |
| Directory | /workspace/43.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.gpio_intr_test.1978869890 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 50762782 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:10:15 PM PST 24 |
| Finished | Jan 10 01:11:29 PM PST 24 |
| Peak memory | 194740 kb |
| Host | smart-a01caac4-8884-4da9-9cf0-25663a459995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978869890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1978869890 |
| Directory | /workspace/44.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.gpio_intr_test.1061878763 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 24129025 ps |
| CPU time | 0.61 seconds |
| Started | Jan 10 01:10:14 PM PST 24 |
| Finished | Jan 10 01:11:36 PM PST 24 |
| Peak memory | 194724 kb |
| Host | smart-ad3c6290-ee76-490b-93e6-6629d93cb066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061878763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1061878763 |
| Directory | /workspace/45.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.gpio_intr_test.3412537178 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 12564057 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:10:10 PM PST 24 |
| Finished | Jan 10 01:11:23 PM PST 24 |
| Peak memory | 194088 kb |
| Host | smart-b83191a8-043d-474d-ab6f-2e3abb9209b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412537178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3412537178 |
| Directory | /workspace/46.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.gpio_intr_test.1343316094 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 11388465 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:10:10 PM PST 24 |
| Finished | Jan 10 01:11:22 PM PST 24 |
| Peak memory | 194076 kb |
| Host | smart-76f2a42d-92ae-4d26-b227-533fa41157c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343316094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1343316094 |
| Directory | /workspace/47.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.gpio_intr_test.3163177332 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 17423248 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:10:10 PM PST 24 |
| Finished | Jan 10 01:11:22 PM PST 24 |
| Peak memory | 194128 kb |
| Host | smart-589ecab9-10fe-4ec9-9b43-791abc734ea2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163177332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3163177332 |
| Directory | /workspace/48.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.gpio_intr_test.2080928667 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 14416644 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:10:14 PM PST 24 |
| Finished | Jan 10 01:11:27 PM PST 24 |
| Peak memory | 194036 kb |
| Host | smart-216c6569-a3e1-4b71-9896-410f737a42b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080928667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2080928667 |
| Directory | /workspace/49.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1913198587 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 35029215 ps |
| CPU time | 1 seconds |
| Started | Jan 10 01:10:09 PM PST 24 |
| Finished | Jan 10 01:11:22 PM PST 24 |
| Peak memory | 198144 kb |
| Host | smart-80ccf0d2-472d-4c7e-ab73-2fa90be9afdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913198587 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1913198587 |
| Directory | /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4266667967 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 18906260 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:09:53 PM PST 24 |
| Finished | Jan 10 01:10:59 PM PST 24 |
| Peak memory | 195124 kb |
| Host | smart-6d83c8af-8a60-4264-b5be-bf4609fd998d |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266667967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio _csr_rw.4266667967 |
| Directory | /workspace/5.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_intr_test.422227248 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 34440176 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:10:01 PM PST 24 |
| Finished | Jan 10 01:11:10 PM PST 24 |
| Peak memory | 193908 kb |
| Host | smart-92e93797-ddd6-44f0-a225-5ab3406392c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422227248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.422227248 |
| Directory | /workspace/5.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3609180400 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 98741764 ps |
| CPU time | 0.75 seconds |
| Started | Jan 10 01:10:09 PM PST 24 |
| Finished | Jan 10 01:11:22 PM PST 24 |
| Peak memory | 196384 kb |
| Host | smart-e1d09c36-8573-49ab-9fb1-0f389759bedf |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609180400 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 5.gpio_same_csr_outstanding.3609180400 |
| Directory | /workspace/5.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1542761128 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 2037432746 ps |
| CPU time | 2.15 seconds |
| Started | Jan 10 01:10:07 PM PST 24 |
| Finished | Jan 10 01:11:19 PM PST 24 |
| Peak memory | 198540 kb |
| Host | smart-e5fb1220-3677-4e03-87ee-e7d79780a976 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542761128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1542761128 |
| Directory | /workspace/5.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.971192747 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 473137436 ps |
| CPU time | 1.47 seconds |
| Started | Jan 10 01:10:08 PM PST 24 |
| Finished | Jan 10 01:11:21 PM PST 24 |
| Peak memory | 198332 kb |
| Host | smart-ddb8823c-8147-4496-b40a-93ac0cec2a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971192747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.gpio_tl_intg_err.971192747 |
| Directory | /workspace/5.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2809024997 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 19225704 ps |
| CPU time | 0.62 seconds |
| Started | Jan 10 01:09:58 PM PST 24 |
| Finished | Jan 10 01:11:07 PM PST 24 |
| Peak memory | 195736 kb |
| Host | smart-d59bc0a2-bbf5-44cb-a948-123fe4437981 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809024997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio _csr_rw.2809024997 |
| Directory | /workspace/6.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_intr_test.3976285340 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 26327466 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:09:52 PM PST 24 |
| Finished | Jan 10 01:10:59 PM PST 24 |
| Peak memory | 194652 kb |
| Host | smart-ee03bef7-3ccd-4f96-ac26-63edbac28b2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976285340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3976285340 |
| Directory | /workspace/6.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1794635467 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 180378012 ps |
| CPU time | 0.72 seconds |
| Started | Jan 10 01:10:01 PM PST 24 |
| Finished | Jan 10 01:11:10 PM PST 24 |
| Peak memory | 196280 kb |
| Host | smart-534522f8-f726-4be0-ba73-23ca7e6699c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794635467 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 6.gpio_same_csr_outstanding.1794635467 |
| Directory | /workspace/6.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_tl_errors.424763442 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 50974391 ps |
| CPU time | 2.54 seconds |
| Started | Jan 10 01:10:04 PM PST 24 |
| Finished | Jan 10 01:11:16 PM PST 24 |
| Peak memory | 198436 kb |
| Host | smart-feba73a2-16ec-4bcd-b8d6-f62ee39fa488 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424763442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.424763442 |
| Directory | /workspace/6.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.617198919 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 78919352 ps |
| CPU time | 1.13 seconds |
| Started | Jan 10 01:10:14 PM PST 24 |
| Finished | Jan 10 01:11:33 PM PST 24 |
| Peak memory | 198400 kb |
| Host | smart-fd290c27-ff2f-4f04-be4f-ac94da41de67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617198919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.gpio_tl_intg_err.617198919 |
| Directory | /workspace/6.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1847639597 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 107763465 ps |
| CPU time | 0.84 seconds |
| Started | Jan 10 01:09:56 PM PST 24 |
| Finished | Jan 10 01:11:03 PM PST 24 |
| Peak memory | 198312 kb |
| Host | smart-6c78d46a-0cd3-4995-9040-ea96ddd9037f |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847639597 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1847639597 |
| Directory | /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1650498125 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 15014013 ps |
| CPU time | 0.61 seconds |
| Started | Jan 10 01:10:22 PM PST 24 |
| Finished | Jan 10 01:11:38 PM PST 24 |
| Peak memory | 195580 kb |
| Host | smart-9af68854-98ec-418e-bc56-70468c04b973 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650498125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio _csr_rw.1650498125 |
| Directory | /workspace/7.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_intr_test.1430992127 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 10421541 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:10:08 PM PST 24 |
| Finished | Jan 10 01:11:18 PM PST 24 |
| Peak memory | 194032 kb |
| Host | smart-fa35eecc-f157-4be1-b1ef-085a7f38206a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430992127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1430992127 |
| Directory | /workspace/7.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.735894313 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 18197229 ps |
| CPU time | 0.72 seconds |
| Started | Jan 10 01:09:48 PM PST 24 |
| Finished | Jan 10 01:10:55 PM PST 24 |
| Peak memory | 196884 kb |
| Host | smart-f854a78e-3ba3-4e0b-9450-fd74338940c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735894313 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 7.gpio_same_csr_outstanding.735894313 |
| Directory | /workspace/7.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_tl_errors.582702494 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 267927998 ps |
| CPU time | 2.25 seconds |
| Started | Jan 10 01:09:56 PM PST 24 |
| Finished | Jan 10 01:11:04 PM PST 24 |
| Peak memory | 198328 kb |
| Host | smart-bf06aa5d-112c-48a0-9d87-430412e9aa8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582702494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.582702494 |
| Directory | /workspace/7.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.232379869 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 393396962 ps |
| CPU time | 1.41 seconds |
| Started | Jan 10 01:10:05 PM PST 24 |
| Finished | Jan 10 01:11:16 PM PST 24 |
| Peak memory | 198440 kb |
| Host | smart-d9024a79-fbab-4579-af3a-9bc43ae18d5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232379869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.gpio_tl_intg_err.232379869 |
| Directory | /workspace/7.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1104289359 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 55156177 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:09:59 PM PST 24 |
| Finished | Jan 10 01:11:08 PM PST 24 |
| Peak memory | 198260 kb |
| Host | smart-45c37cb3-2b87-43f0-9ec3-38544a2b4714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104289359 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1104289359 |
| Directory | /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1044175722 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 37410427 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:09:52 PM PST 24 |
| Finished | Jan 10 01:10:58 PM PST 24 |
| Peak memory | 193528 kb |
| Host | smart-7a7230d0-6257-4f22-b559-b82850614840 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044175722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio _csr_rw.1044175722 |
| Directory | /workspace/8.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_intr_test.1132729057 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 36366049 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:09:48 PM PST 24 |
| Finished | Jan 10 01:10:55 PM PST 24 |
| Peak memory | 194024 kb |
| Host | smart-f08e5aed-0e09-4619-9e06-e9d7fcf27b28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132729057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1132729057 |
| Directory | /workspace/8.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1991040801 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 30329827 ps |
| CPU time | 0.62 seconds |
| Started | Jan 10 01:10:02 PM PST 24 |
| Finished | Jan 10 01:11:11 PM PST 24 |
| Peak memory | 195648 kb |
| Host | smart-ed7d2446-794b-44b9-bad0-0c460a8ef554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991040801 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 8.gpio_same_csr_outstanding.1991040801 |
| Directory | /workspace/8.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_tl_errors.9252594 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 175154541 ps |
| CPU time | 2.01 seconds |
| Started | Jan 10 01:10:04 PM PST 24 |
| Finished | Jan 10 01:11:15 PM PST 24 |
| Peak memory | 198368 kb |
| Host | smart-904e9c5d-5914-44b9-bb67-ad498a5c1a4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9252594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.9252594 |
| Directory | /workspace/8.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2587648248 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 220055541 ps |
| CPU time | 0.86 seconds |
| Started | Jan 10 01:09:58 PM PST 24 |
| Finished | Jan 10 01:11:06 PM PST 24 |
| Peak memory | 197340 kb |
| Host | smart-b7d4b622-fc02-46fb-9aa4-18cb0ee6ee05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587648248 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 8.gpio_tl_intg_err.2587648248 |
| Directory | /workspace/8.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2089744995 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 32591110 ps |
| CPU time | 0.92 seconds |
| Started | Jan 10 01:09:48 PM PST 24 |
| Finished | Jan 10 01:10:55 PM PST 24 |
| Peak memory | 198260 kb |
| Host | smart-e1ba9f85-1d4f-4e63-8718-afe33370cbcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089744995 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2089744995 |
| Directory | /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_csr_rw.936592658 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 89809238 ps |
| CPU time | 0.61 seconds |
| Started | Jan 10 01:10:13 PM PST 24 |
| Finished | Jan 10 01:11:27 PM PST 24 |
| Peak memory | 195600 kb |
| Host | smart-5c5f65c0-a4cf-40e7-8e4a-1ca2903dfcc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936592658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_ csr_rw.936592658 |
| Directory | /workspace/9.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_intr_test.2270433173 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 16035981 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:10:10 PM PST 24 |
| Finished | Jan 10 01:11:23 PM PST 24 |
| Peak memory | 194112 kb |
| Host | smart-c46f20c0-999c-4cd5-aa1e-42b78627039d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270433173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2270433173 |
| Directory | /workspace/9.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2547920099 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 42454970 ps |
| CPU time | 0.65 seconds |
| Started | Jan 10 01:09:59 PM PST 24 |
| Finished | Jan 10 01:11:08 PM PST 24 |
| Peak memory | 194992 kb |
| Host | smart-030197a0-90d7-49b3-935b-3fb3cb79cc00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547920099 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 9.gpio_same_csr_outstanding.2547920099 |
| Directory | /workspace/9.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1774336652 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 240238148 ps |
| CPU time | 1.4 seconds |
| Started | Jan 10 01:10:00 PM PST 24 |
| Finished | Jan 10 01:11:10 PM PST 24 |
| Peak memory | 198452 kb |
| Host | smart-bc92b64a-fbf4-477e-965b-5ff092db3392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774336652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1774336652 |
| Directory | /workspace/9.gpio_tl_errors/latest |
| Test location | /workspace/coverage/default/0.gpio_alert_test.2748540602 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 13419701 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:11:53 PM PST 24 |
| Finished | Jan 10 01:13:24 PM PST 24 |
| Peak memory | 194944 kb |
| Host | smart-30eaa70e-4458-4750-bbfa-e261e1d4a70d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748540602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2748540602 |
| Directory | /workspace/0.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.594854433 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 111190771 ps |
| CPU time | 0.9 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:13 PM PST 24 |
| Peak memory | 196660 kb |
| Host | smart-3831f912-6977-4dfd-80ae-9c72ed79b8ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594854433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.594854433 |
| Directory | /workspace/0.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/0.gpio_filter_stress.3504631013 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1944064415 ps |
| CPU time | 14.43 seconds |
| Started | Jan 10 01:11:56 PM PST 24 |
| Finished | Jan 10 01:13:34 PM PST 24 |
| Peak memory | 195684 kb |
| Host | smart-2a23d25d-8041-401d-a321-494ffddb99dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504631013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres s.3504631013 |
| Directory | /workspace/0.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/0.gpio_full_random.590516752 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 45573644 ps |
| CPU time | 0.75 seconds |
| Started | Jan 10 01:11:47 PM PST 24 |
| Finished | Jan 10 01:13:02 PM PST 24 |
| Peak memory | 196736 kb |
| Host | smart-9c028b6f-d29f-4112-bf7b-73e8e7b9e2b9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590516752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.590516752 |
| Directory | /workspace/0.gpio_full_random/latest |
| Test location | /workspace/coverage/default/0.gpio_intr_rand_pgm.1134786055 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 72211508 ps |
| CPU time | 1.07 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:07 PM PST 24 |
| Peak memory | 196016 kb |
| Host | smart-f44bc556-7d14-42e8-8c2d-0e90b65581b4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134786055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1134786055 |
| Directory | /workspace/0.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.82640089 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 225731977 ps |
| CPU time | 1.31 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:13 PM PST 24 |
| Peak memory | 197928 kb |
| Host | smart-22cd78ed-60c6-49bc-8cdb-cdd74fdb91c5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82640089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.gpio_intr_with_filter_rand_intr_event.82640089 |
| Directory | /workspace/0.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/0.gpio_rand_intr_trigger.4208843704 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 283543422 ps |
| CPU time | 2.25 seconds |
| Started | Jan 10 01:11:52 PM PST 24 |
| Finished | Jan 10 01:13:21 PM PST 24 |
| Peak memory | 198060 kb |
| Host | smart-219b4870-834e-49df-b0a4-a80e1aca6c1a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208843704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger. 4208843704 |
| Directory | /workspace/0.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/0.gpio_random_dout_din.3743394867 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 30413661 ps |
| CPU time | 1.19 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:07 PM PST 24 |
| Peak memory | 197112 kb |
| Host | smart-5222370f-9788-429d-8c49-655fda29e26d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3743394867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3743394867 |
| Directory | /workspace/0.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3424735999 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 119050915 ps |
| CPU time | 1.34 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:07 PM PST 24 |
| Peak memory | 196008 kb |
| Host | smart-d5962f49-1082-4527-b18d-81cac0826e0d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424735999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup _pulldown.3424735999 |
| Directory | /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2138803819 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 164382956 ps |
| CPU time | 1.29 seconds |
| Started | Jan 10 01:11:51 PM PST 24 |
| Finished | Jan 10 01:13:05 PM PST 24 |
| Peak memory | 198008 kb |
| Host | smart-25edd1d7-6cac-4af3-9ad9-c124f8876b22 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138803819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran dom_long_reg_writes_reg_reads.2138803819 |
| Directory | /workspace/0.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/0.gpio_sec_cm.2679215772 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 36715558 ps |
| CPU time | 0.8 seconds |
| Started | Jan 10 01:11:56 PM PST 24 |
| Finished | Jan 10 01:13:13 PM PST 24 |
| Peak memory | 213520 kb |
| Host | smart-6660b207-86f5-43a4-860e-63bdf3d77dd8 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679215772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2679215772 |
| Directory | /workspace/0.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/0.gpio_smoke.281300114 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 37638669 ps |
| CPU time | 0.73 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:06 PM PST 24 |
| Peak memory | 195212 kb |
| Host | smart-8d911b71-ef7b-4152-bb62-4d6c1c3dcbdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=281300114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.281300114 |
| Directory | /workspace/0.gpio_smoke/latest |
| Test location | /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2810145630 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 44094054 ps |
| CPU time | 1.15 seconds |
| Started | Jan 10 01:11:51 PM PST 24 |
| Finished | Jan 10 01:13:17 PM PST 24 |
| Peak memory | 196396 kb |
| Host | smart-4208ca3d-722a-4a8b-ada8-c4eda0d78824 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810145630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2810145630 |
| Directory | /workspace/0.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/0.gpio_stress_all.2952290435 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 4679947935 ps |
| CPU time | 124.97 seconds |
| Started | Jan 10 01:11:53 PM PST 24 |
| Finished | Jan 10 01:15:15 PM PST 24 |
| Peak memory | 198232 kb |
| Host | smart-e3580844-fd24-4e79-97a9-1535018ae7fc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952290435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g pio_stress_all.2952290435 |
| Directory | /workspace/0.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1350086467 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 37243602059 ps |
| CPU time | 241.04 seconds |
| Started | Jan 10 01:11:53 PM PST 24 |
| Finished | Jan 10 01:17:11 PM PST 24 |
| Peak memory | 198304 kb |
| Host | smart-42e37248-929b-4415-925c-f8c8974fcfa8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1350086467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1350086467 |
| Directory | /workspace/0.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.gpio_alert_test.3229865277 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 24846348 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:06 PM PST 24 |
| Peak memory | 194232 kb |
| Host | smart-47f7cb39-bc74-4996-92f0-6d05a72f6657 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229865277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3229865277 |
| Directory | /workspace/1.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2469259247 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 27718647 ps |
| CPU time | 0.72 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:13 PM PST 24 |
| Peak memory | 195228 kb |
| Host | smart-30d180e4-0f87-4fb9-b59a-bc5eb00c3ab7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469259247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2469259247 |
| Directory | /workspace/1.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/1.gpio_filter_stress.97086047 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 509437026 ps |
| CPU time | 25.66 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:32 PM PST 24 |
| Peak memory | 197108 kb |
| Host | smart-4dbeb6f9-81cc-43c1-8d2b-6463fe453128 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97086047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_ stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress.97086047 |
| Directory | /workspace/1.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/1.gpio_full_random.1656581164 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 133521266 ps |
| CPU time | 0.86 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:13 PM PST 24 |
| Peak memory | 196796 kb |
| Host | smart-a55aa4fb-c85f-42f9-8dd7-0d9cf0b0b306 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656581164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1656581164 |
| Directory | /workspace/1.gpio_full_random/latest |
| Test location | /workspace/coverage/default/1.gpio_intr_rand_pgm.2317338143 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 798788435 ps |
| CPU time | 1.01 seconds |
| Started | Jan 10 01:11:49 PM PST 24 |
| Finished | Jan 10 01:13:05 PM PST 24 |
| Peak memory | 196740 kb |
| Host | smart-c56373c4-eed0-4b7f-967b-75d2cf6f92d3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317338143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2317338143 |
| Directory | /workspace/1.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2434529865 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 92468132 ps |
| CPU time | 3.73 seconds |
| Started | Jan 10 01:11:52 PM PST 24 |
| Finished | Jan 10 01:13:13 PM PST 24 |
| Peak memory | 198116 kb |
| Host | smart-9aafeb21-1407-4441-b02f-a6ddd97726d5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434529865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2434529865 |
| Directory | /workspace/1.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/1.gpio_rand_intr_trigger.1321583561 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1120556028 ps |
| CPU time | 3.27 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:09 PM PST 24 |
| Peak memory | 197260 kb |
| Host | smart-18b0897a-f76f-4c58-9334-96351b560b0b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321583561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger. 1321583561 |
| Directory | /workspace/1.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/1.gpio_random_dout_din.33385113 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 32162964 ps |
| CPU time | 0.65 seconds |
| Started | Jan 10 01:11:47 PM PST 24 |
| Finished | Jan 10 01:13:13 PM PST 24 |
| Peak memory | 194332 kb |
| Host | smart-a79619ae-ea94-42c9-b3a5-caa923f2f392 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33385113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.33385113 |
| Directory | /workspace/1.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.4258919627 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 53476125 ps |
| CPU time | 0.68 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:02 PM PST 24 |
| Peak memory | 194860 kb |
| Host | smart-7b5ad26e-9ed8-46b1-999b-86326da12207 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258919627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup _pulldown.4258919627 |
| Directory | /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1384712338 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 322430713 ps |
| CPU time | 3.77 seconds |
| Started | Jan 10 01:11:49 PM PST 24 |
| Finished | Jan 10 01:13:10 PM PST 24 |
| Peak memory | 198080 kb |
| Host | smart-11c87996-2ca8-46e3-a61d-713a428d5417 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384712338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran dom_long_reg_writes_reg_reads.1384712338 |
| Directory | /workspace/1.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/1.gpio_sec_cm.1098991275 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 98269315 ps |
| CPU time | 0.93 seconds |
| Started | Jan 10 01:12:00 PM PST 24 |
| Finished | Jan 10 01:13:13 PM PST 24 |
| Peak memory | 214688 kb |
| Host | smart-fabd424e-5c8e-4e84-9ed6-1c788b9696de |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098991275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1098991275 |
| Directory | /workspace/1.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/1.gpio_smoke.2461116342 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 142074477 ps |
| CPU time | 0.99 seconds |
| Started | Jan 10 01:11:49 PM PST 24 |
| Finished | Jan 10 01:13:07 PM PST 24 |
| Peak memory | 195872 kb |
| Host | smart-7203b39d-3aeb-4862-940c-790667b5716c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461116342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2461116342 |
| Directory | /workspace/1.gpio_smoke/latest |
| Test location | /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.286364923 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 320550725 ps |
| CPU time | 1.32 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:42 PM PST 24 |
| Peak memory | 195564 kb |
| Host | smart-8b2a6882-7387-4e2b-9c16-d9cc32e8730d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286364923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.286364923 |
| Directory | /workspace/1.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/1.gpio_stress_all.1557487510 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 6384807176 ps |
| CPU time | 161.63 seconds |
| Started | Jan 10 01:11:47 PM PST 24 |
| Finished | Jan 10 01:16:01 PM PST 24 |
| Peak memory | 198460 kb |
| Host | smart-0d8d5da8-0011-479d-bd52-b043aaeff6b5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557487510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g pio_stress_all.1557487510 |
| Directory | /workspace/1.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3230315049 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 215999930644 ps |
| CPU time | 736.75 seconds |
| Started | Jan 10 01:11:47 PM PST 24 |
| Finished | Jan 10 01:25:29 PM PST 24 |
| Peak memory | 206636 kb |
| Host | smart-8158e268-fe0b-48a0-b24a-db3d8746162a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3230315049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.3230315049 |
| Directory | /workspace/1.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.gpio_alert_test.4039750744 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 29901083 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:12:16 PM PST 24 |
| Finished | Jan 10 01:13:38 PM PST 24 |
| Peak memory | 193572 kb |
| Host | smart-b8e5caa8-2226-4925-bc4e-1f7b3cea0406 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039750744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.4039750744 |
| Directory | /workspace/10.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2476931281 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 98679931 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:23 PM PST 24 |
| Peak memory | 196040 kb |
| Host | smart-ea8af0bd-7dce-4dc1-884e-b831a173d58b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2476931281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2476931281 |
| Directory | /workspace/10.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/10.gpio_filter_stress.3517081715 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 2086702970 ps |
| CPU time | 20.53 seconds |
| Started | Jan 10 01:12:09 PM PST 24 |
| Finished | Jan 10 01:13:48 PM PST 24 |
| Peak memory | 196952 kb |
| Host | smart-51c0ec53-8d11-48a2-b632-c1c2a24e5ba9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517081715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre ss.3517081715 |
| Directory | /workspace/10.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/10.gpio_full_random.1788197128 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 154824776 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:23 PM PST 24 |
| Peak memory | 195924 kb |
| Host | smart-3d470300-6d0e-4a9d-a26c-2b3bd2e53f11 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788197128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1788197128 |
| Directory | /workspace/10.gpio_full_random/latest |
| Test location | /workspace/coverage/default/10.gpio_intr_rand_pgm.1510817320 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 21249168 ps |
| CPU time | 0.74 seconds |
| Started | Jan 10 01:12:02 PM PST 24 |
| Finished | Jan 10 01:13:15 PM PST 24 |
| Peak memory | 195308 kb |
| Host | smart-7c988058-932e-4b58-a397-9c6ab7c87295 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510817320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1510817320 |
| Directory | /workspace/10.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3064672963 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 703526578 ps |
| CPU time | 2.52 seconds |
| Started | Jan 10 01:12:13 PM PST 24 |
| Finished | Jan 10 01:13:37 PM PST 24 |
| Peak memory | 198084 kb |
| Host | smart-b78a21c9-6fe9-4237-8eec-645b71286af2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064672963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3064672963 |
| Directory | /workspace/10.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/10.gpio_rand_intr_trigger.442234167 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 69554297 ps |
| CPU time | 1.5 seconds |
| Started | Jan 10 01:12:17 PM PST 24 |
| Finished | Jan 10 01:13:37 PM PST 24 |
| Peak memory | 195832 kb |
| Host | smart-deda9bf1-ed27-42ef-a838-20ebbea2bb25 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442234167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger. 442234167 |
| Directory | /workspace/10.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/10.gpio_random_dout_din.2031645949 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 19189836 ps |
| CPU time | 0.77 seconds |
| Started | Jan 10 01:12:14 PM PST 24 |
| Finished | Jan 10 01:13:56 PM PST 24 |
| Peak memory | 195480 kb |
| Host | smart-47962aeb-f7cb-4e96-88b9-aa35882cb6c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2031645949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2031645949 |
| Directory | /workspace/10.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2194378896 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 164234644 ps |
| CPU time | 3.07 seconds |
| Started | Jan 10 01:12:11 PM PST 24 |
| Finished | Jan 10 01:13:40 PM PST 24 |
| Peak memory | 198080 kb |
| Host | smart-866e838f-9fe9-472e-8057-e8fcfc47fd2b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194378896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra ndom_long_reg_writes_reg_reads.2194378896 |
| Directory | /workspace/10.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/10.gpio_smoke.623579412 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 55603548 ps |
| CPU time | 0.94 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:24 PM PST 24 |
| Peak memory | 197048 kb |
| Host | smart-c91de112-d16c-43fd-bbac-29c9f23c8004 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623579412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.623579412 |
| Directory | /workspace/10.gpio_smoke/latest |
| Test location | /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3898976046 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 120149475 ps |
| CPU time | 1 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:25 PM PST 24 |
| Peak memory | 195768 kb |
| Host | smart-34990c1a-aad7-44d6-b24f-c87e5c35806a |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898976046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3898976046 |
| Directory | /workspace/10.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/10.gpio_stress_all.2326720040 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 102711802601 ps |
| CPU time | 133.52 seconds |
| Started | Jan 10 01:12:12 PM PST 24 |
| Finished | Jan 10 01:15:44 PM PST 24 |
| Peak memory | 198160 kb |
| Host | smart-a2ed815b-715f-4a81-a87b-d63182feb06e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326720040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. gpio_stress_all.2326720040 |
| Directory | /workspace/10.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1557705617 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 56467023108 ps |
| CPU time | 694.31 seconds |
| Started | Jan 10 01:12:12 PM PST 24 |
| Finished | Jan 10 01:25:14 PM PST 24 |
| Peak memory | 198400 kb |
| Host | smart-04eb5031-b217-4262-b3bb-a52ca4ae1208 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1557705617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1557705617 |
| Directory | /workspace/10.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.gpio_alert_test.3043184586 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 13131885 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:41 PM PST 24 |
| Peak memory | 194080 kb |
| Host | smart-9910aec0-9969-4dc7-912b-897f6182809e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043184586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3043184586 |
| Directory | /workspace/11.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1115306599 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 157504767 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:23 PM PST 24 |
| Peak memory | 195216 kb |
| Host | smart-ade4ecf8-ee5a-45b0-a89a-6e9b51266d88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1115306599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1115306599 |
| Directory | /workspace/11.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/11.gpio_filter_stress.1149493440 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1078121972 ps |
| CPU time | 26.51 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:14:08 PM PST 24 |
| Peak memory | 196828 kb |
| Host | smart-bebf83e7-0202-46a0-9872-697ad327cbcd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149493440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre ss.1149493440 |
| Directory | /workspace/11.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/11.gpio_full_random.1543063405 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 181032978 ps |
| CPU time | 0.92 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:24 PM PST 24 |
| Peak memory | 196708 kb |
| Host | smart-ff987dd2-c9ef-4dd8-b8e3-e61d1a16fd66 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543063405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1543063405 |
| Directory | /workspace/11.gpio_full_random/latest |
| Test location | /workspace/coverage/default/11.gpio_intr_rand_pgm.3390446255 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 42268150 ps |
| CPU time | 1.1 seconds |
| Started | Jan 10 01:12:36 PM PST 24 |
| Finished | Jan 10 01:13:58 PM PST 24 |
| Peak memory | 196252 kb |
| Host | smart-a09769d7-8cb2-4990-aa91-e6d8fdf52c0d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390446255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3390446255 |
| Directory | /workspace/11.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.630190018 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 93679424 ps |
| CPU time | 1.84 seconds |
| Started | Jan 10 01:11:59 PM PST 24 |
| Finished | Jan 10 01:13:13 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-1032d869-a0a3-4fb2-8829-9c14b2178a97 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630190018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 11.gpio_intr_with_filter_rand_intr_event.630190018 |
| Directory | /workspace/11.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/11.gpio_rand_intr_trigger.471312154 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 82083824 ps |
| CPU time | 1.82 seconds |
| Started | Jan 10 01:12:57 PM PST 24 |
| Finished | Jan 10 01:14:30 PM PST 24 |
| Peak memory | 196120 kb |
| Host | smart-47713998-4b96-4fad-a98a-6e547c329aa9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471312154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger. 471312154 |
| Directory | /workspace/11.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/11.gpio_random_dout_din.1217210481 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 55258383 ps |
| CPU time | 1.3 seconds |
| Started | Jan 10 01:12:15 PM PST 24 |
| Finished | Jan 10 01:13:36 PM PST 24 |
| Peak memory | 198116 kb |
| Host | smart-e2353ba8-cfae-4629-abe0-4789710d7a0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217210481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1217210481 |
| Directory | /workspace/11.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.900058069 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 127946825 ps |
| CPU time | 0.76 seconds |
| Started | Jan 10 01:12:40 PM PST 24 |
| Finished | Jan 10 01:14:06 PM PST 24 |
| Peak memory | 195492 kb |
| Host | smart-5b251d96-3513-4c3f-bf47-387902e7e8a4 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900058069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup _pulldown.900058069 |
| Directory | /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3879207086 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1914411161 ps |
| CPU time | 5.22 seconds |
| Started | Jan 10 01:12:00 PM PST 24 |
| Finished | Jan 10 01:13:16 PM PST 24 |
| Peak memory | 198252 kb |
| Host | smart-7fd7d440-55e4-497c-ae89-2248cbf7540a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879207086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra ndom_long_reg_writes_reg_reads.3879207086 |
| Directory | /workspace/11.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/11.gpio_smoke.4018650704 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 354315223 ps |
| CPU time | 1.27 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:25 PM PST 24 |
| Peak memory | 196712 kb |
| Host | smart-99e43208-546f-44b3-89d2-77ee547e4682 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018650704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.4018650704 |
| Directory | /workspace/11.gpio_smoke/latest |
| Test location | /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1958707104 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 40365215 ps |
| CPU time | 1.15 seconds |
| Started | Jan 10 01:38:46 PM PST 24 |
| Finished | Jan 10 01:38:48 PM PST 24 |
| Peak memory | 195936 kb |
| Host | smart-4f0e40ef-c834-41f8-87ac-7e695de8a895 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958707104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1958707104 |
| Directory | /workspace/11.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/11.gpio_stress_all.373622442 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 72659012674 ps |
| CPU time | 183.9 seconds |
| Started | Jan 10 01:12:24 PM PST 24 |
| Finished | Jan 10 01:16:46 PM PST 24 |
| Peak memory | 191972 kb |
| Host | smart-48836090-1da5-4a72-97ec-6dac6951b89e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373622442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g pio_stress_all.373622442 |
| Directory | /workspace/11.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.3597719504 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 59963705416 ps |
| CPU time | 480.74 seconds |
| Started | Jan 10 01:12:12 PM PST 24 |
| Finished | Jan 10 01:21:29 PM PST 24 |
| Peak memory | 198376 kb |
| Host | smart-aa77df51-ddbb-4bbb-a21b-c63e2f85cde7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3597719504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.3597719504 |
| Directory | /workspace/11.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.gpio_alert_test.3375170385 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 11239846 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:12:49 PM PST 24 |
| Finished | Jan 10 01:14:13 PM PST 24 |
| Peak memory | 194276 kb |
| Host | smart-c1b13b71-5f96-4574-b9f6-411f0e9529bd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375170385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3375170385 |
| Directory | /workspace/12.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.326373590 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 16119964 ps |
| CPU time | 0.76 seconds |
| Started | Jan 10 01:12:05 PM PST 24 |
| Finished | Jan 10 01:13:20 PM PST 24 |
| Peak memory | 194212 kb |
| Host | smart-c7e320f2-1f79-4f6b-b5e8-1ee9f40896a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326373590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.326373590 |
| Directory | /workspace/12.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/12.gpio_filter_stress.433394886 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 4193965591 ps |
| CPU time | 21.36 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:14:16 PM PST 24 |
| Peak memory | 197028 kb |
| Host | smart-ff0ec51d-92db-4efa-a73d-3a902a28f2f3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433394886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres s.433394886 |
| Directory | /workspace/12.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/12.gpio_full_random.3460087724 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 42579069 ps |
| CPU time | 0.66 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:53 PM PST 24 |
| Peak memory | 194732 kb |
| Host | smart-2917a292-b397-4d9a-8a6c-12aecb222d4e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460087724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3460087724 |
| Directory | /workspace/12.gpio_full_random/latest |
| Test location | /workspace/coverage/default/12.gpio_intr_rand_pgm.3962381666 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 170369861 ps |
| CPU time | 1.43 seconds |
| Started | Jan 10 01:12:35 PM PST 24 |
| Finished | Jan 10 01:13:59 PM PST 24 |
| Peak memory | 197016 kb |
| Host | smart-e4641948-91d5-4bc0-a06d-145e179924e8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962381666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3962381666 |
| Directory | /workspace/12.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/12.gpio_rand_intr_trigger.3141672324 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 109905852 ps |
| CPU time | 3.04 seconds |
| Started | Jan 10 01:12:36 PM PST 24 |
| Finished | Jan 10 01:14:00 PM PST 24 |
| Peak memory | 198096 kb |
| Host | smart-685ad1ed-986a-448c-bbe9-ebd3524f809e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141672324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger .3141672324 |
| Directory | /workspace/12.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/12.gpio_random_dout_din.1266483011 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 27026344 ps |
| CPU time | 1 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:45 PM PST 24 |
| Peak memory | 196116 kb |
| Host | smart-ad1929cb-f810-4429-a830-ae21784b3cd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266483011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1266483011 |
| Directory | /workspace/12.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.356662941 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 298325490 ps |
| CPU time | 1.34 seconds |
| Started | Jan 10 01:12:13 PM PST 24 |
| Finished | Jan 10 01:13:36 PM PST 24 |
| Peak memory | 197072 kb |
| Host | smart-133386c7-0894-438e-ad75-31bec670e169 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356662941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup _pulldown.356662941 |
| Directory | /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3079631887 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 211274984 ps |
| CPU time | 1.15 seconds |
| Started | Jan 10 01:12:24 PM PST 24 |
| Finished | Jan 10 01:13:56 PM PST 24 |
| Peak memory | 197116 kb |
| Host | smart-fd6872a7-7542-4aec-a1b1-c7d4fe3679f0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079631887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra ndom_long_reg_writes_reg_reads.3079631887 |
| Directory | /workspace/12.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/12.gpio_smoke.2383946009 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 154915900 ps |
| CPU time | 1.16 seconds |
| Started | Jan 10 01:12:38 PM PST 24 |
| Finished | Jan 10 01:14:01 PM PST 24 |
| Peak memory | 195948 kb |
| Host | smart-323d3433-db55-4687-b131-9b3182d710ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2383946009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2383946009 |
| Directory | /workspace/12.gpio_smoke/latest |
| Test location | /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2005473293 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 78767524 ps |
| CPU time | 0.92 seconds |
| Started | Jan 10 01:12:13 PM PST 24 |
| Finished | Jan 10 01:13:36 PM PST 24 |
| Peak memory | 196284 kb |
| Host | smart-2639bf70-9547-4cba-9e51-2d4403d148e1 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005473293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2005473293 |
| Directory | /workspace/12.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/12.gpio_stress_all.3810823416 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 8898259032 ps |
| CPU time | 94.98 seconds |
| Started | Jan 10 01:12:05 PM PST 24 |
| Finished | Jan 10 01:14:54 PM PST 24 |
| Peak memory | 198288 kb |
| Host | smart-94241241-b2bf-428d-a5ed-0bc419c29c95 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810823416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. gpio_stress_all.3810823416 |
| Directory | /workspace/12.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3313867310 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 62254187494 ps |
| CPU time | 194.27 seconds |
| Started | Jan 10 01:12:41 PM PST 24 |
| Finished | Jan 10 01:17:17 PM PST 24 |
| Peak memory | 198412 kb |
| Host | smart-bb0669d9-3b60-43f2-8cac-453fdfefa6c9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3313867310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3313867310 |
| Directory | /workspace/12.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.gpio_alert_test.2649097490 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 41323367 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:12:09 PM PST 24 |
| Finished | Jan 10 01:13:26 PM PST 24 |
| Peak memory | 194976 kb |
| Host | smart-453769a2-5c0f-43aa-98f6-c5bcfe386e48 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649097490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2649097490 |
| Directory | /workspace/13.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.452901947 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 477654665 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:12:17 PM PST 24 |
| Finished | Jan 10 01:13:38 PM PST 24 |
| Peak memory | 196704 kb |
| Host | smart-1809a157-347b-4f35-b56e-c4c89698b182 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452901947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.452901947 |
| Directory | /workspace/13.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/13.gpio_filter_stress.3554617669 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 358640327 ps |
| CPU time | 17.69 seconds |
| Started | Jan 10 01:12:57 PM PST 24 |
| Finished | Jan 10 01:14:40 PM PST 24 |
| Peak memory | 196912 kb |
| Host | smart-d48d31ff-53cb-4219-8c21-da29b274888a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554617669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre ss.3554617669 |
| Directory | /workspace/13.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/13.gpio_full_random.2915487856 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 118127384 ps |
| CPU time | 1 seconds |
| Started | Jan 10 01:12:45 PM PST 24 |
| Finished | Jan 10 01:14:13 PM PST 24 |
| Peak memory | 196848 kb |
| Host | smart-dc98365d-17f4-4f32-a25c-65b48d15b76f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915487856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2915487856 |
| Directory | /workspace/13.gpio_full_random/latest |
| Test location | /workspace/coverage/default/13.gpio_intr_rand_pgm.2743499538 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 620698120 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:22 PM PST 24 |
| Peak memory | 195500 kb |
| Host | smart-92133a71-f8cc-4577-a19f-e3c0b14889b6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743499538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2743499538 |
| Directory | /workspace/13.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1718921448 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 103515939 ps |
| CPU time | 2.87 seconds |
| Started | Jan 10 01:12:31 PM PST 24 |
| Finished | Jan 10 01:13:54 PM PST 24 |
| Peak memory | 198168 kb |
| Host | smart-9dca704f-0dfa-44af-8809-e40eefafbc68 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718921448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1718921448 |
| Directory | /workspace/13.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/13.gpio_rand_intr_trigger.1536076743 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 110055098 ps |
| CPU time | 2.86 seconds |
| Started | Jan 10 01:12:28 PM PST 24 |
| Finished | Jan 10 01:13:53 PM PST 24 |
| Peak memory | 197104 kb |
| Host | smart-92e60d51-30c3-4ab8-881a-f341dbf9bef7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536076743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger .1536076743 |
| Directory | /workspace/13.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/13.gpio_random_dout_din.3799366065 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 29515452 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:25 PM PST 24 |
| Peak memory | 197272 kb |
| Host | smart-ea7f6bd3-6e87-4f18-acc8-84f8a34806ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3799366065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3799366065 |
| Directory | /workspace/13.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2012775835 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 200428735 ps |
| CPU time | 1.2 seconds |
| Started | Jan 10 01:12:09 PM PST 24 |
| Finished | Jan 10 01:13:34 PM PST 24 |
| Peak memory | 195944 kb |
| Host | smart-d4b1e09e-3ea0-4e71-8549-3ddd5375ea96 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012775835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu p_pulldown.2012775835 |
| Directory | /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2531134484 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 30462610 ps |
| CPU time | 1.27 seconds |
| Started | Jan 10 01:12:16 PM PST 24 |
| Finished | Jan 10 01:13:38 PM PST 24 |
| Peak memory | 198076 kb |
| Host | smart-f05698be-9a3b-4345-8050-13c547bf4a9a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531134484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra ndom_long_reg_writes_reg_reads.2531134484 |
| Directory | /workspace/13.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/13.gpio_smoke.2903839403 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 39476086 ps |
| CPU time | 1.18 seconds |
| Started | Jan 10 01:12:14 PM PST 24 |
| Finished | Jan 10 01:13:39 PM PST 24 |
| Peak memory | 195944 kb |
| Host | smart-73a68d45-8556-487d-9af4-727b2ae8f6ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903839403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2903839403 |
| Directory | /workspace/13.gpio_smoke/latest |
| Test location | /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3011686551 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 91152848 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 01:12:13 PM PST 24 |
| Finished | Jan 10 01:13:35 PM PST 24 |
| Peak memory | 195340 kb |
| Host | smart-9d23cafa-dbf7-4385-8438-9fa04bca0a6c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011686551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3011686551 |
| Directory | /workspace/13.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/13.gpio_stress_all.1574309411 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 50639629837 ps |
| CPU time | 150.73 seconds |
| Started | Jan 10 01:12:09 PM PST 24 |
| Finished | Jan 10 01:16:05 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-0704a322-3e29-41af-a198-64ee9f353ce5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574309411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. gpio_stress_all.1574309411 |
| Directory | /workspace/13.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3952780237 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 115392983975 ps |
| CPU time | 420.93 seconds |
| Started | Jan 10 01:12:14 PM PST 24 |
| Finished | Jan 10 01:20:48 PM PST 24 |
| Peak memory | 198376 kb |
| Host | smart-eb93b346-984f-4898-9c36-8f62a76c1fae |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3952780237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3952780237 |
| Directory | /workspace/13.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.gpio_alert_test.1634125346 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 28825549 ps |
| CPU time | 0.62 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:36 PM PST 24 |
| Peak memory | 194244 kb |
| Host | smart-7f7634b5-c7bd-440e-9f0d-78fa960e2516 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634125346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1634125346 |
| Directory | /workspace/14.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2670032507 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 17264869 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:12:11 PM PST 24 |
| Finished | Jan 10 01:13:32 PM PST 24 |
| Peak memory | 193820 kb |
| Host | smart-fe8a9f34-f92b-4925-bc28-5bac2d6394bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670032507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2670032507 |
| Directory | /workspace/14.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/14.gpio_filter_stress.2460082413 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 3004761292 ps |
| CPU time | 23.67 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:59 PM PST 24 |
| Peak memory | 198172 kb |
| Host | smart-40762dfd-a668-4575-a56c-29ba84a5cc3b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460082413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre ss.2460082413 |
| Directory | /workspace/14.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/14.gpio_full_random.1337037867 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 47470763 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:12:29 PM PST 24 |
| Finished | Jan 10 01:13:54 PM PST 24 |
| Peak memory | 196040 kb |
| Host | smart-a559bf7c-0b0d-4f12-8884-1af290e87a30 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337037867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1337037867 |
| Directory | /workspace/14.gpio_full_random/latest |
| Test location | /workspace/coverage/default/14.gpio_intr_rand_pgm.378223930 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 25013604 ps |
| CPU time | 0.7 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:24 PM PST 24 |
| Peak memory | 195032 kb |
| Host | smart-3711cc1b-5a31-4fd2-8760-7da60d332c70 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378223930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.378223930 |
| Directory | /workspace/14.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1985146851 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 75811523 ps |
| CPU time | 1.52 seconds |
| Started | Jan 10 01:12:49 PM PST 24 |
| Finished | Jan 10 01:14:18 PM PST 24 |
| Peak memory | 196996 kb |
| Host | smart-3627e917-d174-4ee5-bfc9-2a76f8c44a03 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985146851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1985146851 |
| Directory | /workspace/14.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/14.gpio_rand_intr_trigger.3873428362 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 560295650 ps |
| CPU time | 1.71 seconds |
| Started | Jan 10 01:12:12 PM PST 24 |
| Finished | Jan 10 01:13:42 PM PST 24 |
| Peak memory | 195764 kb |
| Host | smart-2447c2e1-fd62-4204-a714-ee39d00a2402 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873428362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger .3873428362 |
| Directory | /workspace/14.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/14.gpio_random_dout_din.1443951592 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 38842434 ps |
| CPU time | 0.84 seconds |
| Started | Jan 10 01:12:12 PM PST 24 |
| Finished | Jan 10 01:13:29 PM PST 24 |
| Peak memory | 196416 kb |
| Host | smart-a92573ba-6df6-4590-97b2-34c3853f1821 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1443951592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1443951592 |
| Directory | /workspace/14.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1295233829 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 40190538 ps |
| CPU time | 0.93 seconds |
| Started | Jan 10 01:12:20 PM PST 24 |
| Finished | Jan 10 01:13:53 PM PST 24 |
| Peak memory | 195948 kb |
| Host | smart-d609135c-9891-49c9-a7aa-2d2291cff88c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295233829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu p_pulldown.1295233829 |
| Directory | /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2496777927 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 544978509 ps |
| CPU time | 2.63 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:46 PM PST 24 |
| Peak memory | 198144 kb |
| Host | smart-802f4ae0-300c-49fb-9324-0638a1453591 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496777927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra ndom_long_reg_writes_reg_reads.2496777927 |
| Directory | /workspace/14.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/14.gpio_smoke.1502867802 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 38734727 ps |
| CPU time | 1.04 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:21 PM PST 24 |
| Peak memory | 195848 kb |
| Host | smart-3a68e2e4-9062-48ae-9f36-10d2c9eb520a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502867802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1502867802 |
| Directory | /workspace/14.gpio_smoke/latest |
| Test location | /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2649301593 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 243864381 ps |
| CPU time | 1.15 seconds |
| Started | Jan 10 01:12:36 PM PST 24 |
| Finished | Jan 10 01:13:58 PM PST 24 |
| Peak memory | 195828 kb |
| Host | smart-ef097bfc-c67c-4a03-b062-4b18accc7954 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649301593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2649301593 |
| Directory | /workspace/14.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/14.gpio_stress_all.3037345959 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 160509636108 ps |
| CPU time | 155.93 seconds |
| Started | Jan 10 01:12:09 PM PST 24 |
| Finished | Jan 10 01:16:02 PM PST 24 |
| Peak memory | 198292 kb |
| Host | smart-1b8406da-ac5b-4126-b2a3-b4e55dd8e54d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037345959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. gpio_stress_all.3037345959 |
| Directory | /workspace/14.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3353024381 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 54190240603 ps |
| CPU time | 360.98 seconds |
| Started | Jan 10 01:12:31 PM PST 24 |
| Finished | Jan 10 01:19:52 PM PST 24 |
| Peak memory | 198388 kb |
| Host | smart-828f003f-70fc-4950-8730-2e6daad56b6b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3353024381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3353024381 |
| Directory | /workspace/14.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.974725069 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 173389213 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:12:23 PM PST 24 |
| Finished | Jan 10 01:13:44 PM PST 24 |
| Peak memory | 196584 kb |
| Host | smart-dfb21c36-a454-4613-bf5c-c4323e2584b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974725069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.974725069 |
| Directory | /workspace/15.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/15.gpio_filter_stress.4280446129 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1928673826 ps |
| CPU time | 24.62 seconds |
| Started | Jan 10 01:12:23 PM PST 24 |
| Finished | Jan 10 01:14:08 PM PST 24 |
| Peak memory | 197064 kb |
| Host | smart-5d0b785e-6e75-45b8-8a26-fceb7bfdd046 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280446129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre ss.4280446129 |
| Directory | /workspace/15.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/15.gpio_full_random.814326624 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 77139882 ps |
| CPU time | 0.66 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:36 PM PST 24 |
| Peak memory | 194700 kb |
| Host | smart-8a57c08c-432a-4bbf-89a3-27a0757e12a0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814326624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.814326624 |
| Directory | /workspace/15.gpio_full_random/latest |
| Test location | /workspace/coverage/default/15.gpio_intr_rand_pgm.71989929 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 41200625 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:41 PM PST 24 |
| Peak memory | 196132 kb |
| Host | smart-84f56551-929c-46aa-839a-dd3aa0eaed6b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71989929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.71989929 |
| Directory | /workspace/15.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2066377964 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 49045871 ps |
| CPU time | 1.12 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:45 PM PST 24 |
| Peak memory | 198100 kb |
| Host | smart-add7737a-411e-4331-a17e-cbbb364654f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066377964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2066377964 |
| Directory | /workspace/15.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/15.gpio_rand_intr_trigger.1894807876 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 309040803 ps |
| CPU time | 3.11 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:13:42 PM PST 24 |
| Peak memory | 196000 kb |
| Host | smart-13d7b38b-aa93-409f-bf99-4539f68ca3e3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894807876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger .1894807876 |
| Directory | /workspace/15.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/15.gpio_random_dout_din.1889136133 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 18918441 ps |
| CPU time | 0.76 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:14:25 PM PST 24 |
| Peak memory | 196196 kb |
| Host | smart-fc20863b-1160-4245-8b86-541c0d212c48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889136133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1889136133 |
| Directory | /workspace/15.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3814929876 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 45827681 ps |
| CPU time | 0.93 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:13:41 PM PST 24 |
| Peak memory | 196668 kb |
| Host | smart-2e585289-f129-4b8d-8979-f20b820ca864 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814929876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu p_pulldown.3814929876 |
| Directory | /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3320452998 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1065231684 ps |
| CPU time | 4.37 seconds |
| Started | Jan 10 01:12:28 PM PST 24 |
| Finished | Jan 10 01:14:18 PM PST 24 |
| Peak memory | 198108 kb |
| Host | smart-f2c08f8a-0b7d-472c-8313-899b542cc02e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320452998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra ndom_long_reg_writes_reg_reads.3320452998 |
| Directory | /workspace/15.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/15.gpio_smoke.4224783901 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 667039684 ps |
| CPU time | 1.09 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:37 PM PST 24 |
| Peak memory | 195544 kb |
| Host | smart-d4fb7f2e-ac41-4d6f-9400-17d9fc572e5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4224783901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.4224783901 |
| Directory | /workspace/15.gpio_smoke/latest |
| Test location | /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1752596208 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 66336896 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:22 PM PST 24 |
| Peak memory | 196136 kb |
| Host | smart-261297b1-2abb-43d8-bd79-e75b1e707612 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752596208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1752596208 |
| Directory | /workspace/15.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/15.gpio_stress_all.3039313383 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 87830761993 ps |
| CPU time | 177.58 seconds |
| Started | Jan 10 01:12:15 PM PST 24 |
| Finished | Jan 10 01:16:29 PM PST 24 |
| Peak memory | 198288 kb |
| Host | smart-5f0c11b0-e6f9-4231-9032-1b89d4b2c964 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039313383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. gpio_stress_all.3039313383 |
| Directory | /workspace/15.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/16.gpio_alert_test.1688798571 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 39833401 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:13:39 PM PST 24 |
| Peak memory | 194764 kb |
| Host | smart-4a4d9c6c-df4f-4acc-b548-8185a31be335 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688798571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1688798571 |
| Directory | /workspace/16.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4086793382 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 46589732 ps |
| CPU time | 0.75 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:43 PM PST 24 |
| Peak memory | 196136 kb |
| Host | smart-38e5ff8f-f345-480c-b75b-be627d062c51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4086793382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4086793382 |
| Directory | /workspace/16.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/16.gpio_filter_stress.2475159306 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 5195656106 ps |
| CPU time | 24.52 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:14:01 PM PST 24 |
| Peak memory | 198136 kb |
| Host | smart-3a519a78-36c0-4a27-99e0-f7dc643d2479 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475159306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre ss.2475159306 |
| Directory | /workspace/16.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/16.gpio_full_random.3143337864 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 71387457 ps |
| CPU time | 1 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:48 PM PST 24 |
| Peak memory | 197744 kb |
| Host | smart-3df16eeb-e0a1-4358-9b6b-9bbeffea6f58 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143337864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3143337864 |
| Directory | /workspace/16.gpio_full_random/latest |
| Test location | /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.4272438098 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 869191601 ps |
| CPU time | 2.89 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:58 PM PST 24 |
| Peak memory | 197944 kb |
| Host | smart-ef82146d-885e-4272-9c7d-2168dcf85c76 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272438098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.gpio_intr_with_filter_rand_intr_event.4272438098 |
| Directory | /workspace/16.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/16.gpio_rand_intr_trigger.2052914722 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 173030379 ps |
| CPU time | 1.17 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:13:40 PM PST 24 |
| Peak memory | 195684 kb |
| Host | smart-a5b37b1c-5f5f-48c3-9ac9-efe9aa6e8342 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052914722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger .2052914722 |
| Directory | /workspace/16.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/16.gpio_random_dout_din.3540798766 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 150308767 ps |
| CPU time | 1.07 seconds |
| Started | Jan 10 01:12:16 PM PST 24 |
| Finished | Jan 10 01:13:35 PM PST 24 |
| Peak memory | 196180 kb |
| Host | smart-22bacc90-5e77-440f-b5b8-b69fdad5b533 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3540798766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3540798766 |
| Directory | /workspace/16.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2870731570 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 20136856 ps |
| CPU time | 0.61 seconds |
| Started | Jan 10 01:12:20 PM PST 24 |
| Finished | Jan 10 01:13:44 PM PST 24 |
| Peak memory | 194272 kb |
| Host | smart-f204bc47-0c96-423d-869f-8044ead319ba |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870731570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu p_pulldown.2870731570 |
| Directory | /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1494704072 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3063652528 ps |
| CPU time | 6.7 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:59 PM PST 24 |
| Peak memory | 198164 kb |
| Host | smart-c632c5ef-cdff-4187-b310-e744268db138 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494704072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra ndom_long_reg_writes_reg_reads.1494704072 |
| Directory | /workspace/16.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/16.gpio_smoke.2287100507 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 254804953 ps |
| CPU time | 1.2 seconds |
| Started | Jan 10 01:12:12 PM PST 24 |
| Finished | Jan 10 01:13:30 PM PST 24 |
| Peak memory | 196492 kb |
| Host | smart-26aa4b7d-7258-4d9c-ba2e-b3f6d2098a65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2287100507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2287100507 |
| Directory | /workspace/16.gpio_smoke/latest |
| Test location | /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2651437375 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 87606911 ps |
| CPU time | 0.92 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:43 PM PST 24 |
| Peak memory | 196328 kb |
| Host | smart-b09ae85a-a0b2-4ea7-a83d-ca7c5c1dc08b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651437375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2651437375 |
| Directory | /workspace/16.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/16.gpio_stress_all.3290638763 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 30765693617 ps |
| CPU time | 169.71 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:16:45 PM PST 24 |
| Peak memory | 198180 kb |
| Host | smart-941cf8f1-74ae-41f8-a2f1-9c12f7c04fcf |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290638763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. gpio_stress_all.3290638763 |
| Directory | /workspace/16.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3338524041 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 57239070388 ps |
| CPU time | 775.78 seconds |
| Started | Jan 10 01:12:24 PM PST 24 |
| Finished | Jan 10 01:26:43 PM PST 24 |
| Peak memory | 198288 kb |
| Host | smart-8967c2e0-9062-4e73-87bb-a52fa98ce859 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3338524041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3338524041 |
| Directory | /workspace/16.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.gpio_alert_test.2310540279 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 38377161 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:12:33 PM PST 24 |
| Finished | Jan 10 01:13:57 PM PST 24 |
| Peak memory | 194284 kb |
| Host | smart-2a9c83c0-2bb6-47c6-8ffd-badeee034075 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310540279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2310540279 |
| Directory | /workspace/17.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.195537729 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 68448485 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:12:31 PM PST 24 |
| Finished | Jan 10 01:13:52 PM PST 24 |
| Peak memory | 195308 kb |
| Host | smart-4291cfd9-b381-4df3-9dd3-9dbcfb94b1c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195537729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.195537729 |
| Directory | /workspace/17.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/17.gpio_filter_stress.48733432 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 7522888669 ps |
| CPU time | 15.44 seconds |
| Started | Jan 10 01:12:27 PM PST 24 |
| Finished | Jan 10 01:14:00 PM PST 24 |
| Peak memory | 197208 kb |
| Host | smart-6b7cb2d7-149f-4ec0-a173-33dc30b070d6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48733432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_ stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stress .48733432 |
| Directory | /workspace/17.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/17.gpio_full_random.1893211501 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 95002231 ps |
| CPU time | 0.8 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:13:53 PM PST 24 |
| Peak memory | 196544 kb |
| Host | smart-ac07aab0-7e9c-488d-977e-ca4fbdbf3a77 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893211501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1893211501 |
| Directory | /workspace/17.gpio_full_random/latest |
| Test location | /workspace/coverage/default/17.gpio_intr_rand_pgm.3101875437 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 214325759 ps |
| CPU time | 0.92 seconds |
| Started | Jan 10 01:12:31 PM PST 24 |
| Finished | Jan 10 01:14:09 PM PST 24 |
| Peak memory | 196968 kb |
| Host | smart-043b2bb4-7c45-4c5a-8e01-e9fb2ec343c1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101875437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3101875437 |
| Directory | /workspace/17.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3963663843 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 87156406 ps |
| CPU time | 0.96 seconds |
| Started | Jan 10 01:12:43 PM PST 24 |
| Finished | Jan 10 01:14:07 PM PST 24 |
| Peak memory | 196080 kb |
| Host | smart-579750fd-093a-4d60-882e-735ef8fa0a83 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963663843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3963663843 |
| Directory | /workspace/17.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/17.gpio_rand_intr_trigger.2514832568 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 322173653 ps |
| CPU time | 2 seconds |
| Started | Jan 10 01:12:36 PM PST 24 |
| Finished | Jan 10 01:13:59 PM PST 24 |
| Peak memory | 196736 kb |
| Host | smart-c715e8b5-2b6d-42e2-baf9-af1cb28ed372 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514832568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger .2514832568 |
| Directory | /workspace/17.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/17.gpio_random_dout_din.3274840657 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 488593569 ps |
| CPU time | 0.96 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:13:37 PM PST 24 |
| Peak memory | 196824 kb |
| Host | smart-ea32a497-60e9-4239-b616-1181352a06e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3274840657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3274840657 |
| Directory | /workspace/17.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1219098999 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 35160148 ps |
| CPU time | 1.26 seconds |
| Started | Jan 10 01:12:46 PM PST 24 |
| Finished | Jan 10 01:14:10 PM PST 24 |
| Peak memory | 196612 kb |
| Host | smart-87cb646d-17b8-4f8d-8fc2-35b057da05aa |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219098999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu p_pulldown.1219098999 |
| Directory | /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1391987258 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 66269629 ps |
| CPU time | 3.07 seconds |
| Started | Jan 10 01:12:30 PM PST 24 |
| Finished | Jan 10 01:14:05 PM PST 24 |
| Peak memory | 198136 kb |
| Host | smart-f96c55fd-a2bb-4f06-b23a-c9abb02c33b9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391987258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra ndom_long_reg_writes_reg_reads.1391987258 |
| Directory | /workspace/17.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/17.gpio_smoke.3372663965 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 65550812 ps |
| CPU time | 1.25 seconds |
| Started | Jan 10 01:12:17 PM PST 24 |
| Finished | Jan 10 01:13:36 PM PST 24 |
| Peak memory | 197224 kb |
| Host | smart-4ae0c7f2-ca51-4bb8-a64a-2927e28f97c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3372663965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3372663965 |
| Directory | /workspace/17.gpio_smoke/latest |
| Test location | /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2044325274 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 102365065 ps |
| CPU time | 1.34 seconds |
| Started | Jan 10 01:12:39 PM PST 24 |
| Finished | Jan 10 01:14:01 PM PST 24 |
| Peak memory | 196980 kb |
| Host | smart-546f5b43-a9f4-4cb0-bde9-91077f586a9e |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044325274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2044325274 |
| Directory | /workspace/17.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/17.gpio_stress_all.1886769200 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 12943518149 ps |
| CPU time | 183.7 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:16:47 PM PST 24 |
| Peak memory | 198260 kb |
| Host | smart-af8ac695-1031-4389-9c9f-a498ccb36f3a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886769200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. gpio_stress_all.1886769200 |
| Directory | /workspace/17.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.264163010 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 82509926764 ps |
| CPU time | 940.51 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:29:20 PM PST 24 |
| Peak memory | 198424 kb |
| Host | smart-63d79260-9537-4d7c-92d0-f7ccf17a2fbf |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =264163010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.264163010 |
| Directory | /workspace/17.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/18.gpio_alert_test.1163207702 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 13289700 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:12:50 PM PST 24 |
| Finished | Jan 10 01:14:18 PM PST 24 |
| Peak memory | 194736 kb |
| Host | smart-1786866c-8cb6-4e5c-9ed1-f6840349b55a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163207702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1163207702 |
| Directory | /workspace/18.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2148574286 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 83388234 ps |
| CPU time | 0.73 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:37 PM PST 24 |
| Peak memory | 196036 kb |
| Host | smart-f24b8f52-3137-4a9f-818b-c5ed4824e4ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148574286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2148574286 |
| Directory | /workspace/18.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/18.gpio_filter_stress.540304018 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 558790455 ps |
| CPU time | 19.06 seconds |
| Started | Jan 10 01:12:24 PM PST 24 |
| Finished | Jan 10 01:14:06 PM PST 24 |
| Peak memory | 196988 kb |
| Host | smart-20e4f36b-385e-40f8-8b2e-38541f3eafe0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540304018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres s.540304018 |
| Directory | /workspace/18.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/18.gpio_full_random.417450669 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 24405202 ps |
| CPU time | 0.67 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:40 PM PST 24 |
| Peak memory | 195460 kb |
| Host | smart-360a371e-5975-4401-acfa-2b19fd832af8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417450669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.417450669 |
| Directory | /workspace/18.gpio_full_random/latest |
| Test location | /workspace/coverage/default/18.gpio_intr_rand_pgm.631628631 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 234894254 ps |
| CPU time | 0.99 seconds |
| Started | Jan 10 01:12:41 PM PST 24 |
| Finished | Jan 10 01:14:17 PM PST 24 |
| Peak memory | 195960 kb |
| Host | smart-d3c26ddc-eded-4745-bca2-ff1e10403fad |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631628631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.631628631 |
| Directory | /workspace/18.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3682053252 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 254767775 ps |
| CPU time | 2.77 seconds |
| Started | Jan 10 01:12:30 PM PST 24 |
| Finished | Jan 10 01:14:05 PM PST 24 |
| Peak memory | 198176 kb |
| Host | smart-f5792a21-8fbe-47b6-8eff-afe3c0edeb91 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682053252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3682053252 |
| Directory | /workspace/18.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/18.gpio_rand_intr_trigger.1725619810 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 244204254 ps |
| CPU time | 1.46 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:13:53 PM PST 24 |
| Peak memory | 196764 kb |
| Host | smart-06f0d490-b57d-4d67-8039-243fc756a02c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725619810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger .1725619810 |
| Directory | /workspace/18.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/18.gpio_random_dout_din.2346497259 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 737177502 ps |
| CPU time | 1.11 seconds |
| Started | Jan 10 01:12:17 PM PST 24 |
| Finished | Jan 10 01:13:39 PM PST 24 |
| Peak memory | 196068 kb |
| Host | smart-662eea38-3d25-40a8-95d6-40429fa2a5b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346497259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2346497259 |
| Directory | /workspace/18.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.4098506960 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 74809291 ps |
| CPU time | 1.29 seconds |
| Started | Jan 10 01:12:13 PM PST 24 |
| Finished | Jan 10 01:13:36 PM PST 24 |
| Peak memory | 195892 kb |
| Host | smart-3d817aff-9855-41e6-a203-e0d66cc7992f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098506960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu p_pulldown.4098506960 |
| Directory | /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2176667298 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 554417765 ps |
| CPU time | 5.71 seconds |
| Started | Jan 10 01:12:21 PM PST 24 |
| Finished | Jan 10 01:13:44 PM PST 24 |
| Peak memory | 198176 kb |
| Host | smart-8d4b7625-63ea-4748-8d05-acb92aecad87 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176667298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra ndom_long_reg_writes_reg_reads.2176667298 |
| Directory | /workspace/18.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/18.gpio_smoke.534197845 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 323506480 ps |
| CPU time | 1.22 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:40 PM PST 24 |
| Peak memory | 195900 kb |
| Host | smart-1c1d3377-bcd1-47ea-95de-bd2599b1e141 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534197845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.534197845 |
| Directory | /workspace/18.gpio_smoke/latest |
| Test location | /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2075322074 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 364597971 ps |
| CPU time | 0.79 seconds |
| Started | Jan 10 01:12:20 PM PST 24 |
| Finished | Jan 10 01:13:44 PM PST 24 |
| Peak memory | 196184 kb |
| Host | smart-c8fcebe0-10f3-488c-b5cf-6a070d1cd02d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075322074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2075322074 |
| Directory | /workspace/18.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/18.gpio_stress_all.3201124121 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 7911503170 ps |
| CPU time | 109.21 seconds |
| Started | Jan 10 01:12:23 PM PST 24 |
| Finished | Jan 10 01:15:30 PM PST 24 |
| Peak memory | 198284 kb |
| Host | smart-8ea48d8a-c191-4b65-b07d-88cd6e91db58 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201124121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. gpio_stress_all.3201124121 |
| Directory | /workspace/18.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3341798613 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 322221081772 ps |
| CPU time | 878.84 seconds |
| Started | Jan 10 01:12:32 PM PST 24 |
| Finished | Jan 10 01:28:31 PM PST 24 |
| Peak memory | 206556 kb |
| Host | smart-a10ff4d1-7171-46d2-a25b-54dfec067fd5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3341798613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3341798613 |
| Directory | /workspace/18.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.gpio_alert_test.604983500 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 33727365 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:42 PM PST 24 |
| Peak memory | 194780 kb |
| Host | smart-004b10f7-d315-4391-9386-98f246e73638 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604983500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.604983500 |
| Directory | /workspace/19.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1090693536 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 316124009 ps |
| CPU time | 0.74 seconds |
| Started | Jan 10 01:12:12 PM PST 24 |
| Finished | Jan 10 01:13:29 PM PST 24 |
| Peak memory | 195376 kb |
| Host | smart-2788b8af-5193-4aa7-a5b5-e556789f77e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090693536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1090693536 |
| Directory | /workspace/19.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/19.gpio_filter_stress.3120658199 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 683113371 ps |
| CPU time | 20.18 seconds |
| Started | Jan 10 01:12:23 PM PST 24 |
| Finished | Jan 10 01:14:04 PM PST 24 |
| Peak memory | 198180 kb |
| Host | smart-2846a27f-37cf-44b1-b011-19b8cb3ef7f1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120658199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre ss.3120658199 |
| Directory | /workspace/19.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/19.gpio_full_random.2834848056 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 95755125 ps |
| CPU time | 0.67 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:13:41 PM PST 24 |
| Peak memory | 194628 kb |
| Host | smart-793c1f3b-6fbe-46fe-a3f1-c7254242b0a1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834848056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2834848056 |
| Directory | /workspace/19.gpio_full_random/latest |
| Test location | /workspace/coverage/default/19.gpio_intr_rand_pgm.3633467571 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 88324589 ps |
| CPU time | 0.7 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:13:41 PM PST 24 |
| Peak memory | 195484 kb |
| Host | smart-eb3b2da1-ecdc-40cd-a3b9-1fb0bf15c0a4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633467571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3633467571 |
| Directory | /workspace/19.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.4125896927 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 50550667 ps |
| CPU time | 2 seconds |
| Started | Jan 10 01:12:30 PM PST 24 |
| Finished | Jan 10 01:13:50 PM PST 24 |
| Peak memory | 198152 kb |
| Host | smart-414c1c7b-e243-4319-a512-f9f4c5a6f497 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125896927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.gpio_intr_with_filter_rand_intr_event.4125896927 |
| Directory | /workspace/19.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/19.gpio_rand_intr_trigger.698413680 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 65477249 ps |
| CPU time | 1.45 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:40 PM PST 24 |
| Peak memory | 196328 kb |
| Host | smart-1d425053-348c-4e42-9af0-3e313bd17904 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698413680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger. 698413680 |
| Directory | /workspace/19.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/19.gpio_random_dout_din.3263704315 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 80286282 ps |
| CPU time | 0.97 seconds |
| Started | Jan 10 01:12:10 PM PST 24 |
| Finished | Jan 10 01:13:27 PM PST 24 |
| Peak memory | 195876 kb |
| Host | smart-45f8260a-e11e-414f-a362-5695134feb63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263704315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3263704315 |
| Directory | /workspace/19.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2133583461 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 381288645 ps |
| CPU time | 0.84 seconds |
| Started | Jan 10 01:12:39 PM PST 24 |
| Finished | Jan 10 01:14:05 PM PST 24 |
| Peak memory | 196464 kb |
| Host | smart-cfaa729e-fb7b-4b65-923d-e797c3505016 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133583461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu p_pulldown.2133583461 |
| Directory | /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3843045570 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 125877354 ps |
| CPU time | 1.82 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:49 PM PST 24 |
| Peak memory | 197992 kb |
| Host | smart-6a693a33-9df1-4d6d-bfe8-c3d533a9aae7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843045570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra ndom_long_reg_writes_reg_reads.3843045570 |
| Directory | /workspace/19.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/19.gpio_smoke.3848891047 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 328269007 ps |
| CPU time | 1.36 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:37 PM PST 24 |
| Peak memory | 196848 kb |
| Host | smart-1911a856-7117-43cc-9b9b-8251bd8dfcb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848891047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3848891047 |
| Directory | /workspace/19.gpio_smoke/latest |
| Test location | /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2810483983 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 140384957 ps |
| CPU time | 1.03 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:39 PM PST 24 |
| Peak memory | 196712 kb |
| Host | smart-d880dc9b-f5e2-4f36-9aef-258860b7d5ad |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810483983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2810483983 |
| Directory | /workspace/19.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/19.gpio_stress_all.977778357 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 10639263609 ps |
| CPU time | 132.28 seconds |
| Started | Jan 10 01:12:21 PM PST 24 |
| Finished | Jan 10 01:15:51 PM PST 24 |
| Peak memory | 198216 kb |
| Host | smart-db3d221b-3ca5-40f7-823f-2f09954858ed |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977778357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g pio_stress_all.977778357 |
| Directory | /workspace/19.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.703135229 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 71895785503 ps |
| CPU time | 1108.31 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:32:07 PM PST 24 |
| Peak memory | 198360 kb |
| Host | smart-ca8715a5-7c5b-47f3-97d4-f68de6447fa6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =703135229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.703135229 |
| Directory | /workspace/19.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.gpio_alert_test.2043753674 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 14884743 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:06 PM PST 24 |
| Peak memory | 194024 kb |
| Host | smart-f87401d3-958c-4d7f-bc65-e25b06da235e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043753674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2043753674 |
| Directory | /workspace/2.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1101701735 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 134516792 ps |
| CPU time | 0.63 seconds |
| Started | Jan 10 01:11:47 PM PST 24 |
| Finished | Jan 10 01:13:13 PM PST 24 |
| Peak memory | 194964 kb |
| Host | smart-95bd3e06-6f1f-4acc-802a-0301a468a8b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101701735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1101701735 |
| Directory | /workspace/2.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/2.gpio_filter_stress.4088664961 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 3037905302 ps |
| CPU time | 25.18 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:31 PM PST 24 |
| Peak memory | 197148 kb |
| Host | smart-2b97127f-0385-40ce-aa30-bd9caba1d1de |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088664961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres s.4088664961 |
| Directory | /workspace/2.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/2.gpio_full_random.3517677751 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 765061392 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:13 PM PST 24 |
| Peak memory | 196096 kb |
| Host | smart-86837ab1-4c31-42fa-9275-84d89be51d1b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517677751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3517677751 |
| Directory | /workspace/2.gpio_full_random/latest |
| Test location | /workspace/coverage/default/2.gpio_intr_rand_pgm.701442754 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 27008321 ps |
| CPU time | 0.89 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:02 PM PST 24 |
| Peak memory | 196464 kb |
| Host | smart-3f0f2ca0-5570-4202-a463-016c69369427 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701442754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.701442754 |
| Directory | /workspace/2.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2467852833 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 176124255 ps |
| CPU time | 3.33 seconds |
| Started | Jan 10 01:11:53 PM PST 24 |
| Finished | Jan 10 01:13:19 PM PST 24 |
| Peak memory | 198292 kb |
| Host | smart-e31e1607-8f3d-4e9a-a66d-a3417bd05a3f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467852833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2467852833 |
| Directory | /workspace/2.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/2.gpio_rand_intr_trigger.2562254135 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 73780732 ps |
| CPU time | 2.03 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:03 PM PST 24 |
| Peak memory | 197152 kb |
| Host | smart-5e86fafc-2b56-499b-b417-f853d47e492f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562254135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger. 2562254135 |
| Directory | /workspace/2.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/2.gpio_random_dout_din.89593044 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 63526493 ps |
| CPU time | 1.22 seconds |
| Started | Jan 10 01:11:49 PM PST 24 |
| Finished | Jan 10 01:13:07 PM PST 24 |
| Peak memory | 198084 kb |
| Host | smart-ee4cc3fb-224e-4922-a74c-d9c0e1c60ac3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89593044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.89593044 |
| Directory | /workspace/2.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2779171006 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 302500252 ps |
| CPU time | 0.99 seconds |
| Started | Jan 10 01:11:49 PM PST 24 |
| Finished | Jan 10 01:13:07 PM PST 24 |
| Peak memory | 196960 kb |
| Host | smart-a77a17c8-ebf7-4a0f-854a-4efe2db4131d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779171006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup _pulldown.2779171006 |
| Directory | /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1244154388 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 50211724 ps |
| CPU time | 1.11 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:02 PM PST 24 |
| Peak memory | 196740 kb |
| Host | smart-1bcb88e8-3576-4fb9-bcca-955560d2ca86 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244154388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran dom_long_reg_writes_reg_reads.1244154388 |
| Directory | /workspace/2.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/2.gpio_smoke.417426186 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 62025747 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:02 PM PST 24 |
| Peak memory | 195820 kb |
| Host | smart-16b41c98-6690-4180-915d-aec7d99614c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=417426186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.417426186 |
| Directory | /workspace/2.gpio_smoke/latest |
| Test location | /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2998329785 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 257708201 ps |
| CPU time | 1.1 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:02 PM PST 24 |
| Peak memory | 195920 kb |
| Host | smart-5c08d299-f678-4129-9b7a-0c2ef0186407 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998329785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2998329785 |
| Directory | /workspace/2.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/2.gpio_stress_all.2259220436 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 7200984571 ps |
| CPU time | 165.37 seconds |
| Started | Jan 10 01:11:50 PM PST 24 |
| Finished | Jan 10 01:16:02 PM PST 24 |
| Peak memory | 198292 kb |
| Host | smart-a7f22be4-c5e0-4a70-aa9e-38c5e35cf24a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259220436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g pio_stress_all.2259220436 |
| Directory | /workspace/2.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.4146992238 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 98805501653 ps |
| CPU time | 694.27 seconds |
| Started | Jan 10 01:11:49 PM PST 24 |
| Finished | Jan 10 01:24:38 PM PST 24 |
| Peak memory | 198292 kb |
| Host | smart-33f00f71-fa73-4ded-8407-371506a02328 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4146992238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.4146992238 |
| Directory | /workspace/2.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.gpio_alert_test.748779818 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 13889178 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:42 PM PST 24 |
| Peak memory | 194672 kb |
| Host | smart-5a6407eb-baa8-4369-9110-b2ff05f74a80 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748779818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.748779818 |
| Directory | /workspace/20.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.743639163 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 35275899 ps |
| CPU time | 0.93 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:44 PM PST 24 |
| Peak memory | 196052 kb |
| Host | smart-bf0ea41b-8e0e-4a69-a740-e6be51761bf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=743639163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.743639163 |
| Directory | /workspace/20.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/20.gpio_filter_stress.1618783600 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1810377063 ps |
| CPU time | 13.37 seconds |
| Started | Jan 10 01:12:20 PM PST 24 |
| Finished | Jan 10 01:14:02 PM PST 24 |
| Peak memory | 197028 kb |
| Host | smart-beebcc2b-549a-430b-8182-3aad53c5dd1e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618783600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre ss.1618783600 |
| Directory | /workspace/20.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/20.gpio_full_random.1113190314 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 44034455 ps |
| CPU time | 0.7 seconds |
| Started | Jan 10 01:12:36 PM PST 24 |
| Finished | Jan 10 01:13:57 PM PST 24 |
| Peak memory | 194948 kb |
| Host | smart-0c702ad7-a4a4-4d47-8be2-56029f648e95 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113190314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1113190314 |
| Directory | /workspace/20.gpio_full_random/latest |
| Test location | /workspace/coverage/default/20.gpio_intr_rand_pgm.2048715269 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 159240158 ps |
| CPU time | 1.39 seconds |
| Started | Jan 10 01:12:36 PM PST 24 |
| Finished | Jan 10 01:13:59 PM PST 24 |
| Peak memory | 196952 kb |
| Host | smart-20c22881-5afd-4f1e-9a37-69bd57bfe9b3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048715269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2048715269 |
| Directory | /workspace/20.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.961637269 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 303086394 ps |
| CPU time | 3.11 seconds |
| Started | Jan 10 01:13:01 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 198208 kb |
| Host | smart-dbe79cf3-182b-4480-b55d-49c0de9e9f8c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961637269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 20.gpio_intr_with_filter_rand_intr_event.961637269 |
| Directory | /workspace/20.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/20.gpio_rand_intr_trigger.957528658 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 109953519 ps |
| CPU time | 1.47 seconds |
| Started | Jan 10 01:12:20 PM PST 24 |
| Finished | Jan 10 01:13:46 PM PST 24 |
| Peak memory | 196148 kb |
| Host | smart-3c09bb98-18ab-492a-9917-0d6d74347217 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957528658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger. 957528658 |
| Directory | /workspace/20.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/20.gpio_random_dout_din.1093926672 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 91632986 ps |
| CPU time | 0.91 seconds |
| Started | Jan 10 01:12:28 PM PST 24 |
| Finished | Jan 10 01:14:05 PM PST 24 |
| Peak memory | 195848 kb |
| Host | smart-fd29544a-129d-4e5b-b3cb-01d03247de06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093926672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1093926672 |
| Directory | /workspace/20.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2287087955 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 30414551 ps |
| CPU time | 1.08 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:43 PM PST 24 |
| Peak memory | 196124 kb |
| Host | smart-0bd3c0f2-788b-436b-bf10-86a074653e1e |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287087955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu p_pulldown.2287087955 |
| Directory | /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3224663137 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 287007774 ps |
| CPU time | 1.53 seconds |
| Started | Jan 10 01:13:06 PM PST 24 |
| Finished | Jan 10 01:14:34 PM PST 24 |
| Peak memory | 197928 kb |
| Host | smart-e7a58ead-9a5c-4954-b722-bc4c6efc7330 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224663137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra ndom_long_reg_writes_reg_reads.3224663137 |
| Directory | /workspace/20.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2925058555 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 146764989 ps |
| CPU time | 1.03 seconds |
| Started | Jan 10 01:12:24 PM PST 24 |
| Finished | Jan 10 01:13:43 PM PST 24 |
| Peak memory | 195708 kb |
| Host | smart-48243f7d-2782-43cb-af49-7c88b1752e46 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925058555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2925058555 |
| Directory | /workspace/20.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/20.gpio_stress_all.4148827899 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3128242149 ps |
| CPU time | 31.66 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:14:12 PM PST 24 |
| Peak memory | 198292 kb |
| Host | smart-7788a83d-c6e4-4de1-a138-47c426e7a7f8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148827899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. gpio_stress_all.4148827899 |
| Directory | /workspace/20.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2498537287 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 167321434062 ps |
| CPU time | 385.37 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:20:18 PM PST 24 |
| Peak memory | 198416 kb |
| Host | smart-0c1688d8-0ac7-4658-8be5-23fd3e283fa3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2498537287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2498537287 |
| Directory | /workspace/20.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2912944410 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 108151828 ps |
| CPU time | 0.75 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:43 PM PST 24 |
| Peak memory | 195264 kb |
| Host | smart-48142520-bab6-438f-94f7-64b6f2991b29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912944410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2912944410 |
| Directory | /workspace/21.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/21.gpio_filter_stress.1434946957 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 2550985803 ps |
| CPU time | 21.36 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:14:00 PM PST 24 |
| Peak memory | 196936 kb |
| Host | smart-bf2f1f21-8d48-42e8-b338-865903403895 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434946957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre ss.1434946957 |
| Directory | /workspace/21.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/21.gpio_full_random.132035099 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 44369686 ps |
| CPU time | 0.76 seconds |
| Started | Jan 10 01:12:24 PM PST 24 |
| Finished | Jan 10 01:13:53 PM PST 24 |
| Peak memory | 196008 kb |
| Host | smart-5c244bd9-736d-4a24-9455-d517267bf3d1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132035099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.132035099 |
| Directory | /workspace/21.gpio_full_random/latest |
| Test location | /workspace/coverage/default/21.gpio_intr_rand_pgm.3713476513 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 312121363 ps |
| CPU time | 1.13 seconds |
| Started | Jan 10 01:12:30 PM PST 24 |
| Finished | Jan 10 01:13:49 PM PST 24 |
| Peak memory | 196004 kb |
| Host | smart-bb0b13d3-cd49-4d8e-bb66-4bda0c60e33f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713476513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3713476513 |
| Directory | /workspace/21.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3724819672 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 34917602 ps |
| CPU time | 1.43 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:37 PM PST 24 |
| Peak memory | 196736 kb |
| Host | smart-bb7e9cbf-86e5-4348-9d82-a82ba2b3b740 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724819672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3724819672 |
| Directory | /workspace/21.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/21.gpio_rand_intr_trigger.2844365729 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 170353304 ps |
| CPU time | 3.22 seconds |
| Started | Jan 10 01:12:31 PM PST 24 |
| Finished | Jan 10 01:13:54 PM PST 24 |
| Peak memory | 198100 kb |
| Host | smart-be5d8e73-0f71-4ce6-b036-bf777326a731 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844365729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger .2844365729 |
| Directory | /workspace/21.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.4148731753 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 477844561 ps |
| CPU time | 1.21 seconds |
| Started | Jan 10 01:12:52 PM PST 24 |
| Finished | Jan 10 01:14:16 PM PST 24 |
| Peak memory | 195940 kb |
| Host | smart-f2ef88b4-68b4-487d-8997-e76895cf6bdb |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148731753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu p_pulldown.4148731753 |
| Directory | /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1449555888 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 437367571 ps |
| CPU time | 5.74 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:14:45 PM PST 24 |
| Peak memory | 198004 kb |
| Host | smart-b1198242-cd72-4d25-91e7-3bc367c96401 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449555888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra ndom_long_reg_writes_reg_reads.1449555888 |
| Directory | /workspace/21.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/21.gpio_smoke.2453127921 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 31503709 ps |
| CPU time | 0.88 seconds |
| Started | Jan 10 01:13:10 PM PST 24 |
| Finished | Jan 10 01:14:37 PM PST 24 |
| Peak memory | 196348 kb |
| Host | smart-16d72eee-ee81-4fc6-b0d7-87162566c975 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2453127921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2453127921 |
| Directory | /workspace/21.gpio_smoke/latest |
| Test location | /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2600935429 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 198907584 ps |
| CPU time | 1.1 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:48 PM PST 24 |
| Peak memory | 196372 kb |
| Host | smart-03901053-b61e-41ad-8df6-0c4ea0f16907 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600935429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2600935429 |
| Directory | /workspace/21.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/21.gpio_stress_all.1520737544 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 12844824308 ps |
| CPU time | 186.96 seconds |
| Started | Jan 10 01:13:23 PM PST 24 |
| Finished | Jan 10 01:18:03 PM PST 24 |
| Peak memory | 198268 kb |
| Host | smart-62463088-42c2-4df2-b168-7d05b3dbc705 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520737544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. gpio_stress_all.1520737544 |
| Directory | /workspace/21.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.115015867 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 61393859006 ps |
| CPU time | 979.34 seconds |
| Started | Jan 10 01:13:28 PM PST 24 |
| Finished | Jan 10 01:31:11 PM PST 24 |
| Peak memory | 198200 kb |
| Host | smart-03f16ccf-fa5f-4c2c-97d6-c59edb175741 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =115015867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.115015867 |
| Directory | /workspace/21.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.gpio_alert_test.4137634896 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 41708037 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:43 PM PST 24 |
| Peak memory | 194080 kb |
| Host | smart-303b18c9-9f15-4857-98a6-4647abcc777e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137634896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.4137634896 |
| Directory | /workspace/22.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1392605141 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 114794557 ps |
| CPU time | 0.88 seconds |
| Started | Jan 10 01:13:10 PM PST 24 |
| Finished | Jan 10 01:14:36 PM PST 24 |
| Peak memory | 197396 kb |
| Host | smart-12b86614-1fba-4996-a093-098b04ebf76b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392605141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1392605141 |
| Directory | /workspace/22.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/22.gpio_filter_stress.1357198015 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1262757062 ps |
| CPU time | 19.28 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:13:55 PM PST 24 |
| Peak memory | 196448 kb |
| Host | smart-1e871f20-0d69-40ff-b6d2-99f9a41733c0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357198015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre ss.1357198015 |
| Directory | /workspace/22.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/22.gpio_full_random.3156679886 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 84543247 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:40 PM PST 24 |
| Peak memory | 196772 kb |
| Host | smart-bbcd3866-1589-4c64-a421-8c1b47b0d98c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156679886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3156679886 |
| Directory | /workspace/22.gpio_full_random/latest |
| Test location | /workspace/coverage/default/22.gpio_intr_rand_pgm.974194050 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 161699480 ps |
| CPU time | 1.22 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:48 PM PST 24 |
| Peak memory | 197104 kb |
| Host | smart-2e741ee5-0985-45a3-90a4-6fc04d4a815c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974194050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.974194050 |
| Directory | /workspace/22.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2684335759 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 58935973 ps |
| CPU time | 2.3 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:41 PM PST 24 |
| Peak memory | 198324 kb |
| Host | smart-f63f5d34-629c-4941-b0b0-1a0af00ff3e0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684335759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2684335759 |
| Directory | /workspace/22.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/22.gpio_rand_intr_trigger.4052711405 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 606041418 ps |
| CPU time | 1.99 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:44 PM PST 24 |
| Peak memory | 196344 kb |
| Host | smart-24362015-acb2-4717-ac29-a51034ebd07f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052711405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger .4052711405 |
| Directory | /workspace/22.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/22.gpio_random_dout_din.1641191687 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 52368558 ps |
| CPU time | 0.7 seconds |
| Started | Jan 10 01:12:31 PM PST 24 |
| Finished | Jan 10 01:13:52 PM PST 24 |
| Peak memory | 195356 kb |
| Host | smart-f2fcaa56-c99b-4527-85d1-71a2f1584696 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641191687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1641191687 |
| Directory | /workspace/22.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1686438927 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 117544030 ps |
| CPU time | 0.79 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:42 PM PST 24 |
| Peak memory | 195444 kb |
| Host | smart-f8953912-724b-4520-8793-25d893657e37 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686438927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu p_pulldown.1686438927 |
| Directory | /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.4241163000 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 198701698 ps |
| CPU time | 2.51 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:49 PM PST 24 |
| Peak memory | 198084 kb |
| Host | smart-4d50fdec-36ed-44cc-8f97-6b3d736ba700 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241163000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra ndom_long_reg_writes_reg_reads.4241163000 |
| Directory | /workspace/22.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/22.gpio_smoke.2839643852 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 96453683 ps |
| CPU time | 0.93 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:40 PM PST 24 |
| Peak memory | 195432 kb |
| Host | smart-6d32f207-c355-48a8-bb66-e9080450875f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839643852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2839643852 |
| Directory | /workspace/22.gpio_smoke/latest |
| Test location | /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2749052967 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 35241993 ps |
| CPU time | 1.09 seconds |
| Started | Jan 10 01:12:20 PM PST 24 |
| Finished | Jan 10 01:13:50 PM PST 24 |
| Peak memory | 196704 kb |
| Host | smart-8035217e-517a-4206-8887-38e4dea19b14 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749052967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2749052967 |
| Directory | /workspace/22.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/22.gpio_stress_all.3893813897 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 6383095985 ps |
| CPU time | 160.07 seconds |
| Started | Jan 10 01:12:28 PM PST 24 |
| Finished | Jan 10 01:16:28 PM PST 24 |
| Peak memory | 198228 kb |
| Host | smart-8ca266c9-5a69-4198-9a63-cfdb75c140e7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893813897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. gpio_stress_all.3893813897 |
| Directory | /workspace/22.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1376721138 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 696259708651 ps |
| CPU time | 745.23 seconds |
| Started | Jan 10 01:12:21 PM PST 24 |
| Finished | Jan 10 01:26:09 PM PST 24 |
| Peak memory | 206524 kb |
| Host | smart-dc48ae40-5304-43f7-abe4-b0abff792d3b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1376721138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1376721138 |
| Directory | /workspace/22.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.gpio_alert_test.1096955117 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 18523444 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:12:28 PM PST 24 |
| Finished | Jan 10 01:14:00 PM PST 24 |
| Peak memory | 194136 kb |
| Host | smart-83a06a43-776f-47c0-acc4-366cb0c648c9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096955117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1096955117 |
| Directory | /workspace/23.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.355112026 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 31908080 ps |
| CPU time | 0.68 seconds |
| Started | Jan 10 01:12:55 PM PST 24 |
| Finished | Jan 10 01:14:24 PM PST 24 |
| Peak memory | 194224 kb |
| Host | smart-65bb0c8d-c060-4db2-87cd-d8fff6be4050 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355112026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.355112026 |
| Directory | /workspace/23.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/23.gpio_filter_stress.2255404238 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1290179576 ps |
| CPU time | 12.72 seconds |
| Started | Jan 10 01:12:26 PM PST 24 |
| Finished | Jan 10 01:14:09 PM PST 24 |
| Peak memory | 196336 kb |
| Host | smart-42c9ab6e-e432-4409-99ee-426b6cd51e44 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255404238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre ss.2255404238 |
| Directory | /workspace/23.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/23.gpio_full_random.3767930555 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 189608328 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:48 PM PST 24 |
| Peak memory | 197172 kb |
| Host | smart-3ebbf612-9fe5-42c2-9bdc-51b66e89b55e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767930555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3767930555 |
| Directory | /workspace/23.gpio_full_random/latest |
| Test location | /workspace/coverage/default/23.gpio_intr_rand_pgm.1369542715 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 127704862 ps |
| CPU time | 1.09 seconds |
| Started | Jan 10 01:12:22 PM PST 24 |
| Finished | Jan 10 01:13:51 PM PST 24 |
| Peak memory | 195896 kb |
| Host | smart-94b56dd0-381e-45bc-bde0-8d1ec454b6c8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369542715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1369542715 |
| Directory | /workspace/23.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1299743126 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 162157995 ps |
| CPU time | 1.59 seconds |
| Started | Jan 10 01:12:30 PM PST 24 |
| Finished | Jan 10 01:13:55 PM PST 24 |
| Peak memory | 198068 kb |
| Host | smart-8b6dd708-8eb9-4054-85a5-167a7198f3b6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299743126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1299743126 |
| Directory | /workspace/23.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/23.gpio_rand_intr_trigger.3549860638 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 245451629 ps |
| CPU time | 1.84 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:13:45 PM PST 24 |
| Peak memory | 197300 kb |
| Host | smart-e74a84ae-9b80-4b3a-b6b0-4d8d38ece561 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549860638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger .3549860638 |
| Directory | /workspace/23.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/23.gpio_random_dout_din.1058761623 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 35902884 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:42 PM PST 24 |
| Peak memory | 196668 kb |
| Host | smart-9b83e2ee-ee3b-4c88-801f-4a8e4c895955 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1058761623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1058761623 |
| Directory | /workspace/23.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3328281521 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 21480499 ps |
| CPU time | 0.66 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:14:48 PM PST 24 |
| Peak memory | 194336 kb |
| Host | smart-f55d4776-915c-4703-99c9-3d31b31a405e |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328281521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu p_pulldown.3328281521 |
| Directory | /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1248708304 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 130831293 ps |
| CPU time | 5.87 seconds |
| Started | Jan 10 01:12:30 PM PST 24 |
| Finished | Jan 10 01:14:08 PM PST 24 |
| Peak memory | 198088 kb |
| Host | smart-02285bd7-15d6-4deb-8a39-7c4b12c0bd44 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248708304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra ndom_long_reg_writes_reg_reads.1248708304 |
| Directory | /workspace/23.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/23.gpio_smoke.1686457171 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 548907403 ps |
| CPU time | 1.21 seconds |
| Started | Jan 10 01:12:26 PM PST 24 |
| Finished | Jan 10 01:13:57 PM PST 24 |
| Peak memory | 195956 kb |
| Host | smart-711b01d8-a4b6-45ee-99de-4ed09d963ade |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686457171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1686457171 |
| Directory | /workspace/23.gpio_smoke/latest |
| Test location | /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1975960014 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 110865901 ps |
| CPU time | 1.04 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:14:39 PM PST 24 |
| Peak memory | 195684 kb |
| Host | smart-63a30f4b-5b86-480b-9ac7-0683eb808983 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975960014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1975960014 |
| Directory | /workspace/23.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/23.gpio_stress_all.1225520226 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 50827342193 ps |
| CPU time | 149.86 seconds |
| Started | Jan 10 01:12:46 PM PST 24 |
| Finished | Jan 10 01:16:39 PM PST 24 |
| Peak memory | 198168 kb |
| Host | smart-bbb827c7-3fbb-46c5-982b-f11eb0d64940 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225520226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. gpio_stress_all.1225520226 |
| Directory | /workspace/23.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3061049661 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 32000130868 ps |
| CPU time | 234.79 seconds |
| Started | Jan 10 01:12:40 PM PST 24 |
| Finished | Jan 10 01:18:11 PM PST 24 |
| Peak memory | 198424 kb |
| Host | smart-6924b13d-8fd5-4497-af03-32b90373a5f3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3061049661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3061049661 |
| Directory | /workspace/23.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.gpio_alert_test.1345380800 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 13274948 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:12:34 PM PST 24 |
| Finished | Jan 10 01:13:59 PM PST 24 |
| Peak memory | 194052 kb |
| Host | smart-d1691346-54a8-4f8e-8be5-be04415aad54 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345380800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1345380800 |
| Directory | /workspace/24.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2943204539 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 101058452 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 01:12:27 PM PST 24 |
| Finished | Jan 10 01:13:45 PM PST 24 |
| Peak memory | 195748 kb |
| Host | smart-a2537a2e-34f2-4ec6-9a40-413ad853c673 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943204539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2943204539 |
| Directory | /workspace/24.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/24.gpio_filter_stress.447696779 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 1075776612 ps |
| CPU time | 13.74 seconds |
| Started | Jan 10 01:12:46 PM PST 24 |
| Finished | Jan 10 01:14:22 PM PST 24 |
| Peak memory | 195560 kb |
| Host | smart-51bf47c7-7e1d-4566-91aa-c17ef8c3afb2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447696779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres s.447696779 |
| Directory | /workspace/24.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/24.gpio_full_random.2061532895 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 32202465 ps |
| CPU time | 0.66 seconds |
| Started | Jan 10 01:12:36 PM PST 24 |
| Finished | Jan 10 01:13:58 PM PST 24 |
| Peak memory | 194832 kb |
| Host | smart-85952e78-443b-47ad-af4b-36eadad1f954 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061532895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2061532895 |
| Directory | /workspace/24.gpio_full_random/latest |
| Test location | /workspace/coverage/default/24.gpio_intr_rand_pgm.956804031 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 16461898 ps |
| CPU time | 0.66 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:54 PM PST 24 |
| Peak memory | 194352 kb |
| Host | smart-4b87d692-f940-49d6-838d-e214195ff36d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956804031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.956804031 |
| Directory | /workspace/24.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3179092888 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 54588467 ps |
| CPU time | 2.17 seconds |
| Started | Jan 10 01:12:28 PM PST 24 |
| Finished | Jan 10 01:13:52 PM PST 24 |
| Peak memory | 198252 kb |
| Host | smart-ee31eff1-41f9-40f6-816e-54139aca6197 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179092888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3179092888 |
| Directory | /workspace/24.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/24.gpio_rand_intr_trigger.2220933984 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 268842273 ps |
| CPU time | 2.1 seconds |
| Started | Jan 10 01:12:33 PM PST 24 |
| Finished | Jan 10 01:13:56 PM PST 24 |
| Peak memory | 198196 kb |
| Host | smart-8ed7ee94-1792-4a12-a01c-f5da9b3a550b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220933984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger .2220933984 |
| Directory | /workspace/24.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/24.gpio_random_dout_din.3059788257 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 110316428 ps |
| CPU time | 0.67 seconds |
| Started | Jan 10 01:12:31 PM PST 24 |
| Finished | Jan 10 01:13:52 PM PST 24 |
| Peak memory | 194396 kb |
| Host | smart-19361821-a737-4093-a4e8-f00b26375fc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3059788257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3059788257 |
| Directory | /workspace/24.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3918993083 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 45043974 ps |
| CPU time | 0.86 seconds |
| Started | Jan 10 01:12:34 PM PST 24 |
| Finished | Jan 10 01:13:58 PM PST 24 |
| Peak memory | 196536 kb |
| Host | smart-a8c9231d-a2bf-4501-9639-b1b11170585f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918993083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu p_pulldown.3918993083 |
| Directory | /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3419069826 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 420445079 ps |
| CPU time | 4.74 seconds |
| Started | Jan 10 01:12:43 PM PST 24 |
| Finished | Jan 10 01:14:24 PM PST 24 |
| Peak memory | 198152 kb |
| Host | smart-0c9b826c-e922-4132-ae77-7239c9377f23 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419069826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra ndom_long_reg_writes_reg_reads.3419069826 |
| Directory | /workspace/24.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/24.gpio_smoke.2117843936 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 136730569 ps |
| CPU time | 1.34 seconds |
| Started | Jan 10 01:12:26 PM PST 24 |
| Finished | Jan 10 01:13:46 PM PST 24 |
| Peak memory | 196984 kb |
| Host | smart-15aa917d-d320-43be-b3ee-7a562b02da1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117843936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2117843936 |
| Directory | /workspace/24.gpio_smoke/latest |
| Test location | /workspace/coverage/default/24.gpio_stress_all.375550672 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 8803095555 ps |
| CPU time | 95.72 seconds |
| Started | Jan 10 01:12:24 PM PST 24 |
| Finished | Jan 10 01:15:18 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-f0a24a0d-897e-4795-a5b0-e3798949ba6a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375550672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g pio_stress_all.375550672 |
| Directory | /workspace/24.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.4254619611 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 156383443052 ps |
| CPU time | 2052.86 seconds |
| Started | Jan 10 01:12:39 PM PST 24 |
| Finished | Jan 10 01:48:13 PM PST 24 |
| Peak memory | 198336 kb |
| Host | smart-391731e9-f4c5-4fae-b788-536ef781b151 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4254619611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.4254619611 |
| Directory | /workspace/24.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.gpio_alert_test.2717538062 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 43442879 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:12:41 PM PST 24 |
| Finished | Jan 10 01:14:08 PM PST 24 |
| Peak memory | 194104 kb |
| Host | smart-d94435b1-1ce5-454f-a766-8ee64826935b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717538062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2717538062 |
| Directory | /workspace/25.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3284781339 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 24669548 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 01:12:48 PM PST 24 |
| Finished | Jan 10 01:14:15 PM PST 24 |
| Peak memory | 195276 kb |
| Host | smart-692b7c9e-4e34-4a8f-8e1a-46874f85b61b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3284781339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3284781339 |
| Directory | /workspace/25.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/25.gpio_filter_stress.956646203 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1932051664 ps |
| CPU time | 14.38 seconds |
| Started | Jan 10 01:12:36 PM PST 24 |
| Finished | Jan 10 01:14:16 PM PST 24 |
| Peak memory | 198092 kb |
| Host | smart-2356be73-4411-4441-8908-3a724d158c7a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956646203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres s.956646203 |
| Directory | /workspace/25.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/25.gpio_full_random.3337899155 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 75422074 ps |
| CPU time | 0.69 seconds |
| Started | Jan 10 01:12:54 PM PST 24 |
| Finished | Jan 10 01:14:31 PM PST 24 |
| Peak memory | 195832 kb |
| Host | smart-cdd9a15b-cec1-44cb-8b4c-ed1baef0415b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337899155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3337899155 |
| Directory | /workspace/25.gpio_full_random/latest |
| Test location | /workspace/coverage/default/25.gpio_intr_rand_pgm.3253717918 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 62634348 ps |
| CPU time | 0.62 seconds |
| Started | Jan 10 01:12:34 PM PST 24 |
| Finished | Jan 10 01:13:59 PM PST 24 |
| Peak memory | 195084 kb |
| Host | smart-9bee9f16-14fb-40ba-bec5-0320d21ac885 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253717918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3253717918 |
| Directory | /workspace/25.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2306771212 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 330486584 ps |
| CPU time | 1.93 seconds |
| Started | Jan 10 01:12:27 PM PST 24 |
| Finished | Jan 10 01:13:51 PM PST 24 |
| Peak memory | 198284 kb |
| Host | smart-66103285-dcad-491a-8a45-792cf5290068 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306771212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2306771212 |
| Directory | /workspace/25.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/25.gpio_random_dout_din.1012728861 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 14533011 ps |
| CPU time | 0.63 seconds |
| Started | Jan 10 01:12:38 PM PST 24 |
| Finished | Jan 10 01:14:00 PM PST 24 |
| Peak memory | 195024 kb |
| Host | smart-86b2c310-32ef-48cb-9742-89dbdb0e6f62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1012728861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1012728861 |
| Directory | /workspace/25.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.719474764 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 54682234 ps |
| CPU time | 1.11 seconds |
| Started | Jan 10 01:12:50 PM PST 24 |
| Finished | Jan 10 01:14:18 PM PST 24 |
| Peak memory | 197056 kb |
| Host | smart-f8a4ab84-d42d-4100-baf8-bb4d1d553e26 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719474764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup _pulldown.719474764 |
| Directory | /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1774479292 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 259650385 ps |
| CPU time | 3.14 seconds |
| Started | Jan 10 01:12:36 PM PST 24 |
| Finished | Jan 10 01:14:00 PM PST 24 |
| Peak memory | 198152 kb |
| Host | smart-3c48b5e2-abbf-4dee-8e94-85739decdf72 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774479292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra ndom_long_reg_writes_reg_reads.1774479292 |
| Directory | /workspace/25.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/25.gpio_smoke.3379885286 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 150592838 ps |
| CPU time | 0.77 seconds |
| Started | Jan 10 01:12:51 PM PST 24 |
| Finished | Jan 10 01:14:16 PM PST 24 |
| Peak memory | 195280 kb |
| Host | smart-8d406866-724a-4625-981b-79a70213b5bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3379885286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3379885286 |
| Directory | /workspace/25.gpio_smoke/latest |
| Test location | /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1811606972 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 336460758 ps |
| CPU time | 1.29 seconds |
| Started | Jan 10 01:12:34 PM PST 24 |
| Finished | Jan 10 01:14:00 PM PST 24 |
| Peak memory | 196700 kb |
| Host | smart-9733059b-5b27-47e6-8176-6e1ea4a41e7d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811606972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1811606972 |
| Directory | /workspace/25.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/25.gpio_stress_all.1404208559 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4737416846 ps |
| CPU time | 118.22 seconds |
| Started | Jan 10 01:12:32 PM PST 24 |
| Finished | Jan 10 01:15:49 PM PST 24 |
| Peak memory | 198168 kb |
| Host | smart-b59c2077-57d2-429d-8703-4575489f7d5d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404208559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. gpio_stress_all.1404208559 |
| Directory | /workspace/25.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.999370171 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 412608465137 ps |
| CPU time | 1697.59 seconds |
| Started | Jan 10 01:12:46 PM PST 24 |
| Finished | Jan 10 01:42:41 PM PST 24 |
| Peak memory | 198228 kb |
| Host | smart-962eaaf1-b895-4bb1-bd59-eb39c8e4f4ce |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =999370171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.999370171 |
| Directory | /workspace/25.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.gpio_alert_test.3870800685 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 79364045 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:12:57 PM PST 24 |
| Finished | Jan 10 01:14:22 PM PST 24 |
| Peak memory | 194424 kb |
| Host | smart-8d283e0c-d905-4523-9714-d3c0bcd22c9c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870800685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3870800685 |
| Directory | /workspace/26.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2199184798 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 21203676 ps |
| CPU time | 0.69 seconds |
| Started | Jan 10 01:12:34 PM PST 24 |
| Finished | Jan 10 01:13:54 PM PST 24 |
| Peak memory | 194304 kb |
| Host | smart-8646bae5-3db4-4341-beed-12fed9a0e405 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2199184798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2199184798 |
| Directory | /workspace/26.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/26.gpio_filter_stress.198952036 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 201656956 ps |
| CPU time | 4.71 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:59 PM PST 24 |
| Peak memory | 197072 kb |
| Host | smart-8803db80-785a-439d-b6fb-1b1fdf13af57 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198952036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres s.198952036 |
| Directory | /workspace/26.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/26.gpio_full_random.428021295 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 66735435 ps |
| CPU time | 0.79 seconds |
| Started | Jan 10 01:12:39 PM PST 24 |
| Finished | Jan 10 01:14:01 PM PST 24 |
| Peak memory | 195988 kb |
| Host | smart-7e83c70e-8062-4c97-9815-b0acd375fa4e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428021295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.428021295 |
| Directory | /workspace/26.gpio_full_random/latest |
| Test location | /workspace/coverage/default/26.gpio_intr_rand_pgm.215440030 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 206067327 ps |
| CPU time | 0.92 seconds |
| Started | Jan 10 01:12:28 PM PST 24 |
| Finished | Jan 10 01:14:00 PM PST 24 |
| Peak memory | 196952 kb |
| Host | smart-aa98a75a-9f00-4563-aae2-b8fe9aa8585d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215440030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.215440030 |
| Directory | /workspace/26.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3173206763 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 183735458 ps |
| CPU time | 1.45 seconds |
| Started | Jan 10 01:12:43 PM PST 24 |
| Finished | Jan 10 01:14:07 PM PST 24 |
| Peak memory | 197960 kb |
| Host | smart-745337fb-241c-4edd-9a50-38ad0b1ea66f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173206763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3173206763 |
| Directory | /workspace/26.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/26.gpio_rand_intr_trigger.3501514656 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 34719404 ps |
| CPU time | 1.15 seconds |
| Started | Jan 10 01:12:42 PM PST 24 |
| Finished | Jan 10 01:14:10 PM PST 24 |
| Peak memory | 196900 kb |
| Host | smart-14679775-e353-4859-9933-837702865538 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501514656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger .3501514656 |
| Directory | /workspace/26.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/26.gpio_random_dout_din.673487945 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 51660997 ps |
| CPU time | 1.09 seconds |
| Started | Jan 10 01:12:42 PM PST 24 |
| Finished | Jan 10 01:14:09 PM PST 24 |
| Peak memory | 196708 kb |
| Host | smart-96a7ac1e-f5f5-472e-b822-30fe346b4de0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=673487945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.673487945 |
| Directory | /workspace/26.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.4003233740 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 138718604 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:12:48 PM PST 24 |
| Finished | Jan 10 01:14:13 PM PST 24 |
| Peak memory | 196836 kb |
| Host | smart-b9fcb48b-e641-4fac-9612-20193fcddb71 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003233740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu p_pulldown.4003233740 |
| Directory | /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.720759486 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 1549381683 ps |
| CPU time | 1.95 seconds |
| Started | Jan 10 01:12:45 PM PST 24 |
| Finished | Jan 10 01:14:14 PM PST 24 |
| Peak memory | 198148 kb |
| Host | smart-ea6956b4-e522-4a5e-98e9-0f073aebd950 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720759486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran dom_long_reg_writes_reg_reads.720759486 |
| Directory | /workspace/26.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/26.gpio_smoke.873018316 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 229358896 ps |
| CPU time | 1.01 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:43 PM PST 24 |
| Peak memory | 197216 kb |
| Host | smart-d9326729-5882-49a2-aea9-dbbdbe2cb882 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=873018316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.873018316 |
| Directory | /workspace/26.gpio_smoke/latest |
| Test location | /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3447753051 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 81460352 ps |
| CPU time | 1.01 seconds |
| Started | Jan 10 01:12:28 PM PST 24 |
| Finished | Jan 10 01:13:51 PM PST 24 |
| Peak memory | 195968 kb |
| Host | smart-898d0dd2-2795-46ae-b26c-909f2eb96f13 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447753051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3447753051 |
| Directory | /workspace/26.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/26.gpio_stress_all.2880329308 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 5392456369 ps |
| CPU time | 141.08 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:16:50 PM PST 24 |
| Peak memory | 198308 kb |
| Host | smart-a9cc5027-1c99-41e3-b317-4f3f05300763 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880329308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. gpio_stress_all.2880329308 |
| Directory | /workspace/26.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.1614637055 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 133340074400 ps |
| CPU time | 1583.92 seconds |
| Started | Jan 10 01:12:26 PM PST 24 |
| Finished | Jan 10 01:40:14 PM PST 24 |
| Peak memory | 198300 kb |
| Host | smart-d8d5fea6-67e7-4cc7-80ef-cc4b0b0cba8f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1614637055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.1614637055 |
| Directory | /workspace/26.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.gpio_alert_test.2033238694 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 34481170 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:12:27 PM PST 24 |
| Finished | Jan 10 01:13:50 PM PST 24 |
| Peak memory | 194884 kb |
| Host | smart-fc2a3233-56ef-4f8a-bfef-8f5b6dbfa9d7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033238694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2033238694 |
| Directory | /workspace/27.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2632575595 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 19394172 ps |
| CPU time | 0.61 seconds |
| Started | Jan 10 01:12:30 PM PST 24 |
| Finished | Jan 10 01:13:49 PM PST 24 |
| Peak memory | 194084 kb |
| Host | smart-4783939c-4a2a-4193-9a6f-92ee7854adcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2632575595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2632575595 |
| Directory | /workspace/27.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/27.gpio_filter_stress.2994614684 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 973691187 ps |
| CPU time | 20.91 seconds |
| Started | Jan 10 01:12:36 PM PST 24 |
| Finished | Jan 10 01:14:18 PM PST 24 |
| Peak memory | 197300 kb |
| Host | smart-16bba377-1973-48fb-a542-d4a1287f8bb5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994614684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre ss.2994614684 |
| Directory | /workspace/27.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/27.gpio_full_random.1973494015 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 98458596 ps |
| CPU time | 1.02 seconds |
| Started | Jan 10 01:12:27 PM PST 24 |
| Finished | Jan 10 01:13:51 PM PST 24 |
| Peak memory | 196648 kb |
| Host | smart-24a95151-dfa7-4108-8c5c-5cc424eff7b8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973494015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1973494015 |
| Directory | /workspace/27.gpio_full_random/latest |
| Test location | /workspace/coverage/default/27.gpio_intr_rand_pgm.1387686519 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 46147450 ps |
| CPU time | 1.09 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:14:35 PM PST 24 |
| Peak memory | 196116 kb |
| Host | smart-27ae08fc-b973-4cad-be40-f05a2bb569ae |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387686519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1387686519 |
| Directory | /workspace/27.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.171439160 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 60930728 ps |
| CPU time | 2.43 seconds |
| Started | Jan 10 01:12:30 PM PST 24 |
| Finished | Jan 10 01:13:51 PM PST 24 |
| Peak memory | 198240 kb |
| Host | smart-2d64e217-9422-4952-a6c0-bb9a66a5e887 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171439160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 27.gpio_intr_with_filter_rand_intr_event.171439160 |
| Directory | /workspace/27.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/27.gpio_rand_intr_trigger.606498114 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 80075754 ps |
| CPU time | 0.86 seconds |
| Started | Jan 10 01:12:59 PM PST 24 |
| Finished | Jan 10 01:14:33 PM PST 24 |
| Peak memory | 195504 kb |
| Host | smart-93ec8b66-c67c-4363-af39-dbfab82f34ae |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606498114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger. 606498114 |
| Directory | /workspace/27.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/27.gpio_random_dout_din.771175111 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 803429234 ps |
| CPU time | 1.14 seconds |
| Started | Jan 10 01:12:39 PM PST 24 |
| Finished | Jan 10 01:14:15 PM PST 24 |
| Peak memory | 197220 kb |
| Host | smart-2b407b65-48fe-4380-9f53-e9e1ef8b7576 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771175111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.771175111 |
| Directory | /workspace/27.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3899327281 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 19719299 ps |
| CPU time | 0.76 seconds |
| Started | Jan 10 01:12:49 PM PST 24 |
| Finished | Jan 10 01:14:18 PM PST 24 |
| Peak memory | 196132 kb |
| Host | smart-c9e05a7e-b3a0-4024-a64d-863a435fcfde |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899327281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu p_pulldown.3899327281 |
| Directory | /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3249297088 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 250963251 ps |
| CPU time | 5.06 seconds |
| Started | Jan 10 01:12:28 PM PST 24 |
| Finished | Jan 10 01:13:55 PM PST 24 |
| Peak memory | 198060 kb |
| Host | smart-46f713ea-910d-4581-8998-839a253610d3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249297088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra ndom_long_reg_writes_reg_reads.3249297088 |
| Directory | /workspace/27.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/27.gpio_smoke.645972677 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 49887274 ps |
| CPU time | 1.02 seconds |
| Started | Jan 10 01:12:36 PM PST 24 |
| Finished | Jan 10 01:13:58 PM PST 24 |
| Peak memory | 195664 kb |
| Host | smart-e3868faf-3706-4c97-a44d-083f4c91dbe9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645972677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.645972677 |
| Directory | /workspace/27.gpio_smoke/latest |
| Test location | /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1453716410 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 677712405 ps |
| CPU time | 1 seconds |
| Started | Jan 10 01:12:28 PM PST 24 |
| Finished | Jan 10 01:13:51 PM PST 24 |
| Peak memory | 195812 kb |
| Host | smart-6b1003ec-a17f-4bd0-9954-6de4eaca0eeb |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453716410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1453716410 |
| Directory | /workspace/27.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/27.gpio_stress_all.541529314 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 5544524040 ps |
| CPU time | 136 seconds |
| Started | Jan 10 01:12:27 PM PST 24 |
| Finished | Jan 10 01:16:01 PM PST 24 |
| Peak memory | 198288 kb |
| Host | smart-ba60f8d2-38c9-403c-98d0-d3ce2d29dfb7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541529314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g pio_stress_all.541529314 |
| Directory | /workspace/27.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1608092767 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 17232579610 ps |
| CPU time | 224.13 seconds |
| Started | Jan 10 01:12:30 PM PST 24 |
| Finished | Jan 10 01:17:46 PM PST 24 |
| Peak memory | 198408 kb |
| Host | smart-efa07f84-7234-41a2-83c6-912bbd6ac57d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1608092767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1608092767 |
| Directory | /workspace/27.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.gpio_alert_test.3900210766 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 16172923 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:12:49 PM PST 24 |
| Finished | Jan 10 01:14:13 PM PST 24 |
| Peak memory | 194480 kb |
| Host | smart-5f222fdd-d5de-46c1-8956-c8f592400903 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900210766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3900210766 |
| Directory | /workspace/28.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/28.gpio_filter_stress.421265293 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2484889271 ps |
| CPU time | 21.31 seconds |
| Started | Jan 10 01:12:54 PM PST 24 |
| Finished | Jan 10 01:14:39 PM PST 24 |
| Peak memory | 196112 kb |
| Host | smart-54f8a55f-40dc-4f91-a4cf-a37f94e76aee |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421265293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres s.421265293 |
| Directory | /workspace/28.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/28.gpio_full_random.56109363 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 721001520 ps |
| CPU time | 1 seconds |
| Started | Jan 10 01:12:48 PM PST 24 |
| Finished | Jan 10 01:14:16 PM PST 24 |
| Peak memory | 196764 kb |
| Host | smart-e922430b-6a99-4e2e-81ce-04f79ac885f5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56109363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.56109363 |
| Directory | /workspace/28.gpio_full_random/latest |
| Test location | /workspace/coverage/default/28.gpio_intr_rand_pgm.4084238960 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 120246330 ps |
| CPU time | 0.85 seconds |
| Started | Jan 10 01:12:28 PM PST 24 |
| Finished | Jan 10 01:14:00 PM PST 24 |
| Peak memory | 196012 kb |
| Host | smart-6b7df857-3ddc-46d6-8d9d-8da10dab95d6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084238960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.4084238960 |
| Directory | /workspace/28.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3302940279 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 88172601 ps |
| CPU time | 1.47 seconds |
| Started | Jan 10 01:13:12 PM PST 24 |
| Finished | Jan 10 01:14:39 PM PST 24 |
| Peak memory | 196908 kb |
| Host | smart-dad417f1-5008-4fa1-940b-bb576a01d96f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302940279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3302940279 |
| Directory | /workspace/28.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/28.gpio_rand_intr_trigger.1732310882 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 403714712 ps |
| CPU time | 2.82 seconds |
| Started | Jan 10 01:12:46 PM PST 24 |
| Finished | Jan 10 01:14:15 PM PST 24 |
| Peak memory | 195932 kb |
| Host | smart-ef0cf73d-72f5-49c5-af20-95f01a904b39 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732310882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger .1732310882 |
| Directory | /workspace/28.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/28.gpio_random_dout_din.2783787802 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 132530844 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:12:30 PM PST 24 |
| Finished | Jan 10 01:13:54 PM PST 24 |
| Peak memory | 196856 kb |
| Host | smart-1088a6dd-d45d-4ba4-bf0d-c149e37d1aef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783787802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2783787802 |
| Directory | /workspace/28.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.847767492 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 58241570 ps |
| CPU time | 0.73 seconds |
| Started | Jan 10 01:12:29 PM PST 24 |
| Finished | Jan 10 01:13:49 PM PST 24 |
| Peak memory | 196312 kb |
| Host | smart-8244e7ff-35f5-46c2-8688-c6ee9150e52b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847767492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup _pulldown.847767492 |
| Directory | /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2225890520 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 119404577 ps |
| CPU time | 5.12 seconds |
| Started | Jan 10 01:12:39 PM PST 24 |
| Finished | Jan 10 01:14:05 PM PST 24 |
| Peak memory | 198148 kb |
| Host | smart-05649ed4-f355-4cf5-8683-0573140b1529 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225890520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra ndom_long_reg_writes_reg_reads.2225890520 |
| Directory | /workspace/28.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/28.gpio_smoke.2582200489 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 42273573 ps |
| CPU time | 0.95 seconds |
| Started | Jan 10 01:12:31 PM PST 24 |
| Finished | Jan 10 01:13:51 PM PST 24 |
| Peak memory | 195900 kb |
| Host | smart-64465b06-a4f6-4599-aa7a-f31e0313de54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582200489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2582200489 |
| Directory | /workspace/28.gpio_smoke/latest |
| Test location | /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3475394710 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 92638726 ps |
| CPU time | 0.91 seconds |
| Started | Jan 10 01:12:30 PM PST 24 |
| Finished | Jan 10 01:13:54 PM PST 24 |
| Peak memory | 195776 kb |
| Host | smart-022f0ece-1ad6-4d82-920c-657d590cfc1d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475394710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3475394710 |
| Directory | /workspace/28.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/28.gpio_stress_all.1215946278 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 6707411357 ps |
| CPU time | 23.05 seconds |
| Started | Jan 10 01:12:45 PM PST 24 |
| Finished | Jan 10 01:14:35 PM PST 24 |
| Peak memory | 198252 kb |
| Host | smart-3f00fd1e-6702-4499-9df5-829197e4e942 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215946278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. gpio_stress_all.1215946278 |
| Directory | /workspace/28.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3715039190 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 46278582370 ps |
| CPU time | 285.28 seconds |
| Started | Jan 10 01:12:48 PM PST 24 |
| Finished | Jan 10 01:19:00 PM PST 24 |
| Peak memory | 198396 kb |
| Host | smart-0e4a456d-15a4-4551-81b8-0a082e1874e4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3715039190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3715039190 |
| Directory | /workspace/28.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.gpio_alert_test.3080122247 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 39820385 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:12:46 PM PST 24 |
| Finished | Jan 10 01:14:19 PM PST 24 |
| Peak memory | 194156 kb |
| Host | smart-4b36af2d-51bb-4d69-9297-417b0c69b325 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080122247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3080122247 |
| Directory | /workspace/29.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3183828707 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 16791311 ps |
| CPU time | 0.63 seconds |
| Started | Jan 10 01:12:43 PM PST 24 |
| Finished | Jan 10 01:14:07 PM PST 24 |
| Peak memory | 194116 kb |
| Host | smart-899a303b-b0a0-4855-9df7-dd0f97f31a52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3183828707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3183828707 |
| Directory | /workspace/29.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/29.gpio_filter_stress.4082419374 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2869762358 ps |
| CPU time | 19.17 seconds |
| Started | Jan 10 01:12:42 PM PST 24 |
| Finished | Jan 10 01:14:27 PM PST 24 |
| Peak memory | 197636 kb |
| Host | smart-da647969-1092-4d1c-a6f6-97acdb23afa2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082419374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre ss.4082419374 |
| Directory | /workspace/29.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/29.gpio_full_random.1578887645 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 34955979 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 01:12:48 PM PST 24 |
| Finished | Jan 10 01:14:13 PM PST 24 |
| Peak memory | 194848 kb |
| Host | smart-89697f74-3764-4a32-a659-ac6a21006f68 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578887645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1578887645 |
| Directory | /workspace/29.gpio_full_random/latest |
| Test location | /workspace/coverage/default/29.gpio_intr_rand_pgm.326403329 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 110200630 ps |
| CPU time | 0.96 seconds |
| Started | Jan 10 01:12:51 PM PST 24 |
| Finished | Jan 10 01:14:20 PM PST 24 |
| Peak memory | 196232 kb |
| Host | smart-68d8bec3-c1cc-4262-b819-1477ef88dc12 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326403329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.326403329 |
| Directory | /workspace/29.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1982585240 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 87635882 ps |
| CPU time | 1.26 seconds |
| Started | Jan 10 01:12:50 PM PST 24 |
| Finished | Jan 10 01:14:19 PM PST 24 |
| Peak memory | 198320 kb |
| Host | smart-e5a99e23-f918-47ed-87f2-b38d86bc2d0e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982585240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1982585240 |
| Directory | /workspace/29.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/29.gpio_rand_intr_trigger.644328282 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 147258435 ps |
| CPU time | 2.86 seconds |
| Started | Jan 10 01:12:58 PM PST 24 |
| Finished | Jan 10 01:14:25 PM PST 24 |
| Peak memory | 196660 kb |
| Host | smart-bfb59e8d-e4d1-4a2b-8209-d4417e0a84e0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644328282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger. 644328282 |
| Directory | /workspace/29.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/29.gpio_random_dout_din.1290345697 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 22686179 ps |
| CPU time | 0.77 seconds |
| Started | Jan 10 01:12:51 PM PST 24 |
| Finished | Jan 10 01:14:21 PM PST 24 |
| Peak memory | 196464 kb |
| Host | smart-b9d3198a-5722-4ebc-bc26-0c62e76fc449 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290345697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1290345697 |
| Directory | /workspace/29.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3546776700 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 35957613 ps |
| CPU time | 0.76 seconds |
| Started | Jan 10 01:12:41 PM PST 24 |
| Finished | Jan 10 01:14:17 PM PST 24 |
| Peak memory | 195568 kb |
| Host | smart-3b548379-429d-418c-acbb-6be183102650 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546776700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu p_pulldown.3546776700 |
| Directory | /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3898219589 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 4824689004 ps |
| CPU time | 5.28 seconds |
| Started | Jan 10 01:12:48 PM PST 24 |
| Finished | Jan 10 01:14:20 PM PST 24 |
| Peak memory | 198236 kb |
| Host | smart-f67178a5-fe95-47bf-a971-8ca1129f0bb8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898219589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra ndom_long_reg_writes_reg_reads.3898219589 |
| Directory | /workspace/29.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/29.gpio_smoke.4275208073 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 34262716 ps |
| CPU time | 0.9 seconds |
| Started | Jan 10 01:12:41 PM PST 24 |
| Finished | Jan 10 01:14:09 PM PST 24 |
| Peak memory | 196652 kb |
| Host | smart-6bdc6a34-29a8-4f8f-9568-50cc36ba1102 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275208073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.4275208073 |
| Directory | /workspace/29.gpio_smoke/latest |
| Test location | /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1367607195 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 40266664 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:21 PM PST 24 |
| Peak memory | 195300 kb |
| Host | smart-1179b118-6cb8-4623-b813-0f9222b96c70 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367607195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1367607195 |
| Directory | /workspace/29.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/29.gpio_stress_all.608044494 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 1399008729 ps |
| CPU time | 33.68 seconds |
| Started | Jan 10 01:12:55 PM PST 24 |
| Finished | Jan 10 01:14:58 PM PST 24 |
| Peak memory | 198124 kb |
| Host | smart-e7b158cf-3dad-4518-a9c3-096d0cac9b4f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608044494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g pio_stress_all.608044494 |
| Directory | /workspace/29.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.291349310 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 960891962828 ps |
| CPU time | 1195.63 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:34:46 PM PST 24 |
| Peak memory | 198356 kb |
| Host | smart-0f58cdd4-8d26-4cc8-b2ad-da1d3f923023 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =291349310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.291349310 |
| Directory | /workspace/29.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.gpio_alert_test.854723597 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 43902024 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:22 PM PST 24 |
| Peak memory | 193992 kb |
| Host | smart-59f7844b-27f1-46a4-99ae-f829cc2eb877 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854723597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.854723597 |
| Directory | /workspace/3.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3770390485 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 100647623 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 01:11:52 PM PST 24 |
| Finished | Jan 10 01:13:04 PM PST 24 |
| Peak memory | 196408 kb |
| Host | smart-d00c7262-b84c-4681-935e-375aafc72d13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770390485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3770390485 |
| Directory | /workspace/3.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/3.gpio_filter_stress.1833838739 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1661190567 ps |
| CPU time | 22.45 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:24 PM PST 24 |
| Peak memory | 197096 kb |
| Host | smart-8c526172-04a3-4c74-af60-c6671244ed33 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833838739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres s.1833838739 |
| Directory | /workspace/3.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/3.gpio_full_random.608683989 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 305653088 ps |
| CPU time | 0.65 seconds |
| Started | Jan 10 01:12:16 PM PST 24 |
| Finished | Jan 10 01:13:38 PM PST 24 |
| Peak memory | 195380 kb |
| Host | smart-a591c926-ec87-4dde-8862-e5ff607b2433 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608683989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.608683989 |
| Directory | /workspace/3.gpio_full_random/latest |
| Test location | /workspace/coverage/default/3.gpio_intr_rand_pgm.3863153866 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 100926407 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 01:11:49 PM PST 24 |
| Finished | Jan 10 01:13:07 PM PST 24 |
| Peak memory | 196084 kb |
| Host | smart-5a5071ca-6203-4d3d-a34d-4b3f6f342bd3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863153866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3863153866 |
| Directory | /workspace/3.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.187797530 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 125704984 ps |
| CPU time | 2.4 seconds |
| Started | Jan 10 01:11:53 PM PST 24 |
| Finished | Jan 10 01:13:18 PM PST 24 |
| Peak memory | 198200 kb |
| Host | smart-2940c3f3-1d33-49ba-8e34-bb2cdb5d9913 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187797530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 3.gpio_intr_with_filter_rand_intr_event.187797530 |
| Directory | /workspace/3.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/3.gpio_rand_intr_trigger.322880488 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 174414369 ps |
| CPU time | 3.42 seconds |
| Started | Jan 10 01:11:50 PM PST 24 |
| Finished | Jan 10 01:13:19 PM PST 24 |
| Peak memory | 197012 kb |
| Host | smart-c0c8f264-4572-44e8-8700-1c78277bf294 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322880488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.322880488 |
| Directory | /workspace/3.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/3.gpio_random_dout_din.31754135 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 98302585 ps |
| CPU time | 1.12 seconds |
| Started | Jan 10 01:11:47 PM PST 24 |
| Finished | Jan 10 01:13:02 PM PST 24 |
| Peak memory | 196924 kb |
| Host | smart-85407701-0dfd-41f4-91ad-6c91be648676 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31754135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.31754135 |
| Directory | /workspace/3.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1781042225 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 43154793 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 01:11:49 PM PST 24 |
| Finished | Jan 10 01:13:05 PM PST 24 |
| Peak memory | 195452 kb |
| Host | smart-6eff9536-50e8-4056-8c2c-443962f85a1f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781042225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup _pulldown.1781042225 |
| Directory | /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2974804898 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 586073933 ps |
| CPU time | 4.6 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:28 PM PST 24 |
| Peak memory | 198148 kb |
| Host | smart-d5189e9e-0562-4a2f-9a35-3cacddbe6500 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974804898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran dom_long_reg_writes_reg_reads.2974804898 |
| Directory | /workspace/3.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/3.gpio_sec_cm.3106454034 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 36831928 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:23 PM PST 24 |
| Peak memory | 213396 kb |
| Host | smart-6bb28938-e68a-4f00-b850-599449705a3c |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106454034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3106454034 |
| Directory | /workspace/3.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/3.gpio_smoke.290317844 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 71149442 ps |
| CPU time | 1.03 seconds |
| Started | Jan 10 01:11:48 PM PST 24 |
| Finished | Jan 10 01:13:03 PM PST 24 |
| Peak memory | 195680 kb |
| Host | smart-0bee08c8-0956-4256-bc41-939879544fe1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290317844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.290317844 |
| Directory | /workspace/3.gpio_smoke/latest |
| Test location | /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3470438462 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 91568418 ps |
| CPU time | 0.74 seconds |
| Started | Jan 10 01:11:51 PM PST 24 |
| Finished | Jan 10 01:13:05 PM PST 24 |
| Peak memory | 195160 kb |
| Host | smart-ddf4a062-af97-4d25-b7f7-8a005813dde6 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470438462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3470438462 |
| Directory | /workspace/3.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/3.gpio_stress_all.3578866228 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 96293183281 ps |
| CPU time | 135.09 seconds |
| Started | Jan 10 01:11:57 PM PST 24 |
| Finished | Jan 10 01:15:42 PM PST 24 |
| Peak memory | 197972 kb |
| Host | smart-d64c4578-6b51-459b-82cb-f5201496244d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578866228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g pio_stress_all.3578866228 |
| Directory | /workspace/3.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2477525823 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 129578541663 ps |
| CPU time | 833.63 seconds |
| Started | Jan 10 01:12:00 PM PST 24 |
| Finished | Jan 10 01:27:10 PM PST 24 |
| Peak memory | 198316 kb |
| Host | smart-32c5c73e-441b-4c52-bdb0-e4d6d27ed8f8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2477525823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2477525823 |
| Directory | /workspace/3.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.gpio_alert_test.1033154717 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 37764017 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:12:46 PM PST 24 |
| Finished | Jan 10 01:14:09 PM PST 24 |
| Peak memory | 194712 kb |
| Host | smart-65de0fe9-2504-49c7-a2a8-ec33c3bcbc6f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033154717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1033154717 |
| Directory | /workspace/30.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1424702293 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 52130979 ps |
| CPU time | 1.02 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:21 PM PST 24 |
| Peak memory | 196620 kb |
| Host | smart-82d9b75f-2966-4be4-94ed-4774803f4ad4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1424702293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1424702293 |
| Directory | /workspace/30.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/30.gpio_filter_stress.3583338305 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1496258448 ps |
| CPU time | 10.07 seconds |
| Started | Jan 10 01:12:52 PM PST 24 |
| Finished | Jan 10 01:14:25 PM PST 24 |
| Peak memory | 197248 kb |
| Host | smart-39b15bb9-00db-45fb-b569-fcd2dccc1792 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583338305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre ss.3583338305 |
| Directory | /workspace/30.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/30.gpio_full_random.2880246753 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 63961736 ps |
| CPU time | 0.85 seconds |
| Started | Jan 10 01:12:48 PM PST 24 |
| Finished | Jan 10 01:14:28 PM PST 24 |
| Peak memory | 197136 kb |
| Host | smart-e16076cd-86a5-4f43-9946-f61256c71483 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880246753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2880246753 |
| Directory | /workspace/30.gpio_full_random/latest |
| Test location | /workspace/coverage/default/30.gpio_intr_rand_pgm.2762821114 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 28325309 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:12:49 PM PST 24 |
| Finished | Jan 10 01:14:28 PM PST 24 |
| Peak memory | 195660 kb |
| Host | smart-05d18205-d4e0-40fa-aa18-c8f53dc77793 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762821114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2762821114 |
| Directory | /workspace/30.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2727310854 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 66708811 ps |
| CPU time | 2.49 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:23 PM PST 24 |
| Peak memory | 197960 kb |
| Host | smart-30e50086-1718-4504-908c-4a7e60f92039 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727310854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2727310854 |
| Directory | /workspace/30.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/30.gpio_rand_intr_trigger.2153817158 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 183567989 ps |
| CPU time | 2.61 seconds |
| Started | Jan 10 01:12:59 PM PST 24 |
| Finished | Jan 10 01:14:34 PM PST 24 |
| Peak memory | 198176 kb |
| Host | smart-a4a11310-ff0c-42cd-918a-3c74d549e95d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153817158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger .2153817158 |
| Directory | /workspace/30.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/30.gpio_random_dout_din.2809632677 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 80753432 ps |
| CPU time | 0.93 seconds |
| Started | Jan 10 01:12:49 PM PST 24 |
| Finished | Jan 10 01:14:28 PM PST 24 |
| Peak memory | 196152 kb |
| Host | smart-507c34b3-9931-483c-a532-5bfc9acf0d4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809632677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2809632677 |
| Directory | /workspace/30.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.811780155 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 25907102 ps |
| CPU time | 0.94 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:19 PM PST 24 |
| Peak memory | 196868 kb |
| Host | smart-f872db93-5357-44d5-b659-f5d54283f5a0 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811780155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup _pulldown.811780155 |
| Directory | /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2807784365 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 7084019240 ps |
| CPU time | 5.83 seconds |
| Started | Jan 10 01:12:54 PM PST 24 |
| Finished | Jan 10 01:14:40 PM PST 24 |
| Peak memory | 198248 kb |
| Host | smart-f71a6ce3-e51c-4aea-b64f-d50e66ed0fca |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807784365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra ndom_long_reg_writes_reg_reads.2807784365 |
| Directory | /workspace/30.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/30.gpio_smoke.1658394969 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 39700486 ps |
| CPU time | 1.08 seconds |
| Started | Jan 10 01:12:37 PM PST 24 |
| Finished | Jan 10 01:14:03 PM PST 24 |
| Peak memory | 195640 kb |
| Host | smart-497fc375-2719-484c-9510-77228d72f8f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658394969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1658394969 |
| Directory | /workspace/30.gpio_smoke/latest |
| Test location | /workspace/coverage/default/30.gpio_stress_all.3105985211 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 74008628209 ps |
| CPU time | 179.55 seconds |
| Started | Jan 10 01:12:54 PM PST 24 |
| Finished | Jan 10 01:17:19 PM PST 24 |
| Peak memory | 198404 kb |
| Host | smart-8614442a-4609-4d8a-a0b7-3a4fe2969b78 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105985211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. gpio_stress_all.3105985211 |
| Directory | /workspace/30.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.916169454 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 38374775017 ps |
| CPU time | 466.87 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:22:07 PM PST 24 |
| Peak memory | 198388 kb |
| Host | smart-f087e6f9-1dce-42f8-9928-c6422da9a2c1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =916169454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.916169454 |
| Directory | /workspace/30.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.gpio_alert_test.722831827 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 60894215 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:12:51 PM PST 24 |
| Finished | Jan 10 01:14:20 PM PST 24 |
| Peak memory | 194812 kb |
| Host | smart-c511062d-e9ab-4936-be47-09a98c9bbf7d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722831827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.722831827 |
| Directory | /workspace/31.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3070138077 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 16209748 ps |
| CPU time | 0.64 seconds |
| Started | Jan 10 01:12:49 PM PST 24 |
| Finished | Jan 10 01:14:28 PM PST 24 |
| Peak memory | 194148 kb |
| Host | smart-0b1a6372-e416-4d14-ab62-8a27f1b3fee5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3070138077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3070138077 |
| Directory | /workspace/31.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/31.gpio_filter_stress.3331941463 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 930648564 ps |
| CPU time | 12.15 seconds |
| Started | Jan 10 01:12:50 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 197244 kb |
| Host | smart-053da7de-6ad4-42a2-864e-5f26d833cf68 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331941463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre ss.3331941463 |
| Directory | /workspace/31.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/31.gpio_full_random.903399200 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 204973282 ps |
| CPU time | 1 seconds |
| Started | Jan 10 01:12:46 PM PST 24 |
| Finished | Jan 10 01:14:14 PM PST 24 |
| Peak memory | 196760 kb |
| Host | smart-73a3588b-c99d-42ae-8f7e-9747ec7528dd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903399200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.903399200 |
| Directory | /workspace/31.gpio_full_random/latest |
| Test location | /workspace/coverage/default/31.gpio_intr_rand_pgm.3431157411 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 105683809 ps |
| CPU time | 0.85 seconds |
| Started | Jan 10 01:12:49 PM PST 24 |
| Finished | Jan 10 01:14:13 PM PST 24 |
| Peak memory | 196884 kb |
| Host | smart-9a1836e3-9ebc-47e0-b3d5-7746c216f74c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431157411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3431157411 |
| Directory | /workspace/31.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.324516331 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 108543966 ps |
| CPU time | 1.28 seconds |
| Started | Jan 10 01:12:45 PM PST 24 |
| Finished | Jan 10 01:14:13 PM PST 24 |
| Peak memory | 196784 kb |
| Host | smart-1576ce86-9ed8-48ba-999c-a3917518c109 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324516331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 31.gpio_intr_with_filter_rand_intr_event.324516331 |
| Directory | /workspace/31.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/31.gpio_rand_intr_trigger.4014252003 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 77779027 ps |
| CPU time | 1.25 seconds |
| Started | Jan 10 01:12:54 PM PST 24 |
| Finished | Jan 10 01:14:19 PM PST 24 |
| Peak memory | 195856 kb |
| Host | smart-a61f4919-e6ef-4943-8dd9-bbefaa713509 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014252003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger .4014252003 |
| Directory | /workspace/31.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/31.gpio_random_dout_din.763770184 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 64637987 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 01:13:11 PM PST 24 |
| Finished | Jan 10 01:14:37 PM PST 24 |
| Peak memory | 195444 kb |
| Host | smart-fcdd128d-6aea-447d-9d1b-8eab5217a591 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=763770184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.763770184 |
| Directory | /workspace/31.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.846307030 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 87281190 ps |
| CPU time | 1.07 seconds |
| Started | Jan 10 01:12:52 PM PST 24 |
| Finished | Jan 10 01:14:16 PM PST 24 |
| Peak memory | 196956 kb |
| Host | smart-0ee0c72b-1936-4f01-a4e6-e95c0e4aaa3b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846307030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup _pulldown.846307030 |
| Directory | /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3208820689 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 68597245 ps |
| CPU time | 3.04 seconds |
| Started | Jan 10 01:12:47 PM PST 24 |
| Finished | Jan 10 01:14:13 PM PST 24 |
| Peak memory | 198176 kb |
| Host | smart-2c060ab5-4f14-4ada-9f8a-a0aa96cf3d91 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208820689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra ndom_long_reg_writes_reg_reads.3208820689 |
| Directory | /workspace/31.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/31.gpio_smoke.3666337311 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 66730806 ps |
| CPU time | 1.2 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:19 PM PST 24 |
| Peak memory | 195844 kb |
| Host | smart-bc698d48-eeb1-48fa-b9d7-cbd44abef106 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666337311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3666337311 |
| Directory | /workspace/31.gpio_smoke/latest |
| Test location | /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.4272219506 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 236967831 ps |
| CPU time | 1.06 seconds |
| Started | Jan 10 01:12:50 PM PST 24 |
| Finished | Jan 10 01:14:18 PM PST 24 |
| Peak memory | 196004 kb |
| Host | smart-477a5b8f-5297-4e89-8ce1-268e7a8d280e |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272219506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.4272219506 |
| Directory | /workspace/31.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/31.gpio_stress_all.397359592 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 4902590249 ps |
| CPU time | 123 seconds |
| Started | Jan 10 01:12:51 PM PST 24 |
| Finished | Jan 10 01:16:30 PM PST 24 |
| Peak memory | 198272 kb |
| Host | smart-22eab87f-4a8c-40d3-81cc-bee9cce5c162 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397359592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g pio_stress_all.397359592 |
| Directory | /workspace/31.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3154928894 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 271048866280 ps |
| CPU time | 1242.54 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:35:03 PM PST 24 |
| Peak memory | 198420 kb |
| Host | smart-973c9c8f-d9a2-496a-bf4f-0e52f84e9bda |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3154928894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3154928894 |
| Directory | /workspace/31.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.gpio_alert_test.1332557144 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 14828366 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:12:51 PM PST 24 |
| Finished | Jan 10 01:14:28 PM PST 24 |
| Peak memory | 194268 kb |
| Host | smart-f795950c-6bc3-435d-900c-04da0f09ac9e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332557144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1332557144 |
| Directory | /workspace/32.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3812653499 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 34381312 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:14:33 PM PST 24 |
| Peak memory | 196340 kb |
| Host | smart-e6b70b1e-739e-4655-8824-9bf184678a53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3812653499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3812653499 |
| Directory | /workspace/32.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/32.gpio_filter_stress.2922525760 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 675565573 ps |
| CPU time | 6.87 seconds |
| Started | Jan 10 01:12:46 PM PST 24 |
| Finished | Jan 10 01:14:16 PM PST 24 |
| Peak memory | 197196 kb |
| Host | smart-95f542ab-caa9-4724-a527-51452a3920cd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922525760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre ss.2922525760 |
| Directory | /workspace/32.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/32.gpio_full_random.335305706 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 71716540 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 01:13:20 PM PST 24 |
| Finished | Jan 10 01:15:01 PM PST 24 |
| Peak memory | 196708 kb |
| Host | smart-bba9476d-0b90-4b23-a0c0-90cea4c97b52 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335305706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.335305706 |
| Directory | /workspace/32.gpio_full_random/latest |
| Test location | /workspace/coverage/default/32.gpio_intr_rand_pgm.3585165080 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 332141326 ps |
| CPU time | 1.4 seconds |
| Started | Jan 10 01:12:48 PM PST 24 |
| Finished | Jan 10 01:14:28 PM PST 24 |
| Peak memory | 197352 kb |
| Host | smart-7de3d4c0-6184-479c-a2a7-bf3b6d556e36 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585165080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3585165080 |
| Directory | /workspace/32.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3712748646 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 234006024 ps |
| CPU time | 2.34 seconds |
| Started | Jan 10 01:13:01 PM PST 24 |
| Finished | Jan 10 01:14:34 PM PST 24 |
| Peak memory | 198172 kb |
| Host | smart-a4c398ec-b6c2-49ae-a00a-a97f2781bea5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712748646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3712748646 |
| Directory | /workspace/32.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/32.gpio_rand_intr_trigger.3193230085 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 684042183 ps |
| CPU time | 2.98 seconds |
| Started | Jan 10 01:12:46 PM PST 24 |
| Finished | Jan 10 01:14:12 PM PST 24 |
| Peak memory | 196816 kb |
| Host | smart-d0c55e1a-8e9d-4a03-b34f-31772be591f3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193230085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger .3193230085 |
| Directory | /workspace/32.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/32.gpio_random_dout_din.2013078474 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 138574819 ps |
| CPU time | 0.91 seconds |
| Started | Jan 10 01:12:51 PM PST 24 |
| Finished | Jan 10 01:14:16 PM PST 24 |
| Peak memory | 196820 kb |
| Host | smart-e8f7e516-7cc0-457e-adb6-0e95f60caff6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013078474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2013078474 |
| Directory | /workspace/32.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3126730942 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 243258554 ps |
| CPU time | 0.89 seconds |
| Started | Jan 10 01:12:41 PM PST 24 |
| Finished | Jan 10 01:14:08 PM PST 24 |
| Peak memory | 195996 kb |
| Host | smart-021508a8-d533-4c5d-9169-6c0b68b1bec6 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126730942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu p_pulldown.3126730942 |
| Directory | /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1325464217 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 434980320 ps |
| CPU time | 2.14 seconds |
| Started | Jan 10 01:12:51 PM PST 24 |
| Finished | Jan 10 01:14:22 PM PST 24 |
| Peak memory | 198084 kb |
| Host | smart-a96d8b16-f30f-45de-b15f-13a4f7f87122 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325464217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra ndom_long_reg_writes_reg_reads.1325464217 |
| Directory | /workspace/32.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/32.gpio_smoke.2656880818 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 137382836 ps |
| CPU time | 1.36 seconds |
| Started | Jan 10 01:12:57 PM PST 24 |
| Finished | Jan 10 01:14:25 PM PST 24 |
| Peak memory | 198116 kb |
| Host | smart-195affa2-e981-4055-8b18-cf09a611ebfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656880818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2656880818 |
| Directory | /workspace/32.gpio_smoke/latest |
| Test location | /workspace/coverage/default/32.gpio_stress_all.1854175565 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 17405185869 ps |
| CPU time | 58.14 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:15:48 PM PST 24 |
| Peak memory | 198248 kb |
| Host | smart-4d3cb152-0836-4156-a7b9-7e1d7bc663d1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854175565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. gpio_stress_all.1854175565 |
| Directory | /workspace/32.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.134313383 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 236176415403 ps |
| CPU time | 1655.09 seconds |
| Started | Jan 10 01:12:45 PM PST 24 |
| Finished | Jan 10 01:41:46 PM PST 24 |
| Peak memory | 198344 kb |
| Host | smart-a961ab65-7d81-4eba-91af-39bbf6a01c02 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =134313383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.134313383 |
| Directory | /workspace/32.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.gpio_alert_test.197843550 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 36809837 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:14:57 PM PST 24 |
| Peak memory | 194076 kb |
| Host | smart-345944c3-28f0-471f-84e2-95001130ad5d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197843550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.197843550 |
| Directory | /workspace/33.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.517647513 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 80581471 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:12:59 PM PST 24 |
| Finished | Jan 10 01:14:33 PM PST 24 |
| Peak memory | 197292 kb |
| Host | smart-27a6704e-54cb-4b1d-a261-cce9190b6fd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517647513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.517647513 |
| Directory | /workspace/33.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/33.gpio_filter_stress.2027176913 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 4694234912 ps |
| CPU time | 25.79 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:14:54 PM PST 24 |
| Peak memory | 198376 kb |
| Host | smart-0c12f8cd-e586-49b1-8b65-9147aecbe14e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027176913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre ss.2027176913 |
| Directory | /workspace/33.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/33.gpio_intr_rand_pgm.3973658130 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 302485207 ps |
| CPU time | 0.99 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:14:22 PM PST 24 |
| Peak memory | 196060 kb |
| Host | smart-9d441590-633d-458e-9e3a-ac4a7d5bdeb5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973658130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3973658130 |
| Directory | /workspace/33.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2553784231 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 65433522 ps |
| CPU time | 1.49 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:22 PM PST 24 |
| Peak memory | 196448 kb |
| Host | smart-f11b1570-7e22-48cb-a93a-e1ac8cc5246b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553784231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2553784231 |
| Directory | /workspace/33.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/33.gpio_rand_intr_trigger.2669851840 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 648892276 ps |
| CPU time | 1.32 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:31 PM PST 24 |
| Peak memory | 196028 kb |
| Host | smart-a053ec15-cb06-4f25-87aa-5ca11731168d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669851840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger .2669851840 |
| Directory | /workspace/33.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/33.gpio_random_dout_din.1255962172 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 37978756 ps |
| CPU time | 0.95 seconds |
| Started | Jan 10 01:12:58 PM PST 24 |
| Finished | Jan 10 01:14:24 PM PST 24 |
| Peak memory | 195876 kb |
| Host | smart-9668b858-7428-42dd-8d34-3af2949d1bce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1255962172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1255962172 |
| Directory | /workspace/33.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2130120874 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 78560403 ps |
| CPU time | 0.93 seconds |
| Started | Jan 10 01:12:58 PM PST 24 |
| Finished | Jan 10 01:14:35 PM PST 24 |
| Peak memory | 195960 kb |
| Host | smart-383b6d8c-2e4b-4829-b531-940393889bd0 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130120874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu p_pulldown.2130120874 |
| Directory | /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1620396607 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1784670965 ps |
| CPU time | 5.93 seconds |
| Started | Jan 10 01:12:57 PM PST 24 |
| Finished | Jan 10 01:14:27 PM PST 24 |
| Peak memory | 198104 kb |
| Host | smart-299ed14a-d084-4c49-bb55-1658582ce950 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620396607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra ndom_long_reg_writes_reg_reads.1620396607 |
| Directory | /workspace/33.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/33.gpio_smoke.3076886100 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 170028312 ps |
| CPU time | 1.28 seconds |
| Started | Jan 10 01:12:59 PM PST 24 |
| Finished | Jan 10 01:14:33 PM PST 24 |
| Peak memory | 196952 kb |
| Host | smart-c441a4ca-910d-42cd-bd63-d17775034013 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3076886100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3076886100 |
| Directory | /workspace/33.gpio_smoke/latest |
| Test location | /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.704116353 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 56364102 ps |
| CPU time | 1 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:21 PM PST 24 |
| Peak memory | 197384 kb |
| Host | smart-81a877be-9d97-45c6-be3f-87d0c402f1d3 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704116353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.704116353 |
| Directory | /workspace/33.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/33.gpio_stress_all.3663896878 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3976057570 ps |
| CPU time | 54.5 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:15:45 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-c1dcd4be-81b1-4d29-9a72-fe1a03c653f0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663896878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. gpio_stress_all.3663896878 |
| Directory | /workspace/33.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1337162711 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 66776967758 ps |
| CPU time | 941.18 seconds |
| Started | Jan 10 01:13:22 PM PST 24 |
| Finished | Jan 10 01:30:27 PM PST 24 |
| Peak memory | 198340 kb |
| Host | smart-29af52d9-1ac6-4b55-acb3-b5e2031e4955 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1337162711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1337162711 |
| Directory | /workspace/33.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.gpio_alert_test.2538945839 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 171830413 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:14:34 PM PST 24 |
| Peak memory | 194280 kb |
| Host | smart-08e05f9e-6ef9-439e-ae44-e007a8907f56 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538945839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2538945839 |
| Directory | /workspace/34.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2593464617 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 29147250 ps |
| CPU time | 0.73 seconds |
| Started | Jan 10 01:13:23 PM PST 24 |
| Finished | Jan 10 01:14:58 PM PST 24 |
| Peak memory | 195260 kb |
| Host | smart-996b4a15-5312-4805-8e1f-6d99356ada93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2593464617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2593464617 |
| Directory | /workspace/34.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/34.gpio_filter_stress.3361814491 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 589646229 ps |
| CPU time | 19.63 seconds |
| Started | Jan 10 01:12:55 PM PST 24 |
| Finished | Jan 10 01:14:37 PM PST 24 |
| Peak memory | 195604 kb |
| Host | smart-dd01fcdb-8a13-4e5b-8ba4-04c9ab2fb31c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361814491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre ss.3361814491 |
| Directory | /workspace/34.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/34.gpio_full_random.1149158389 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 40429027 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 01:12:52 PM PST 24 |
| Finished | Jan 10 01:14:16 PM PST 24 |
| Peak memory | 194728 kb |
| Host | smart-21925414-c8a5-42cd-8265-e4ed1ef70c2a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149158389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1149158389 |
| Directory | /workspace/34.gpio_full_random/latest |
| Test location | /workspace/coverage/default/34.gpio_intr_rand_pgm.2242996187 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 65332409 ps |
| CPU time | 0.92 seconds |
| Started | Jan 10 01:13:05 PM PST 24 |
| Finished | Jan 10 01:14:32 PM PST 24 |
| Peak memory | 196704 kb |
| Host | smart-5a5a2eac-b76e-47f9-b63c-58b9db0301d4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242996187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2242996187 |
| Directory | /workspace/34.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3936974322 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 365528598 ps |
| CPU time | 3.51 seconds |
| Started | Jan 10 01:13:01 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 198072 kb |
| Host | smart-b1aff985-a9ff-4868-87e7-b32fbc2e7de8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936974322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3936974322 |
| Directory | /workspace/34.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/34.gpio_rand_intr_trigger.3146223720 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 34909064 ps |
| CPU time | 1.01 seconds |
| Started | Jan 10 01:13:24 PM PST 24 |
| Finished | Jan 10 01:15:03 PM PST 24 |
| Peak memory | 195372 kb |
| Host | smart-8a9fdc22-bb05-48d1-a5e5-a9b2e29505fb |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146223720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger .3146223720 |
| Directory | /workspace/34.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/34.gpio_random_dout_din.3523280594 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 20604668 ps |
| CPU time | 0.65 seconds |
| Started | Jan 10 01:12:58 PM PST 24 |
| Finished | Jan 10 01:14:23 PM PST 24 |
| Peak memory | 194336 kb |
| Host | smart-2a9b246e-f717-4a7e-b995-8185af534935 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523280594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3523280594 |
| Directory | /workspace/34.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2123072019 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 658015750 ps |
| CPU time | 1.15 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:31 PM PST 24 |
| Peak memory | 197248 kb |
| Host | smart-7d2a6a1d-10a2-4987-a322-c299e8576b10 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123072019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu p_pulldown.2123072019 |
| Directory | /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3157006871 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 41220648 ps |
| CPU time | 1.61 seconds |
| Started | Jan 10 01:12:55 PM PST 24 |
| Finished | Jan 10 01:14:36 PM PST 24 |
| Peak memory | 198108 kb |
| Host | smart-810a2845-8a01-4dcd-b08b-9a01fd38a59a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157006871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra ndom_long_reg_writes_reg_reads.3157006871 |
| Directory | /workspace/34.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/34.gpio_smoke.271096379 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 51537816 ps |
| CPU time | 1.26 seconds |
| Started | Jan 10 01:12:57 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 197024 kb |
| Host | smart-87230b69-084c-48a7-937f-0d4c6103be2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271096379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.271096379 |
| Directory | /workspace/34.gpio_smoke/latest |
| Test location | /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.806151741 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 39666659 ps |
| CPU time | 1.07 seconds |
| Started | Jan 10 01:12:59 PM PST 24 |
| Finished | Jan 10 01:14:33 PM PST 24 |
| Peak memory | 195336 kb |
| Host | smart-ab43a4eb-3015-421f-8713-54e92cce6705 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806151741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.806151741 |
| Directory | /workspace/34.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/34.gpio_stress_all.819412871 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 12318000468 ps |
| CPU time | 145.4 seconds |
| Started | Jan 10 01:12:57 PM PST 24 |
| Finished | Jan 10 01:16:49 PM PST 24 |
| Peak memory | 198220 kb |
| Host | smart-d5e0c670-544b-48f6-8da1-5d78a7dda145 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819412871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g pio_stress_all.819412871 |
| Directory | /workspace/34.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.393009907 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 352753976683 ps |
| CPU time | 2047.36 seconds |
| Started | Jan 10 01:13:03 PM PST 24 |
| Finished | Jan 10 01:48:36 PM PST 24 |
| Peak memory | 198352 kb |
| Host | smart-378a2014-e15e-46a3-ba38-1ce0f39e05cf |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =393009907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.393009907 |
| Directory | /workspace/34.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.gpio_alert_test.1432279632 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 13084659 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:13:02 PM PST 24 |
| Finished | Jan 10 01:14:31 PM PST 24 |
| Peak memory | 194196 kb |
| Host | smart-1f257223-c1da-4814-a3a2-718c13363818 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432279632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1432279632 |
| Directory | /workspace/35.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3885914980 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 43645124 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:13:21 PM PST 24 |
| Finished | Jan 10 01:14:48 PM PST 24 |
| Peak memory | 197064 kb |
| Host | smart-a7dff673-6c97-4892-9582-6110cd216d99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885914980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3885914980 |
| Directory | /workspace/35.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/35.gpio_filter_stress.1679895934 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 295857661 ps |
| CPU time | 14.25 seconds |
| Started | Jan 10 01:13:40 PM PST 24 |
| Finished | Jan 10 01:15:15 PM PST 24 |
| Peak memory | 196896 kb |
| Host | smart-f6bf83cf-a6a3-41a2-ab99-813cce80148c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679895934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre ss.1679895934 |
| Directory | /workspace/35.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/35.gpio_full_random.212778450 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 62189000 ps |
| CPU time | 0.73 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:14:33 PM PST 24 |
| Peak memory | 195888 kb |
| Host | smart-7c15c97d-85d4-4ccd-a9ca-05312b345bee |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212778450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.212778450 |
| Directory | /workspace/35.gpio_full_random/latest |
| Test location | /workspace/coverage/default/35.gpio_intr_rand_pgm.1206104310 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 152828112 ps |
| CPU time | 1.12 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:14:34 PM PST 24 |
| Peak memory | 195948 kb |
| Host | smart-0d84f3f9-e8b9-479a-b6d9-c4fd0dd56999 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206104310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1206104310 |
| Directory | /workspace/35.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3059063449 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 148877292 ps |
| CPU time | 2.78 seconds |
| Started | Jan 10 01:12:58 PM PST 24 |
| Finished | Jan 10 01:14:26 PM PST 24 |
| Peak memory | 198116 kb |
| Host | smart-59c7cb25-c2a6-4b68-950e-06ff61abd479 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059063449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3059063449 |
| Directory | /workspace/35.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/35.gpio_rand_intr_trigger.249685859 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 124478706 ps |
| CPU time | 3.42 seconds |
| Started | Jan 10 01:12:59 PM PST 24 |
| Finished | Jan 10 01:14:31 PM PST 24 |
| Peak memory | 196864 kb |
| Host | smart-b12f4005-9097-4b57-a9f9-3b66ec47a2a1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249685859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger. 249685859 |
| Directory | /workspace/35.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/35.gpio_random_dout_din.2195978830 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 90409410 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:12:50 PM PST 24 |
| Finished | Jan 10 01:14:18 PM PST 24 |
| Peak memory | 196004 kb |
| Host | smart-eaed66be-d06f-4a73-8841-8aef28481697 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2195978830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2195978830 |
| Directory | /workspace/35.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1651194588 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 57696322 ps |
| CPU time | 1.07 seconds |
| Started | Jan 10 01:12:43 PM PST 24 |
| Finished | Jan 10 01:14:12 PM PST 24 |
| Peak memory | 196268 kb |
| Host | smart-2f64494a-0699-4119-b52f-df9aa8107d4b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651194588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu p_pulldown.1651194588 |
| Directory | /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1682307815 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 42058244 ps |
| CPU time | 1.83 seconds |
| Started | Jan 10 01:12:40 PM PST 24 |
| Finished | Jan 10 01:14:05 PM PST 24 |
| Peak memory | 198120 kb |
| Host | smart-d710064f-5eec-47c3-84ad-5b4551932472 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682307815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra ndom_long_reg_writes_reg_reads.1682307815 |
| Directory | /workspace/35.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/35.gpio_smoke.4230107063 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 141255954 ps |
| CPU time | 0.85 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:14:51 PM PST 24 |
| Peak memory | 196000 kb |
| Host | smart-4a4c05b6-5761-451f-b094-502c8b601a3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4230107063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.4230107063 |
| Directory | /workspace/35.gpio_smoke/latest |
| Test location | /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1683808482 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 114736654 ps |
| CPU time | 1.06 seconds |
| Started | Jan 10 01:12:57 PM PST 24 |
| Finished | Jan 10 01:14:35 PM PST 24 |
| Peak memory | 196324 kb |
| Host | smart-c875bb39-a23e-42ff-8be3-b4b69c5ccf35 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683808482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1683808482 |
| Directory | /workspace/35.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/35.gpio_stress_all.1524584053 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 10648083670 ps |
| CPU time | 140.71 seconds |
| Started | Jan 10 01:13:10 PM PST 24 |
| Finished | Jan 10 01:16:56 PM PST 24 |
| Peak memory | 198228 kb |
| Host | smart-0d07fd7c-5c14-4bfa-9a09-3303cbe99c1b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524584053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. gpio_stress_all.1524584053 |
| Directory | /workspace/35.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3937135516 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 68009568839 ps |
| CPU time | 1176.86 seconds |
| Started | Jan 10 01:12:55 PM PST 24 |
| Finished | Jan 10 01:34:11 PM PST 24 |
| Peak memory | 206600 kb |
| Host | smart-8684e88b-8e8e-4e06-9e48-648ad2fab8a6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3937135516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3937135516 |
| Directory | /workspace/35.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.gpio_alert_test.2237167322 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 15640293 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:21 PM PST 24 |
| Peak memory | 194296 kb |
| Host | smart-a3ebbc43-592b-44d1-82ff-3af62b6764dd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237167322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2237167322 |
| Directory | /workspace/36.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3321002172 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 33711103 ps |
| CPU time | 0.75 seconds |
| Started | Jan 10 01:12:51 PM PST 24 |
| Finished | Jan 10 01:14:16 PM PST 24 |
| Peak memory | 195260 kb |
| Host | smart-c93e93d8-fbcf-4442-b218-1789826eb7f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3321002172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3321002172 |
| Directory | /workspace/36.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/36.gpio_filter_stress.4131176016 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 212049211 ps |
| CPU time | 6.62 seconds |
| Started | Jan 10 01:13:23 PM PST 24 |
| Finished | Jan 10 01:15:03 PM PST 24 |
| Peak memory | 197116 kb |
| Host | smart-bf3314b8-b6af-4d5e-987f-56d4627e040c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131176016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre ss.4131176016 |
| Directory | /workspace/36.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/36.gpio_full_random.3638250698 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 133195923 ps |
| CPU time | 0.85 seconds |
| Started | Jan 10 01:12:55 PM PST 24 |
| Finished | Jan 10 01:14:24 PM PST 24 |
| Peak memory | 196096 kb |
| Host | smart-4bb12a4b-43fb-4057-8402-a1dc52e97ed3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638250698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3638250698 |
| Directory | /workspace/36.gpio_full_random/latest |
| Test location | /workspace/coverage/default/36.gpio_intr_rand_pgm.1028414253 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 106240031 ps |
| CPU time | 0.74 seconds |
| Started | Jan 10 01:12:55 PM PST 24 |
| Finished | Jan 10 01:14:20 PM PST 24 |
| Peak memory | 195584 kb |
| Host | smart-d6b1ca61-3ab9-48ac-9dea-5471a39fb2bd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028414253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1028414253 |
| Directory | /workspace/36.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2560556444 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 175875177 ps |
| CPU time | 3.31 seconds |
| Started | Jan 10 01:13:03 PM PST 24 |
| Finished | Jan 10 01:14:33 PM PST 24 |
| Peak memory | 196592 kb |
| Host | smart-b3a67cb5-b34e-4485-8d81-dc5837a8d10f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560556444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2560556444 |
| Directory | /workspace/36.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/36.gpio_rand_intr_trigger.138205729 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 571898217 ps |
| CPU time | 2.87 seconds |
| Started | Jan 10 01:12:46 PM PST 24 |
| Finished | Jan 10 01:14:17 PM PST 24 |
| Peak memory | 196116 kb |
| Host | smart-4dbf05af-7606-40bc-a57e-a22b56424798 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138205729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger. 138205729 |
| Directory | /workspace/36.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/36.gpio_random_dout_din.2901150420 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 68242425 ps |
| CPU time | 1.27 seconds |
| Started | Jan 10 01:13:53 PM PST 24 |
| Finished | Jan 10 01:15:06 PM PST 24 |
| Peak memory | 197116 kb |
| Host | smart-98789f1d-85d2-41be-893f-986e81261051 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2901150420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2901150420 |
| Directory | /workspace/36.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.476486657 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 52483029 ps |
| CPU time | 1.03 seconds |
| Started | Jan 10 01:13:54 PM PST 24 |
| Finished | Jan 10 01:15:06 PM PST 24 |
| Peak memory | 196752 kb |
| Host | smart-0e0d885f-a2d8-4083-ba6c-721d763d0c86 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476486657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup _pulldown.476486657 |
| Directory | /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1479800187 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 325679082 ps |
| CPU time | 2.79 seconds |
| Started | Jan 10 01:13:02 PM PST 24 |
| Finished | Jan 10 01:14:34 PM PST 24 |
| Peak memory | 198100 kb |
| Host | smart-eb661da4-204e-4f71-a0cb-b111776a511a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479800187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra ndom_long_reg_writes_reg_reads.1479800187 |
| Directory | /workspace/36.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/36.gpio_smoke.1550538910 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 141659161 ps |
| CPU time | 1.23 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:22 PM PST 24 |
| Peak memory | 196924 kb |
| Host | smart-cc62bb58-115e-4172-aabc-7f6f70b55d35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550538910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1550538910 |
| Directory | /workspace/36.gpio_smoke/latest |
| Test location | /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3903339243 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 130817819 ps |
| CPU time | 0.85 seconds |
| Started | Jan 10 01:13:01 PM PST 24 |
| Finished | Jan 10 01:14:32 PM PST 24 |
| Peak memory | 196032 kb |
| Host | smart-751972bd-1fb1-469a-abae-187226b2a4b2 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903339243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3903339243 |
| Directory | /workspace/36.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/36.gpio_stress_all.954139197 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 18317883108 ps |
| CPU time | 101.54 seconds |
| Started | Jan 10 01:12:57 PM PST 24 |
| Finished | Jan 10 01:16:04 PM PST 24 |
| Peak memory | 198148 kb |
| Host | smart-6bdcc0bb-24c6-4610-9b40-69bdb528e616 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954139197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g pio_stress_all.954139197 |
| Directory | /workspace/36.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1056870907 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 64462584760 ps |
| CPU time | 443.55 seconds |
| Started | Jan 10 01:13:00 PM PST 24 |
| Finished | Jan 10 01:22:18 PM PST 24 |
| Peak memory | 198284 kb |
| Host | smart-12aef2b0-0702-49f4-9161-d7e697a7f957 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1056870907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1056870907 |
| Directory | /workspace/36.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.gpio_alert_test.2973267664 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 20597328 ps |
| CPU time | 0.63 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:14:51 PM PST 24 |
| Peak memory | 194808 kb |
| Host | smart-09886df7-535d-47b5-a687-88e5b031f8f4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973267664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2973267664 |
| Directory | /workspace/37.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1198141474 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 30137558 ps |
| CPU time | 0.76 seconds |
| Started | Jan 10 01:12:57 PM PST 24 |
| Finished | Jan 10 01:14:22 PM PST 24 |
| Peak memory | 195448 kb |
| Host | smart-065f7fb6-cac0-4f0b-8ae5-9fb2fd44133c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1198141474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1198141474 |
| Directory | /workspace/37.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/37.gpio_filter_stress.2320682959 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2088980971 ps |
| CPU time | 25.25 seconds |
| Started | Jan 10 01:13:15 PM PST 24 |
| Finished | Jan 10 01:15:05 PM PST 24 |
| Peak memory | 197100 kb |
| Host | smart-afc3b914-c4e0-40e1-b7db-d0564ac91154 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320682959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre ss.2320682959 |
| Directory | /workspace/37.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/37.gpio_full_random.140967633 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 173777801 ps |
| CPU time | 1.07 seconds |
| Started | Jan 10 01:13:23 PM PST 24 |
| Finished | Jan 10 01:14:50 PM PST 24 |
| Peak memory | 196480 kb |
| Host | smart-b22aec33-f7bf-46a3-8b8c-102084ea09fe |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140967633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.140967633 |
| Directory | /workspace/37.gpio_full_random/latest |
| Test location | /workspace/coverage/default/37.gpio_intr_rand_pgm.1274207938 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 110824489 ps |
| CPU time | 1.01 seconds |
| Started | Jan 10 01:12:57 PM PST 24 |
| Finished | Jan 10 01:14:23 PM PST 24 |
| Peak memory | 196008 kb |
| Host | smart-2891c22a-463f-4abc-864f-75da319c2edd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274207938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1274207938 |
| Directory | /workspace/37.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.613656979 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 176311266 ps |
| CPU time | 1.8 seconds |
| Started | Jan 10 01:13:10 PM PST 24 |
| Finished | Jan 10 01:14:38 PM PST 24 |
| Peak memory | 198188 kb |
| Host | smart-691796a0-5d35-4d4a-b607-0badb9380765 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613656979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 37.gpio_intr_with_filter_rand_intr_event.613656979 |
| Directory | /workspace/37.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/37.gpio_rand_intr_trigger.2149576980 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 92890621 ps |
| CPU time | 2.18 seconds |
| Started | Jan 10 01:13:15 PM PST 24 |
| Finished | Jan 10 01:14:44 PM PST 24 |
| Peak memory | 197028 kb |
| Host | smart-f7f2ce3e-7338-4bfa-9770-9bc5506b7a61 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149576980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger .2149576980 |
| Directory | /workspace/37.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/37.gpio_random_dout_din.2677721766 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 429215188 ps |
| CPU time | 0.9 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:19 PM PST 24 |
| Peak memory | 195888 kb |
| Host | smart-307dce1b-6535-4715-b943-15dc223a47ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677721766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2677721766 |
| Directory | /workspace/37.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2003884073 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 21921672 ps |
| CPU time | 0.69 seconds |
| Started | Jan 10 01:13:10 PM PST 24 |
| Finished | Jan 10 01:14:37 PM PST 24 |
| Peak memory | 195320 kb |
| Host | smart-b67bc8fe-97e1-4f83-a095-1029412adf31 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003884073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu p_pulldown.2003884073 |
| Directory | /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3413475516 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 596248703 ps |
| CPU time | 2.74 seconds |
| Started | Jan 10 01:13:00 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 198108 kb |
| Host | smart-c10784d1-2175-48c5-a334-7b34f11314b9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413475516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra ndom_long_reg_writes_reg_reads.3413475516 |
| Directory | /workspace/37.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/37.gpio_smoke.3992523043 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 34777796 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 01:13:41 PM PST 24 |
| Finished | Jan 10 01:15:02 PM PST 24 |
| Peak memory | 195680 kb |
| Host | smart-4bef47c2-da19-4d22-8a5d-38ef6d52861f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992523043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3992523043 |
| Directory | /workspace/37.gpio_smoke/latest |
| Test location | /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1823864544 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 213063167 ps |
| CPU time | 0.89 seconds |
| Started | Jan 10 01:12:59 PM PST 24 |
| Finished | Jan 10 01:14:33 PM PST 24 |
| Peak memory | 195928 kb |
| Host | smart-bdec94aa-16d1-4370-a969-ab870cff23ff |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823864544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1823864544 |
| Directory | /workspace/37.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/37.gpio_stress_all.2066627094 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 21180004713 ps |
| CPU time | 215.44 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:18:13 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-08bdeec8-b53f-40f6-9f35-719a2ca75dc6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066627094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. gpio_stress_all.2066627094 |
| Directory | /workspace/37.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3573272378 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 344723651302 ps |
| CPU time | 1099.08 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:32:43 PM PST 24 |
| Peak memory | 198392 kb |
| Host | smart-6c31e29b-e37f-4cf9-9b95-f3b90adec8fe |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3573272378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3573272378 |
| Directory | /workspace/37.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.gpio_alert_test.1423242954 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 12121538 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:12:59 PM PST 24 |
| Finished | Jan 10 01:14:28 PM PST 24 |
| Peak memory | 193984 kb |
| Host | smart-84306956-0163-4953-a0e5-06c2c39faf1c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423242954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1423242954 |
| Directory | /workspace/38.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.172713744 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 53049746 ps |
| CPU time | 0.89 seconds |
| Started | Jan 10 01:12:58 PM PST 24 |
| Finished | Jan 10 01:14:28 PM PST 24 |
| Peak memory | 196880 kb |
| Host | smart-31277524-1aa9-4a19-995a-964497881dbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=172713744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.172713744 |
| Directory | /workspace/38.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/38.gpio_filter_stress.2283269058 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 380234974 ps |
| CPU time | 19.12 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:14:40 PM PST 24 |
| Peak memory | 197032 kb |
| Host | smart-060d089d-8c0d-4837-9545-2429bd768ba7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283269058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre ss.2283269058 |
| Directory | /workspace/38.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/38.gpio_full_random.1476020447 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 439304291 ps |
| CPU time | 0.95 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 197324 kb |
| Host | smart-66a0944b-cc23-4eff-b8ba-255405f5e318 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476020447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1476020447 |
| Directory | /workspace/38.gpio_full_random/latest |
| Test location | /workspace/coverage/default/38.gpio_intr_rand_pgm.2198179622 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 1091367379 ps |
| CPU time | 1.03 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:14:39 PM PST 24 |
| Peak memory | 196868 kb |
| Host | smart-27a24a76-e6c3-47b5-86ee-57ab9e059293 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198179622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2198179622 |
| Directory | /workspace/38.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.4000127805 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 157277334 ps |
| CPU time | 0.99 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:14:49 PM PST 24 |
| Peak memory | 196052 kb |
| Host | smart-fa00f023-3de4-4d09-8a02-0d5e098dbb72 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000127805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.gpio_intr_with_filter_rand_intr_event.4000127805 |
| Directory | /workspace/38.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/38.gpio_rand_intr_trigger.671292546 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 430062701 ps |
| CPU time | 2.42 seconds |
| Started | Jan 10 01:13:11 PM PST 24 |
| Finished | Jan 10 01:14:38 PM PST 24 |
| Peak memory | 197352 kb |
| Host | smart-58f1b951-fe44-462b-b7a1-3ef0e207f4c6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671292546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger. 671292546 |
| Directory | /workspace/38.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/38.gpio_random_dout_din.742668667 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 28327781 ps |
| CPU time | 1.04 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:14:49 PM PST 24 |
| Peak memory | 196860 kb |
| Host | smart-f2767f52-4418-484a-b981-447f6d7fa8a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742668667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.742668667 |
| Directory | /workspace/38.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3056676583 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 260752772 ps |
| CPU time | 1.17 seconds |
| Started | Jan 10 01:13:18 PM PST 24 |
| Finished | Jan 10 01:14:45 PM PST 24 |
| Peak memory | 197360 kb |
| Host | smart-e14ee308-a0f2-4fbd-b645-ab936d3ab8c9 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056676583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu p_pulldown.3056676583 |
| Directory | /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3901577496 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 402575878 ps |
| CPU time | 1.52 seconds |
| Started | Jan 10 01:12:55 PM PST 24 |
| Finished | Jan 10 01:14:25 PM PST 24 |
| Peak memory | 198040 kb |
| Host | smart-6b848167-e294-474f-8d40-af800a2f4322 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901577496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra ndom_long_reg_writes_reg_reads.3901577496 |
| Directory | /workspace/38.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/38.gpio_smoke.2133658133 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 40706070 ps |
| CPU time | 1.07 seconds |
| Started | Jan 10 01:12:55 PM PST 24 |
| Finished | Jan 10 01:14:20 PM PST 24 |
| Peak memory | 195816 kb |
| Host | smart-b612b299-6c34-4a5d-954c-b7522121e7ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2133658133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2133658133 |
| Directory | /workspace/38.gpio_smoke/latest |
| Test location | /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3328063624 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 62547394 ps |
| CPU time | 1.14 seconds |
| Started | Jan 10 01:13:10 PM PST 24 |
| Finished | Jan 10 01:14:38 PM PST 24 |
| Peak memory | 195888 kb |
| Host | smart-bf44edc8-ef29-4c3e-b634-db4e9483fb7f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328063624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3328063624 |
| Directory | /workspace/38.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/38.gpio_stress_all.29062752 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 48781342081 ps |
| CPU time | 171.65 seconds |
| Started | Jan 10 01:13:02 PM PST 24 |
| Finished | Jan 10 01:17:23 PM PST 24 |
| Peak memory | 198184 kb |
| Host | smart-d5119c33-0ee5-45c4-bd7f-70e5fa759c38 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29062752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gp io_stress_all.29062752 |
| Directory | /workspace/38.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.291745741 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 281128864908 ps |
| CPU time | 1043.34 seconds |
| Started | Jan 10 01:13:00 PM PST 24 |
| Finished | Jan 10 01:31:53 PM PST 24 |
| Peak memory | 198352 kb |
| Host | smart-0bea631e-9b15-4abf-8a9d-e53deca78153 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =291745741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.291745741 |
| Directory | /workspace/38.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.gpio_alert_test.3899884492 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 20065005 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:13:03 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 194164 kb |
| Host | smart-6c281e99-f15e-4b3b-a648-37efd55c184d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899884492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3899884492 |
| Directory | /workspace/39.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1118290932 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 63461952 ps |
| CPU time | 0.66 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:14:50 PM PST 24 |
| Peak memory | 194136 kb |
| Host | smart-5f1edf24-f206-4239-8cf7-067d58932758 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118290932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1118290932 |
| Directory | /workspace/39.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/39.gpio_filter_stress.2114777794 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 1196078989 ps |
| CPU time | 15.61 seconds |
| Started | Jan 10 01:13:00 PM PST 24 |
| Finished | Jan 10 01:14:41 PM PST 24 |
| Peak memory | 198168 kb |
| Host | smart-d48916b8-0ebd-43ce-8f38-0d78a639568a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114777794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre ss.2114777794 |
| Directory | /workspace/39.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/39.gpio_full_random.1454266342 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 72921701 ps |
| CPU time | 0.65 seconds |
| Started | Jan 10 01:13:12 PM PST 24 |
| Finished | Jan 10 01:14:42 PM PST 24 |
| Peak memory | 195464 kb |
| Host | smart-bba06407-edf4-42cd-9582-068449a52266 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454266342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1454266342 |
| Directory | /workspace/39.gpio_full_random/latest |
| Test location | /workspace/coverage/default/39.gpio_intr_rand_pgm.529163589 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 174146098 ps |
| CPU time | 1.21 seconds |
| Started | Jan 10 01:13:03 PM PST 24 |
| Finished | Jan 10 01:14:30 PM PST 24 |
| Peak memory | 196852 kb |
| Host | smart-a8c7f81f-c55b-4891-85a7-878e8cca26c4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529163589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.529163589 |
| Directory | /workspace/39.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.795660666 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 260294496 ps |
| CPU time | 2.37 seconds |
| Started | Jan 10 01:13:22 PM PST 24 |
| Finished | Jan 10 01:14:50 PM PST 24 |
| Peak memory | 198116 kb |
| Host | smart-531062f0-8c93-47fd-acb5-7e5790f5689e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795660666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 39.gpio_intr_with_filter_rand_intr_event.795660666 |
| Directory | /workspace/39.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/39.gpio_rand_intr_trigger.4166312274 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 48790828 ps |
| CPU time | 1.51 seconds |
| Started | Jan 10 01:13:07 PM PST 24 |
| Finished | Jan 10 01:14:36 PM PST 24 |
| Peak memory | 196216 kb |
| Host | smart-5af62e03-b091-40cf-9f5f-9e09bff42abd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166312274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger .4166312274 |
| Directory | /workspace/39.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/39.gpio_random_dout_din.2093746269 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 20239090 ps |
| CPU time | 0.68 seconds |
| Started | Jan 10 01:13:04 PM PST 24 |
| Finished | Jan 10 01:14:31 PM PST 24 |
| Peak memory | 194272 kb |
| Host | smart-2d70083a-9770-4370-acc2-00fb24bcb85b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2093746269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2093746269 |
| Directory | /workspace/39.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2198381457 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 34001837 ps |
| CPU time | 1.06 seconds |
| Started | Jan 10 01:12:58 PM PST 24 |
| Finished | Jan 10 01:14:24 PM PST 24 |
| Peak memory | 196224 kb |
| Host | smart-9c7a5c6f-f79e-4f6b-a952-558c6d72ec5e |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198381457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu p_pulldown.2198381457 |
| Directory | /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3713691368 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 31234027 ps |
| CPU time | 1.43 seconds |
| Started | Jan 10 01:13:01 PM PST 24 |
| Finished | Jan 10 01:14:27 PM PST 24 |
| Peak memory | 197972 kb |
| Host | smart-2efeb901-cc20-4918-bc6d-f04e7d84effe |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713691368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra ndom_long_reg_writes_reg_reads.3713691368 |
| Directory | /workspace/39.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/39.gpio_smoke.320165337 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 64687460 ps |
| CPU time | 0.91 seconds |
| Started | Jan 10 01:13:03 PM PST 24 |
| Finished | Jan 10 01:14:31 PM PST 24 |
| Peak memory | 195672 kb |
| Host | smart-a34a851e-5f1c-4508-a062-6efd6ceec09e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320165337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.320165337 |
| Directory | /workspace/39.gpio_smoke/latest |
| Test location | /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1981139360 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 202850679 ps |
| CPU time | 0.89 seconds |
| Started | Jan 10 01:13:22 PM PST 24 |
| Finished | Jan 10 01:14:48 PM PST 24 |
| Peak memory | 197304 kb |
| Host | smart-48a254bf-6533-44ee-8a60-307b4341f89f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981139360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1981139360 |
| Directory | /workspace/39.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/39.gpio_stress_all.1379303369 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 135740729124 ps |
| CPU time | 160.81 seconds |
| Started | Jan 10 01:13:00 PM PST 24 |
| Finished | Jan 10 01:17:06 PM PST 24 |
| Peak memory | 198192 kb |
| Host | smart-b53e7d1b-c496-41d2-b774-132221117f69 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379303369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. gpio_stress_all.1379303369 |
| Directory | /workspace/39.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.3007671735 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 109769375360 ps |
| CPU time | 1420.77 seconds |
| Started | Jan 10 01:13:05 PM PST 24 |
| Finished | Jan 10 01:38:12 PM PST 24 |
| Peak memory | 198368 kb |
| Host | smart-3cd6bbde-3747-4ab0-91ae-1fe3873311d3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3007671735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.3007671735 |
| Directory | /workspace/39.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.gpio_alert_test.1740644999 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 45048274 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:24 PM PST 24 |
| Peak memory | 194260 kb |
| Host | smart-afd31e26-ee88-42e1-83dd-5331d93d1c89 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740644999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1740644999 |
| Directory | /workspace/4.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3331171458 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 25757455 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 01:12:02 PM PST 24 |
| Finished | Jan 10 01:13:16 PM PST 24 |
| Peak memory | 194300 kb |
| Host | smart-70dcba2a-dae0-4182-9cab-7b6c029c7f1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3331171458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3331171458 |
| Directory | /workspace/4.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/4.gpio_filter_stress.2520179836 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 4913635840 ps |
| CPU time | 27.47 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:14:08 PM PST 24 |
| Peak memory | 197660 kb |
| Host | smart-309708a4-c09c-4e7a-b337-a166b25383a9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520179836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres s.2520179836 |
| Directory | /workspace/4.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/4.gpio_full_random.2325680261 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 79796242 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 01:12:05 PM PST 24 |
| Finished | Jan 10 01:13:20 PM PST 24 |
| Peak memory | 196584 kb |
| Host | smart-8ae98d3b-c64b-467b-8c7d-6555cd911603 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325680261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2325680261 |
| Directory | /workspace/4.gpio_full_random/latest |
| Test location | /workspace/coverage/default/4.gpio_intr_rand_pgm.2534656040 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 97166965 ps |
| CPU time | 1.51 seconds |
| Started | Jan 10 01:11:59 PM PST 24 |
| Finished | Jan 10 01:13:12 PM PST 24 |
| Peak memory | 198104 kb |
| Host | smart-7d7662cd-927e-4849-a90c-1bc3c7fd7d9b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534656040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2534656040 |
| Directory | /workspace/4.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1147993537 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 141999343 ps |
| CPU time | 2.69 seconds |
| Started | Jan 10 01:12:36 PM PST 24 |
| Finished | Jan 10 01:13:59 PM PST 24 |
| Peak memory | 198324 kb |
| Host | smart-8824740f-3543-4b0f-b4ac-4e91a765d29c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147993537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1147993537 |
| Directory | /workspace/4.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/4.gpio_rand_intr_trigger.1219917723 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 144457400 ps |
| CPU time | 1.87 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:26 PM PST 24 |
| Peak memory | 195916 kb |
| Host | smart-ceeddbe1-855b-4c39-af5c-0975ceb16ebc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219917723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger. 1219917723 |
| Directory | /workspace/4.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/4.gpio_random_dout_din.1159506501 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 41665163 ps |
| CPU time | 1.02 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:13:41 PM PST 24 |
| Peak memory | 196092 kb |
| Host | smart-745f5d31-c1ae-4e7a-943f-8b250904c4e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1159506501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1159506501 |
| Directory | /workspace/4.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2517607848 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 84172635 ps |
| CPU time | 0.92 seconds |
| Started | Jan 10 01:12:09 PM PST 24 |
| Finished | Jan 10 01:13:25 PM PST 24 |
| Peak memory | 196692 kb |
| Host | smart-be60d010-d149-476b-8c78-1238e698b2b2 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517607848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup _pulldown.2517607848 |
| Directory | /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2325447153 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2014127061 ps |
| CPU time | 5.75 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:27 PM PST 24 |
| Peak memory | 197992 kb |
| Host | smart-c6c5ee5b-9979-4d37-93b5-c04ebf8e94c0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325447153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran dom_long_reg_writes_reg_reads.2325447153 |
| Directory | /workspace/4.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/4.gpio_sec_cm.275339874 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 62960776 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:12:01 PM PST 24 |
| Finished | Jan 10 01:13:15 PM PST 24 |
| Peak memory | 213424 kb |
| Host | smart-c3cddbd0-2e19-4a01-a422-73e5791240e2 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275339874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.275339874 |
| Directory | /workspace/4.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/4.gpio_smoke.2141318396 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 339943978 ps |
| CPU time | 1.38 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:38 PM PST 24 |
| Peak memory | 196760 kb |
| Host | smart-a577da96-7cd8-4731-8c71-b47b8045e9b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2141318396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2141318396 |
| Directory | /workspace/4.gpio_smoke/latest |
| Test location | /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.518148743 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 75494852 ps |
| CPU time | 1.15 seconds |
| Started | Jan 10 01:12:14 PM PST 24 |
| Finished | Jan 10 01:13:36 PM PST 24 |
| Peak memory | 198240 kb |
| Host | smart-db6e4cd8-6700-42f0-a648-30916c2e2d01 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518148743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.518148743 |
| Directory | /workspace/4.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/4.gpio_stress_all.1358417577 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4168990996 ps |
| CPU time | 44.08 seconds |
| Started | Jan 10 01:12:00 PM PST 24 |
| Finished | Jan 10 01:13:56 PM PST 24 |
| Peak memory | 198104 kb |
| Host | smart-a7117590-380a-4d10-b8ef-fc1e4db8eb83 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358417577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g pio_stress_all.1358417577 |
| Directory | /workspace/4.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.47865080 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 243754989510 ps |
| CPU time | 1674.78 seconds |
| Started | Jan 10 01:12:06 PM PST 24 |
| Finished | Jan 10 01:41:15 PM PST 24 |
| Peak memory | 198244 kb |
| Host | smart-98a7fecf-3a45-4bc1-ad61-d8638d5ef01f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =47865080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.47865080 |
| Directory | /workspace/4.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.gpio_alert_test.434141312 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 16423961 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:12:55 PM PST 24 |
| Finished | Jan 10 01:14:19 PM PST 24 |
| Peak memory | 194984 kb |
| Host | smart-93abb06f-4a1d-457c-83e1-c3fb8d8a7ada |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434141312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.434141312 |
| Directory | /workspace/40.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2050044799 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 87918654 ps |
| CPU time | 0.8 seconds |
| Started | Jan 10 01:13:30 PM PST 24 |
| Finished | Jan 10 01:14:55 PM PST 24 |
| Peak memory | 196184 kb |
| Host | smart-75cb5349-80e1-4871-984a-92edf4329b97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2050044799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2050044799 |
| Directory | /workspace/40.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/40.gpio_filter_stress.3806604249 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 897186792 ps |
| CPU time | 13.67 seconds |
| Started | Jan 10 01:12:53 PM PST 24 |
| Finished | Jan 10 01:14:34 PM PST 24 |
| Peak memory | 197296 kb |
| Host | smart-234cb209-af71-44ea-8258-0a3272be38e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806604249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre ss.3806604249 |
| Directory | /workspace/40.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/40.gpio_full_random.3244787668 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 326996551 ps |
| CPU time | 0.63 seconds |
| Started | Jan 10 01:12:57 PM PST 24 |
| Finished | Jan 10 01:14:23 PM PST 24 |
| Peak memory | 194592 kb |
| Host | smart-97a0a872-59fd-44f9-9b26-c9e42495afa8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244787668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3244787668 |
| Directory | /workspace/40.gpio_full_random/latest |
| Test location | /workspace/coverage/default/40.gpio_intr_rand_pgm.1223959880 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 144640019 ps |
| CPU time | 0.74 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:14:53 PM PST 24 |
| Peak memory | 195636 kb |
| Host | smart-9b0a7210-931c-48af-b03a-4bfd293f26c7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223959880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1223959880 |
| Directory | /workspace/40.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1402430173 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 85663309 ps |
| CPU time | 1.12 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:14:39 PM PST 24 |
| Peak memory | 196420 kb |
| Host | smart-eab1a1f5-92fe-45ad-8f03-aea71fe1dd0c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402430173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1402430173 |
| Directory | /workspace/40.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/40.gpio_rand_intr_trigger.1314642603 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 47491875 ps |
| CPU time | 1.07 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:14:34 PM PST 24 |
| Peak memory | 195884 kb |
| Host | smart-ded65810-67a4-4712-9d2e-5a260f651c11 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314642603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger .1314642603 |
| Directory | /workspace/40.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/40.gpio_random_dout_din.1908123260 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 88905983 ps |
| CPU time | 0.67 seconds |
| Started | Jan 10 01:13:16 PM PST 24 |
| Finished | Jan 10 01:14:53 PM PST 24 |
| Peak memory | 194244 kb |
| Host | smart-0d56b210-ed08-43d3-a021-81e253f34a32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908123260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1908123260 |
| Directory | /workspace/40.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.951168676 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 40465563 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:12:59 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 195608 kb |
| Host | smart-4878454f-1461-4faa-bf4c-52902ea7d3c5 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951168676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup _pulldown.951168676 |
| Directory | /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3808260505 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 49580636 ps |
| CPU time | 2.03 seconds |
| Started | Jan 10 01:13:00 PM PST 24 |
| Finished | Jan 10 01:14:56 PM PST 24 |
| Peak memory | 197964 kb |
| Host | smart-3e5cc1a9-4c13-4be5-a6a5-611bf7502c91 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808260505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra ndom_long_reg_writes_reg_reads.3808260505 |
| Directory | /workspace/40.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/40.gpio_smoke.3572849755 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 39636983 ps |
| CPU time | 1.25 seconds |
| Started | Jan 10 01:13:06 PM PST 24 |
| Finished | Jan 10 01:14:52 PM PST 24 |
| Peak memory | 195800 kb |
| Host | smart-99aa01e1-0dfd-450f-9c92-ec7664b06c1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3572849755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3572849755 |
| Directory | /workspace/40.gpio_smoke/latest |
| Test location | /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2978294293 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 52959803 ps |
| CPU time | 1.36 seconds |
| Started | Jan 10 01:12:59 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 195696 kb |
| Host | smart-df2643f9-dbf6-40c7-99d9-8874d57c80ec |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978294293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2978294293 |
| Directory | /workspace/40.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/40.gpio_stress_all.1157191332 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 16295418126 ps |
| CPU time | 162.89 seconds |
| Started | Jan 10 01:12:52 PM PST 24 |
| Finished | Jan 10 01:17:02 PM PST 24 |
| Peak memory | 198104 kb |
| Host | smart-ca6b3921-90ae-4aad-81cb-007118a8230e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157191332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. gpio_stress_all.1157191332 |
| Directory | /workspace/40.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.3437373916 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 219904374316 ps |
| CPU time | 1289.97 seconds |
| Started | Jan 10 01:13:01 PM PST 24 |
| Finished | Jan 10 01:36:02 PM PST 24 |
| Peak memory | 198316 kb |
| Host | smart-02b9f88f-7f5a-4058-a642-b3845a1ab79e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3437373916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.3437373916 |
| Directory | /workspace/40.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.gpio_alert_test.4136423846 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13743544 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:13:27 PM PST 24 |
| Finished | Jan 10 01:14:59 PM PST 24 |
| Peak memory | 193556 kb |
| Host | smart-a833ae04-223e-4616-9cbd-5f823311435e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136423846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.4136423846 |
| Directory | /workspace/41.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3300094046 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 15319275 ps |
| CPU time | 0.61 seconds |
| Started | Jan 10 01:13:19 PM PST 24 |
| Finished | Jan 10 01:14:47 PM PST 24 |
| Peak memory | 193908 kb |
| Host | smart-b413c6bf-eb98-496e-a4bb-dd38192ada10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3300094046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3300094046 |
| Directory | /workspace/41.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/41.gpio_filter_stress.3986909206 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 280776648 ps |
| CPU time | 8.48 seconds |
| Started | Jan 10 01:13:19 PM PST 24 |
| Finished | Jan 10 01:14:56 PM PST 24 |
| Peak memory | 197084 kb |
| Host | smart-5ba3dfce-f195-413c-aaa9-f31687d1b7d1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986909206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre ss.3986909206 |
| Directory | /workspace/41.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/41.gpio_full_random.2292213628 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 128464569 ps |
| CPU time | 0.64 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:14:53 PM PST 24 |
| Peak memory | 195412 kb |
| Host | smart-f1795a40-5b3c-4bd7-b899-50e9343ddba8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292213628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2292213628 |
| Directory | /workspace/41.gpio_full_random/latest |
| Test location | /workspace/coverage/default/41.gpio_intr_rand_pgm.1151488910 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 333081474 ps |
| CPU time | 1.27 seconds |
| Started | Jan 10 01:13:23 PM PST 24 |
| Finished | Jan 10 01:14:51 PM PST 24 |
| Peak memory | 198188 kb |
| Host | smart-4bde36d7-000f-4d0c-8088-d96c7ae01344 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151488910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1151488910 |
| Directory | /workspace/41.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3848204010 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 92283330 ps |
| CPU time | 1.12 seconds |
| Started | Jan 10 01:13:23 PM PST 24 |
| Finished | Jan 10 01:14:58 PM PST 24 |
| Peak memory | 197528 kb |
| Host | smart-f4297e79-7831-40f8-b040-56ed3d71ea81 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848204010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3848204010 |
| Directory | /workspace/41.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/41.gpio_rand_intr_trigger.2347528052 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 641817036 ps |
| CPU time | 2.95 seconds |
| Started | Jan 10 01:13:08 PM PST 24 |
| Finished | Jan 10 01:14:37 PM PST 24 |
| Peak memory | 197032 kb |
| Host | smart-c01bd7f4-b6f8-4a23-8395-c1231735d054 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347528052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger .2347528052 |
| Directory | /workspace/41.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/41.gpio_random_dout_din.3536137783 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 44537327 ps |
| CPU time | 1.04 seconds |
| Started | Jan 10 01:13:05 PM PST 24 |
| Finished | Jan 10 01:14:36 PM PST 24 |
| Peak memory | 196956 kb |
| Host | smart-20cfd25a-7ae7-4e56-9e7b-12777074f296 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3536137783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3536137783 |
| Directory | /workspace/41.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.4011968535 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 32567924 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:14:39 PM PST 24 |
| Peak memory | 196072 kb |
| Host | smart-dca3a61b-ff68-4107-b31e-fe2d8d9ffb5b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011968535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu p_pulldown.4011968535 |
| Directory | /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1420902185 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 88639916 ps |
| CPU time | 2.17 seconds |
| Started | Jan 10 01:13:01 PM PST 24 |
| Finished | Jan 10 01:14:28 PM PST 24 |
| Peak memory | 198100 kb |
| Host | smart-c78af72c-2852-45ed-beff-33ea5dc26fc7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420902185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra ndom_long_reg_writes_reg_reads.1420902185 |
| Directory | /workspace/41.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/41.gpio_smoke.541649172 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 148367922 ps |
| CPU time | 1.33 seconds |
| Started | Jan 10 01:13:04 PM PST 24 |
| Finished | Jan 10 01:14:31 PM PST 24 |
| Peak memory | 196972 kb |
| Host | smart-fd575187-2d20-4a52-982e-870da572c060 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=541649172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.541649172 |
| Directory | /workspace/41.gpio_smoke/latest |
| Test location | /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1127196816 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 221252404 ps |
| CPU time | 0.8 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:14:51 PM PST 24 |
| Peak memory | 195300 kb |
| Host | smart-daf92f01-e6b3-4510-8825-d86c75c6229b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127196816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1127196816 |
| Directory | /workspace/41.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/41.gpio_stress_all.3392591641 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 278851514927 ps |
| CPU time | 244.67 seconds |
| Started | Jan 10 01:13:01 PM PST 24 |
| Finished | Jan 10 01:18:36 PM PST 24 |
| Peak memory | 198264 kb |
| Host | smart-7920012f-3863-47a5-80be-235fd35fd88a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392591641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. gpio_stress_all.3392591641 |
| Directory | /workspace/41.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.2760596708 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 14090449731 ps |
| CPU time | 191.86 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:18:08 PM PST 24 |
| Peak memory | 198396 kb |
| Host | smart-6764b971-5e33-4efc-b2eb-1456d5c2e292 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2760596708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.2760596708 |
| Directory | /workspace/41.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.gpio_alert_test.3395769314 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 24445285 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:13:16 PM PST 24 |
| Finished | Jan 10 01:14:51 PM PST 24 |
| Peak memory | 194296 kb |
| Host | smart-a82fa9cd-a4a5-44cc-bcca-0b8ea5752adb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395769314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3395769314 |
| Directory | /workspace/42.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1114242193 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 70745932 ps |
| CPU time | 0.62 seconds |
| Started | Jan 10 01:13:05 PM PST 24 |
| Finished | Jan 10 01:14:36 PM PST 24 |
| Peak memory | 194892 kb |
| Host | smart-74f0c97a-4cbf-4937-85ca-489c2cbb00dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114242193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1114242193 |
| Directory | /workspace/42.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/42.gpio_filter_stress.1608928963 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 192577798 ps |
| CPU time | 9.45 seconds |
| Started | Jan 10 01:13:06 PM PST 24 |
| Finished | Jan 10 01:14:42 PM PST 24 |
| Peak memory | 197080 kb |
| Host | smart-a22aee68-e1b3-4ca4-8824-1f3828969d96 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608928963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre ss.1608928963 |
| Directory | /workspace/42.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/42.gpio_full_random.3804323104 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 104656214 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:13:33 PM PST 24 |
| Finished | Jan 10 01:14:57 PM PST 24 |
| Peak memory | 196764 kb |
| Host | smart-486cad32-2e22-4678-aaa5-c7f58301b7d0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804323104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3804323104 |
| Directory | /workspace/42.gpio_full_random/latest |
| Test location | /workspace/coverage/default/42.gpio_intr_rand_pgm.2256760767 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 28009091 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 01:13:02 PM PST 24 |
| Finished | Jan 10 01:14:32 PM PST 24 |
| Peak memory | 195388 kb |
| Host | smart-cf5fb138-7da4-4a84-bf41-7423f8e61bb4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256760767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2256760767 |
| Directory | /workspace/42.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.122949754 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 879411745 ps |
| CPU time | 3.6 seconds |
| Started | Jan 10 01:13:38 PM PST 24 |
| Finished | Jan 10 01:15:02 PM PST 24 |
| Peak memory | 198208 kb |
| Host | smart-5ebd28f9-eded-4562-88c8-b5bbf3b196bb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122949754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 42.gpio_intr_with_filter_rand_intr_event.122949754 |
| Directory | /workspace/42.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/42.gpio_rand_intr_trigger.2278695920 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 150788324 ps |
| CPU time | 1.55 seconds |
| Started | Jan 10 01:13:44 PM PST 24 |
| Finished | Jan 10 01:15:04 PM PST 24 |
| Peak memory | 196020 kb |
| Host | smart-8894da86-cfbc-4f32-b2fd-1320727a561b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278695920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger .2278695920 |
| Directory | /workspace/42.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/42.gpio_random_dout_din.1517528526 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 58385040 ps |
| CPU time | 1.08 seconds |
| Started | Jan 10 01:13:03 PM PST 24 |
| Finished | Jan 10 01:14:30 PM PST 24 |
| Peak memory | 195932 kb |
| Host | smart-043fb640-1eac-4133-a4a2-9adfc7a01475 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1517528526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1517528526 |
| Directory | /workspace/42.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3963652389 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 31765198 ps |
| CPU time | 1.13 seconds |
| Started | Jan 10 01:13:03 PM PST 24 |
| Finished | Jan 10 01:14:31 PM PST 24 |
| Peak memory | 197368 kb |
| Host | smart-1ac50bd5-ba86-4625-b6da-77b695aee7bd |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963652389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu p_pulldown.3963652389 |
| Directory | /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2592320997 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 120736606 ps |
| CPU time | 1.25 seconds |
| Started | Jan 10 01:13:40 PM PST 24 |
| Finished | Jan 10 01:15:00 PM PST 24 |
| Peak memory | 198124 kb |
| Host | smart-3153ea39-3a51-43de-b4bd-cc2e90578336 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592320997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra ndom_long_reg_writes_reg_reads.2592320997 |
| Directory | /workspace/42.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/42.gpio_smoke.3340059883 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 52256212 ps |
| CPU time | 1.09 seconds |
| Started | Jan 10 01:13:53 PM PST 24 |
| Finished | Jan 10 01:15:06 PM PST 24 |
| Peak memory | 195820 kb |
| Host | smart-3407431c-6f88-4651-b2da-be64b3bf800d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340059883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3340059883 |
| Directory | /workspace/42.gpio_smoke/latest |
| Test location | /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2113673647 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 646573792 ps |
| CPU time | 1.19 seconds |
| Started | Jan 10 01:13:12 PM PST 24 |
| Finished | Jan 10 01:14:43 PM PST 24 |
| Peak memory | 195940 kb |
| Host | smart-845c740d-8aec-4f25-8599-72e92c3ce084 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113673647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2113673647 |
| Directory | /workspace/42.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/42.gpio_stress_all.1269761293 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2163594476 ps |
| CPU time | 27.01 seconds |
| Started | Jan 10 01:13:10 PM PST 24 |
| Finished | Jan 10 01:15:03 PM PST 24 |
| Peak memory | 198276 kb |
| Host | smart-89618ace-c536-44cf-9c74-8b5298330a7c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269761293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. gpio_stress_all.1269761293 |
| Directory | /workspace/42.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.4064090535 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 672303972243 ps |
| CPU time | 1099.95 seconds |
| Started | Jan 10 01:13:16 PM PST 24 |
| Finished | Jan 10 01:33:12 PM PST 24 |
| Peak memory | 198400 kb |
| Host | smart-121fc9f2-ddfd-4966-93f1-d2544b2b3b60 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4064090535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.4064090535 |
| Directory | /workspace/42.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.gpio_alert_test.2043973786 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 37092911 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:13:04 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 194084 kb |
| Host | smart-b19a22a5-7a22-4797-9c54-6fde5a4f22c8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043973786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2043973786 |
| Directory | /workspace/43.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.569295526 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 36290488 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:14:54 PM PST 24 |
| Peak memory | 196272 kb |
| Host | smart-250dc23c-fd0d-441c-9244-0826cf7ced94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=569295526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.569295526 |
| Directory | /workspace/43.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/43.gpio_filter_stress.3813275816 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 788468696 ps |
| CPU time | 20.45 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:15:10 PM PST 24 |
| Peak memory | 197024 kb |
| Host | smart-b33e75ce-e4c6-413d-9589-bdbe245ca922 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813275816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre ss.3813275816 |
| Directory | /workspace/43.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/43.gpio_full_random.2926466109 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 70146608 ps |
| CPU time | 0.98 seconds |
| Started | Jan 10 01:13:10 PM PST 24 |
| Finished | Jan 10 01:14:38 PM PST 24 |
| Peak memory | 197616 kb |
| Host | smart-f0b968bb-56c0-4784-b909-1d496b998cf2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926466109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2926466109 |
| Directory | /workspace/43.gpio_full_random/latest |
| Test location | /workspace/coverage/default/43.gpio_intr_rand_pgm.2412614276 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 47507572 ps |
| CPU time | 0.84 seconds |
| Started | Jan 10 01:13:20 PM PST 24 |
| Finished | Jan 10 01:15:01 PM PST 24 |
| Peak memory | 195648 kb |
| Host | smart-ce34ce60-c446-4675-a0d1-5f83bd1af148 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412614276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2412614276 |
| Directory | /workspace/43.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2744965721 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 72129295 ps |
| CPU time | 2.7 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:14:42 PM PST 24 |
| Peak memory | 198116 kb |
| Host | smart-c4af8e15-bcea-47b0-b3de-3d630cb4dbfe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744965721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2744965721 |
| Directory | /workspace/43.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/43.gpio_rand_intr_trigger.2458453910 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 184947925 ps |
| CPU time | 2.59 seconds |
| Started | Jan 10 01:13:14 PM PST 24 |
| Finished | Jan 10 01:14:43 PM PST 24 |
| Peak memory | 197240 kb |
| Host | smart-510a5e4e-d9b0-43cf-bfa9-d9293bd96de6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458453910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger .2458453910 |
| Directory | /workspace/43.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/43.gpio_random_dout_din.2432050599 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 66204421 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:13:08 PM PST 24 |
| Finished | Jan 10 01:14:35 PM PST 24 |
| Peak memory | 195844 kb |
| Host | smart-8f53a45a-b2b7-4bfe-a580-aef0e79dcc22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2432050599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2432050599 |
| Directory | /workspace/43.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2550617707 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 85220675 ps |
| CPU time | 0.77 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:14:40 PM PST 24 |
| Peak memory | 195408 kb |
| Host | smart-69ad0e9a-2957-4219-ac0b-f349840464bc |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550617707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu p_pulldown.2550617707 |
| Directory | /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2380969060 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 135541031 ps |
| CPU time | 1.78 seconds |
| Started | Jan 10 01:12:59 PM PST 24 |
| Finished | Jan 10 01:14:34 PM PST 24 |
| Peak memory | 198128 kb |
| Host | smart-3803fff6-4876-497e-90e7-2e76f6a77457 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380969060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra ndom_long_reg_writes_reg_reads.2380969060 |
| Directory | /workspace/43.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/43.gpio_smoke.3428469188 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 269700552 ps |
| CPU time | 1.25 seconds |
| Started | Jan 10 01:13:06 PM PST 24 |
| Finished | Jan 10 01:14:34 PM PST 24 |
| Peak memory | 196912 kb |
| Host | smart-56a5a43d-5e4d-4fcd-aa88-5ff0e8fbc633 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3428469188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3428469188 |
| Directory | /workspace/43.gpio_smoke/latest |
| Test location | /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3484755771 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 91623375 ps |
| CPU time | 1.01 seconds |
| Started | Jan 10 01:13:14 PM PST 24 |
| Finished | Jan 10 01:14:42 PM PST 24 |
| Peak memory | 196504 kb |
| Host | smart-dcd17869-d176-478e-bc47-cdfec8807a49 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484755771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3484755771 |
| Directory | /workspace/43.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/43.gpio_stress_all.3022995972 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 4360789706 ps |
| CPU time | 21.67 seconds |
| Started | Jan 10 01:13:47 PM PST 24 |
| Finished | Jan 10 01:15:25 PM PST 24 |
| Peak memory | 198284 kb |
| Host | smart-47607027-7bde-4f02-8b63-11af3b8aadd7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022995972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. gpio_stress_all.3022995972 |
| Directory | /workspace/43.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.4101618192 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 39531601609 ps |
| CPU time | 468.51 seconds |
| Started | Jan 10 01:13:15 PM PST 24 |
| Finished | Jan 10 01:22:28 PM PST 24 |
| Peak memory | 198400 kb |
| Host | smart-bbdbc91a-a055-448d-853a-352261570850 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4101618192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.4101618192 |
| Directory | /workspace/43.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.gpio_alert_test.4024299517 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 50705205 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:13:12 PM PST 24 |
| Finished | Jan 10 01:14:43 PM PST 24 |
| Peak memory | 194292 kb |
| Host | smart-6ffed69d-fa8e-4787-8df4-bad94d575c2a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024299517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.4024299517 |
| Directory | /workspace/44.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.4205874222 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 48919694 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:13:08 PM PST 24 |
| Finished | Jan 10 01:14:36 PM PST 24 |
| Peak memory | 196496 kb |
| Host | smart-e11c4d69-b523-4efc-b012-fb2f88f03e5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205874222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.4205874222 |
| Directory | /workspace/44.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/44.gpio_filter_stress.2813214829 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 302691595 ps |
| CPU time | 14.82 seconds |
| Started | Jan 10 01:13:00 PM PST 24 |
| Finished | Jan 10 01:14:40 PM PST 24 |
| Peak memory | 196756 kb |
| Host | smart-3ffa9cb8-72fa-491e-beef-fdff18824385 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813214829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre ss.2813214829 |
| Directory | /workspace/44.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/44.gpio_full_random.1445628032 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 124559974 ps |
| CPU time | 0.91 seconds |
| Started | Jan 10 01:13:03 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 197256 kb |
| Host | smart-ebb97e47-2ab8-46d1-b10e-9d1574d6d6f3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445628032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1445628032 |
| Directory | /workspace/44.gpio_full_random/latest |
| Test location | /workspace/coverage/default/44.gpio_intr_rand_pgm.2421499290 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 152427000 ps |
| CPU time | 0.93 seconds |
| Started | Jan 10 01:13:03 PM PST 24 |
| Finished | Jan 10 01:14:30 PM PST 24 |
| Peak memory | 196928 kb |
| Host | smart-93a5ee37-ebd6-479a-a2e9-05914c8f8088 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421499290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2421499290 |
| Directory | /workspace/44.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.250854723 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 51808970 ps |
| CPU time | 2.05 seconds |
| Started | Jan 10 01:13:15 PM PST 24 |
| Finished | Jan 10 01:14:43 PM PST 24 |
| Peak memory | 198188 kb |
| Host | smart-2eee2918-12c8-44ac-8224-292f20d97f02 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250854723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 44.gpio_intr_with_filter_rand_intr_event.250854723 |
| Directory | /workspace/44.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/44.gpio_rand_intr_trigger.3055459340 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 268404533 ps |
| CPU time | 2.83 seconds |
| Started | Jan 10 01:13:00 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 196520 kb |
| Host | smart-12cab991-b249-4d90-8dd5-34d46991a9aa |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055459340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger .3055459340 |
| Directory | /workspace/44.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/44.gpio_random_dout_din.2333078879 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 41071853 ps |
| CPU time | 0.96 seconds |
| Started | Jan 10 01:13:03 PM PST 24 |
| Finished | Jan 10 01:14:31 PM PST 24 |
| Peak memory | 195904 kb |
| Host | smart-097822e3-15df-4235-b58d-1544e472464a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2333078879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2333078879 |
| Directory | /workspace/44.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.4222717060 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 34309159 ps |
| CPU time | 0.8 seconds |
| Started | Jan 10 01:13:27 PM PST 24 |
| Finished | Jan 10 01:14:58 PM PST 24 |
| Peak memory | 196692 kb |
| Host | smart-a3b122a4-bb99-4187-8f30-6ac1688f9937 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222717060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu p_pulldown.4222717060 |
| Directory | /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1708798924 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 355258846 ps |
| CPU time | 4.26 seconds |
| Started | Jan 10 01:13:30 PM PST 24 |
| Finished | Jan 10 01:14:59 PM PST 24 |
| Peak memory | 198108 kb |
| Host | smart-dcd8e451-fb5b-4945-a4fd-0e6133b4732f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708798924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra ndom_long_reg_writes_reg_reads.1708798924 |
| Directory | /workspace/44.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/44.gpio_smoke.3415790083 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 26473700 ps |
| CPU time | 0.69 seconds |
| Started | Jan 10 01:13:48 PM PST 24 |
| Finished | Jan 10 01:15:04 PM PST 24 |
| Peak memory | 194868 kb |
| Host | smart-14185393-36a5-4e90-9def-65ed35454c3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3415790083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3415790083 |
| Directory | /workspace/44.gpio_smoke/latest |
| Test location | /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2176645733 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 170288629 ps |
| CPU time | 0.92 seconds |
| Started | Jan 10 01:13:07 PM PST 24 |
| Finished | Jan 10 01:14:35 PM PST 24 |
| Peak memory | 195812 kb |
| Host | smart-fb23f14f-81aa-4492-8f3a-5565d0eda935 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176645733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2176645733 |
| Directory | /workspace/44.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/44.gpio_stress_all.4019634026 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2226795705 ps |
| CPU time | 23.12 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:15:17 PM PST 24 |
| Peak memory | 198348 kb |
| Host | smart-72095ca0-9ea1-43f0-9eef-66c1e42e3300 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019634026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. gpio_stress_all.4019634026 |
| Directory | /workspace/44.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.1148185388 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 24503149118 ps |
| CPU time | 218.75 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:18:16 PM PST 24 |
| Peak memory | 198416 kb |
| Host | smart-5e5ffc6d-ba26-4669-a0a5-5e968d0e151b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1148185388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.1148185388 |
| Directory | /workspace/44.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.gpio_alert_test.2893699525 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 58043351 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:13:12 PM PST 24 |
| Finished | Jan 10 01:14:38 PM PST 24 |
| Peak memory | 194896 kb |
| Host | smart-e97379e3-55f2-4392-876f-5df2893999ac |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893699525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2893699525 |
| Directory | /workspace/45.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.935834737 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 64040351 ps |
| CPU time | 0.7 seconds |
| Started | Jan 10 01:13:16 PM PST 24 |
| Finished | Jan 10 01:14:43 PM PST 24 |
| Peak memory | 194168 kb |
| Host | smart-67313f52-54fc-48bb-b080-7ed8dbf63934 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935834737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.935834737 |
| Directory | /workspace/45.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/45.gpio_filter_stress.2681700297 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 1136039882 ps |
| CPU time | 9.21 seconds |
| Started | Jan 10 01:15:55 PM PST 24 |
| Finished | Jan 10 01:16:06 PM PST 24 |
| Peak memory | 195440 kb |
| Host | smart-38467095-9669-463d-9042-c0861900bb0f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681700297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre ss.2681700297 |
| Directory | /workspace/45.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/45.gpio_full_random.2032172747 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 36216349 ps |
| CPU time | 0.68 seconds |
| Started | Jan 10 01:13:22 PM PST 24 |
| Finished | Jan 10 01:14:48 PM PST 24 |
| Peak memory | 194644 kb |
| Host | smart-34f34381-ad40-49af-ae89-5f797468c3c5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032172747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2032172747 |
| Directory | /workspace/45.gpio_full_random/latest |
| Test location | /workspace/coverage/default/45.gpio_intr_rand_pgm.2053399670 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 142523831 ps |
| CPU time | 0.99 seconds |
| Started | Jan 10 01:13:17 PM PST 24 |
| Finished | Jan 10 01:14:44 PM PST 24 |
| Peak memory | 196044 kb |
| Host | smart-702fae1c-dae8-4f2e-a897-b27418b243a9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053399670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2053399670 |
| Directory | /workspace/45.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2442550729 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 92762175 ps |
| CPU time | 3.52 seconds |
| Started | Jan 10 01:13:15 PM PST 24 |
| Finished | Jan 10 01:14:45 PM PST 24 |
| Peak memory | 198172 kb |
| Host | smart-f52dd943-1e96-47af-bd6b-55988de228cd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442550729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2442550729 |
| Directory | /workspace/45.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/45.gpio_rand_intr_trigger.3851522815 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 101041260 ps |
| CPU time | 2.84 seconds |
| Started | Jan 10 01:13:16 PM PST 24 |
| Finished | Jan 10 01:14:53 PM PST 24 |
| Peak memory | 198200 kb |
| Host | smart-be683e6e-9f0e-45ea-86c6-77d61ae2ab15 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851522815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger .3851522815 |
| Directory | /workspace/45.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/45.gpio_random_dout_din.2714212163 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 106750929 ps |
| CPU time | 0.77 seconds |
| Started | Jan 10 01:13:46 PM PST 24 |
| Finished | Jan 10 01:15:03 PM PST 24 |
| Peak memory | 196156 kb |
| Host | smart-bc78f20c-bf18-43e2-b126-72f58bb9816e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714212163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2714212163 |
| Directory | /workspace/45.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3928340426 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 70566267 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:14:36 PM PST 24 |
| Peak memory | 196388 kb |
| Host | smart-bbfd55de-5873-4d48-90b5-b2ea917cccca |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928340426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu p_pulldown.3928340426 |
| Directory | /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.810341825 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2419055017 ps |
| CPU time | 6.52 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:15:03 PM PST 24 |
| Peak memory | 198048 kb |
| Host | smart-bb8211ce-eece-4db8-888a-3adfb15b5ac7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810341825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran dom_long_reg_writes_reg_reads.810341825 |
| Directory | /workspace/45.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/45.gpio_smoke.2945783282 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 94393342 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 01:13:10 PM PST 24 |
| Finished | Jan 10 01:14:38 PM PST 24 |
| Peak memory | 195868 kb |
| Host | smart-5cd47b39-f0be-4637-b08a-8e79049fd4d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2945783282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2945783282 |
| Directory | /workspace/45.gpio_smoke/latest |
| Test location | /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.835352294 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 28654766 ps |
| CPU time | 0.94 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:14:51 PM PST 24 |
| Peak memory | 196696 kb |
| Host | smart-f6012481-d88d-40eb-b7ee-d54110c154fe |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835352294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.835352294 |
| Directory | /workspace/45.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/45.gpio_stress_all.1477221623 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 26109879145 ps |
| CPU time | 88.05 seconds |
| Started | Jan 10 01:13:19 PM PST 24 |
| Finished | Jan 10 01:16:13 PM PST 24 |
| Peak memory | 198096 kb |
| Host | smart-6e7ea1f5-7c7b-4b13-9ff3-763cc6206b73 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477221623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. gpio_stress_all.1477221623 |
| Directory | /workspace/45.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1757830570 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 56639969685 ps |
| CPU time | 1441.65 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:38:51 PM PST 24 |
| Peak memory | 198400 kb |
| Host | smart-87ba66b4-448a-4212-b8e5-899348df59b9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1757830570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1757830570 |
| Directory | /workspace/45.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.gpio_alert_test.4265553864 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 13191915 ps |
| CPU time | 0.54 seconds |
| Started | Jan 10 01:13:50 PM PST 24 |
| Finished | Jan 10 01:15:04 PM PST 24 |
| Peak memory | 194084 kb |
| Host | smart-54a89767-bb72-4188-97a1-7f4467996f16 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265553864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.4265553864 |
| Directory | /workspace/46.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3770241685 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 149898307 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:13:09 PM PST 24 |
| Finished | Jan 10 01:14:54 PM PST 24 |
| Peak memory | 195488 kb |
| Host | smart-d132fcd1-992d-4c6a-aff6-9a92f69c760e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770241685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3770241685 |
| Directory | /workspace/46.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/46.gpio_filter_stress.4263827082 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 2017764796 ps |
| CPU time | 16.94 seconds |
| Started | Jan 10 01:13:20 PM PST 24 |
| Finished | Jan 10 01:15:11 PM PST 24 |
| Peak memory | 196820 kb |
| Host | smart-2fdc5dc3-3f6f-4b7d-9401-11779bc211b2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263827082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre ss.4263827082 |
| Directory | /workspace/46.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/46.gpio_full_random.71542015 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 36804466 ps |
| CPU time | 0.68 seconds |
| Started | Jan 10 01:13:19 PM PST 24 |
| Finished | Jan 10 01:14:48 PM PST 24 |
| Peak memory | 194720 kb |
| Host | smart-ae3f4085-3916-4211-85bf-7d4d5823450d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71542015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.71542015 |
| Directory | /workspace/46.gpio_full_random/latest |
| Test location | /workspace/coverage/default/46.gpio_intr_rand_pgm.788196528 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 202757986 ps |
| CPU time | 1.04 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:14:40 PM PST 24 |
| Peak memory | 196172 kb |
| Host | smart-d9da7314-6f16-4605-b5ea-57a6e0407c71 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788196528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.788196528 |
| Directory | /workspace/46.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2231978177 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 31718761 ps |
| CPU time | 1.34 seconds |
| Started | Jan 10 01:13:36 PM PST 24 |
| Finished | Jan 10 01:14:58 PM PST 24 |
| Peak memory | 198328 kb |
| Host | smart-eebe7a9d-4a65-4791-8712-e368f6f0ec3e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231978177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2231978177 |
| Directory | /workspace/46.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/46.gpio_rand_intr_trigger.2890886501 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2336290202 ps |
| CPU time | 3.58 seconds |
| Started | Jan 10 01:13:12 PM PST 24 |
| Finished | Jan 10 01:14:42 PM PST 24 |
| Peak memory | 197044 kb |
| Host | smart-841dd1bf-01a2-4d93-bcda-c96c2693c725 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890886501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger .2890886501 |
| Directory | /workspace/46.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/46.gpio_random_dout_din.419208067 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 168927273 ps |
| CPU time | 0.75 seconds |
| Started | Jan 10 01:13:22 PM PST 24 |
| Finished | Jan 10 01:14:48 PM PST 24 |
| Peak memory | 196280 kb |
| Host | smart-8f233c00-a3c8-4c21-9b4e-c69da73a433c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419208067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.419208067 |
| Directory | /workspace/46.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3316816346 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 62747169 ps |
| CPU time | 1.15 seconds |
| Started | Jan 10 01:13:14 PM PST 24 |
| Finished | Jan 10 01:14:40 PM PST 24 |
| Peak memory | 195868 kb |
| Host | smart-20c67250-e032-4fac-a535-10ff0fddac1e |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316816346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu p_pulldown.3316816346 |
| Directory | /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2726122378 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 541686215 ps |
| CPU time | 3.34 seconds |
| Started | Jan 10 01:13:29 PM PST 24 |
| Finished | Jan 10 01:14:55 PM PST 24 |
| Peak memory | 197964 kb |
| Host | smart-fa23cb86-9df9-4364-be07-0d95f6ac7f84 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726122378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra ndom_long_reg_writes_reg_reads.2726122378 |
| Directory | /workspace/46.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/46.gpio_smoke.2571058501 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 231691317 ps |
| CPU time | 1.22 seconds |
| Started | Jan 10 01:15:29 PM PST 24 |
| Finished | Jan 10 01:15:40 PM PST 24 |
| Peak memory | 194896 kb |
| Host | smart-93f7a081-ba46-48ea-bfb5-f4f07afee5be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2571058501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2571058501 |
| Directory | /workspace/46.gpio_smoke/latest |
| Test location | /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1369786205 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 23259071 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:13:17 PM PST 24 |
| Finished | Jan 10 01:14:44 PM PST 24 |
| Peak memory | 197128 kb |
| Host | smart-04f0cca2-e517-460d-aa6c-0d7d24170614 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369786205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1369786205 |
| Directory | /workspace/46.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/46.gpio_stress_all.1848597566 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 150748861952 ps |
| CPU time | 137.83 seconds |
| Started | Jan 10 01:13:37 PM PST 24 |
| Finished | Jan 10 01:17:21 PM PST 24 |
| Peak memory | 198228 kb |
| Host | smart-7ea62f9a-2b5e-40bd-925c-611856f831a8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848597566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. gpio_stress_all.1848597566 |
| Directory | /workspace/46.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.76245535 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 561139129728 ps |
| CPU time | 1253.46 seconds |
| Started | Jan 10 01:13:07 PM PST 24 |
| Finished | Jan 10 01:35:27 PM PST 24 |
| Peak memory | 198360 kb |
| Host | smart-60e768ba-2006-4d62-bf18-aa912c9fb00b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =76245535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.76245535 |
| Directory | /workspace/46.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.gpio_alert_test.4286742061 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 41905236 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:13:29 PM PST 24 |
| Finished | Jan 10 01:14:53 PM PST 24 |
| Peak memory | 194100 kb |
| Host | smart-b391e280-763b-40a4-9f99-4da9491ce4b3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286742061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.4286742061 |
| Directory | /workspace/47.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3337366702 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 208479877 ps |
| CPU time | 0.94 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:14:57 PM PST 24 |
| Peak memory | 196044 kb |
| Host | smart-c71f4f9d-8814-4a68-8518-9a4333a721c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337366702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3337366702 |
| Directory | /workspace/47.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/47.gpio_filter_stress.1117674478 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 762124194 ps |
| CPU time | 9.21 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:14:59 PM PST 24 |
| Peak memory | 197068 kb |
| Host | smart-086e06c8-ddd8-40f1-bd6c-8fbfd6052ca2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117674478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre ss.1117674478 |
| Directory | /workspace/47.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/47.gpio_full_random.1946561911 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 62788155 ps |
| CPU time | 0.96 seconds |
| Started | Jan 10 01:13:18 PM PST 24 |
| Finished | Jan 10 01:14:46 PM PST 24 |
| Peak memory | 196476 kb |
| Host | smart-f0a45980-95d7-42a4-8816-fd8a425fa8c2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946561911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1946561911 |
| Directory | /workspace/47.gpio_full_random/latest |
| Test location | /workspace/coverage/default/47.gpio_intr_rand_pgm.2946063715 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 26669748 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 01:13:19 PM PST 24 |
| Finished | Jan 10 01:14:48 PM PST 24 |
| Peak memory | 195572 kb |
| Host | smart-6fd0196a-4ffe-4d7c-9dbd-c55a216feba1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946063715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2946063715 |
| Directory | /workspace/47.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.4293268376 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 88367520 ps |
| CPU time | 3.2 seconds |
| Started | Jan 10 01:15:57 PM PST 24 |
| Finished | Jan 10 01:16:02 PM PST 24 |
| Peak memory | 197908 kb |
| Host | smart-4c8e1d1f-c083-4000-adf2-4c63e5ddeb68 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293268376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.gpio_intr_with_filter_rand_intr_event.4293268376 |
| Directory | /workspace/47.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/47.gpio_rand_intr_trigger.282077458 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 67709466 ps |
| CPU time | 1.93 seconds |
| Started | Jan 10 01:13:19 PM PST 24 |
| Finished | Jan 10 01:14:49 PM PST 24 |
| Peak memory | 197256 kb |
| Host | smart-de3ca51d-194b-4a57-bac7-eb0e666fba4b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282077458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger. 282077458 |
| Directory | /workspace/47.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/47.gpio_random_dout_din.74528670 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 63913377 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 01:13:16 PM PST 24 |
| Finished | Jan 10 01:14:58 PM PST 24 |
| Peak memory | 195604 kb |
| Host | smart-0f7af056-4a7b-436d-8797-673e6c4268eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74528670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.74528670 |
| Directory | /workspace/47.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2703317032 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 47607430 ps |
| CPU time | 0.79 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:14:51 PM PST 24 |
| Peak memory | 195464 kb |
| Host | smart-8b310255-ad39-45de-8af7-843e59a948f4 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703317032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu p_pulldown.2703317032 |
| Directory | /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1242697642 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 768587464 ps |
| CPU time | 4.35 seconds |
| Started | Jan 10 01:13:10 PM PST 24 |
| Finished | Jan 10 01:14:41 PM PST 24 |
| Peak memory | 198052 kb |
| Host | smart-97e70ccd-8de7-454f-88f8-6a4a8caa53c9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242697642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra ndom_long_reg_writes_reg_reads.1242697642 |
| Directory | /workspace/47.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/47.gpio_smoke.1150421671 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 234196734 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 01:13:19 PM PST 24 |
| Finished | Jan 10 01:14:46 PM PST 24 |
| Peak memory | 195492 kb |
| Host | smart-47d0d7d8-41d9-4a2d-a173-6c34c30a512a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150421671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1150421671 |
| Directory | /workspace/47.gpio_smoke/latest |
| Test location | /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3722836152 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 86720638 ps |
| CPU time | 1.38 seconds |
| Started | Jan 10 01:13:12 PM PST 24 |
| Finished | Jan 10 01:14:39 PM PST 24 |
| Peak memory | 197060 kb |
| Host | smart-07322fcc-ec2c-4dd6-bdfa-4dce87a760ed |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722836152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3722836152 |
| Directory | /workspace/47.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/47.gpio_stress_all.1078731948 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 19558672330 ps |
| CPU time | 147.87 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:17:18 PM PST 24 |
| Peak memory | 198128 kb |
| Host | smart-f7aa8f11-7641-4e29-bfa2-750677056221 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078731948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. gpio_stress_all.1078731948 |
| Directory | /workspace/47.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.4156549946 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 36709370865 ps |
| CPU time | 470.21 seconds |
| Started | Jan 10 01:13:16 PM PST 24 |
| Finished | Jan 10 01:22:40 PM PST 24 |
| Peak memory | 198392 kb |
| Host | smart-993712ba-998a-49c7-8a61-a6137a571aef |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4156549946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.4156549946 |
| Directory | /workspace/47.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.gpio_alert_test.2340379946 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 13145327 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:14:53 PM PST 24 |
| Peak memory | 194700 kb |
| Host | smart-3faf0d97-88b0-4e0d-ab37-aa70dd667aad |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340379946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2340379946 |
| Directory | /workspace/48.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.377537595 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 15600454 ps |
| CPU time | 0.64 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:14:57 PM PST 24 |
| Peak memory | 194012 kb |
| Host | smart-4792a055-8a28-412c-8591-805796d6eb79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=377537595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.377537595 |
| Directory | /workspace/48.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/48.gpio_filter_stress.1128465903 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 790869966 ps |
| CPU time | 22.37 seconds |
| Started | Jan 10 01:13:18 PM PST 24 |
| Finished | Jan 10 01:15:06 PM PST 24 |
| Peak memory | 196932 kb |
| Host | smart-c8b95136-a9f9-4ac7-b813-1369ef2b4ad3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128465903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre ss.1128465903 |
| Directory | /workspace/48.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/48.gpio_full_random.3634340777 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 95989626 ps |
| CPU time | 0.98 seconds |
| Started | Jan 10 01:13:16 PM PST 24 |
| Finished | Jan 10 01:14:53 PM PST 24 |
| Peak memory | 196560 kb |
| Host | smart-83dbcc15-9d6f-4e79-9d6d-1139a5428a6d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634340777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3634340777 |
| Directory | /workspace/48.gpio_full_random/latest |
| Test location | /workspace/coverage/default/48.gpio_intr_rand_pgm.2066509881 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 159772437 ps |
| CPU time | 1.08 seconds |
| Started | Jan 10 01:13:19 PM PST 24 |
| Finished | Jan 10 01:14:48 PM PST 24 |
| Peak memory | 195728 kb |
| Host | smart-5c1ab412-aaff-44eb-aea7-b845f1e09bb5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066509881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2066509881 |
| Directory | /workspace/48.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.464087082 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 55190460 ps |
| CPU time | 1.24 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:14:50 PM PST 24 |
| Peak memory | 197876 kb |
| Host | smart-8fc46ef7-c5b4-417f-969c-44b28775eaea |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464087082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 48.gpio_intr_with_filter_rand_intr_event.464087082 |
| Directory | /workspace/48.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/48.gpio_rand_intr_trigger.2284999924 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 73535131 ps |
| CPU time | 1.34 seconds |
| Started | Jan 10 01:13:20 PM PST 24 |
| Finished | Jan 10 01:14:55 PM PST 24 |
| Peak memory | 196084 kb |
| Host | smart-e1817fa5-3b39-462c-afb8-ab7ed1bb781c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284999924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger .2284999924 |
| Directory | /workspace/48.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/48.gpio_random_dout_din.4235937330 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 441538214 ps |
| CPU time | 0.79 seconds |
| Started | Jan 10 01:13:16 PM PST 24 |
| Finished | Jan 10 01:14:54 PM PST 24 |
| Peak memory | 195628 kb |
| Host | smart-bb2a473b-50f9-4cda-b670-002209713a65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235937330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.4235937330 |
| Directory | /workspace/48.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1883049191 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 132637259 ps |
| CPU time | 0.88 seconds |
| Started | Jan 10 01:15:29 PM PST 24 |
| Finished | Jan 10 01:15:40 PM PST 24 |
| Peak memory | 194828 kb |
| Host | smart-56940e8b-aa81-4b6b-8c59-49fc07893987 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883049191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu p_pulldown.1883049191 |
| Directory | /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1722560828 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 324550530 ps |
| CPU time | 2.97 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:14:58 PM PST 24 |
| Peak memory | 197248 kb |
| Host | smart-ec4e017f-1adb-46b9-b02f-a4d6fef37408 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722560828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra ndom_long_reg_writes_reg_reads.1722560828 |
| Directory | /workspace/48.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/48.gpio_smoke.4054240210 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 114528646 ps |
| CPU time | 0.8 seconds |
| Started | Jan 10 01:13:19 PM PST 24 |
| Finished | Jan 10 01:14:54 PM PST 24 |
| Peak memory | 196160 kb |
| Host | smart-daa6fe21-bb6e-4f65-a31a-92fb9d278df5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4054240210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.4054240210 |
| Directory | /workspace/48.gpio_smoke/latest |
| Test location | /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2318316102 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 364561050 ps |
| CPU time | 1.29 seconds |
| Started | Jan 10 01:13:53 PM PST 24 |
| Finished | Jan 10 01:15:06 PM PST 24 |
| Peak memory | 195856 kb |
| Host | smart-d09e3bb5-47f0-4dc9-b018-11466b51d605 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318316102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2318316102 |
| Directory | /workspace/48.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/48.gpio_stress_all.1647028925 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 51187350970 ps |
| CPU time | 94.35 seconds |
| Started | Jan 10 01:13:52 PM PST 24 |
| Finished | Jan 10 01:16:39 PM PST 24 |
| Peak memory | 198272 kb |
| Host | smart-c1a5e5e7-164e-44c8-8103-d48382289c88 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647028925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. gpio_stress_all.1647028925 |
| Directory | /workspace/48.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3309023297 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 876530677055 ps |
| CPU time | 2630.5 seconds |
| Started | Jan 10 01:15:23 PM PST 24 |
| Finished | Jan 10 01:59:18 PM PST 24 |
| Peak memory | 197668 kb |
| Host | smart-7dc49c34-1b8c-4ab1-8aef-b760b1d6754f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3309023297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3309023297 |
| Directory | /workspace/48.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.gpio_alert_test.27390660 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 18305127 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:13:30 PM PST 24 |
| Finished | Jan 10 01:14:55 PM PST 24 |
| Peak memory | 193980 kb |
| Host | smart-207a886a-d624-4ae0-ba1d-d367c9fa9fc5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27390660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.27390660 |
| Directory | /workspace/49.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1544047059 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 21038000 ps |
| CPU time | 0.63 seconds |
| Started | Jan 10 01:15:21 PM PST 24 |
| Finished | Jan 10 01:15:26 PM PST 24 |
| Peak memory | 193780 kb |
| Host | smart-7732afdb-79c4-4809-bacb-33f5a238bf24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1544047059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1544047059 |
| Directory | /workspace/49.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/49.gpio_filter_stress.3719380019 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 408172560 ps |
| CPU time | 12.42 seconds |
| Started | Jan 10 01:15:23 PM PST 24 |
| Finished | Jan 10 01:15:40 PM PST 24 |
| Peak memory | 197828 kb |
| Host | smart-15ffdf5e-1035-42ca-b021-c06bf44ce075 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719380019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre ss.3719380019 |
| Directory | /workspace/49.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/49.gpio_full_random.1757496005 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 137642938 ps |
| CPU time | 0.7 seconds |
| Started | Jan 10 01:15:23 PM PST 24 |
| Finished | Jan 10 01:15:28 PM PST 24 |
| Peak memory | 195132 kb |
| Host | smart-71bc8eea-2a9b-469a-b01d-77223aa942d3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757496005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1757496005 |
| Directory | /workspace/49.gpio_full_random/latest |
| Test location | /workspace/coverage/default/49.gpio_intr_rand_pgm.2167016800 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 455171207 ps |
| CPU time | 1 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:14:40 PM PST 24 |
| Peak memory | 196960 kb |
| Host | smart-e3e4567b-89a7-473d-adac-e10cbe298109 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167016800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2167016800 |
| Directory | /workspace/49.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.381683456 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 78490052 ps |
| CPU time | 1.02 seconds |
| Started | Jan 10 01:13:25 PM PST 24 |
| Finished | Jan 10 01:14:49 PM PST 24 |
| Peak memory | 197112 kb |
| Host | smart-5d6a2ed6-177b-4ddc-bf7e-561d697d301d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381683456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 49.gpio_intr_with_filter_rand_intr_event.381683456 |
| Directory | /workspace/49.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/49.gpio_rand_intr_trigger.758213573 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 27378172 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 01:15:21 PM PST 24 |
| Finished | Jan 10 01:15:26 PM PST 24 |
| Peak memory | 194200 kb |
| Host | smart-7fbe7390-06a9-411b-bd4c-ef80d02029c6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758213573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger. 758213573 |
| Directory | /workspace/49.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/49.gpio_random_dout_din.2854066748 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 119659645 ps |
| CPU time | 1.14 seconds |
| Started | Jan 10 01:13:26 PM PST 24 |
| Finished | Jan 10 01:14:58 PM PST 24 |
| Peak memory | 196684 kb |
| Host | smart-52d828e5-49e6-4e48-bee1-5b3906f4f96a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854066748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2854066748 |
| Directory | /workspace/49.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.920447927 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 48794406 ps |
| CPU time | 1.07 seconds |
| Started | Jan 10 01:13:29 PM PST 24 |
| Finished | Jan 10 01:14:53 PM PST 24 |
| Peak memory | 196100 kb |
| Host | smart-e44ddfb0-e8ed-4412-90b2-90d38e954c46 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920447927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup _pulldown.920447927 |
| Directory | /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1521147528 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 53992705 ps |
| CPU time | 2.3 seconds |
| Started | Jan 10 01:13:41 PM PST 24 |
| Finished | Jan 10 01:15:01 PM PST 24 |
| Peak memory | 197992 kb |
| Host | smart-ad3f53a4-26d4-4fea-a64d-cefcd2745e86 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521147528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra ndom_long_reg_writes_reg_reads.1521147528 |
| Directory | /workspace/49.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/49.gpio_smoke.160524367 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 51673488 ps |
| CPU time | 1.28 seconds |
| Started | Jan 10 01:13:32 PM PST 24 |
| Finished | Jan 10 01:14:55 PM PST 24 |
| Peak memory | 196956 kb |
| Host | smart-47cd15af-53d8-4098-b73d-a3dcdf463be4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=160524367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.160524367 |
| Directory | /workspace/49.gpio_smoke/latest |
| Test location | /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3802974576 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 147273197 ps |
| CPU time | 1.14 seconds |
| Started | Jan 10 01:13:43 PM PST 24 |
| Finished | Jan 10 01:15:04 PM PST 24 |
| Peak memory | 195548 kb |
| Host | smart-d2cfce2d-a89e-4a9a-b66c-173d3e74cfea |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802974576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3802974576 |
| Directory | /workspace/49.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/49.gpio_stress_all.2713909443 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 26920437712 ps |
| CPU time | 158.47 seconds |
| Started | Jan 10 01:13:29 PM PST 24 |
| Finished | Jan 10 01:17:31 PM PST 24 |
| Peak memory | 198232 kb |
| Host | smart-41ee696f-d813-4aa1-9eaf-69469f7d6c54 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713909443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. gpio_stress_all.2713909443 |
| Directory | /workspace/49.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.462450367 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 16621041377 ps |
| CPU time | 302.82 seconds |
| Started | Jan 10 01:13:13 PM PST 24 |
| Finished | Jan 10 01:19:53 PM PST 24 |
| Peak memory | 198400 kb |
| Host | smart-ffeaefc8-71ce-4437-a99c-95b40a014088 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =462450367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.462450367 |
| Directory | /workspace/49.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.gpio_alert_test.1183484053 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 93145142 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:12:38 PM PST 24 |
| Finished | Jan 10 01:14:03 PM PST 24 |
| Peak memory | 192828 kb |
| Host | smart-bdb7350f-6ee3-4d5d-9427-6839f6a4bfa5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183484053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1183484053 |
| Directory | /workspace/5.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1028749785 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 102811696 ps |
| CPU time | 0.96 seconds |
| Started | Jan 10 01:12:04 PM PST 24 |
| Finished | Jan 10 01:13:17 PM PST 24 |
| Peak memory | 195696 kb |
| Host | smart-1a84d428-183e-41f2-82a2-c8ef7db34ef3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1028749785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1028749785 |
| Directory | /workspace/5.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/5.gpio_filter_stress.3003092067 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 360990767 ps |
| CPU time | 4.42 seconds |
| Started | Jan 10 01:12:04 PM PST 24 |
| Finished | Jan 10 01:13:20 PM PST 24 |
| Peak memory | 195836 kb |
| Host | smart-9e52a394-dab9-4442-9cce-6a45b272e601 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003092067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres s.3003092067 |
| Directory | /workspace/5.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/5.gpio_full_random.3845206332 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 58357431 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:12:21 PM PST 24 |
| Finished | Jan 10 01:13:53 PM PST 24 |
| Peak memory | 195924 kb |
| Host | smart-79d115fb-da83-435f-8a5c-8545828f188d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845206332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3845206332 |
| Directory | /workspace/5.gpio_full_random/latest |
| Test location | /workspace/coverage/default/5.gpio_intr_rand_pgm.454001119 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 105844446 ps |
| CPU time | 0.98 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:25 PM PST 24 |
| Peak memory | 195976 kb |
| Host | smart-7026fbab-cc04-439e-ad29-9e672c45b432 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454001119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.454001119 |
| Directory | /workspace/5.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2554298898 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 121048349 ps |
| CPU time | 2.35 seconds |
| Started | Jan 10 01:12:16 PM PST 24 |
| Finished | Jan 10 01:13:35 PM PST 24 |
| Peak memory | 198112 kb |
| Host | smart-cdaad039-b233-4987-845e-1571b9671d8a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554298898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2554298898 |
| Directory | /workspace/5.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/5.gpio_rand_intr_trigger.2418305068 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 419069700 ps |
| CPU time | 2.09 seconds |
| Started | Jan 10 01:12:07 PM PST 24 |
| Finished | Jan 10 01:13:26 PM PST 24 |
| Peak memory | 196140 kb |
| Host | smart-7c25c76a-ed88-4c97-9b84-d6dd4fe27810 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418305068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger. 2418305068 |
| Directory | /workspace/5.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/5.gpio_random_dout_din.964505879 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 102446074 ps |
| CPU time | 1.01 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:25 PM PST 24 |
| Peak memory | 196228 kb |
| Host | smart-0eea95c4-d1a1-47b5-afd7-88a653c4cd67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=964505879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.964505879 |
| Directory | /workspace/5.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3177440958 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 95864846 ps |
| CPU time | 0.96 seconds |
| Started | Jan 10 01:12:16 PM PST 24 |
| Finished | Jan 10 01:13:35 PM PST 24 |
| Peak memory | 195984 kb |
| Host | smart-24c44c1b-3893-4027-ae6f-37bf061227c2 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177440958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup _pulldown.3177440958 |
| Directory | /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2061970172 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 56868669 ps |
| CPU time | 2.4 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:27 PM PST 24 |
| Peak memory | 198168 kb |
| Host | smart-01b0487c-84d5-4ea1-ab1b-4b08a24309d7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061970172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran dom_long_reg_writes_reg_reads.2061970172 |
| Directory | /workspace/5.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/5.gpio_smoke.955221325 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 83302496 ps |
| CPU time | 0.97 seconds |
| Started | Jan 10 01:12:37 PM PST 24 |
| Finished | Jan 10 01:13:58 PM PST 24 |
| Peak memory | 195784 kb |
| Host | smart-8b0fefd9-b42d-4daf-a39e-abab98f0b957 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955221325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.955221325 |
| Directory | /workspace/5.gpio_smoke/latest |
| Test location | /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3081173519 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 273437246 ps |
| CPU time | 1.24 seconds |
| Started | Jan 10 01:12:16 PM PST 24 |
| Finished | Jan 10 01:13:35 PM PST 24 |
| Peak memory | 196804 kb |
| Host | smart-1b1043a3-295e-4f0e-9dc5-087c658c6eec |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081173519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3081173519 |
| Directory | /workspace/5.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/5.gpio_stress_all.1995527462 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 6951298168 ps |
| CPU time | 71.9 seconds |
| Started | Jan 10 01:11:59 PM PST 24 |
| Finished | Jan 10 01:14:24 PM PST 24 |
| Peak memory | 198300 kb |
| Host | smart-98973446-127a-48fe-b202-4af11feb7bc5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995527462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g pio_stress_all.1995527462 |
| Directory | /workspace/5.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.715287519 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 38221918925 ps |
| CPU time | 930.51 seconds |
| Started | Jan 10 01:12:41 PM PST 24 |
| Finished | Jan 10 01:29:34 PM PST 24 |
| Peak memory | 198348 kb |
| Host | smart-710af9ef-9f51-43cb-b743-92a79fb8e40d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =715287519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.715287519 |
| Directory | /workspace/5.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.gpio_alert_test.2371172739 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 49489293 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:12:09 PM PST 24 |
| Finished | Jan 10 01:13:28 PM PST 24 |
| Peak memory | 194800 kb |
| Host | smart-64b2065e-ed32-4ff0-9c68-dc82a0746f0e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371172739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2371172739 |
| Directory | /workspace/6.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1419431972 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 125323356 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:12:17 PM PST 24 |
| Finished | Jan 10 01:13:39 PM PST 24 |
| Peak memory | 196528 kb |
| Host | smart-7abb20ff-5935-42d9-9530-89239b6f3987 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1419431972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1419431972 |
| Directory | /workspace/6.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/6.gpio_filter_stress.4057455863 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 892603295 ps |
| CPU time | 31.48 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:56 PM PST 24 |
| Peak memory | 198156 kb |
| Host | smart-3f85a14a-0e46-4924-a77c-d1afb214f268 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057455863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres s.4057455863 |
| Directory | /workspace/6.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/6.gpio_full_random.3334725533 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 195512626 ps |
| CPU time | 0.88 seconds |
| Started | Jan 10 01:12:04 PM PST 24 |
| Finished | Jan 10 01:13:17 PM PST 24 |
| Peak memory | 197204 kb |
| Host | smart-779a9cac-b25d-44be-b909-d6ebd69086b7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334725533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3334725533 |
| Directory | /workspace/6.gpio_full_random/latest |
| Test location | /workspace/coverage/default/6.gpio_intr_rand_pgm.3754561420 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 109908088 ps |
| CPU time | 1.45 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:42 PM PST 24 |
| Peak memory | 198112 kb |
| Host | smart-a2c5e825-397f-4bea-bccd-34454a094bd1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754561420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3754561420 |
| Directory | /workspace/6.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1340868776 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 284166025 ps |
| CPU time | 1.95 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:24 PM PST 24 |
| Peak memory | 198240 kb |
| Host | smart-85ed7c41-355d-4fdb-844f-3d0ff2b9a446 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340868776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1340868776 |
| Directory | /workspace/6.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/6.gpio_rand_intr_trigger.2240635020 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 2736128191 ps |
| CPU time | 2.93 seconds |
| Started | Jan 10 01:11:52 PM PST 24 |
| Finished | Jan 10 01:13:12 PM PST 24 |
| Peak memory | 198232 kb |
| Host | smart-15ab0504-2818-466e-947c-063d24199e69 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240635020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger. 2240635020 |
| Directory | /workspace/6.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/6.gpio_random_dout_din.1294554956 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 31387581 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:12:42 PM PST 24 |
| Finished | Jan 10 01:14:09 PM PST 24 |
| Peak memory | 196388 kb |
| Host | smart-0fac6073-fe36-4651-a1c1-9870d4707ff6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1294554956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1294554956 |
| Directory | /workspace/6.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1629835481 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 106387292 ps |
| CPU time | 0.77 seconds |
| Started | Jan 10 01:12:11 PM PST 24 |
| Finished | Jan 10 01:13:32 PM PST 24 |
| Peak memory | 195444 kb |
| Host | smart-b9c860b8-cec6-4f9e-9932-665e8e460ed4 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629835481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup _pulldown.1629835481 |
| Directory | /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2885212444 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 447762071 ps |
| CPU time | 5.45 seconds |
| Started | Jan 10 01:12:00 PM PST 24 |
| Finished | Jan 10 01:13:18 PM PST 24 |
| Peak memory | 198144 kb |
| Host | smart-35f607ee-e740-441c-a243-347ce56a2a50 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885212444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran dom_long_reg_writes_reg_reads.2885212444 |
| Directory | /workspace/6.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2505052136 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 26141213 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:23 PM PST 24 |
| Peak memory | 195260 kb |
| Host | smart-b20ca6f5-0207-4837-9397-ef40ba054546 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505052136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2505052136 |
| Directory | /workspace/6.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/6.gpio_stress_all.2485091674 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 9027257313 ps |
| CPU time | 112.94 seconds |
| Started | Jan 10 01:12:04 PM PST 24 |
| Finished | Jan 10 01:15:09 PM PST 24 |
| Peak memory | 198188 kb |
| Host | smart-048aa729-0d3d-4317-b033-4ce351b95398 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485091674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g pio_stress_all.2485091674 |
| Directory | /workspace/6.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3683885839 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 60136687582 ps |
| CPU time | 1663.86 seconds |
| Started | Jan 10 01:12:01 PM PST 24 |
| Finished | Jan 10 01:41:00 PM PST 24 |
| Peak memory | 198424 kb |
| Host | smart-5c365cbe-a174-4832-83cc-5a3c806089dc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3683885839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3683885839 |
| Directory | /workspace/6.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.gpio_alert_test.1366291571 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 57559632 ps |
| CPU time | 0.53 seconds |
| Started | Jan 10 01:12:45 PM PST 24 |
| Finished | Jan 10 01:14:12 PM PST 24 |
| Peak memory | 194016 kb |
| Host | smart-e9819d3d-e4ac-416c-9fbb-a1b5ade8a74c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366291571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1366291571 |
| Directory | /workspace/7.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/7.gpio_filter_stress.824499279 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3851087467 ps |
| CPU time | 12.45 seconds |
| Started | Jan 10 01:12:15 PM PST 24 |
| Finished | Jan 10 01:13:45 PM PST 24 |
| Peak memory | 195932 kb |
| Host | smart-bc163719-6efb-40db-8b02-c6a6dfbb618e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824499279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress .824499279 |
| Directory | /workspace/7.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/7.gpio_full_random.3471290520 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 146646061 ps |
| CPU time | 0.98 seconds |
| Started | Jan 10 01:12:09 PM PST 24 |
| Finished | Jan 10 01:13:25 PM PST 24 |
| Peak memory | 196776 kb |
| Host | smart-e45b9b84-57ed-425b-8943-6e2c5f842a31 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471290520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3471290520 |
| Directory | /workspace/7.gpio_full_random/latest |
| Test location | /workspace/coverage/default/7.gpio_intr_rand_pgm.1114842727 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 70993092 ps |
| CPU time | 1.15 seconds |
| Started | Jan 10 01:12:42 PM PST 24 |
| Finished | Jan 10 01:14:28 PM PST 24 |
| Peak memory | 196204 kb |
| Host | smart-69a76beb-d385-49d5-a0d6-49c9972ccac3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114842727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1114842727 |
| Directory | /workspace/7.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2985952545 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 245472537 ps |
| CPU time | 2.17 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:24 PM PST 24 |
| Peak memory | 198104 kb |
| Host | smart-32a8e479-48f3-49d2-97da-a2f6df65a948 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985952545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2985952545 |
| Directory | /workspace/7.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/7.gpio_rand_intr_trigger.4283667736 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 32672636 ps |
| CPU time | 1.11 seconds |
| Started | Jan 10 01:12:21 PM PST 24 |
| Finished | Jan 10 01:13:51 PM PST 24 |
| Peak memory | 196556 kb |
| Host | smart-df2e8f24-b326-4b78-b089-a52979f860d0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283667736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger. 4283667736 |
| Directory | /workspace/7.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/7.gpio_random_dout_din.2001585347 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 37860780 ps |
| CPU time | 0.75 seconds |
| Started | Jan 10 01:12:12 PM PST 24 |
| Finished | Jan 10 01:13:37 PM PST 24 |
| Peak memory | 195540 kb |
| Host | smart-46535010-88d2-4845-ac49-f5a6bd29af20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2001585347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2001585347 |
| Directory | /workspace/7.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3499224890 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 22589716 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 01:12:12 PM PST 24 |
| Finished | Jan 10 01:13:38 PM PST 24 |
| Peak memory | 196152 kb |
| Host | smart-d05280da-9f2d-4573-bbd9-2fed20419226 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499224890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup _pulldown.3499224890 |
| Directory | /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.4291261267 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 482120913 ps |
| CPU time | 5.12 seconds |
| Started | Jan 10 01:12:12 PM PST 24 |
| Finished | Jan 10 01:13:39 PM PST 24 |
| Peak memory | 197988 kb |
| Host | smart-ccca5c12-f483-4efb-931f-b4c5db0ff04a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291261267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran dom_long_reg_writes_reg_reads.4291261267 |
| Directory | /workspace/7.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/7.gpio_smoke.1330467075 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 61213732 ps |
| CPU time | 0.96 seconds |
| Started | Jan 10 01:12:00 PM PST 24 |
| Finished | Jan 10 01:13:12 PM PST 24 |
| Peak memory | 195584 kb |
| Host | smart-a0fc4caa-f74d-47b3-be94-907043792873 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330467075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1330467075 |
| Directory | /workspace/7.gpio_smoke/latest |
| Test location | /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2622594976 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 68076178 ps |
| CPU time | 1.26 seconds |
| Started | Jan 10 01:11:59 PM PST 24 |
| Finished | Jan 10 01:13:13 PM PST 24 |
| Peak memory | 195656 kb |
| Host | smart-32ec098b-fd22-4373-9281-2d29c5c1c45c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622594976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2622594976 |
| Directory | /workspace/7.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/7.gpio_stress_all.607942567 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 7354625267 ps |
| CPU time | 91.96 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:15:07 PM PST 24 |
| Peak memory | 198068 kb |
| Host | smart-a3bfeaff-0276-4287-8740-7a5aebd4cb4c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607942567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp io_stress_all.607942567 |
| Directory | /workspace/7.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.4139877817 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 55434655706 ps |
| CPU time | 315.92 seconds |
| Started | Jan 10 01:12:16 PM PST 24 |
| Finished | Jan 10 01:18:53 PM PST 24 |
| Peak memory | 198376 kb |
| Host | smart-7f73ff18-a937-4ea8-8d77-b5ccc330379a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4139877817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.4139877817 |
| Directory | /workspace/7.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.gpio_alert_test.1514122715 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 14596670 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:42 PM PST 24 |
| Peak memory | 193972 kb |
| Host | smart-bf8947c5-48ca-4259-b717-1513ea3edfb9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514122715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1514122715 |
| Directory | /workspace/8.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1343518508 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 162798093 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:12:13 PM PST 24 |
| Finished | Jan 10 01:13:30 PM PST 24 |
| Peak memory | 196424 kb |
| Host | smart-906cfc65-88d1-455d-9dd8-e361806477fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1343518508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1343518508 |
| Directory | /workspace/8.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/8.gpio_filter_stress.1296543966 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 3532591951 ps |
| CPU time | 24.75 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:49 PM PST 24 |
| Peak memory | 196788 kb |
| Host | smart-163a2212-bb1b-4a0b-a1d9-92c280e10341 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296543966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres s.1296543966 |
| Directory | /workspace/8.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/8.gpio_full_random.3059792235 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 357143698 ps |
| CPU time | 0.94 seconds |
| Started | Jan 10 01:12:07 PM PST 24 |
| Finished | Jan 10 01:13:25 PM PST 24 |
| Peak memory | 196648 kb |
| Host | smart-23a07080-5021-4693-b563-670fc0deb616 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059792235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3059792235 |
| Directory | /workspace/8.gpio_full_random/latest |
| Test location | /workspace/coverage/default/8.gpio_intr_rand_pgm.3253995674 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 201619587 ps |
| CPU time | 0.94 seconds |
| Started | Jan 10 01:12:29 PM PST 24 |
| Finished | Jan 10 01:13:49 PM PST 24 |
| Peak memory | 196080 kb |
| Host | smart-c1506abd-1722-465f-8e8f-901a66fded5d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253995674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3253995674 |
| Directory | /workspace/8.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2148399177 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 489644155 ps |
| CPU time | 2.19 seconds |
| Started | Jan 10 01:12:09 PM PST 24 |
| Finished | Jan 10 01:13:30 PM PST 24 |
| Peak memory | 198248 kb |
| Host | smart-c4dffe61-959f-4c74-8240-4c5e060906bd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148399177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2148399177 |
| Directory | /workspace/8.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/8.gpio_rand_intr_trigger.2653413215 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 96969442 ps |
| CPU time | 1.92 seconds |
| Started | Jan 10 01:13:04 PM PST 24 |
| Finished | Jan 10 01:14:32 PM PST 24 |
| Peak memory | 196368 kb |
| Host | smart-a2a367b9-30d2-432c-a2da-d40d2c1da047 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653413215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger. 2653413215 |
| Directory | /workspace/8.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/8.gpio_random_dout_din.2221264047 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 29870016 ps |
| CPU time | 0.79 seconds |
| Started | Jan 10 01:12:28 PM PST 24 |
| Finished | Jan 10 01:13:51 PM PST 24 |
| Peak memory | 196420 kb |
| Host | smart-d57ae463-7ded-4e09-ac70-c5b23e65d4a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221264047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2221264047 |
| Directory | /workspace/8.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2762250260 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 29321170 ps |
| CPU time | 0.77 seconds |
| Started | Jan 10 01:12:09 PM PST 24 |
| Finished | Jan 10 01:13:28 PM PST 24 |
| Peak memory | 195612 kb |
| Host | smart-bf817f41-7ab2-43f3-af9d-ad5435ed14c2 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762250260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup _pulldown.2762250260 |
| Directory | /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2254285081 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 40904569 ps |
| CPU time | 1.71 seconds |
| Started | Jan 10 01:12:09 PM PST 24 |
| Finished | Jan 10 01:13:27 PM PST 24 |
| Peak memory | 198036 kb |
| Host | smart-437e619f-38ef-4af8-a714-8e9d7819932f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254285081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran dom_long_reg_writes_reg_reads.2254285081 |
| Directory | /workspace/8.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/8.gpio_smoke.3905331972 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 56729590 ps |
| CPU time | 1.42 seconds |
| Started | Jan 10 01:12:56 PM PST 24 |
| Finished | Jan 10 01:14:52 PM PST 24 |
| Peak memory | 195684 kb |
| Host | smart-e62ba9d5-4414-4cc2-ba1a-587892528523 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905331972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3905331972 |
| Directory | /workspace/8.gpio_smoke/latest |
| Test location | /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1034044541 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1270269809 ps |
| CPU time | 1.43 seconds |
| Started | Jan 10 01:12:48 PM PST 24 |
| Finished | Jan 10 01:14:16 PM PST 24 |
| Peak memory | 198048 kb |
| Host | smart-a3ab5f02-b1d4-48dd-85c3-05ff42881636 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034044541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1034044541 |
| Directory | /workspace/8.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/8.gpio_stress_all.3287539520 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 15248855543 ps |
| CPU time | 180.15 seconds |
| Started | Jan 10 01:12:19 PM PST 24 |
| Finished | Jan 10 01:16:44 PM PST 24 |
| Peak memory | 198236 kb |
| Host | smart-efb3f171-db4a-4a0d-bb79-9a30361c497b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287539520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g pio_stress_all.3287539520 |
| Directory | /workspace/8.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.802766699 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 94012384093 ps |
| CPU time | 1349.01 seconds |
| Started | Jan 10 01:12:20 PM PST 24 |
| Finished | Jan 10 01:36:14 PM PST 24 |
| Peak memory | 198448 kb |
| Host | smart-e1c21b9c-7e47-4147-aa2e-4a6556c2063a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =802766699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.802766699 |
| Directory | /workspace/8.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.gpio_alert_test.609937886 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 13025938 ps |
| CPU time | 0.54 seconds |
| Started | Jan 10 01:12:17 PM PST 24 |
| Finished | Jan 10 01:13:36 PM PST 24 |
| Peak memory | 194092 kb |
| Host | smart-085e18b1-fa80-484b-93d8-b34c5141f3f7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609937886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.609937886 |
| Directory | /workspace/9.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1464051004 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 91393460 ps |
| CPU time | 0.75 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:23 PM PST 24 |
| Peak memory | 194136 kb |
| Host | smart-6ade1c18-9395-42da-bf0d-8cfc2f8dd2c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1464051004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1464051004 |
| Directory | /workspace/9.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/9.gpio_filter_stress.2767082210 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 558083901 ps |
| CPU time | 15.38 seconds |
| Started | Jan 10 01:12:35 PM PST 24 |
| Finished | Jan 10 01:14:12 PM PST 24 |
| Peak memory | 196760 kb |
| Host | smart-98281465-2558-4ed5-b084-2c1526ff6f80 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767082210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres s.2767082210 |
| Directory | /workspace/9.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/9.gpio_full_random.3741663976 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 141501200 ps |
| CPU time | 0.7 seconds |
| Started | Jan 10 01:12:25 PM PST 24 |
| Finished | Jan 10 01:13:43 PM PST 24 |
| Peak memory | 195588 kb |
| Host | smart-ae5b83dc-a6e7-48f4-b87a-1dab9b368926 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741663976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3741663976 |
| Directory | /workspace/9.gpio_full_random/latest |
| Test location | /workspace/coverage/default/9.gpio_intr_rand_pgm.810365283 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 366084376 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:12:04 PM PST 24 |
| Finished | Jan 10 01:13:16 PM PST 24 |
| Peak memory | 195636 kb |
| Host | smart-3a02f802-fb6c-4e3d-9e55-f601233c3fa4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810365283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.810365283 |
| Directory | /workspace/9.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.703559865 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 74282701 ps |
| CPU time | 2.67 seconds |
| Started | Jan 10 01:12:12 PM PST 24 |
| Finished | Jan 10 01:13:39 PM PST 24 |
| Peak memory | 198196 kb |
| Host | smart-de51bb95-2eb8-4c0b-aa00-95a65e99485c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703559865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.gpio_intr_with_filter_rand_intr_event.703559865 |
| Directory | /workspace/9.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/9.gpio_rand_intr_trigger.2993837630 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 65001096 ps |
| CPU time | 1.19 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:13:23 PM PST 24 |
| Peak memory | 197304 kb |
| Host | smart-9d386771-a605-44a0-8963-07fe22a3d3cc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993837630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger. 2993837630 |
| Directory | /workspace/9.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/9.gpio_random_dout_din.1764322553 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 58523457 ps |
| CPU time | 0.72 seconds |
| Started | Jan 10 01:12:17 PM PST 24 |
| Finished | Jan 10 01:13:36 PM PST 24 |
| Peak memory | 195496 kb |
| Host | smart-2464ef35-7bf1-4ba4-b5fd-4f2892f93fb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764322553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1764322553 |
| Directory | /workspace/9.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3597699530 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 33214588 ps |
| CPU time | 1.18 seconds |
| Started | Jan 10 01:12:12 PM PST 24 |
| Finished | Jan 10 01:13:32 PM PST 24 |
| Peak memory | 195992 kb |
| Host | smart-3b5b8cd5-6e05-47fd-ad1a-94b106029593 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597699530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup _pulldown.3597699530 |
| Directory | /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3888311339 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 757216489 ps |
| CPU time | 2.65 seconds |
| Started | Jan 10 01:12:50 PM PST 24 |
| Finished | Jan 10 01:14:20 PM PST 24 |
| Peak memory | 198308 kb |
| Host | smart-4090cbbb-b03a-47f5-bf82-681fc908c277 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888311339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran dom_long_reg_writes_reg_reads.3888311339 |
| Directory | /workspace/9.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/9.gpio_smoke.3628708162 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 80759021 ps |
| CPU time | 0.89 seconds |
| Started | Jan 10 01:12:18 PM PST 24 |
| Finished | Jan 10 01:13:37 PM PST 24 |
| Peak memory | 196380 kb |
| Host | smart-25c5a0b4-3c8e-45eb-9308-9116fa629ee4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628708162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3628708162 |
| Directory | /workspace/9.gpio_smoke/latest |
| Test location | /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.4037017888 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 452813936 ps |
| CPU time | 1 seconds |
| Started | Jan 10 01:12:20 PM PST 24 |
| Finished | Jan 10 01:13:50 PM PST 24 |
| Peak memory | 196536 kb |
| Host | smart-ed91b868-3df2-4ac4-8727-0fc5cad5ba94 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037017888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.4037017888 |
| Directory | /workspace/9.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/9.gpio_stress_all.3544940816 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 37841648094 ps |
| CPU time | 107.95 seconds |
| Started | Jan 10 01:12:08 PM PST 24 |
| Finished | Jan 10 01:15:12 PM PST 24 |
| Peak memory | 198276 kb |
| Host | smart-72ef84a2-76f1-4bef-abc6-04187aef7b8e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544940816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g pio_stress_all.3544940816 |
| Directory | /workspace/9.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.241140164 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 33371202682 ps |
| CPU time | 544.12 seconds |
| Started | Jan 10 01:12:04 PM PST 24 |
| Finished | Jan 10 01:22:20 PM PST 24 |
| Peak memory | 198252 kb |
| Host | smart-492a80d2-ac0d-44e2-bdef-62946ad97d5e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =241140164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.241140164 |
| Directory | /workspace/9.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.152400625 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 266702351 ps |
| CPU time | 1.32 seconds |
| Started | Jan 10 12:57:33 PM PST 24 |
| Finished | Jan 10 12:58:49 PM PST 24 |
| Peak memory | 196272 kb |
| Host | smart-3240ba64-334e-493b-a19c-5981a7157dc8 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=152400625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.152400625 |
| Directory | /workspace/0.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4003179975 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 120130573 ps |
| CPU time | 1 seconds |
| Started | Jan 10 12:57:36 PM PST 24 |
| Finished | Jan 10 12:58:57 PM PST 24 |
| Peak memory | 195292 kb |
| Host | smart-cfb22880-7855-45df-be00-e2e022628197 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4003179975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.4003179975 |
| Directory | /workspace/1.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2976722995 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 59791419 ps |
| CPU time | 1 seconds |
| Started | Jan 10 12:57:34 PM PST 24 |
| Finished | Jan 10 12:58:54 PM PST 24 |
| Peak memory | 195528 kb |
| Host | smart-6c521d31-c882-4796-8fc3-23a6d773e686 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976722995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.2976722995 |
| Directory | /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.660540368 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 174084068 ps |
| CPU time | 1.02 seconds |
| Started | Jan 10 12:57:40 PM PST 24 |
| Finished | Jan 10 12:58:59 PM PST 24 |
| Peak memory | 196052 kb |
| Host | smart-ede58168-9f5f-4122-a0fe-8618c9edf677 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=660540368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.660540368 |
| Directory | /workspace/10.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3952657020 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 114807973 ps |
| CPU time | 1.18 seconds |
| Started | Jan 10 12:57:30 PM PST 24 |
| Finished | Jan 10 12:58:47 PM PST 24 |
| Peak memory | 196448 kb |
| Host | smart-fe48300e-a6b5-4eff-9e9c-7d788077f56d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952657020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3952657020 |
| Directory | /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.665817442 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 186628195 ps |
| CPU time | 1.46 seconds |
| Started | Jan 10 12:57:30 PM PST 24 |
| Finished | Jan 10 12:58:47 PM PST 24 |
| Peak memory | 197684 kb |
| Host | smart-f283330c-bd08-41f7-a7f2-df7478489b7e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=665817442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.665817442 |
| Directory | /workspace/11.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1953616871 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 34995144 ps |
| CPU time | 1.01 seconds |
| Started | Jan 10 12:57:40 PM PST 24 |
| Finished | Jan 10 12:58:59 PM PST 24 |
| Peak memory | 195984 kb |
| Host | smart-1fbf9d9b-37ae-4f5d-90ec-166b20394c05 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953616871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1953616871 |
| Directory | /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4022603970 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 589208539 ps |
| CPU time | 1.12 seconds |
| Started | Jan 10 12:57:40 PM PST 24 |
| Finished | Jan 10 12:58:58 PM PST 24 |
| Peak memory | 196460 kb |
| Host | smart-1ba9ab0c-ebd5-4724-a979-e8e255076699 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4022603970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.4022603970 |
| Directory | /workspace/12.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3016114522 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 43674092 ps |
| CPU time | 1 seconds |
| Started | Jan 10 12:57:34 PM PST 24 |
| Finished | Jan 10 12:58:54 PM PST 24 |
| Peak memory | 197004 kb |
| Host | smart-d7931f4a-e5a9-47d6-a0f1-ed460da0bd41 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016114522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3016114522 |
| Directory | /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1402684226 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 98003477 ps |
| CPU time | 1.52 seconds |
| Started | Jan 10 12:57:32 PM PST 24 |
| Finished | Jan 10 12:58:49 PM PST 24 |
| Peak memory | 196448 kb |
| Host | smart-3a84d68f-65dd-4c68-8907-3d883601e1dc |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1402684226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1402684226 |
| Directory | /workspace/13.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2714101355 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 96952263 ps |
| CPU time | 0.9 seconds |
| Started | Jan 10 12:57:33 PM PST 24 |
| Finished | Jan 10 12:58:50 PM PST 24 |
| Peak memory | 196156 kb |
| Host | smart-37d358f6-7382-4748-946d-8cde9e9b2f2b |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714101355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2714101355 |
| Directory | /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4191095829 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 37529680 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 12:57:32 PM PST 24 |
| Finished | Jan 10 12:58:48 PM PST 24 |
| Peak memory | 195528 kb |
| Host | smart-0da970da-e2cf-4db6-b00c-6cc56e4dd3b9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4191095829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.4191095829 |
| Directory | /workspace/14.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1766182737 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 34906193 ps |
| CPU time | 0.93 seconds |
| Started | Jan 10 12:57:30 PM PST 24 |
| Finished | Jan 10 12:58:47 PM PST 24 |
| Peak memory | 196372 kb |
| Host | smart-7f18c20c-d24a-4e11-94a9-df7c4f713ce2 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766182737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1766182737 |
| Directory | /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2366162330 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 155657218 ps |
| CPU time | 1.17 seconds |
| Started | Jan 10 12:57:42 PM PST 24 |
| Finished | Jan 10 12:59:03 PM PST 24 |
| Peak memory | 196348 kb |
| Host | smart-e6278ae3-499a-424c-a8f7-1c9f5d074728 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2366162330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2366162330 |
| Directory | /workspace/15.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.333984026 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 97614119 ps |
| CPU time | 1.28 seconds |
| Started | Jan 10 12:57:36 PM PST 24 |
| Finished | Jan 10 12:58:53 PM PST 24 |
| Peak memory | 197652 kb |
| Host | smart-e83ab0f6-ea51-469c-ad07-e8228c8156b3 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333984026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.333984026 |
| Directory | /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.659352097 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 141754334 ps |
| CPU time | 1.28 seconds |
| Started | Jan 10 12:57:41 PM PST 24 |
| Finished | Jan 10 12:59:00 PM PST 24 |
| Peak memory | 196220 kb |
| Host | smart-ec00bfdb-85cf-4c6f-879b-0b40478ce493 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=659352097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.659352097 |
| Directory | /workspace/16.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2899384816 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 240523050 ps |
| CPU time | 1.15 seconds |
| Started | Jan 10 12:57:43 PM PST 24 |
| Finished | Jan 10 12:59:03 PM PST 24 |
| Peak memory | 195516 kb |
| Host | smart-b3995f33-64f9-4fc9-98c6-88a71a15f06d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899384816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2899384816 |
| Directory | /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2077206724 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 275006594 ps |
| CPU time | 1.12 seconds |
| Started | Jan 10 12:57:46 PM PST 24 |
| Finished | Jan 10 12:59:05 PM PST 24 |
| Peak memory | 196560 kb |
| Host | smart-906bb965-e9e7-477f-9ae3-aa7353cbf478 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2077206724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2077206724 |
| Directory | /workspace/17.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3912628751 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 84261646 ps |
| CPU time | 0.92 seconds |
| Started | Jan 10 12:57:42 PM PST 24 |
| Finished | Jan 10 12:59:02 PM PST 24 |
| Peak memory | 196068 kb |
| Host | smart-e7faf69c-f1ac-4ef9-ae67-7553dfb8b8b5 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912628751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3912628751 |
| Directory | /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1748013025 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 68441254 ps |
| CPU time | 0.74 seconds |
| Started | Jan 10 12:57:39 PM PST 24 |
| Finished | Jan 10 12:58:55 PM PST 24 |
| Peak memory | 195152 kb |
| Host | smart-ef3e94ef-f42c-476f-bfc7-39a644685b06 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1748013025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1748013025 |
| Directory | /workspace/18.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3031413069 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 24246871 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 12:57:35 PM PST 24 |
| Finished | Jan 10 12:58:51 PM PST 24 |
| Peak memory | 195236 kb |
| Host | smart-92dfe510-2eb0-466c-b7fe-10b23982c1d6 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031413069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3031413069 |
| Directory | /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3546446431 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 19977720 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 12:57:42 PM PST 24 |
| Finished | Jan 10 12:59:01 PM PST 24 |
| Peak memory | 195836 kb |
| Host | smart-11a4b70c-a9a1-4539-b44c-24cec678e352 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3546446431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3546446431 |
| Directory | /workspace/19.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2215659336 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 74620911 ps |
| CPU time | 1.34 seconds |
| Started | Jan 10 12:57:46 PM PST 24 |
| Finished | Jan 10 12:59:06 PM PST 24 |
| Peak memory | 195308 kb |
| Host | smart-fb9015e8-1d41-4dd5-9800-9b7f8466cc2c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215659336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2215659336 |
| Directory | /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1816729476 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 214268371 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 12:57:38 PM PST 24 |
| Finished | Jan 10 12:58:55 PM PST 24 |
| Peak memory | 195068 kb |
| Host | smart-603f66c9-0cf0-4f86-b352-35b71c1430e8 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1816729476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1816729476 |
| Directory | /workspace/2.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1417621937 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 20399765 ps |
| CPU time | 0.75 seconds |
| Started | Jan 10 12:57:32 PM PST 24 |
| Finished | Jan 10 12:58:48 PM PST 24 |
| Peak memory | 195084 kb |
| Host | smart-d6c5da45-f07f-4aff-8b91-8f0e5a9ae1bc |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417621937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.1417621937 |
| Directory | /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3806339718 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 117881782 ps |
| CPU time | 1.01 seconds |
| Started | Jan 10 12:57:37 PM PST 24 |
| Finished | Jan 10 12:58:57 PM PST 24 |
| Peak memory | 196092 kb |
| Host | smart-4babab30-7748-4367-9a7c-33915a958f1b |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3806339718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3806339718 |
| Directory | /workspace/20.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3718126908 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 44531973 ps |
| CPU time | 1.28 seconds |
| Started | Jan 10 12:57:49 PM PST 24 |
| Finished | Jan 10 12:59:09 PM PST 24 |
| Peak memory | 197632 kb |
| Host | smart-781a48c7-038d-4e8a-aca4-8b7fbde24d6f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718126908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3718126908 |
| Directory | /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1747087374 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 298984950 ps |
| CPU time | 1.16 seconds |
| Started | Jan 10 01:00:02 PM PST 24 |
| Finished | Jan 10 01:01:39 PM PST 24 |
| Peak memory | 195904 kb |
| Host | smart-c6499324-4b0f-444b-ae41-bface3fe888a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1747087374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1747087374 |
| Directory | /workspace/21.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3993368664 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 129549082 ps |
| CPU time | 1.18 seconds |
| Started | Jan 10 12:57:45 PM PST 24 |
| Finished | Jan 10 12:59:04 PM PST 24 |
| Peak memory | 197616 kb |
| Host | smart-ea417e00-de18-4c5f-bc7c-2640ac91f217 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993368664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3993368664 |
| Directory | /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1428956927 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 43407740 ps |
| CPU time | 0.9 seconds |
| Started | Jan 10 12:57:39 PM PST 24 |
| Finished | Jan 10 12:58:56 PM PST 24 |
| Peak memory | 196308 kb |
| Host | smart-461d9a33-1753-4183-ac61-ac70f9b342b4 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1428956927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1428956927 |
| Directory | /workspace/22.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.102601376 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 176060248 ps |
| CPU time | 1.02 seconds |
| Started | Jan 10 12:57:42 PM PST 24 |
| Finished | Jan 10 12:59:02 PM PST 24 |
| Peak memory | 195364 kb |
| Host | smart-a4e4bf77-11f8-4435-ab87-1e3ea4c23887 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102601376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.102601376 |
| Directory | /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3743876425 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 72293214 ps |
| CPU time | 1.07 seconds |
| Started | Jan 10 12:57:44 PM PST 24 |
| Finished | Jan 10 12:59:03 PM PST 24 |
| Peak memory | 197660 kb |
| Host | smart-a8177062-9bf3-4551-b653-43583f78a1fb |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743876425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3743876425 |
| Directory | /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.974697660 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 42882740 ps |
| CPU time | 0.89 seconds |
| Started | Jan 10 12:57:45 PM PST 24 |
| Finished | Jan 10 12:59:04 PM PST 24 |
| Peak memory | 196056 kb |
| Host | smart-7446a8c0-4903-4fff-8b58-de9e075993c7 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=974697660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.974697660 |
| Directory | /workspace/24.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.75078247 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 84981882 ps |
| CPU time | 1.22 seconds |
| Started | Jan 10 12:57:35 PM PST 24 |
| Finished | Jan 10 12:58:52 PM PST 24 |
| Peak memory | 196296 kb |
| Host | smart-19fa6cec-113b-4280-8bb5-718c4c3d222a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75078247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_e n_cdc_prim.75078247 |
| Directory | /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3154880293 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 198933333 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 12:57:42 PM PST 24 |
| Finished | Jan 10 12:59:02 PM PST 24 |
| Peak memory | 196192 kb |
| Host | smart-ea46928a-b613-45df-af00-38919a40568b |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3154880293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3154880293 |
| Directory | /workspace/25.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.618022094 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 45583348 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 12:57:45 PM PST 24 |
| Finished | Jan 10 12:59:04 PM PST 24 |
| Peak memory | 196192 kb |
| Host | smart-8f8be8f8-c26d-47a1-aa80-230f4c9a93f2 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618022094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.618022094 |
| Directory | /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.744830537 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 61265883 ps |
| CPU time | 1.11 seconds |
| Started | Jan 10 12:57:40 PM PST 24 |
| Finished | Jan 10 12:58:59 PM PST 24 |
| Peak memory | 197612 kb |
| Host | smart-e4310969-c576-433b-81f4-a3265ee5f7ca |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=744830537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.744830537 |
| Directory | /workspace/26.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.249023160 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 145023692 ps |
| CPU time | 0.91 seconds |
| Started | Jan 10 12:57:44 PM PST 24 |
| Finished | Jan 10 12:59:03 PM PST 24 |
| Peak memory | 196128 kb |
| Host | smart-4ec9151e-9708-4303-8151-d0a26ef73272 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249023160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.249023160 |
| Directory | /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1271526890 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 191506349 ps |
| CPU time | 1.44 seconds |
| Started | Jan 10 12:57:43 PM PST 24 |
| Finished | Jan 10 12:59:02 PM PST 24 |
| Peak memory | 197588 kb |
| Host | smart-ede105af-4433-471e-89fa-62836dc455c2 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1271526890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1271526890 |
| Directory | /workspace/27.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1895975619 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 50977405 ps |
| CPU time | 1.3 seconds |
| Started | Jan 10 12:57:37 PM PST 24 |
| Finished | Jan 10 12:58:55 PM PST 24 |
| Peak memory | 197568 kb |
| Host | smart-af8da358-5c16-44a7-ac56-cf5e6714e4a3 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895975619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1895975619 |
| Directory | /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.784388998 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 89400181 ps |
| CPU time | 0.92 seconds |
| Started | Jan 10 12:57:39 PM PST 24 |
| Finished | Jan 10 12:58:56 PM PST 24 |
| Peak memory | 196304 kb |
| Host | smart-82d9a5ab-ffdc-4ccf-95d7-c4a65df67306 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=784388998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.784388998 |
| Directory | /workspace/28.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1001972907 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 63214718 ps |
| CPU time | 1.21 seconds |
| Started | Jan 10 12:57:38 PM PST 24 |
| Finished | Jan 10 12:58:55 PM PST 24 |
| Peak memory | 197692 kb |
| Host | smart-0ff7335d-06ee-4979-af72-655646f25a0c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001972907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1001972907 |
| Directory | /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1105071633 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 175494972 ps |
| CPU time | 1.16 seconds |
| Started | Jan 10 12:57:40 PM PST 24 |
| Finished | Jan 10 12:58:58 PM PST 24 |
| Peak memory | 196440 kb |
| Host | smart-9e62b97a-b33d-4df5-8258-279eb97267c3 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1105071633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1105071633 |
| Directory | /workspace/29.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3762541904 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 60550573 ps |
| CPU time | 1.21 seconds |
| Started | Jan 10 12:57:45 PM PST 24 |
| Finished | Jan 10 12:59:04 PM PST 24 |
| Peak memory | 196232 kb |
| Host | smart-ece826df-93e9-41dc-88b8-bf14ed6f68d6 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762541904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3762541904 |
| Directory | /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1878657195 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 346671701 ps |
| CPU time | 1.45 seconds |
| Started | Jan 10 12:57:29 PM PST 24 |
| Finished | Jan 10 12:58:45 PM PST 24 |
| Peak memory | 196520 kb |
| Host | smart-1e38f7da-fa05-49d3-9584-7b03ed06be30 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1878657195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1878657195 |
| Directory | /workspace/3.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.660353915 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 74948230 ps |
| CPU time | 0.77 seconds |
| Started | Jan 10 12:57:31 PM PST 24 |
| Finished | Jan 10 12:58:48 PM PST 24 |
| Peak memory | 195892 kb |
| Host | smart-95a3d277-865e-4898-97ee-d2b2678f4c09 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660353915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e n_cdc_prim.660353915 |
| Directory | /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2686394985 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 92903254 ps |
| CPU time | 1.28 seconds |
| Started | Jan 10 12:57:40 PM PST 24 |
| Finished | Jan 10 12:59:00 PM PST 24 |
| Peak memory | 197716 kb |
| Host | smart-d15fa752-1d4a-423c-a015-768a33e7b387 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2686394985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2686394985 |
| Directory | /workspace/30.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3912510299 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 107971364 ps |
| CPU time | 0.96 seconds |
| Started | Jan 10 12:57:46 PM PST 24 |
| Finished | Jan 10 12:59:05 PM PST 24 |
| Peak memory | 195460 kb |
| Host | smart-286c6d96-b026-4d07-9b11-cb539627fdfd |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912510299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3912510299 |
| Directory | /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.625857629 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 35324570 ps |
| CPU time | 0.97 seconds |
| Started | Jan 10 01:00:02 PM PST 24 |
| Finished | Jan 10 01:01:39 PM PST 24 |
| Peak memory | 196164 kb |
| Host | smart-4d030032-7a8b-4481-be16-cf28b9077813 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=625857629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.625857629 |
| Directory | /workspace/31.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.278743118 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 123362949 ps |
| CPU time | 1.1 seconds |
| Started | Jan 10 12:57:41 PM PST 24 |
| Finished | Jan 10 12:59:00 PM PST 24 |
| Peak memory | 195588 kb |
| Host | smart-8b21b8da-2319-4f38-aeea-d7c0d1c82d34 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278743118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.278743118 |
| Directory | /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2776018144 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 215047125 ps |
| CPU time | 1.12 seconds |
| Started | Jan 10 12:57:41 PM PST 24 |
| Finished | Jan 10 12:59:00 PM PST 24 |
| Peak memory | 196200 kb |
| Host | smart-98f5931c-dc8f-4dd3-ba65-ff96988090c7 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2776018144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2776018144 |
| Directory | /workspace/32.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2053229510 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 198092351 ps |
| CPU time | 1.04 seconds |
| Started | Jan 10 12:57:44 PM PST 24 |
| Finished | Jan 10 12:59:03 PM PST 24 |
| Peak memory | 195300 kb |
| Host | smart-5aefd7e6-6b86-4ba5-a5eb-c9863b367320 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053229510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2053229510 |
| Directory | /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3714059071 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 91276542 ps |
| CPU time | 1.46 seconds |
| Started | Jan 10 12:57:46 PM PST 24 |
| Finished | Jan 10 12:59:06 PM PST 24 |
| Peak memory | 196616 kb |
| Host | smart-9fb949b2-5d64-42c2-bc65-718ea887743d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3714059071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3714059071 |
| Directory | /workspace/33.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3130186357 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 344511335 ps |
| CPU time | 1.5 seconds |
| Started | Jan 10 12:57:47 PM PST 24 |
| Finished | Jan 10 12:59:10 PM PST 24 |
| Peak memory | 196256 kb |
| Host | smart-955bcde4-c588-4fdb-bb1a-d4c3dc21c54e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130186357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3130186357 |
| Directory | /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3908959681 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 233339969 ps |
| CPU time | 1.17 seconds |
| Started | Jan 10 12:57:50 PM PST 24 |
| Finished | Jan 10 12:59:09 PM PST 24 |
| Peak memory | 195320 kb |
| Host | smart-d6e4e1f8-c726-4edd-a8ad-c68a145d8237 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3908959681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3908959681 |
| Directory | /workspace/34.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1019112911 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 411535435 ps |
| CPU time | 1.4 seconds |
| Started | Jan 10 12:57:42 PM PST 24 |
| Finished | Jan 10 12:59:01 PM PST 24 |
| Peak memory | 196736 kb |
| Host | smart-ac0bb393-cd0e-49cb-b6dd-655c337006d5 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019112911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1019112911 |
| Directory | /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.660281049 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 32729674 ps |
| CPU time | 1 seconds |
| Started | Jan 10 12:57:44 PM PST 24 |
| Finished | Jan 10 12:59:03 PM PST 24 |
| Peak memory | 197656 kb |
| Host | smart-a805afb8-d7d3-4372-933c-709c90fb15ad |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=660281049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.660281049 |
| Directory | /workspace/35.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1167013778 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 44192520 ps |
| CPU time | 1.27 seconds |
| Started | Jan 10 12:57:47 PM PST 24 |
| Finished | Jan 10 12:59:06 PM PST 24 |
| Peak memory | 197636 kb |
| Host | smart-03a2ec93-85aa-4049-b757-fefd28075d85 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167013778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1167013778 |
| Directory | /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2692467211 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 120854580 ps |
| CPU time | 1.15 seconds |
| Started | Jan 10 12:57:45 PM PST 24 |
| Finished | Jan 10 12:59:04 PM PST 24 |
| Peak memory | 196264 kb |
| Host | smart-81926bd0-1a4e-43fb-b025-11b3d86a8e90 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2692467211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2692467211 |
| Directory | /workspace/36.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3773891772 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 314558334 ps |
| CPU time | 1.35 seconds |
| Started | Jan 10 12:57:44 PM PST 24 |
| Finished | Jan 10 12:59:04 PM PST 24 |
| Peak memory | 196444 kb |
| Host | smart-8d114ae5-b0fa-473b-adfa-4c413b5d93f3 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773891772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3773891772 |
| Directory | /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3031996815 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 64193444 ps |
| CPU time | 1.06 seconds |
| Started | Jan 10 12:57:49 PM PST 24 |
| Finished | Jan 10 12:59:08 PM PST 24 |
| Peak memory | 196648 kb |
| Host | smart-76d329c6-1f4a-4691-a463-0c217d1b8068 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3031996815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3031996815 |
| Directory | /workspace/37.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3561472818 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 70403410 ps |
| CPU time | 1.28 seconds |
| Started | Jan 10 12:57:46 PM PST 24 |
| Finished | Jan 10 12:59:06 PM PST 24 |
| Peak memory | 197656 kb |
| Host | smart-efdea085-8706-42b6-87c5-177ec7d81475 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561472818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3561472818 |
| Directory | /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.4127540670 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 70743118 ps |
| CPU time | 1.37 seconds |
| Started | Jan 10 12:57:45 PM PST 24 |
| Finished | Jan 10 12:59:04 PM PST 24 |
| Peak memory | 196388 kb |
| Host | smart-6ec58caf-a81c-41b2-9d09-e048a48f1e13 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4127540670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.4127540670 |
| Directory | /workspace/38.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3016716023 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 135445620 ps |
| CPU time | 1.33 seconds |
| Started | Jan 10 12:57:43 PM PST 24 |
| Finished | Jan 10 12:59:03 PM PST 24 |
| Peak memory | 197604 kb |
| Host | smart-02bf32b9-50fd-4aea-b6ae-7dc7720b8021 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016716023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3016716023 |
| Directory | /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2565373884 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 32944151 ps |
| CPU time | 0.75 seconds |
| Started | Jan 10 12:57:46 PM PST 24 |
| Finished | Jan 10 12:59:05 PM PST 24 |
| Peak memory | 195164 kb |
| Host | smart-e1f8c378-9155-41a3-887c-02e686a2a6b3 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2565373884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2565373884 |
| Directory | /workspace/39.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3711678059 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 32676621 ps |
| CPU time | 1.03 seconds |
| Started | Jan 10 12:57:50 PM PST 24 |
| Finished | Jan 10 12:59:09 PM PST 24 |
| Peak memory | 195560 kb |
| Host | smart-dbc4a01c-fc8c-42a8-8c5f-05e8044d204c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711678059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3711678059 |
| Directory | /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1556736219 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 31724678 ps |
| CPU time | 0.9 seconds |
| Started | Jan 10 12:57:28 PM PST 24 |
| Finished | Jan 10 12:58:44 PM PST 24 |
| Peak memory | 196196 kb |
| Host | smart-34bd3b07-d43b-4d9a-9a88-c68135a150a2 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1556736219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1556736219 |
| Directory | /workspace/4.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3938462553 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 48674952 ps |
| CPU time | 1.31 seconds |
| Started | Jan 10 12:57:39 PM PST 24 |
| Finished | Jan 10 12:58:56 PM PST 24 |
| Peak memory | 196644 kb |
| Host | smart-329603ac-217f-499f-a434-5038dad9ba01 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938462553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.3938462553 |
| Directory | /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4064524901 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 83687582 ps |
| CPU time | 1.17 seconds |
| Started | Jan 10 12:57:46 PM PST 24 |
| Finished | Jan 10 12:59:05 PM PST 24 |
| Peak memory | 197664 kb |
| Host | smart-a70eb491-94b0-4000-9b78-fca1bb043a52 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4064524901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.4064524901 |
| Directory | /workspace/40.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3573038112 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 75133612 ps |
| CPU time | 1.4 seconds |
| Started | Jan 10 12:57:45 PM PST 24 |
| Finished | Jan 10 12:59:05 PM PST 24 |
| Peak memory | 197704 kb |
| Host | smart-115e1c69-a3c4-4e56-b659-274c9708fbd1 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573038112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3573038112 |
| Directory | /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1086281887 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 174719578 ps |
| CPU time | 0.99 seconds |
| Started | Jan 10 12:57:54 PM PST 24 |
| Finished | Jan 10 12:59:14 PM PST 24 |
| Peak memory | 195576 kb |
| Host | smart-ad978c2a-a349-4e5d-8ba0-06cde40833cf |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1086281887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1086281887 |
| Directory | /workspace/41.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.890288231 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 57025238 ps |
| CPU time | 0.97 seconds |
| Started | Jan 10 01:00:02 PM PST 24 |
| Finished | Jan 10 01:01:31 PM PST 24 |
| Peak memory | 195852 kb |
| Host | smart-3299022c-4a73-4900-b5c8-dcc005e5a103 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890288231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.890288231 |
| Directory | /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1827448513 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 132579037 ps |
| CPU time | 1.03 seconds |
| Started | Jan 10 12:57:45 PM PST 24 |
| Finished | Jan 10 12:59:04 PM PST 24 |
| Peak memory | 195524 kb |
| Host | smart-8c3967c7-0ea1-4212-bcf8-12a3eeae58c9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1827448513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1827448513 |
| Directory | /workspace/42.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2672961561 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 57427227 ps |
| CPU time | 1.11 seconds |
| Started | Jan 10 12:57:47 PM PST 24 |
| Finished | Jan 10 12:59:10 PM PST 24 |
| Peak memory | 197640 kb |
| Host | smart-1b866f66-061b-45d0-905e-23a07c3bf6a4 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672961561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2672961561 |
| Directory | /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4140728240 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 306010238 ps |
| CPU time | 0.97 seconds |
| Started | Jan 10 12:57:53 PM PST 24 |
| Finished | Jan 10 12:59:13 PM PST 24 |
| Peak memory | 196344 kb |
| Host | smart-ae347459-0287-4098-9da9-ddbe06f11add |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4140728240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.4140728240 |
| Directory | /workspace/43.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.379849857 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 87511334 ps |
| CPU time | 1.43 seconds |
| Started | Jan 10 12:57:44 PM PST 24 |
| Finished | Jan 10 12:59:04 PM PST 24 |
| Peak memory | 195892 kb |
| Host | smart-4e11c1f1-97b5-469f-842e-560753f7819a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379849857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.379849857 |
| Directory | /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.369186582 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 60080846 ps |
| CPU time | 0.95 seconds |
| Started | Jan 10 12:57:48 PM PST 24 |
| Finished | Jan 10 12:59:08 PM PST 24 |
| Peak memory | 195228 kb |
| Host | smart-011f98e5-c3cf-44bd-87c6-32e41006e2c3 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=369186582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.369186582 |
| Directory | /workspace/44.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1120276858 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 155479375 ps |
| CPU time | 1.11 seconds |
| Started | Jan 10 12:57:45 PM PST 24 |
| Finished | Jan 10 12:59:05 PM PST 24 |
| Peak memory | 195536 kb |
| Host | smart-ed5b05cd-15fb-4e09-b53d-c5ea3249e147 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120276858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1120276858 |
| Directory | /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3650659387 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 70820003 ps |
| CPU time | 0.91 seconds |
| Started | Jan 10 12:57:47 PM PST 24 |
| Finished | Jan 10 12:59:10 PM PST 24 |
| Peak memory | 196840 kb |
| Host | smart-ddce6a09-9099-41a4-ba8f-079bf31c8db0 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3650659387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3650659387 |
| Directory | /workspace/45.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2361740170 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 49612274 ps |
| CPU time | 0.78 seconds |
| Started | Jan 10 12:57:48 PM PST 24 |
| Finished | Jan 10 12:59:07 PM PST 24 |
| Peak memory | 195860 kb |
| Host | smart-040d9643-8e29-4f0c-a2fa-ebaa8a5f0922 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361740170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2361740170 |
| Directory | /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1399297886 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 143368738 ps |
| CPU time | 1.34 seconds |
| Started | Jan 10 12:57:49 PM PST 24 |
| Finished | Jan 10 12:59:09 PM PST 24 |
| Peak memory | 195376 kb |
| Host | smart-e587977b-2fb0-4676-9138-f135d4e3d100 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1399297886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1399297886 |
| Directory | /workspace/46.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3438936196 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 89603698 ps |
| CPU time | 1.42 seconds |
| Started | Jan 10 12:57:46 PM PST 24 |
| Finished | Jan 10 12:59:06 PM PST 24 |
| Peak memory | 196452 kb |
| Host | smart-cb8de5d0-e575-4bf0-97df-7e03bacb2ea2 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438936196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3438936196 |
| Directory | /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2920389040 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 56651515 ps |
| CPU time | 0.97 seconds |
| Started | Jan 10 12:57:48 PM PST 24 |
| Finished | Jan 10 12:59:08 PM PST 24 |
| Peak memory | 196444 kb |
| Host | smart-70da2fee-4d97-4f2c-891a-57ad356a38d8 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2920389040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2920389040 |
| Directory | /workspace/47.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3824501600 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 58923464 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 01:00:01 PM PST 24 |
| Finished | Jan 10 01:01:38 PM PST 24 |
| Peak memory | 196196 kb |
| Host | smart-0cc8395d-37fa-44f0-a88c-c7256290d960 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824501600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3824501600 |
| Directory | /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3919292048 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 84063499 ps |
| CPU time | 1.34 seconds |
| Started | Jan 10 12:57:48 PM PST 24 |
| Finished | Jan 10 12:59:07 PM PST 24 |
| Peak memory | 196556 kb |
| Host | smart-7e1d703a-5021-4ae1-8eec-462f5794a24f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3919292048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3919292048 |
| Directory | /workspace/48.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1076069544 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 88469947 ps |
| CPU time | 1.12 seconds |
| Started | Jan 10 12:57:48 PM PST 24 |
| Finished | Jan 10 12:59:08 PM PST 24 |
| Peak memory | 195564 kb |
| Host | smart-62e1c85e-8581-4d8b-9855-9c48debb9d2a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076069544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1076069544 |
| Directory | /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.944361550 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 271048407 ps |
| CPU time | 1.4 seconds |
| Started | Jan 10 12:57:44 PM PST 24 |
| Finished | Jan 10 12:59:04 PM PST 24 |
| Peak memory | 196032 kb |
| Host | smart-5746516a-68c4-4d34-876e-5f4f906c2747 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=944361550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.944361550 |
| Directory | /workspace/49.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.634039418 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 147784804 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 01:00:02 PM PST 24 |
| Finished | Jan 10 01:01:31 PM PST 24 |
| Peak memory | 197408 kb |
| Host | smart-0147ba56-d4b3-4bde-afbb-001284bcb970 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634039418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.634039418 |
| Directory | /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.24296906 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 107341675 ps |
| CPU time | 0.94 seconds |
| Started | Jan 10 12:57:33 PM PST 24 |
| Finished | Jan 10 12:58:49 PM PST 24 |
| Peak memory | 196236 kb |
| Host | smart-2ae06470-62a3-40e8-9213-be62cab4af76 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=24296906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.24296906 |
| Directory | /workspace/5.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3527997153 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 21587811 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 12:57:33 PM PST 24 |
| Finished | Jan 10 12:58:50 PM PST 24 |
| Peak memory | 194080 kb |
| Host | smart-52e1b6a6-ad68-4dff-b1f1-c32dc517430d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527997153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.3527997153 |
| Directory | /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1159736577 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 91383703 ps |
| CPU time | 1.36 seconds |
| Started | Jan 10 12:57:39 PM PST 24 |
| Finished | Jan 10 12:58:58 PM PST 24 |
| Peak memory | 196568 kb |
| Host | smart-a9b9a87b-8bff-4176-9fc0-ed2d0d5a81a1 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1159736577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1159736577 |
| Directory | /workspace/6.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1740002987 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 45707853 ps |
| CPU time | 0.9 seconds |
| Started | Jan 10 12:57:35 PM PST 24 |
| Finished | Jan 10 12:58:51 PM PST 24 |
| Peak memory | 196260 kb |
| Host | smart-53220729-50a7-461e-8eae-ad2a4966ecf6 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740002987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.1740002987 |
| Directory | /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1489016565 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 38977964 ps |
| CPU time | 0.98 seconds |
| Started | Jan 10 12:57:31 PM PST 24 |
| Finished | Jan 10 12:58:48 PM PST 24 |
| Peak memory | 196312 kb |
| Host | smart-eca94881-6196-4b72-9778-e40257217360 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1489016565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1489016565 |
| Directory | /workspace/7.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4262556252 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 385012843 ps |
| CPU time | 1.32 seconds |
| Started | Jan 10 12:57:35 PM PST 24 |
| Finished | Jan 10 12:58:52 PM PST 24 |
| Peak memory | 196664 kb |
| Host | smart-530657a9-a066-4920-aaa8-9b35909b1a66 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262556252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.4262556252 |
| Directory | /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.994177517 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 619378866 ps |
| CPU time | 1.31 seconds |
| Started | Jan 10 12:57:40 PM PST 24 |
| Finished | Jan 10 12:58:59 PM PST 24 |
| Peak memory | 197700 kb |
| Host | smart-e816e3a6-eccb-4ba2-aa0e-874824f39167 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=994177517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.994177517 |
| Directory | /workspace/8.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1755896297 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 257754677 ps |
| CPU time | 1.13 seconds |
| Started | Jan 10 12:57:33 PM PST 24 |
| Finished | Jan 10 12:58:50 PM PST 24 |
| Peak memory | 196232 kb |
| Host | smart-fe67dab6-a237-45df-b2a2-dbd0e85c5384 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755896297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.1755896297 |
| Directory | /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.922850276 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 298200467 ps |
| CPU time | 1.01 seconds |
| Started | Jan 10 12:57:34 PM PST 24 |
| Finished | Jan 10 12:58:54 PM PST 24 |
| Peak memory | 197548 kb |
| Host | smart-272a5c3f-1fa8-46ad-80de-a0eb5ad6945a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=922850276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.922850276 |
| Directory | /workspace/9.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1635276071 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 527178711 ps |
| CPU time | 1.23 seconds |
| Started | Jan 10 12:57:31 PM PST 24 |
| Finished | Jan 10 12:58:48 PM PST 24 |
| Peak memory | 195408 kb |
| Host | smart-4014c834-77c0-4693-bea2-929e27f8a061 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635276071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.1635276071 |
| Directory | /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
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