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Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3278400 1 T42 178 T43 76 T44 172
auto[1] 2854748 1 T42 176 T43 74 T44 192


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3861155 1 T42 187 T43 79 T44 188
auto[1] 2271993 1 T42 167 T43 71 T44 176


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2133599 1 T42 87 T43 42 T44 88
auto[0] auto[1] 1144801 1 T42 91 T43 34 T44 84
auto[1] auto[0] 1727556 1 T42 100 T43 37 T44 100
auto[1] auto[1] 1127192 1 T42 76 T43 37 T44 92


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3273763 1 T42 160 T43 72 T44 172
auto[1] 2859385 1 T42 194 T43 78 T44 192


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3861365 1 T42 173 T43 65 T44 171
auto[1] 2271783 1 T42 181 T43 85 T44 193


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2131372 1 T42 74 T43 28 T44 77
auto[0] auto[1] 1142391 1 T42 86 T43 44 T44 95
auto[1] auto[0] 1729993 1 T42 99 T43 37 T44 94
auto[1] auto[1] 1129392 1 T42 95 T43 41 T44 98


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3277308 1 T42 190 T43 76 T44 168
auto[1] 2855840 1 T42 164 T43 74 T44 196


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3859910 1 T42 173 T43 67 T44 198
auto[1] 2273238 1 T42 181 T43 83 T44 166


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2133054 1 T42 96 T43 38 T44 90
auto[0] auto[1] 1144254 1 T42 94 T43 38 T44 78
auto[1] auto[0] 1726856 1 T42 77 T43 29 T44 108
auto[1] auto[1] 1128984 1 T42 87 T43 45 T44 88


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3280522 1 T42 174 T43 76 T44 184
auto[1] 2852626 1 T42 180 T43 74 T44 180


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3862483 1 T42 156 T43 74 T44 181
auto[1] 2270665 1 T42 198 T43 76 T44 183


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2135212 1 T42 70 T43 38 T44 86
auto[0] auto[1] 1145310 1 T42 104 T43 38 T44 98
auto[1] auto[0] 1727271 1 T42 86 T43 36 T44 95
auto[1] auto[1] 1125355 1 T42 94 T43 38 T44 85


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3278159 1 T42 178 T43 76 T44 168
auto[1] 2854989 1 T42 176 T43 74 T44 196


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3864377 1 T42 164 T43 67 T44 179
auto[1] 2268771 1 T42 190 T43 83 T44 185


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2134670 1 T42 80 T43 34 T44 77
auto[0] auto[1] 1143489 1 T42 98 T43 42 T44 91
auto[1] auto[0] 1729707 1 T42 84 T43 33 T44 102
auto[1] auto[1] 1125282 1 T42 92 T43 41 T44 94


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3272042 1 T42 200 T43 66 T44 192
auto[1] 2861106 1 T42 154 T43 84 T44 172


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3861771 1 T42 168 T43 70 T44 174
auto[1] 2271377 1 T42 186 T43 80 T44 190


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2127922 1 T42 88 T43 31 T44 94
auto[0] auto[1] 1144120 1 T42 112 T43 35 T44 98
auto[1] auto[0] 1733849 1 T42 80 T43 39 T44 80
auto[1] auto[1] 1127257 1 T42 74 T43 45 T44 92


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3266883 1 T42 182 T43 74 T44 204
auto[1] 2866265 1 T42 172 T43 76 T44 160


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3860246 1 T42 176 T43 86 T44 183
auto[1] 2272902 1 T42 178 T43 64 T44 181


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2124689 1 T42 107 T43 43 T44 108
auto[0] auto[1] 1142194 1 T42 75 T43 31 T44 96
auto[1] auto[0] 1735557 1 T42 69 T43 43 T44 75
auto[1] auto[1] 1130708 1 T42 103 T43 33 T44 85


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3276681 1 T42 182 T43 70 T44 184
auto[1] 2856467 1 T42 172 T43 80 T44 180


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3860068 1 T42 164 T43 75 T44 184
auto[1] 2273080 1 T42 190 T43 75 T44 180


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2130767 1 T42 79 T43 34 T44 96
auto[0] auto[1] 1145914 1 T42 103 T43 36 T44 88
auto[1] auto[0] 1729301 1 T42 85 T43 41 T44 88
auto[1] auto[1] 1127166 1 T42 87 T43 39 T44 92


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3275015 1 T42 162 T43 66 T44 198
auto[1] 2858133 1 T42 192 T43 84 T44 166


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3874819 1 T42 180 T43 67 T44 195
auto[1] 2258329 1 T42 174 T43 83 T44 169


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2138088 1 T42 84 T43 32 T44 98
auto[0] auto[1] 1136927 1 T42 78 T43 34 T44 100
auto[1] auto[0] 1736731 1 T42 96 T43 35 T44 97
auto[1] auto[1] 1121402 1 T42 96 T43 49 T44 69


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3279239 1 T42 140 T43 70 T44 200
auto[1] 2853909 1 T42 214 T43 80 T44 164


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3874858 1 T42 169 T43 77 T44 172
auto[1] 2258290 1 T42 185 T43 73 T44 192


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2141349 1 T42 66 T43 34 T44 97
auto[0] auto[1] 1137890 1 T42 74 T43 36 T44 103
auto[1] auto[0] 1733509 1 T42 103 T43 43 T44 75
auto[1] auto[1] 1120400 1 T42 111 T43 37 T44 89


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3279452 1 T42 168 T43 76 T44 212
auto[1] 2853696 1 T42 186 T43 74 T44 152


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3872615 1 T42 181 T43 67 T44 208
auto[1] 2260533 1 T42 173 T43 83 T44 156


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2140023 1 T42 97 T43 32 T44 125
auto[0] auto[1] 1139429 1 T42 71 T43 44 T44 87
auto[1] auto[0] 1732592 1 T42 84 T43 35 T44 83
auto[1] auto[1] 1121104 1 T42 102 T43 39 T44 69


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3274739 1 T42 188 T43 70 T44 170
auto[1] 2858409 1 T42 166 T43 80 T44 194


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3876353 1 T42 169 T43 74 T44 187
auto[1] 2256795 1 T42 185 T43 76 T44 177


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2139238 1 T42 82 T43 39 T44 80
auto[0] auto[1] 1135501 1 T42 106 T43 31 T44 90
auto[1] auto[0] 1737115 1 T42 87 T43 35 T44 107
auto[1] auto[1] 1121294 1 T42 79 T43 45 T44 87


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3275010 1 T42 164 T43 72 T44 162
auto[1] 2858138 1 T42 190 T43 78 T44 202


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3857383 1 T42 173 T43 72 T44 183
auto[1] 2275765 1 T42 181 T43 78 T44 181


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2130161 1 T42 77 T43 34 T44 79
auto[0] auto[1] 1144849 1 T42 87 T43 38 T44 83
auto[1] auto[0] 1727222 1 T42 96 T43 38 T44 104
auto[1] auto[1] 1130916 1 T42 94 T43 40 T44 98


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3270373 1 T42 188 T43 94 T44 178
auto[1] 2862775 1 T42 166 T43 56 T44 186


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3879719 1 T42 175 T43 82 T44 179
auto[1] 2253429 1 T42 179 T43 68 T44 185


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2138753 1 T42 98 T43 48 T44 88
auto[0] auto[1] 1131620 1 T42 90 T43 46 T44 90
auto[1] auto[0] 1740966 1 T42 77 T43 34 T44 91
auto[1] auto[1] 1121809 1 T42 89 T43 22 T44 95


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3273560 1 T42 170 T43 68 T44 184
auto[1] 2859588 1 T42 184 T43 82 T44 180


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3872740 1 T42 183 T43 76 T44 182
auto[1] 2260408 1 T42 171 T43 74 T44 182


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2136796 1 T42 90 T43 31 T44 89
auto[0] auto[1] 1136764 1 T42 80 T43 37 T44 95
auto[1] auto[0] 1735944 1 T42 93 T43 45 T44 93
auto[1] auto[1] 1123644 1 T42 91 T43 37 T44 87


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3276118 1 T42 186 T43 88 T44 176
auto[1] 2857030 1 T42 168 T43 62 T44 188


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3870925 1 T42 198 T43 71 T44 174
auto[1] 2262223 1 T42 156 T43 79 T44 190


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2137730 1 T42 98 T43 42 T44 82
auto[0] auto[1] 1138388 1 T42 88 T43 46 T44 94
auto[1] auto[0] 1733195 1 T42 100 T43 29 T44 92
auto[1] auto[1] 1123835 1 T42 68 T43 33 T44 96


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3277323 1 T42 184 T43 76 T44 178
auto[1] 2855825 1 T42 170 T43 74 T44 186


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3875564 1 T42 180 T43 77 T44 160
auto[1] 2257584 1 T42 174 T43 73 T44 204


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2139313 1 T42 96 T43 42 T44 75
auto[0] auto[1] 1138010 1 T42 88 T43 34 T44 103
auto[1] auto[0] 1736251 1 T42 84 T43 35 T44 85
auto[1] auto[1] 1119574 1 T42 86 T43 39 T44 101


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3274419 1 T42 176 T43 80 T44 178
auto[1] 2858729 1 T42 178 T43 70 T44 186


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3878194 1 T42 183 T43 65 T44 172
auto[1] 2254954 1 T42 171 T43 85 T44 192


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2139335 1 T42 93 T43 38 T44 79
auto[0] auto[1] 1135084 1 T42 83 T43 42 T44 99
auto[1] auto[0] 1738859 1 T42 90 T43 27 T44 93
auto[1] auto[1] 1119870 1 T42 88 T43 43 T44 93


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3275845 1 T42 172 T43 70 T44 206
auto[1] 2857303 1 T42 182 T43 80 T44 158


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3871666 1 T42 149 T43 75 T44 191
auto[1] 2261482 1 T42 205 T43 75 T44 173


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2137831 1 T42 73 T43 33 T44 105
auto[0] auto[1] 1138014 1 T42 99 T43 37 T44 101
auto[1] auto[0] 1733835 1 T42 76 T43 42 T44 86
auto[1] auto[1] 1123468 1 T42 106 T43 38 T44 72


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3277146 1 T42 190 T43 78 T44 194
auto[1] 2856002 1 T42 164 T43 72 T44 170


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3877573 1 T42 166 T43 84 T44 173
auto[1] 2255575 1 T42 188 T43 66 T44 191


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2139614 1 T42 92 T43 45 T44 82
auto[0] auto[1] 1137532 1 T42 98 T43 33 T44 112
auto[1] auto[0] 1737959 1 T42 74 T43 39 T44 91
auto[1] auto[1] 1118043 1 T42 90 T43 33 T44 79


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3274323 1 T42 172 T43 60 T44 194
auto[1] 2858825 1 T42 182 T43 90 T44 170


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3872763 1 T42 178 T43 73 T44 190
auto[1] 2260385 1 T42 176 T43 77 T44 174


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2137050 1 T42 79 T43 24 T44 106
auto[0] auto[1] 1137273 1 T42 93 T43 36 T44 88
auto[1] auto[0] 1735713 1 T42 99 T43 49 T44 84
auto[1] auto[1] 1123112 1 T42 83 T43 41 T44 86


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3279477 1 T42 192 T43 60 T44 162
auto[1] 2853671 1 T42 162 T43 90 T44 202


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3873459 1 T42 185 T43 62 T44 202
auto[1] 2259689 1 T42 169 T43 88 T44 162


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2139464 1 T42 104 T43 23 T44 87
auto[0] auto[1] 1140013 1 T42 88 T43 37 T44 75
auto[1] auto[0] 1733995 1 T42 81 T43 39 T44 115
auto[1] auto[1] 1119676 1 T42 81 T43 51 T44 87


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3275606 1 T42 164 T43 74 T44 182
auto[1] 2857542 1 T42 190 T43 76 T44 182


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3874885 1 T42 139 T43 72 T44 173
auto[1] 2258263 1 T42 215 T43 78 T44 191


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2137046 1 T42 68 T43 35 T44 85
auto[0] auto[1] 1138560 1 T42 96 T43 39 T44 97
auto[1] auto[0] 1737839 1 T42 71 T43 37 T44 88
auto[1] auto[1] 1119703 1 T42 119 T43 39 T44 94


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3271064 1 T42 184 T43 82 T44 196
auto[1] 2862084 1 T42 170 T43 68 T44 168


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3865638 1 T42 181 T43 87 T44 165
auto[1] 2267510 1 T42 173 T43 63 T44 199


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2130477 1 T42 97 T43 40 T44 90
auto[0] auto[1] 1140587 1 T42 87 T43 42 T44 106
auto[1] auto[0] 1735161 1 T42 84 T43 47 T44 75
auto[1] auto[1] 1126923 1 T42 86 T43 21 T44 93


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3275663 1 T42 196 T43 62 T44 198
auto[1] 2857485 1 T42 158 T43 88 T44 166


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3880796 1 T42 179 T43 74 T44 178
auto[1] 2252352 1 T42 175 T43 76 T44 186


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2142218 1 T42 100 T43 29 T44 96
auto[0] auto[1] 1133445 1 T42 96 T43 33 T44 102
auto[1] auto[0] 1738578 1 T42 79 T43 45 T44 82
auto[1] auto[1] 1118907 1 T42 79 T43 43 T44 84

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%