Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6483893	1			T21	127		T1	3		T11	9
all_pins[1]	6483893	1			T21	127		T1	3		T11	9
all_pins[2]	6483893	1			T21	127		T1	3		T11	9
all_pins[3]	6483893	1			T21	127		T1	3		T11	9
all_pins[4]	6483893	1			T21	127		T1	3		T11	9
all_pins[5]	6483893	1			T21	127		T1	3		T11	9
all_pins[6]	6483893	1			T21	127		T1	3		T11	9
all_pins[7]	6483893	1			T21	127		T1	3		T11	9
all_pins[8]	6483893	1			T21	127		T1	3		T11	9
all_pins[9]	6483893	1			T21	127		T1	3		T11	9
all_pins[10]	6483893	1			T21	127		T1	3		T11	9
all_pins[11]	6483893	1			T21	127		T1	3		T11	9
all_pins[12]	6483893	1			T21	127		T1	3		T11	9
all_pins[13]	6483893	1			T21	127		T1	3		T11	9
all_pins[14]	6483893	1			T21	127		T1	3		T11	9
all_pins[15]	6483893	1			T21	127		T1	3		T11	9
all_pins[16]	6483893	1			T21	127		T1	3		T11	9
all_pins[17]	6483893	1			T21	127		T1	3		T11	9
all_pins[18]	6483893	1			T21	127		T1	3		T11	9
all_pins[19]	6483893	1			T21	127		T1	3		T11	9
all_pins[20]	6483893	1			T21	127		T1	3		T11	9
all_pins[21]	6483893	1			T21	127		T1	3		T11	9
all_pins[22]	6483893	1			T21	127		T1	3		T11	9
all_pins[23]	6483893	1			T21	127		T1	3		T11	9
all_pins[24]	6483893	1			T21	127		T1	3		T11	9
all_pins[25]	6483893	1			T21	127		T1	3		T11	9
all_pins[26]	6483893	1			T21	127		T1	3		T11	9
all_pins[27]	6483893	1			T21	127		T1	3		T11	9
all_pins[28]	6483893	1			T21	127		T1	3		T11	9
all_pins[29]	6483893	1			T21	127		T1	3		T11	9
all_pins[30]	6483893	1			T21	127		T1	3		T11	9
all_pins[31]	6483893	1			T21	127		T1	3		T11	9

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	128649245	1			T21	4001		T1	82		T11	246
values[0x1]	78835331	1			T21	63		T1	14		T11	42
transitions[0x0=>0x1]	47146543	1			T21	63		T1	8		T11	32
transitions[0x1=>0x0]	47146377	1			T21	63		T1	8		T11	32

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	4018191	1			T21	126		T1	2		T11	9
all_pins[0]	values[0x1]	2465702	1			T21	1		T1	1		T12	3
all_pins[0]	transitions[0x0=>0x1]	1525657	1			T21	1		T1	1		T13	5
all_pins[0]	transitions[0x1=>0x0]	1523054	1			T21	2		T1	1		T11	1
all_pins[1]	values[0x0]	4015175	1			T21	125		T1	3		T11	7
all_pins[1]	values[0x1]	2468718	1			T21	2		T11	2		T12	2
all_pins[1]	transitions[0x0=>0x1]	1472576	1			T21	2		T11	2		T12	1
all_pins[1]	transitions[0x1=>0x0]	1469560	1			T21	1		T1	1		T12	2
all_pins[2]	values[0x0]	4025166	1			T21	125		T1	3		T11	8
all_pins[2]	values[0x1]	2458727	1			T21	2		T11	1		T12	4
all_pins[2]	transitions[0x0=>0x1]	1466705	1			T21	2		T11	1		T12	4
all_pins[2]	transitions[0x1=>0x0]	1476696	1			T21	2		T11	2		T12	2
all_pins[3]	values[0x0]	4025322	1			T21	125		T1	2		T11	8
all_pins[3]	values[0x1]	2458571	1			T21	2		T1	1		T11	1
all_pins[3]	transitions[0x0=>0x1]	1467868	1			T21	2		T1	1		T13	1
all_pins[3]	transitions[0x1=>0x0]	1468024	1			T21	2		T12	4		T13	3
all_pins[4]	values[0x0]	4020515	1			T21	125		T1	3		T11	3
all_pins[4]	values[0x1]	2463378	1			T21	2		T11	6		T12	4
all_pins[4]	transitions[0x0=>0x1]	1472013	1			T21	2		T11	6		T12	4
all_pins[4]	transitions[0x1=>0x0]	1467206	1			T21	2		T1	1		T11	1
all_pins[5]	values[0x0]	4018157	1			T21	125		T1	3		T11	7
all_pins[5]	values[0x1]	2465736	1			T21	2		T11	2		T12	1
all_pins[5]	transitions[0x0=>0x1]	1474938	1			T21	2		T11	1		T12	1
all_pins[5]	transitions[0x1=>0x0]	1472580	1			T21	2		T11	5		T12	4
all_pins[6]	values[0x0]	4023051	1			T21	125		T1	3		T11	8
all_pins[6]	values[0x1]	2460842	1			T21	2		T11	1		T13	4
all_pins[6]	transitions[0x0=>0x1]	1469820	1			T21	2		T13	4		T17	2
all_pins[6]	transitions[0x1=>0x0]	1474714	1			T21	2		T11	1		T12	1
all_pins[7]	values[0x0]	4018859	1			T21	125		T1	3		T11	8
all_pins[7]	values[0x1]	2465034	1			T21	2		T11	1		T12	2
all_pins[7]	transitions[0x0=>0x1]	1474588	1			T21	2		T12	2		T13	2
all_pins[7]	transitions[0x1=>0x0]	1470396	1			T21	2		T13	3		T17	3
all_pins[8]	values[0x0]	4019589	1			T21	125		T1	3		T11	9
all_pins[8]	values[0x1]	2464304	1			T21	2		T13	3		T14	2
all_pins[8]	transitions[0x0=>0x1]	1469252	1			T21	2		T13	2		T14	2
all_pins[8]	transitions[0x1=>0x0]	1469982	1			T21	2		T11	1		T12	2
all_pins[9]	values[0x0]	4017926	1			T21	125		T1	3		T11	8
all_pins[9]	values[0x1]	2465967	1			T21	2		T11	1		T13	11
all_pins[9]	transitions[0x0=>0x1]	1470599	1			T21	2		T11	1		T13	8
all_pins[9]	transitions[0x1=>0x0]	1468936	1			T21	2		T14	1		T15	4
all_pins[10]	values[0x0]	4013839	1			T21	125		T1	2		T11	6
all_pins[10]	values[0x1]	2470054	1			T21	2		T1	1		T11	3
all_pins[10]	transitions[0x0=>0x1]	1474693	1			T21	2		T1	1		T11	3
all_pins[10]	transitions[0x1=>0x0]	1470606	1			T21	2		T11	1		T13	5
all_pins[11]	values[0x0]	4016618	1			T21	125		T1	3		T11	8
all_pins[11]	values[0x1]	2467275	1			T21	2		T11	1		T12	2
all_pins[11]	transitions[0x0=>0x1]	1471057	1			T21	2		T12	1		T13	4
all_pins[11]	transitions[0x1=>0x0]	1473836	1			T21	2		T1	1		T11	2
all_pins[12]	values[0x0]	4027136	1			T21	125		T1	3		T11	9
all_pins[12]	values[0x1]	2456757	1			T21	2		T13	8		T15	2
all_pins[12]	transitions[0x0=>0x1]	1467277	1			T21	2		T13	4		T15	2
all_pins[12]	transitions[0x1=>0x0]	1477795	1			T21	2		T11	1		T12	2
all_pins[13]	values[0x0]	4021773	1			T21	125		T1	3		T11	8
all_pins[13]	values[0x1]	2462120	1			T21	2		T11	1		T12	3
all_pins[13]	transitions[0x0=>0x1]	1476189	1			T21	2		T11	1		T12	3
all_pins[13]	transitions[0x1=>0x0]	1470826	1			T21	2		T13	6		T15	2
all_pins[14]	values[0x0]	4024257	1			T21	125		T1	3		T11	7
all_pins[14]	values[0x1]	2459636	1			T21	2		T11	2		T12	2
all_pins[14]	transitions[0x0=>0x1]	1470865	1			T21	2		T11	2		T12	2
all_pins[14]	transitions[0x1=>0x0]	1473349	1			T21	2		T11	1		T12	3
all_pins[15]	values[0x0]	4017684	1			T21	125		T1	2		T11	5
all_pins[15]	values[0x1]	2466209	1			T21	2		T1	1		T11	4
all_pins[15]	transitions[0x0=>0x1]	1473826	1			T21	2		T1	1		T11	2
all_pins[15]	transitions[0x1=>0x0]	1467253	1			T21	2		T12	2		T13	4
all_pins[16]	values[0x0]	4024192	1			T21	125		T1	3		T11	9
all_pins[16]	values[0x1]	2459701	1			T21	2		T13	3		T15	5
all_pins[16]	transitions[0x0=>0x1]	1469237	1			T21	2		T13	3		T15	5
all_pins[16]	transitions[0x1=>0x0]	1475745	1			T21	2		T1	1		T11	4
all_pins[17]	values[0x0]	4029291	1			T21	125		T1	2		T11	9
all_pins[17]	values[0x1]	2454602	1			T21	2		T1	1		T12	1
all_pins[17]	transitions[0x0=>0x1]	1468751	1			T21	2		T1	1		T12	1
all_pins[17]	transitions[0x1=>0x0]	1473850	1			T21	2		T13	3		T15	5
all_pins[18]	values[0x0]	4015783	1			T21	125		T1	2		T11	9
all_pins[18]	values[0x1]	2468110	1			T21	2		T1	1		T13	4
all_pins[18]	transitions[0x0=>0x1]	1478201	1			T21	2		T13	4		T15	10
all_pins[18]	transitions[0x1=>0x0]	1464693	1			T21	2		T12	1		T13	3
all_pins[19]	values[0x0]	4013437	1			T21	125		T1	3		T11	2
all_pins[19]	values[0x1]	2470456	1			T21	2		T11	7		T12	4
all_pins[19]	transitions[0x0=>0x1]	1472999	1			T21	2		T11	7		T12	4
all_pins[19]	transitions[0x1=>0x0]	1470653	1			T21	2		T1	1		T15	7
all_pins[20]	values[0x0]	4014212	1			T21	125		T1	2		T11	8
all_pins[20]	values[0x1]	2469681	1			T21	2		T1	1		T11	1
all_pins[20]	transitions[0x0=>0x1]	1469812	1			T21	2		T1	1		T13	1
all_pins[20]	transitions[0x1=>0x0]	1470587	1			T21	2		T11	6		T12	2
all_pins[21]	values[0x0]	4022916	1			T21	125		T1	2		T11	9
all_pins[21]	values[0x1]	2460977	1			T21	2		T1	1		T12	4
all_pins[21]	transitions[0x0=>0x1]	1467342	1			T21	2		T12	3		T13	4
all_pins[21]	transitions[0x1=>0x0]	1476046	1			T21	2		T11	1		T12	1
all_pins[22]	values[0x0]	4022493	1			T21	125		T1	2		T11	9
all_pins[22]	values[0x1]	2461400	1			T21	2		T1	1		T12	4
all_pins[22]	transitions[0x0=>0x1]	1469957	1			T21	2		T12	2		T13	5
all_pins[22]	transitions[0x1=>0x0]	1469534	1			T21	2		T12	2		T13	2
all_pins[23]	values[0x0]	4021944	1			T21	125		T1	2		T11	9
all_pins[23]	values[0x1]	2461949	1			T21	2		T1	1		T12	3
all_pins[23]	transitions[0x0=>0x1]	1471612	1			T21	2		T12	2		T13	6
all_pins[23]	transitions[0x1=>0x0]	1471063	1			T21	2		T12	3		T13	6
all_pins[24]	values[0x0]	4015900	1			T21	125		T1	2		T11	9
all_pins[24]	values[0x1]	2467993	1			T21	2		T1	1		T13	10
all_pins[24]	transitions[0x0=>0x1]	1474866	1			T21	2		T13	7		T19	3
all_pins[24]	transitions[0x1=>0x0]	1468822	1			T21	2		T12	3		T13	4
all_pins[25]	values[0x0]	4020104	1			T21	125		T1	3		T11	7
all_pins[25]	values[0x1]	2463789	1			T21	2		T11	2		T12	2
all_pins[25]	transitions[0x0=>0x1]	1471892	1			T21	2		T11	2		T12	2
all_pins[25]	transitions[0x1=>0x0]	1476096	1			T21	2		T1	1		T13	9
all_pins[26]	values[0x0]	4018410	1			T21	125		T1	2		T11	7
all_pins[26]	values[0x1]	2465483	1			T21	2		T1	1		T11	2
all_pins[26]	transitions[0x0=>0x1]	1472676	1			T21	2		T1	1		T11	2
all_pins[26]	transitions[0x1=>0x0]	1470982	1			T21	2		T11	2		T12	2
all_pins[27]	values[0x0]	4020830	1			T21	125		T1	3		T11	7
all_pins[27]	values[0x1]	2463063	1			T21	2		T11	2		T12	2
all_pins[27]	transitions[0x0=>0x1]	1470186	1			T21	2		T12	2		T13	6
all_pins[27]	transitions[0x1=>0x0]	1472606	1			T21	2		T1	1		T13	3
all_pins[28]	values[0x0]	4019813	1			T21	125		T1	3		T11	8
all_pins[28]	values[0x1]	2464080	1			T21	2		T11	1		T12	3
all_pins[28]	transitions[0x0=>0x1]	1472883	1			T21	2		T11	1		T12	1
all_pins[28]	transitions[0x1=>0x0]	1471866	1			T21	2		T11	2		T13	8
all_pins[29]	values[0x0]	4022069	1			T21	125		T1	3		T11	9
all_pins[29]	values[0x1]	2461824	1			T21	2		T13	4		T14	2
all_pins[29]	transitions[0x0=>0x1]	1472267	1			T21	2		T13	2		T14	2
all_pins[29]	transitions[0x1=>0x0]	1474523	1			T21	2		T11	1		T12	3
all_pins[30]	values[0x0]	4023965	1			T21	125		T1	2		T11	9
all_pins[30]	values[0x1]	2459928	1			T21	2		T1	1		T13	2
all_pins[30]	transitions[0x0=>0x1]	1471260	1			T21	2		T1	1		T13	2
all_pins[30]	transitions[0x1=>0x0]	1473156	1			T21	2		T13	4		T14	2
all_pins[31]	values[0x0]	4020628	1			T21	125		T1	2		T11	8
all_pins[31]	values[0x1]	2463265	1			T21	2		T1	1		T11	1
all_pins[31]	transitions[0x0=>0x1]	1474679	1			T21	2		T11	1		T12	3
all_pins[31]	transitions[0x1=>0x0]	1471342	1			T21	2		T13	1		T15	4