Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	21663471	1			T21	1		T1	13		T11	12
all_values[1]	21663471	1			T21	1		T1	13		T11	12
all_values[2]	21663471	1			T21	1		T1	13		T11	12
all_values[3]	21663471	1			T21	1		T1	13		T11	12
all_values[4]	21663471	1			T21	1		T1	13		T11	12
all_values[5]	21663471	1			T21	1		T1	13		T11	12
all_values[6]	21663471	1			T21	1		T1	13		T11	12
all_values[7]	21663471	1			T21	1		T1	13		T11	12
all_values[8]	21663471	1			T21	1		T1	13		T11	12
all_values[9]	21663471	1			T21	1		T1	13		T11	12
all_values[10]	21663471	1			T21	1		T1	13		T11	12
all_values[11]	21663471	1			T21	1		T1	13		T11	12
all_values[12]	21663471	1			T21	1		T1	13		T11	12
all_values[13]	21663471	1			T21	1		T1	13		T11	12
all_values[14]	21663471	1			T21	1		T1	13		T11	12
all_values[15]	21663471	1			T21	1		T1	13		T11	12
all_values[16]	21663471	1			T21	1		T1	13		T11	12
all_values[17]	21663471	1			T21	1		T1	13		T11	12
all_values[18]	21663471	1			T21	1		T1	13		T11	12
all_values[19]	21663471	1			T21	1		T1	13		T11	12
all_values[20]	21663471	1			T21	1		T1	13		T11	12
all_values[21]	21663471	1			T21	1		T1	13		T11	12
all_values[22]	21663471	1			T21	1		T1	13		T11	12
all_values[23]	21663471	1			T21	1		T1	13		T11	12
all_values[24]	21663471	1			T21	1		T1	13		T11	12
all_values[25]	21663471	1			T21	1		T1	13		T11	12
all_values[26]	21663471	1			T21	1		T1	13		T11	12
all_values[27]	21663471	1			T21	1		T1	13		T11	12
all_values[28]	21663471	1			T21	1		T1	13		T11	12
all_values[29]	21663471	1			T21	1		T1	13		T11	12
all_values[30]	21663471	1			T21	1		T1	13		T11	12
all_values[31]	21663471	1			T21	1		T1	13		T11	12

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

383257233

1

T21

32

T1

262

T11

210

auto[1]

309973839

1

T1

154

T11

174

T12

172

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130913059

1

T21

32

T1

210

T11

270

auto[1]

562318013

1

T1

206

T11

114

T12

116

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

685338573

1

T21

32

T1

416

T11

345

auto[1]

7892499

1

T11

39

T12

36

T13

133

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3185149	1			T21	1		T1	2		T11	8
all_values[0]	auto[0]	auto[0]	auto[1]	8649881	1			T11	1		T12	3		T13	11
all_values[0]	auto[0]	auto[1]	auto[0]	901207	1			T11	2		T12	2		T15	8
all_values[0]	auto[0]	auto[1]	auto[1]	8680657	1			T1	11		T12	2		T13	6
all_values[0]	auto[1]	auto[0]	auto[1]	123618	1			T11	1		T12	1		T13	4
all_values[0]	auto[1]	auto[1]	auto[1]	122959	1			T12	1		T13	1		T73	1
all_values[1]	auto[0]	auto[0]	auto[0]	3179857	1			T21	1		T1	13		T11	5
all_values[1]	auto[0]	auto[0]	auto[1]	8628429	1			T11	2		T12	4		T13	2
all_values[1]	auto[0]	auto[1]	auto[0]	903422	1			T11	2		T12	1		T13	12
all_values[1]	auto[0]	auto[1]	auto[1]	8705467	1			T11	1		T13	4		T15	5
all_values[1]	auto[1]	auto[0]	auto[1]	123362	1			T11	1		T13	4		T15	2
all_values[1]	auto[1]	auto[1]	auto[1]	122934	1			T11	1		T12	2		T13	2
all_values[2]	auto[0]	auto[0]	auto[0]	3190434	1			T21	1		T1	13		T11	5
all_values[2]	auto[0]	auto[0]	auto[1]	8708079	1			T11	4		T12	1		T13	7
all_values[2]	auto[0]	auto[1]	auto[0]	912972	1			T11	1		T12	3		T13	6
all_values[2]	auto[0]	auto[1]	auto[1]	8605082	1			T12	4		T13	3		T15	8
all_values[2]	auto[1]	auto[0]	auto[1]	123512	1			T11	1		T12	1		T13	2
all_values[2]	auto[1]	auto[1]	auto[1]	123392	1			T11	1		T13	2		T73	2
all_values[3]	auto[0]	auto[0]	auto[0]	3184101	1			T21	1		T1	2		T11	4
all_values[3]	auto[0]	auto[0]	auto[1]	8659959	1			T11	1		T13	3		T14	1
all_values[3]	auto[0]	auto[1]	auto[0]	912620	1			T1	11		T11	5		T12	5
all_values[3]	auto[0]	auto[1]	auto[1]	8659839	1			T13	1		T73	5		T22	1
all_values[3]	auto[1]	auto[0]	auto[1]	123819	1			T11	1		T13	2		T15	2
all_values[3]	auto[1]	auto[1]	auto[1]	123133	1			T11	1		T13	3		T73	3
all_values[4]	auto[0]	auto[0]	auto[0]	3183602	1			T21	1		T1	13		T11	3
all_values[4]	auto[0]	auto[0]	auto[1]	8676428	1			T12	2		T13	3		T15	1
all_values[4]	auto[0]	auto[1]	auto[0]	903924	1			T11	1		T12	3		T13	14
all_values[4]	auto[0]	auto[1]	auto[1]	8652689	1			T11	6		T12	4		T13	7
all_values[4]	auto[1]	auto[0]	auto[1]	123625	1			T11	1		T13	1		T15	3
all_values[4]	auto[1]	auto[1]	auto[1]	123203	1			T11	1		T12	1		T13	3
all_values[5]	auto[0]	auto[0]	auto[0]	3192600	1			T21	1		T1	13		T11	2
all_values[5]	auto[0]	auto[0]	auto[1]	8689437	1			T12	1		T13	5		T14	1
all_values[5]	auto[0]	auto[1]	auto[0]	904329	1			T11	8		T12	6		T13	3
all_values[5]	auto[0]	auto[1]	auto[1]	8630414	1			T11	1		T12	1		T13	5
all_values[5]	auto[1]	auto[0]	auto[1]	124143	1			T12	1		T13	3		T102	1
all_values[5]	auto[1]	auto[1]	auto[1]	122548	1			T11	1		T13	1		T15	1
all_values[6]	auto[0]	auto[0]	auto[0]	3192326	1			T21	1		T1	2		T11	3
all_values[6]	auto[0]	auto[0]	auto[1]	8686240	1			T1	11		T11	7		T12	1
all_values[6]	auto[0]	auto[1]	auto[0]	901062	1			T11	1		T13	4		T17	1
all_values[6]	auto[0]	auto[1]	auto[1]	8637105	1			T13	2		T17	1		T73	5
all_values[6]	auto[1]	auto[0]	auto[1]	123879	1			T12	2		T13	3		T15	3
all_values[6]	auto[1]	auto[1]	auto[1]	122859	1			T11	1		T13	2		T73	3
all_values[7]	auto[0]	auto[0]	auto[0]	3194278	1			T21	1		T1	13		T11	5
all_values[7]	auto[0]	auto[0]	auto[1]	8638979	1			T11	1		T12	5		T13	2
all_values[7]	auto[0]	auto[1]	auto[0]	899046	1			T11	5		T12	1		T13	13
all_values[7]	auto[0]	auto[1]	auto[1]	8684378	1			T12	1		T13	2		T15	1
all_values[7]	auto[1]	auto[0]	auto[1]	123605	1			T12	1		T15	2		T73	2
all_values[7]	auto[1]	auto[1]	auto[1]	123185	1			T11	1		T12	1		T13	2
all_values[8]	auto[0]	auto[0]	auto[0]	3188188	1			T21	1		T1	2		T11	6
all_values[8]	auto[0]	auto[0]	auto[1]	8630201	1			T1	11		T13	12		T14	1
all_values[8]	auto[0]	auto[1]	auto[0]	906706	1			T11	6		T12	8		T13	4
all_values[8]	auto[0]	auto[1]	auto[1]	8691212	1			T13	2		T15	3		T17	1
all_values[8]	auto[1]	auto[0]	auto[1]	124004	1			T13	2		T73	2		T108	2
all_values[8]	auto[1]	auto[1]	auto[1]	123160	1			T13	1		T15	5		T73	1
all_values[9]	auto[0]	auto[0]	auto[0]	3190641	1			T21	1		T1	2		T11	7
all_values[9]	auto[0]	auto[0]	auto[1]	8673874	1			T1	11		T11	3		T12	2
all_values[9]	auto[0]	auto[1]	auto[0]	890309	1			T11	1		T13	7		T15	7
all_values[9]	auto[0]	auto[1]	auto[1]	8661985	1			T13	8		T15	2		T17	1
all_values[9]	auto[1]	auto[0]	auto[1]	123351	1			T12	1		T13	3		T15	1
all_values[9]	auto[1]	auto[1]	auto[1]	123311	1			T11	1		T13	4		T15	2
all_values[10]	auto[0]	auto[0]	auto[0]	3189825	1			T21	1		T1	2		T11	3
all_values[10]	auto[0]	auto[0]	auto[1]	8652885	1			T13	4		T14	1		T15	7
all_values[10]	auto[0]	auto[1]	auto[0]	908479	1			T11	5		T12	8		T13	4
all_values[10]	auto[0]	auto[1]	auto[1]	8666090	1			T1	11		T11	2		T12	1
all_values[10]	auto[1]	auto[0]	auto[1]	123053	1			T11	1		T13	3		T15	3
all_values[10]	auto[1]	auto[1]	auto[1]	123139	1			T11	1		T12	1		T13	3
all_values[11]	auto[0]	auto[0]	auto[0]	3174985	1			T21	1		T1	13		T11	7
all_values[11]	auto[0]	auto[0]	auto[1]	8683190	1			T12	4		T13	1		T73	5
all_values[11]	auto[0]	auto[1]	auto[0]	907551	1			T11	3		T13	18		T15	15
all_values[11]	auto[0]	auto[1]	auto[1]	8651082	1			T11	1		T12	2		T13	4
all_values[11]	auto[1]	auto[0]	auto[1]	123721	1			T11	1		T12	2		T73	1
all_values[11]	auto[1]	auto[1]	auto[1]	122942	1			T13	5		T73	3		T102	1
all_values[12]	auto[0]	auto[0]	auto[0]	3196543	1			T21	1		T1	2		T11	2
all_values[12]	auto[0]	auto[0]	auto[1]	8687524	1			T1	11		T13	7		T14	1
all_values[12]	auto[0]	auto[1]	auto[0]	900544	1			T11	10		T12	5		T13	2
all_values[12]	auto[0]	auto[1]	auto[1]	8632508	1			T13	7		T15	1		T19	1
all_values[12]	auto[1]	auto[0]	auto[1]	123860	1			T13	2		T15	2		T73	1
all_values[12]	auto[1]	auto[1]	auto[1]	122492	1			T13	2		T15	1		T73	2
all_values[13]	auto[0]	auto[0]	auto[0]	3187893	1			T21	1		T1	13		T11	6
all_values[13]	auto[0]	auto[0]	auto[1]	8720238	1			T13	6		T15	4		T18	1
all_values[13]	auto[0]	auto[1]	auto[0]	897428	1			T11	4		T12	2		T13	14
all_values[13]	auto[0]	auto[1]	auto[1]	8611323	1			T11	1		T12	1		T13	3
all_values[13]	auto[1]	auto[0]	auto[1]	124008	1			T13	1		T73	4		T102	4
all_values[13]	auto[1]	auto[1]	auto[1]	122581	1			T11	1		T12	2		T13	2
all_values[14]	auto[0]	auto[0]	auto[0]	3184939	1			T21	1		T1	2		T11	5
all_values[14]	auto[0]	auto[0]	auto[1]	8629292	1			T1	11		T11	2		T13	4
all_values[14]	auto[0]	auto[1]	auto[0]	909596	1			T11	2		T12	5		T13	7
all_values[14]	auto[0]	auto[1]	auto[1]	8692988	1			T11	1		T12	2		T13	2
all_values[14]	auto[1]	auto[0]	auto[1]	123534	1			T11	1		T13	1		T73	2
all_values[14]	auto[1]	auto[1]	auto[1]	123122	1			T11	1		T12	1		T13	4
all_values[15]	auto[0]	auto[0]	auto[0]	3179456	1			T21	1		T1	2		T11	2
all_values[15]	auto[0]	auto[0]	auto[1]	8659327	1			T12	2		T13	5		T14	1
all_values[15]	auto[0]	auto[1]	auto[0]	906983	1			T11	5		T12	2		T13	11
all_values[15]	auto[0]	auto[1]	auto[1]	8670773	1			T1	11		T11	3		T13	1
all_values[15]	auto[1]	auto[0]	auto[1]	123189	1			T12	1		T13	2		T15	2
all_values[15]	auto[1]	auto[1]	auto[1]	123743	1			T11	2		T13	1		T15	2
all_values[16]	auto[0]	auto[0]	auto[0]	3201052	1			T21	1		T1	13		T11	10
all_values[16]	auto[0]	auto[0]	auto[1]	8635771	1			T11	1		T13	2		T15	6
all_values[16]	auto[0]	auto[1]	auto[0]	905689	1			T12	3		T13	15		T15	6
all_values[16]	auto[0]	auto[1]	auto[1]	8674378	1			T13	2		T15	3		T73	1
all_values[16]	auto[1]	auto[0]	auto[1]	123114	1			T11	1		T13	1		T15	1
all_values[16]	auto[1]	auto[1]	auto[1]	123467	1			T13	3		T15	3		T102	1
all_values[17]	auto[0]	auto[0]	auto[0]	3200526	1			T21	1		T1	2		T11	2
all_values[17]	auto[0]	auto[0]	auto[1]	8689992	1			T13	7		T18	1		T73	11
all_values[17]	auto[0]	auto[1]	auto[0]	909189	1			T11	10		T12	7		T13	5
all_values[17]	auto[0]	auto[1]	auto[1]	8617395	1			T1	11		T13	3		T73	1
all_values[17]	auto[1]	auto[0]	auto[1]	123374	1			T13	5		T15	1		T73	1
all_values[17]	auto[1]	auto[1]	auto[1]	122995	1			T12	1		T73	1		T102	2
all_values[18]	auto[0]	auto[0]	auto[0]	3185336	1			T21	1		T1	2		T11	7
all_values[18]	auto[0]	auto[0]	auto[1]	8660961	1			T11	3		T12	2		T13	2
all_values[18]	auto[0]	auto[1]	auto[0]	905857	1			T1	11		T12	5		T13	7
all_values[18]	auto[0]	auto[1]	auto[1]	8664452	1			T13	4		T15	9		T17	1
all_values[18]	auto[1]	auto[0]	auto[1]	123853	1			T11	2		T12	1		T13	3
all_values[18]	auto[1]	auto[1]	auto[1]	123012	1			T13	1		T15	2		T73	1
all_values[19]	auto[0]	auto[0]	auto[0]	3190704	1			T21	1		T1	5		T11	2
all_values[19]	auto[0]	auto[0]	auto[1]	8637280	1			T1	8		T13	10		T15	2
all_values[19]	auto[0]	auto[1]	auto[0]	902760	1			T11	2		T12	6		T13	3
all_values[19]	auto[0]	auto[1]	auto[1]	8685887	1			T11	5		T12	2		T13	6
all_values[19]	auto[1]	auto[0]	auto[1]	123404	1			T13	2		T15	1		T73	1
all_values[19]	auto[1]	auto[1]	auto[1]	123436	1			T11	3		T12	2		T13	3
all_values[20]	auto[0]	auto[0]	auto[0]	3188561	1			T21	1		T1	2		T11	7
all_values[20]	auto[0]	auto[0]	auto[1]	8664040	1			T11	2		T13	2		T15	3
all_values[20]	auto[0]	auto[1]	auto[0]	901585	1			T11	1		T12	3		T13	15
all_values[20]	auto[0]	auto[1]	auto[1]	8662637	1			T1	11		T12	1		T13	4
all_values[20]	auto[1]	auto[0]	auto[1]	123883	1			T11	1		T12	1		T13	1
all_values[20]	auto[1]	auto[1]	auto[1]	122765	1			T11	1		T12	1		T13	1
all_values[21]	auto[0]	auto[0]	auto[0]	3177526	1			T21	1		T1	2		T11	4
all_values[21]	auto[0]	auto[0]	auto[1]	8676707	1			T11	7		T12	1		T13	3
all_values[21]	auto[0]	auto[1]	auto[0]	892239	1			T12	3		T13	12		T15	7
all_values[21]	auto[0]	auto[1]	auto[1]	8670399	1			T1	11		T12	4		T13	2
all_values[21]	auto[1]	auto[0]	auto[1]	123677	1			T11	1		T12	1		T13	1
all_values[21]	auto[1]	auto[1]	auto[1]	122923	1			T13	2		T15	1		T73	2
all_values[22]	auto[0]	auto[0]	auto[0]	3185573	1			T21	1		T1	2		T11	2
all_values[22]	auto[0]	auto[0]	auto[1]	8652769	1			T12	3		T13	5		T14	1
all_values[22]	auto[0]	auto[1]	auto[0]	906879	1			T1	11		T11	10		T12	1
all_values[22]	auto[0]	auto[1]	auto[1]	8671949	1			T12	3		T13	6		T15	5
all_values[22]	auto[1]	auto[0]	auto[1]	123741	1			T12	1		T13	1		T73	2
all_values[22]	auto[1]	auto[1]	auto[1]	122560	1			T12	1		T13	2		T15	4
all_values[23]	auto[0]	auto[0]	auto[0]	3190215	1			T21	1		T1	2		T11	4
all_values[23]	auto[0]	auto[0]	auto[1]	8642617	1			T12	2		T13	2		T14	1
all_values[23]	auto[0]	auto[1]	auto[0]	900232	1			T11	8		T12	5		T13	9
all_values[23]	auto[0]	auto[1]	auto[1]	8683669	1			T1	11		T12	2		T13	6
all_values[23]	auto[1]	auto[0]	auto[1]	123420	1			T13	2		T15	3		T73	2
all_values[23]	auto[1]	auto[1]	auto[1]	123318	1			T12	1		T13	2		T15	1
all_values[24]	auto[0]	auto[0]	auto[0]	3176374	1			T21	1		T1	2		T11	2
all_values[24]	auto[0]	auto[0]	auto[1]	8671034	1			T12	2		T13	2		T15	6
all_values[24]	auto[0]	auto[1]	auto[0]	902522	1			T11	10		T12	5		T13	14
all_values[24]	auto[0]	auto[1]	auto[1]	8666841	1			T1	11		T13	6		T15	2
all_values[24]	auto[1]	auto[0]	auto[1]	123276	1			T12	1		T13	1		T15	5
all_values[24]	auto[1]	auto[1]	auto[1]	123424	1			T13	4		T73	2		T102	2
all_values[25]	auto[0]	auto[0]	auto[0]	3193508	1			T21	1		T1	2		T11	3
all_values[25]	auto[0]	auto[0]	auto[1]	8654710	1			T1	11		T13	1		T14	1
all_values[25]	auto[0]	auto[1]	auto[0]	905946	1			T11	6		T12	2		T13	17
all_values[25]	auto[0]	auto[1]	auto[1]	8662929	1			T11	1		T12	2		T15	3
all_values[25]	auto[1]	auto[0]	auto[1]	123382	1			T11	1		T13	1		T73	1
all_values[25]	auto[1]	auto[1]	auto[1]	122996	1			T11	1		T12	1		T13	3
all_values[26]	auto[0]	auto[0]	auto[0]	3188585	1			T21	1		T1	2		T11	4
all_values[26]	auto[0]	auto[0]	auto[1]	8676174	1			T11	1		T13	1		T14	1
all_values[26]	auto[0]	auto[1]	auto[0]	901530	1			T11	3		T12	3		T13	14
all_values[26]	auto[0]	auto[1]	auto[1]	8650102	1			T1	11		T11	3		T13	2
all_values[26]	auto[1]	auto[0]	auto[1]	123959	1			T11	1		T12	1		T13	2
all_values[26]	auto[1]	auto[1]	auto[1]	123121	1			T13	4		T15	3		T73	2
all_values[27]	auto[0]	auto[0]	auto[0]	3189879	1			T21	1		T1	13		T11	4
all_values[27]	auto[0]	auto[0]	auto[1]	8653536	1			T11	1		T12	2		T14	1
all_values[27]	auto[0]	auto[1]	auto[0]	901277	1			T11	3		T12	2		T13	10
all_values[27]	auto[0]	auto[1]	auto[1]	8672260	1			T11	3		T12	2		T13	8
all_values[27]	auto[1]	auto[0]	auto[1]	123742	1			T11	1		T12	1		T13	1
all_values[27]	auto[1]	auto[1]	auto[1]	122777	1			T12	1		T13	1		T15	1
all_values[28]	auto[0]	auto[0]	auto[0]	3182064	1			T21	1		T1	13		T11	3
all_values[28]	auto[0]	auto[0]	auto[1]	8696809	1			T11	7		T12	3		T15	1
all_values[28]	auto[0]	auto[1]	auto[0]	903040	1			T11	1		T12	1		T13	9
all_values[28]	auto[0]	auto[1]	auto[1]	8635501	1			T12	4		T13	2		T15	1
all_values[28]	auto[1]	auto[0]	auto[1]	122635	1			T12	1		T13	2		T15	1
all_values[28]	auto[1]	auto[1]	auto[1]	123422	1			T11	1		T13	1		T15	1
all_values[29]	auto[0]	auto[0]	auto[0]	3185952	1			T21	1		T1	2		T11	6
all_values[29]	auto[0]	auto[0]	auto[1]	8704624	1			T1	11		T11	1		T13	3
all_values[29]	auto[0]	auto[1]	auto[0]	896628	1			T11	4		T12	8		T13	6
all_values[29]	auto[0]	auto[1]	auto[1]	8629839	1			T13	3		T17	1		T73	4
all_values[29]	auto[1]	auto[0]	auto[1]	123863	1			T11	1		T13	1		T15	2
all_values[29]	auto[1]	auto[1]	auto[1]	122565	1			T13	1		T15	1		T73	3
all_values[30]	auto[0]	auto[0]	auto[0]	3192907	1			T21	1		T1	2		T11	6
all_values[30]	auto[0]	auto[0]	auto[1]	8666023	1			T13	10		T15	2		T73	1
all_values[30]	auto[0]	auto[1]	auto[0]	905734	1			T11	6		T12	2		T13	4
all_values[30]	auto[0]	auto[1]	auto[1]	8652517	1			T1	11		T13	2		T15	4
all_values[30]	auto[1]	auto[0]	auto[1]	123814	1			T13	5		T15	1		T102	1
all_values[30]	auto[1]	auto[1]	auto[1]	122476	1			T15	1		T73	2		T102	1
all_values[31]	auto[0]	auto[0]	auto[0]	3180102	1			T21	1		T1	2		T11	5
all_values[31]	auto[0]	auto[0]	auto[1]	8641245	1			T11	3		T13	5		T15	1
all_values[31]	auto[0]	auto[1]	auto[0]	902093	1			T11	1		T12	7		T13	10
all_values[31]	auto[0]	auto[1]	auto[1]	8692912	1			T1	11		T12	2		T13	7
all_values[31]	auto[1]	auto[0]	auto[1]	123877	1			T11	2		T13	2		T15	1
all_values[31]	auto[1]	auto[1]	auto[1]	123242	1			T11	1		T12	1		T13	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal