Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[1]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[2]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[3]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[4]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[5]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[6]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[7]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[8]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[9]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[10]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[11]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[12]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[13]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[14]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[15]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[16]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[17]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[18]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[19]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[20]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[21]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[22]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[23]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[24]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[25]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[26]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[27]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[28]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[29]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[30]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[31]	21378587	1			T21	1		T1	13		T11	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

423699859

1

T21

32

T1

416

T11

32

auto[1]

260414925

1

T42

6288

T43

4821

T44

6515

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

543728779

1

T21

32

T1

416

T11

32

auto[1]

140386005

1

T42

11427

T43

4951

T44

11609

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

502271597

1

T21

32

T1

416

T11

32

auto[1]

181843187

1

T42

11261

T43

4902

T44

11621

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	8042830	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	5448810	1			T42	13		T43	77		T44	25
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	2210740	1			T42	181		T43	68		T44	168
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2990759	1			T42	200		T43	74		T44	199
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	497764	1			T53	180		T59	122		T114	95
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	2187684	1			T42	152		T43	73		T44	184
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	8024164	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	5462852	1			T42	20		T43	72		T44	25
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	2206287	1			T42	172		T43	87		T44	189
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2993395	1			T42	198		T43	74		T44	188
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	499975	1			T53	138		T59	161		T114	72
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	2191914	1			T42	189		T43	82		T44	196
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	8035500	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	5449682	1			T42	19		T43	79		T44	26
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	2210923	1			T42	174		T43	76		T44	165
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2991824	1			T42	192		T43	75		T44	208
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	495785	1			T53	155		T59	147		T114	94
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	2194873	1			T42	187		T43	80		T44	196
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	8039385	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	5445182	1			T42	18		T43	78		T44	26
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	2202384	1			T42	173		T43	84		T44	212
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	3000824	1			T42	168		T43	94		T44	150
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	503651	1			T53	149		T59	127		T114	82
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	2187161	1			T42	172		T43	41		T44	185
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	8039546	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	5448901	1			T42	26		T43	73		T44	24
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	2209647	1			T42	170		T43	47		T44	170
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2992361	1			T42	157		T43	114		T44	176
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	497754	1			T53	188		T59	131		T114	67
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	2190378	1			T42	150		T43	70		T44	195
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	8027454	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	5461687	1			T42	16		T43	57		T44	26
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	2201977	1			T42	191		T43	92		T44	142
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	3003745	1			T42	186		T43	63		T44	217
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	495889	1			T53	164		T59	132		T114	126
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	2187835	1			T42	158		T43	68		T44	194
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	8025202	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	5462052	1			T42	17		T43	69		T44	24
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	2210894	1			T42	169		T43	76		T44	188
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2990137	1			T42	192		T43	75		T44	182
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	499102	1			T53	145		T59	127		T114	94
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	2191200	1			T42	168		T43	72		T44	217
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	8051057	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	5442750	1			T42	20		T43	79		T44	20
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	2211605	1			T42	192		T43	66		T44	152
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2991732	1			T42	167		T43	53		T44	192
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	498281	1			T53	162		T59	146		T114	74
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	2183162	1			T42	176		T43	114		T44	200
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	8034345	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	5450935	1			T42	18		T43	75		T44	22
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	2211195	1			T42	180		T43	84		T44	146
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2996144	1			T42	182		T43	59		T44	216
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	498837	1			T53	173		T59	154		T114	106
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	2187131	1			T42	165		T43	92		T44	195
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	8027434	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	5456844	1			T42	20		T43	70		T44	23
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	2202803	1			T42	160		T43	78		T44	207
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2999210	1			T42	207		T43	77		T44	162
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	497378	1			T53	164		T59	139		T114	80
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	2194918	1			T42	180		T43	90		T44	182
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	8031367	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	5458309	1			T42	19		T43	70		T44	26
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	2209696	1			T42	187		T43	75		T44	156
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2988409	1			T42	154		T43	58		T44	216
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	499633	1			T53	134		T59	160		T114	84
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	2191173	1			T42	174		T43	90		T44	176
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	8029267	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	5465886	1			T42	19		T43	70		T44	23
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	2211048	1			T42	208		T43	76		T44	196
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2992024	1			T42	172		T43	71		T44	190
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	495798	1			T53	170		T59	118		T114	84
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	2184564	1			T42	188		T43	76		T44	169
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	8034424	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	5459031	1			T42	18		T43	77		T44	23
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	2207854	1			T42	196		T43	83		T44	181
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2993952	1			T42	167		T43	66		T44	204
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	498977	1			T53	138		T59	153		T114	96
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	2184349	1			T42	184		T43	82		T44	188
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	8035154	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	5444489	1			T42	19		T43	74		T44	24
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	2209368	1			T42	224		T43	70		T44	196
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	3000781	1			T42	159		T43	77		T44	160
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	500836	1			T53	144		T59	133		T114	100
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	2187959	1			T42	148		T43	90		T44	184
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	8028967	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	5444497	1			T42	24		T43	73		T44	26
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	2205245	1			T42	150		T43	62		T44	192
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	3004759	1			T42	138		T43	86		T44	150
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	500739	1			T53	180		T59	128		T114	68
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	2194380	1			T42	206		T43	66		T44	169
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	8032669	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	5452880	1			T42	16		T43	82		T44	29
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	2213057	1			T42	206		T43	72		T44	176
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2993681	1			T42	169		T43	82		T44	176
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	498792	1			T53	160		T59	120		T114	93
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	2187508	1			T42	174		T43	77		T44	184
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	8037293	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	5458820	1			T42	22		T43	77		T44	22
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	2198292	1			T42	156		T43	67		T44	199
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	3004564	1			T42	191		T43	70		T44	194
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	500361	1			T53	146		T59	127		T114	81
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	2179257	1			T42	192		T43	98		T44	138
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	8052773	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	5451642	1			T42	16		T43	65		T44	29
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	2199862	1			T42	148		T43	72		T44	206
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2998897	1			T42	206		T43	86		T44	149
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	498227	1			T53	140		T59	134		T114	104
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	2177186	1			T42	221		T43	73		T44	178
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	8044264	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	5457541	1			T42	23		T43	75		T44	20
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	2202736	1			T42	142		T43	87		T44	174
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2998897	1			T42	168		T43	70		T44	165
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	496898	1			T53	147		T59	136		T114	78
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	2178251	1			T42	203		T43	78		T44	138
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	8038772	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	5460789	1			T42	25		T43	72		T44	19
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	2195495	1			T42	212		T43	62		T44	179
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	3004757	1			T42	174		T43	69		T44	214
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	499960	1			T53	170		T59	178		T114	98
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	2178814	1			T42	157		T43	90		T44	174
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	8041186	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	5456449	1			T42	20		T43	68		T44	25
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	2187722	1			T42	179		T43	92		T44	179
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	3009572	1			T42	154		T43	68		T44	182
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	503384	1			T53	132		T59	138		T114	106
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	2180274	1			T42	178		T43	44		T44	190
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	8039633	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	5455103	1			T42	22		T43	65		T44	29
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	2197567	1			T42	159		T43	74		T44	190
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	3005024	1			T42	186		T43	89		T44	185
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	497831	1			T53	160		T59	129		T114	82
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	2183429	1			T42	182		T43	74		T44	174
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	8037126	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	5459682	1			T42	18		T43	69		T44	23
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	2200849	1			T42	176		T43	91		T44	188
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2998826	1			T42	199		T43	58		T44	184
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	498331	1			T53	182		T59	104		T114	104
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	2183773	1			T42	136		T43	66		T44	192
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	8038157	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	5461676	1			T42	18		T43	76		T44	25
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	2199951	1			T42	176		T43	68		T44	206
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	3005248	1			T42	167		T43	70		T44	169
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	498035	1			T53	140		T59	142		T114	77
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	2175520	1			T42	172		T43	77		T44	202
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	8047715	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	5451176	1			T42	22		T43	71		T44	22
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	2194799	1			T42	166		T43	83		T44	198
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	3008389	1			T42	180		T43	54		T44	186
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	500002	1			T53	130		T59	108		T114	110
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	2176506	1			T42	175		T43	86		T44	186
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	8041875	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	5455695	1			T42	19		T43	71		T44	17
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	2199809	1			T42	198		T43	73		T44	201
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2997931	1			T42	152		T43	84		T44	172
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	500494	1			T53	142		T59	136		T114	86
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	2182783	1			T42	211		T43	76		T44	144
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	8051120	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	5449200	1			T42	21		T43	74		T44	23
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	2199463	1			T42	196		T43	66		T44	224
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	3006128	1			T42	148		T43	78		T44	182
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	499870	1			T53	190		T59	140		T114	95
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	2172806	1			T42	180		T43	66		T44	157
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	8047084	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	5447813	1			T42	17		T43	75		T44	23
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	2198282	1			T42	186		T43	72		T44	176
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	3004278	1			T42	198		T43	98		T44	168
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	498527	1			T53	145		T59	128		T114	94
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	2182603	1			T42	166		T43	81		T44	172
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	8028733	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	5470959	1			T42	20		T43	64		T44	22
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	2203479	1			T42	176		T43	74		T44	150
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2998792	1			T42	162		T43	77		T44	230
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	500112	1			T53	160		T59	124		T114	64
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	2176512	1			T42	161		T43	102		T44	174
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	8043040	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	5453046	1			T42	19		T43	63		T44	29
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	2200752	1			T42	191		T43	78		T44	194
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	3005994	1			T42	142		T43	73		T44	176
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	499698	1			T53	168		T59	147		T114	102
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	2176057	1			T42	238		T43	78		T44	187
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	8042888	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	5463063	1			T42	14		T43	69		T44	27
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	2190974	1			T42	191		T43	66		T44	204
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	3009955	1			T42	158		T43	90		T44	163
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	497119	1			T53	131		T59	122		T114	86
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	2174588	1			T42	158		T43	86		T44	168
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	8038530	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	5454136	1			T42	16		T43	70		T44	28
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	2196311	1			T42	168		T43	108		T44	165
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	3008850	1			T42	194		T43	48		T44	176
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	500369	1			T53	165		T59	106		T114	79
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	2180391	1			T42	173		T43	84		T44	152

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal