Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[1]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[2]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[3]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[4]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[5]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[6]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[7]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[8]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[9]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[10]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[11]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[12]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[13]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[14]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[15]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[16]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[17]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[18]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[19]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[20]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[21]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[22]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[23]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[24]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[25]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[26]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[27]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[28]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[29]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[30]	21378587	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[31]	21378587	1			T21	1		T1	13		T11	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

423699859

1

T21

32

T1

416

T11

32

auto[1]

260414925

1

T42

6288

T43

4821

T44

6515

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

423690352

1

T21

32

T1

345

T11

32

auto[1]

260424432

1

T1

71

T14

7

T17

15

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	12852195	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	391833	1			T42	44		T43	14		T44	47
bins_for_gpio_bits[0]	auto[1]	auto[0]	392134	1			T17	1		T19	1		T22	4
bins_for_gpio_bits[0]	auto[1]	auto[1]	7742425	1			T42	121		T43	136		T44	162
bins_for_gpio_bits[1]	auto[0]	auto[0]	12831887	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	391667	1			T42	44		T43	23		T44	43
bins_for_gpio_bits[1]	auto[1]	auto[0]	391959	1			T18	1		T22	1		T51	2
bins_for_gpio_bits[1]	auto[1]	auto[1]	7763074	1			T42	165		T43	131		T44	178
bins_for_gpio_bits[2]	auto[0]	auto[0]	12845609	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	392396	1			T42	44		T43	19		T44	48
bins_for_gpio_bits[2]	auto[1]	auto[0]	392638	1			T22	4		T51	3		T23	6
bins_for_gpio_bits[2]	auto[1]	auto[1]	7747944	1			T42	162		T43	140		T44	174
bins_for_gpio_bits[3]	auto[0]	auto[0]	12851355	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	390954	1			T42	41		T43	12		T44	42
bins_for_gpio_bits[3]	auto[1]	auto[0]	391238	1			T17	1		T22	2		T51	2
bins_for_gpio_bits[3]	auto[1]	auto[1]	7745040	1			T42	149		T43	107		T44	169
bins_for_gpio_bits[4]	auto[0]	auto[0]	12849637	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	391598	1			T42	36		T43	16		T44	46
bins_for_gpio_bits[4]	auto[1]	auto[0]	391917	1			T22	1		T51	1		T23	9
bins_for_gpio_bits[4]	auto[1]	auto[1]	7745435	1			T42	140		T43	127		T44	173
bins_for_gpio_bits[5]	auto[0]	auto[0]	12841500	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	391395	1			T42	43		T43	23		T44	42
bins_for_gpio_bits[5]	auto[1]	auto[0]	391676	1			T14	1		T22	3		T51	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	7754016	1			T42	131		T43	102		T44	178
bins_for_gpio_bits[6]	auto[0]	auto[0]	12834065	1			T21	1		T1	7		T11	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	391843	1			T42	43		T43	17		T44	48
bins_for_gpio_bits[6]	auto[1]	auto[0]	392168	1			T1	6		T17	1		T22	2
bins_for_gpio_bits[6]	auto[1]	auto[1]	7760511	1			T42	142		T43	124		T44	193
bins_for_gpio_bits[7]	auto[0]	auto[0]	12862726	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	391383	1			T42	45		T43	22		T44	45
bins_for_gpio_bits[7]	auto[1]	auto[0]	391668	1			T14	1		T22	5		T23	6
bins_for_gpio_bits[7]	auto[1]	auto[1]	7732810	1			T42	151		T43	171		T44	175
bins_for_gpio_bits[8]	auto[0]	auto[0]	12849900	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	391477	1			T42	49		T43	16		T44	51
bins_for_gpio_bits[8]	auto[1]	auto[0]	391784	1			T17	1		T18	1		T19	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	7745426	1			T42	134		T43	151		T44	166
bins_for_gpio_bits[9]	auto[0]	auto[0]	12836603	1			T21	1		T1	9		T11	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	392516	1			T42	45		T43	20		T44	46
bins_for_gpio_bits[9]	auto[1]	auto[0]	392844	1			T1	4		T14	1		T17	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	7756624	1			T42	155		T43	140		T44	159
bins_for_gpio_bits[10]	auto[0]	auto[0]	12837595	1			T21	1		T1	6		T11	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	391606	1			T42	44		T43	20		T44	46
bins_for_gpio_bits[10]	auto[1]	auto[0]	391877	1			T1	7		T14	1		T17	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	7757509	1			T42	149		T43	140		T44	156
bins_for_gpio_bits[11]	auto[0]	auto[0]	12840275	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	391766	1			T42	46		T43	24		T44	42
bins_for_gpio_bits[11]	auto[1]	auto[0]	392064	1			T17	1		T22	1		T23	5
bins_for_gpio_bits[11]	auto[1]	auto[1]	7754482	1			T42	161		T43	122		T44	150
bins_for_gpio_bits[12]	auto[0]	auto[0]	12844069	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	391868	1			T42	45		T43	18		T44	44
bins_for_gpio_bits[12]	auto[1]	auto[0]	392161	1			T14	1		T17	1		T19	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	7750489	1			T42	157		T43	141		T44	167
bins_for_gpio_bits[13]	auto[0]	auto[0]	12852519	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	392491	1			T42	39		T43	20		T44	50
bins_for_gpio_bits[13]	auto[1]	auto[0]	392784	1			T18	1		T22	5		T51	2
bins_for_gpio_bits[13]	auto[1]	auto[1]	7740793	1			T42	128		T43	144		T44	158
bins_for_gpio_bits[14]	auto[0]	auto[0]	12846075	1			T21	1		T1	9		T11	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	392570	1			T42	44		T43	17		T44	45
bins_for_gpio_bits[14]	auto[1]	auto[0]	392896	1			T1	4		T22	5		T51	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	7747046	1			T42	186		T43	122		T44	150
bins_for_gpio_bits[15]	auto[0]	auto[0]	12848075	1			T21	1		T1	9		T11	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	391054	1			T42	41		T43	17		T44	45
bins_for_gpio_bits[15]	auto[1]	auto[0]	391332	1			T1	4		T17	1		T22	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	7748126	1			T42	149		T43	142		T44	168
bins_for_gpio_bits[16]	auto[0]	auto[0]	12847648	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	392175	1			T42	48		T43	21		T44	47
bins_for_gpio_bits[16]	auto[1]	auto[0]	392501	1			T19	1		T22	3		T51	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	7746263	1			T42	166		T43	154		T44	113
bins_for_gpio_bits[17]	auto[0]	auto[0]	12859785	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	391472	1			T42	52		T43	16		T44	43
bins_for_gpio_bits[17]	auto[1]	auto[0]	391747	1			T18	1		T19	1		T51	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	7735583	1			T42	185		T43	122		T44	164
bins_for_gpio_bits[18]	auto[0]	auto[0]	12853967	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	391659	1			T42	39		T43	20		T44	37
bins_for_gpio_bits[18]	auto[1]	auto[0]	391930	1			T23	10		T100	3		T24	2
bins_for_gpio_bits[18]	auto[1]	auto[1]	7741031	1			T42	187		T43	133		T44	121
bins_for_gpio_bits[19]	auto[0]	auto[0]	12847144	1			T21	1		T1	8		T11	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	391543	1			T42	43		T43	20		T44	46
bins_for_gpio_bits[19]	auto[1]	auto[0]	391880	1			T1	5		T14	1		T17	2
bins_for_gpio_bits[19]	auto[1]	auto[1]	7748020	1			T42	139		T43	142		T44	147
bins_for_gpio_bits[20]	auto[0]	auto[0]	12846825	1			T21	1		T1	6		T11	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	391327	1			T42	45		T43	13		T44	47
bins_for_gpio_bits[20]	auto[1]	auto[0]	391655	1			T1	7		T19	1		T22	2
bins_for_gpio_bits[20]	auto[1]	auto[1]	7748780	1			T42	153		T43	99		T44	168
bins_for_gpio_bits[21]	auto[0]	auto[0]	12849910	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	391997	1			T42	43		T43	21		T44	44
bins_for_gpio_bits[21]	auto[1]	auto[0]	392314	1			T19	1		T22	2		T51	4
bins_for_gpio_bits[21]	auto[1]	auto[1]	7744366	1			T42	161		T43	118		T44	159
bins_for_gpio_bits[22]	auto[0]	auto[0]	12844270	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	392217	1			T42	39		T43	17		T44	44
bins_for_gpio_bits[22]	auto[1]	auto[0]	392531	1			T17	1		T22	3		T23	12
bins_for_gpio_bits[22]	auto[1]	auto[1]	7749569	1			T42	115		T43	118		T44	171
bins_for_gpio_bits[23]	auto[0]	auto[0]	12851733	1			T21	1		T1	8		T11	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	391326	1			T42	42		T43	18		T44	49
bins_for_gpio_bits[23]	auto[1]	auto[0]	391623	1			T1	5		T22	2		T51	3
bins_for_gpio_bits[23]	auto[1]	auto[1]	7743905	1			T42	148		T43	135		T44	178
bins_for_gpio_bits[24]	auto[0]	auto[0]	12859437	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	391198	1			T42	47		T43	25		T44	53
bins_for_gpio_bits[24]	auto[1]	auto[0]	391466	1			T17	2		T19	1		T22	3
bins_for_gpio_bits[24]	auto[1]	auto[1]	7736486	1			T42	150		T43	132		T44	155
bins_for_gpio_bits[25]	auto[0]	auto[0]	12847793	1			T21	1		T1	8		T11	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	391515	1			T42	49		T43	20		T44	36
bins_for_gpio_bits[25]	auto[1]	auto[0]	391822	1			T1	5		T17	1		T18	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	7747457	1			T42	181		T43	127		T44	125
bins_for_gpio_bits[26]	auto[0]	auto[0]	12865669	1			T21	1		T1	8		T11	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	390762	1			T42	44		T43	17		T44	44
bins_for_gpio_bits[26]	auto[1]	auto[0]	391042	1			T1	5		T19	1		T22	2
bins_for_gpio_bits[26]	auto[1]	auto[1]	7731114	1			T42	157		T43	123		T44	136
bins_for_gpio_bits[27]	auto[0]	auto[0]	12857406	1			T21	1		T1	8		T11	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	391923	1			T42	49		T43	22		T44	45
bins_for_gpio_bits[27]	auto[1]	auto[0]	392238	1			T1	5		T14	1		T22	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	7737020	1			T42	134		T43	134		T44	150
bins_for_gpio_bits[28]	auto[0]	auto[0]	12839350	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	391350	1			T42	40		T43	25		T44	45
bins_for_gpio_bits[28]	auto[1]	auto[0]	391654	1			T22	2		T51	1		T23	6
bins_for_gpio_bits[28]	auto[1]	auto[1]	7756233	1			T42	141		T43	141		T44	151
bins_for_gpio_bits[29]	auto[0]	auto[0]	12858595	1			T21	1		T1	7		T11	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	390895	1			T42	45		T43	16		T44	41
bins_for_gpio_bits[29]	auto[1]	auto[0]	391191	1			T1	6		T19	1		T22	4
bins_for_gpio_bits[29]	auto[1]	auto[1]	7737906	1			T42	212		T43	125		T44	175
bins_for_gpio_bits[30]	auto[0]	auto[0]	12852595	1			T21	1		T1	5		T11	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	390943	1			T42	41		T43	22		T44	42
bins_for_gpio_bits[30]	auto[1]	auto[0]	391222	1			T1	8		T18	1		T22	7
bins_for_gpio_bits[30]	auto[1]	auto[1]	7743827	1			T42	131		T43	133		T44	153
bins_for_gpio_bits[31]	auto[0]	auto[0]	12851877	1			T21	1		T1	13		T11	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	391544	1			T42	47		T43	18		T44	42
bins_for_gpio_bits[31]	auto[1]	auto[0]	391814	1			T18	1		T19	1		T23	12
bins_for_gpio_bits[31]	auto[1]	auto[1]	7743352	1			T42	142		T43	136		T44	138