Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11958648 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
10 |
| auto[1] |
9704823 |
1 |
|
|
T1 |
11 |
|
T11 |
2 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20416335 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1247136 |
1 |
|
|
T51 |
1 |
|
T5 |
1 |
|
T9 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11989995 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9673476 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4203641 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
2 |
| auto[1] |
auto[0] |
auto[1] |
621362 |
1 |
|
|
T51 |
1 |
|
T9 |
2 |
|
T104 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4222699 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
1 |
| auto[1] |
auto[1] |
auto[1] |
625774 |
1 |
|
|
T5 |
1 |
|
T52 |
7371 |
|
T105 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11931648 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
8 |
| auto[1] |
9731823 |
1 |
|
|
T11 |
4 |
|
T12 |
3 |
|
T13 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20420079 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1243392 |
1 |
|
|
T75 |
1 |
|
T5 |
3 |
|
T115 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12019551 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9643920 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4172449 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T17 |
1 |
| auto[1] |
auto[0] |
auto[1] |
614905 |
1 |
|
|
T5 |
1 |
|
T115 |
1 |
|
T104 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4228079 |
1 |
|
|
T22 |
1 |
|
T23 |
4 |
|
T75 |
4 |
| auto[1] |
auto[1] |
auto[1] |
628487 |
1 |
|
|
T75 |
1 |
|
T5 |
2 |
|
T77 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11965763 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
4 |
| auto[1] |
9697708 |
1 |
|
|
T1 |
11 |
|
T11 |
8 |
|
T12 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20415126 |
1 |
|
|
T21 |
1 |
|
T1 |
10 |
|
T11 |
12 |
| auto[1] |
1248345 |
1 |
|
|
T1 |
3 |
|
T9 |
3 |
|
T77 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11989495 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9673976 |
1 |
|
|
T1 |
11 |
|
T19 |
1 |
|
T22 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4204417 |
1 |
|
|
T19 |
1 |
|
T22 |
1 |
|
T51 |
1 |
| auto[1] |
auto[0] |
auto[1] |
621785 |
1 |
|
|
T104 |
4 |
|
T52 |
7850 |
|
T105 |
9 |
| auto[1] |
auto[1] |
auto[0] |
4221214 |
1 |
|
|
T1 |
8 |
|
T22 |
1 |
|
T51 |
3 |
| auto[1] |
auto[1] |
auto[1] |
626560 |
1 |
|
|
T1 |
3 |
|
T9 |
3 |
|
T77 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11981896 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
8 |
| auto[1] |
9681575 |
1 |
|
|
T11 |
4 |
|
T12 |
2 |
|
T13 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20419703 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1243768 |
1 |
|
|
T5 |
2 |
|
T115 |
1 |
|
T104 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12011987 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9651484 |
1 |
|
|
T1 |
11 |
|
T17 |
1 |
|
T22 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4209022 |
1 |
|
|
T1 |
11 |
|
T22 |
1 |
|
T23 |
6 |
| auto[1] |
auto[0] |
auto[1] |
621705 |
1 |
|
|
T5 |
2 |
|
T115 |
1 |
|
T104 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4198694 |
1 |
|
|
T17 |
1 |
|
T22 |
2 |
|
T51 |
2 |
| auto[1] |
auto[1] |
auto[1] |
622063 |
1 |
|
|
T52 |
8023 |
|
T105 |
6 |
|
T109 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12007927 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
2 |
| auto[1] |
9655544 |
1 |
|
|
T11 |
10 |
|
T12 |
5 |
|
T13 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20417183 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1246288 |
1 |
|
|
T75 |
1 |
|
T52 |
15686 |
|
T105 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12016047 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9647424 |
1 |
|
|
T19 |
1 |
|
T22 |
2 |
|
T51 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4221977 |
1 |
|
|
T22 |
1 |
|
T23 |
11 |
|
T75 |
4 |
| auto[1] |
auto[0] |
auto[1] |
626924 |
1 |
|
|
T75 |
1 |
|
T52 |
7763 |
|
T105 |
4 |
| auto[1] |
auto[1] |
auto[0] |
4179159 |
1 |
|
|
T19 |
1 |
|
T22 |
1 |
|
T51 |
1 |
| auto[1] |
auto[1] |
auto[1] |
619364 |
1 |
|
|
T52 |
7923 |
|
T105 |
5 |
|
T109 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12032139 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
6 |
| auto[1] |
9631332 |
1 |
|
|
T11 |
6 |
|
T12 |
5 |
|
T13 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20417604 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1245867 |
1 |
|
|
T51 |
1 |
|
T9 |
3 |
|
T77 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12002741 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9660730 |
1 |
|
|
T1 |
11 |
|
T19 |
1 |
|
T22 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4211651 |
1 |
|
|
T1 |
11 |
|
T22 |
1 |
|
T23 |
4 |
| auto[1] |
auto[0] |
auto[1] |
623060 |
1 |
|
|
T104 |
2 |
|
T52 |
8144 |
|
T105 |
6 |
| auto[1] |
auto[1] |
auto[0] |
4203212 |
1 |
|
|
T19 |
1 |
|
T22 |
2 |
|
T51 |
4 |
| auto[1] |
auto[1] |
auto[1] |
622807 |
1 |
|
|
T51 |
1 |
|
T9 |
3 |
|
T77 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11937765 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
8 |
| auto[1] |
9725706 |
1 |
|
|
T11 |
4 |
|
T12 |
8 |
|
T13 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20414851 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1248620 |
1 |
|
|
T51 |
1 |
|
T5 |
3 |
|
T9 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11986629 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9676842 |
1 |
|
|
T19 |
1 |
|
T22 |
2 |
|
T51 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4177755 |
1 |
|
|
T19 |
1 |
|
T22 |
2 |
|
T51 |
1 |
| auto[1] |
auto[0] |
auto[1] |
618204 |
1 |
|
|
T5 |
3 |
|
T9 |
7 |
|
T79 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4250467 |
1 |
|
|
T51 |
1 |
|
T23 |
6 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[1] |
630416 |
1 |
|
|
T51 |
1 |
|
T104 |
1 |
|
T52 |
8295 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11961972 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
2 |
| auto[1] |
9701499 |
1 |
|
|
T1 |
11 |
|
T11 |
10 |
|
T12 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20420641 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1242830 |
1 |
|
|
T104 |
2 |
|
T52 |
16113 |
|
T105 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12022629 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9640842 |
1 |
|
|
T17 |
1 |
|
T51 |
3 |
|
T23 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4189023 |
1 |
|
|
T17 |
1 |
|
T23 |
10 |
|
T111 |
1 |
| auto[1] |
auto[0] |
auto[1] |
619752 |
1 |
|
|
T104 |
1 |
|
T52 |
8715 |
|
T105 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4208989 |
1 |
|
|
T51 |
3 |
|
T23 |
2 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[1] |
623078 |
1 |
|
|
T104 |
1 |
|
T52 |
7398 |
|
T105 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11959937 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9703534 |
1 |
|
|
T12 |
3 |
|
T13 |
20 |
|
T15 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20417637 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1245834 |
1 |
|
|
T51 |
1 |
|
T77 |
1 |
|
T52 |
15138 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12022837 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9640634 |
1 |
|
|
T1 |
11 |
|
T17 |
1 |
|
T22 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4193653 |
1 |
|
|
T1 |
11 |
|
T17 |
1 |
|
T22 |
1 |
| auto[1] |
auto[0] |
auto[1] |
623768 |
1 |
|
|
T77 |
1 |
|
T52 |
7310 |
|
T105 |
4 |
| auto[1] |
auto[1] |
auto[0] |
4201147 |
1 |
|
|
T22 |
2 |
|
T51 |
1 |
|
T23 |
3 |
| auto[1] |
auto[1] |
auto[1] |
622066 |
1 |
|
|
T51 |
1 |
|
T52 |
7828 |
|
T105 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12013892 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
2 |
| auto[1] |
9649579 |
1 |
|
|
T1 |
11 |
|
T11 |
10 |
|
T12 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20412699 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1250772 |
1 |
|
|
T115 |
1 |
|
T104 |
3 |
|
T52 |
17181 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11976488 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9686983 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4231692 |
1 |
|
|
T14 |
1 |
|
T19 |
1 |
|
T22 |
3 |
| auto[1] |
auto[0] |
auto[1] |
626957 |
1 |
|
|
T104 |
1 |
|
T52 |
8825 |
|
T105 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4204519 |
1 |
|
|
T17 |
1 |
|
T23 |
1 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[1] |
623815 |
1 |
|
|
T115 |
1 |
|
T104 |
2 |
|
T52 |
8356 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11970150 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9693321 |
1 |
|
|
T1 |
11 |
|
T12 |
5 |
|
T13 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20413775 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1249696 |
1 |
|
|
T5 |
1 |
|
T79 |
1 |
|
T104 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11970824 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9692647 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T19 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4231106 |
1 |
|
|
T14 |
1 |
|
T19 |
1 |
|
T22 |
3 |
| auto[1] |
auto[0] |
auto[1] |
626557 |
1 |
|
|
T5 |
1 |
|
T79 |
1 |
|
T104 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4211845 |
1 |
|
|
T1 |
11 |
|
T51 |
3 |
|
T23 |
3 |
| auto[1] |
auto[1] |
auto[1] |
623139 |
1 |
|
|
T52 |
9102 |
|
T105 |
13 |
|
T109 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11951388 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
2 |
| auto[1] |
9712083 |
1 |
|
|
T11 |
10 |
|
T12 |
10 |
|
T13 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20414111 |
1 |
|
|
T21 |
1 |
|
T1 |
10 |
|
T11 |
12 |
| auto[1] |
1249360 |
1 |
|
|
T1 |
3 |
|
T100 |
1 |
|
T4 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11986086 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9677385 |
1 |
|
|
T1 |
11 |
|
T22 |
2 |
|
T51 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4204513 |
1 |
|
|
T1 |
8 |
|
T22 |
2 |
|
T51 |
1 |
| auto[1] |
auto[0] |
auto[1] |
623653 |
1 |
|
|
T1 |
3 |
|
T5 |
1 |
|
T104 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4223512 |
1 |
|
|
T51 |
3 |
|
T23 |
4 |
|
T100 |
1 |
| auto[1] |
auto[1] |
auto[1] |
625707 |
1 |
|
|
T100 |
1 |
|
T4 |
2 |
|
T104 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12022025 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
10 |
| auto[1] |
9641446 |
1 |
|
|
T11 |
2 |
|
T12 |
7 |
|
T13 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20415388 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1248083 |
1 |
|
|
T104 |
5 |
|
T52 |
15412 |
|
T105 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11997408 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9666063 |
1 |
|
|
T1 |
11 |
|
T17 |
1 |
|
T22 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4215627 |
1 |
|
|
T1 |
11 |
|
T17 |
1 |
|
T22 |
2 |
| auto[1] |
auto[0] |
auto[1] |
626194 |
1 |
|
|
T104 |
1 |
|
T52 |
7586 |
|
T105 |
6 |
| auto[1] |
auto[1] |
auto[0] |
4202353 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
4 |
| auto[1] |
auto[1] |
auto[1] |
621889 |
1 |
|
|
T104 |
4 |
|
T52 |
7826 |
|
T105 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11976484 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
10 |
| auto[1] |
9686987 |
1 |
|
|
T1 |
11 |
|
T11 |
2 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20417557 |
1 |
|
|
T21 |
1 |
|
T1 |
10 |
|
T11 |
12 |
| auto[1] |
1245914 |
1 |
|
|
T1 |
3 |
|
T9 |
2 |
|
T115 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11996621 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9666850 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T19 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4212816 |
1 |
|
|
T14 |
1 |
|
T22 |
1 |
|
T51 |
1 |
| auto[1] |
auto[0] |
auto[1] |
622205 |
1 |
|
|
T9 |
2 |
|
T115 |
1 |
|
T52 |
7983 |
| auto[1] |
auto[1] |
auto[0] |
4208120 |
1 |
|
|
T1 |
8 |
|
T19 |
1 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[1] |
623709 |
1 |
|
|
T1 |
3 |
|
T104 |
3 |
|
T52 |
8348 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11977910 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9685561 |
1 |
|
|
T1 |
11 |
|
T12 |
7 |
|
T13 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20407773 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1255698 |
1 |
|
|
T5 |
2 |
|
T9 |
3 |
|
T115 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11932940 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9730531 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4244101 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
2 |
| auto[1] |
auto[0] |
auto[1] |
627426 |
1 |
|
|
T9 |
3 |
|
T52 |
7405 |
|
T105 |
6 |
| auto[1] |
auto[1] |
auto[0] |
4230732 |
1 |
|
|
T1 |
11 |
|
T51 |
3 |
|
T23 |
5 |
| auto[1] |
auto[1] |
auto[1] |
628272 |
1 |
|
|
T5 |
2 |
|
T115 |
1 |
|
T52 |
8966 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11962083 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
2 |
| auto[1] |
9701388 |
1 |
|
|
T1 |
11 |
|
T11 |
10 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20415050 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1248421 |
1 |
|
|
T5 |
3 |
|
T9 |
2 |
|
T115 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11980399 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9683072 |
1 |
|
|
T1 |
11 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4205773 |
1 |
|
|
T19 |
1 |
|
T22 |
1 |
|
T23 |
11 |
| auto[1] |
auto[0] |
auto[1] |
622028 |
1 |
|
|
T5 |
3 |
|
T9 |
2 |
|
T115 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4228878 |
1 |
|
|
T1 |
11 |
|
T17 |
1 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[1] |
626393 |
1 |
|
|
T104 |
2 |
|
T52 |
8792 |
|
T105 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11956252 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
4 |
| auto[1] |
9707219 |
1 |
|
|
T1 |
11 |
|
T11 |
8 |
|
T12 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20410308 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1253163 |
1 |
|
|
T100 |
1 |
|
T9 |
3 |
|
T115 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11966655 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9696816 |
1 |
|
|
T14 |
1 |
|
T22 |
3 |
|
T23 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4220284 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T23 |
8 |
| auto[1] |
auto[0] |
auto[1] |
626913 |
1 |
|
|
T104 |
2 |
|
T52 |
7580 |
|
T105 |
5 |
| auto[1] |
auto[1] |
auto[0] |
4223369 |
1 |
|
|
T22 |
1 |
|
T23 |
3 |
|
T100 |
1 |
| auto[1] |
auto[1] |
auto[1] |
626250 |
1 |
|
|
T100 |
1 |
|
T9 |
3 |
|
T115 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11970684 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
2 |
| auto[1] |
9692787 |
1 |
|
|
T1 |
11 |
|
T11 |
10 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20413118 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1250353 |
1 |
|
|
T104 |
2 |
|
T52 |
15736 |
|
T105 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11989933 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9673538 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4205214 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
1 |
| auto[1] |
auto[0] |
auto[1] |
624329 |
1 |
|
|
T104 |
2 |
|
T52 |
8033 |
|
T105 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4217971 |
1 |
|
|
T51 |
1 |
|
T23 |
5 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[1] |
626024 |
1 |
|
|
T52 |
7703 |
|
T105 |
10 |
|
T109 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11971600 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
4 |
| auto[1] |
9691871 |
1 |
|
|
T11 |
8 |
|
T12 |
5 |
|
T13 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20416957 |
1 |
|
|
T21 |
1 |
|
T1 |
11 |
|
T11 |
12 |
| auto[1] |
1246514 |
1 |
|
|
T1 |
2 |
|
T5 |
1 |
|
T104 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11999019 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9664452 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4195323 |
1 |
|
|
T1 |
9 |
|
T14 |
1 |
|
T22 |
1 |
| auto[1] |
auto[0] |
auto[1] |
619741 |
1 |
|
|
T1 |
2 |
|
T5 |
1 |
|
T104 |
4 |
| auto[1] |
auto[1] |
auto[0] |
4222615 |
1 |
|
|
T17 |
1 |
|
T22 |
1 |
|
T23 |
4 |
| auto[1] |
auto[1] |
auto[1] |
626773 |
1 |
|
|
T52 |
8602 |
|
T105 |
12 |
|
T109 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11988718 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
6 |
| auto[1] |
9674753 |
1 |
|
|
T1 |
11 |
|
T11 |
6 |
|
T12 |
3 |