Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11976484 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
10 |
auto[1] |
9686987 |
1 |
|
|
T1 |
11 |
|
T11 |
2 |
|
T12 |
5 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
17809247 |
1 |
|
|
T21 |
1 |
|
T1 |
6 |
|
T11 |
12 |
auto[1] |
3854224 |
1 |
|
|
T1 |
7 |
|
T19 |
1 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11946718 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
auto[1] |
9716753 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T18 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2955010 |
1 |
|
|
T14 |
1 |
|
T18 |
1 |
|
T22 |
2 |
auto[1] |
auto[0] |
auto[1] |
1936829 |
1 |
|
|
T22 |
1 |
|
T23 |
1 |
|
T35 |
1 |
auto[1] |
auto[1] |
auto[0] |
2907519 |
1 |
|
|
T1 |
4 |
|
T22 |
2 |
|
T51 |
2 |
auto[1] |
auto[1] |
auto[1] |
1917395 |
1 |
|
|
T1 |
7 |
|
T19 |
1 |
|
T3 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |