Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11967879 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
6 |
| auto[1] |
9695592 |
1 |
|
|
T1 |
11 |
|
T11 |
6 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20412344 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
1251127 |
1 |
|
|
T104 |
1 |
|
T52 |
16382 |
|
T105 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11982369 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9681102 |
1 |
|
|
T14 |
1 |
|
T19 |
1 |
|
T22 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4229771 |
1 |
|
|
T14 |
1 |
|
T19 |
1 |
|
T22 |
3 |
| auto[1] |
auto[0] |
auto[1] |
627921 |
1 |
|
|
T52 |
7947 |
|
T105 |
5 |
|
T109 |
5 |
| auto[1] |
auto[1] |
auto[0] |
4200204 |
1 |
|
|
T22 |
1 |
|
T51 |
2 |
|
T23 |
3 |
| auto[1] |
auto[1] |
auto[1] |
623206 |
1 |
|
|
T104 |
1 |
|
T52 |
8435 |
|
T105 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |