Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11931648 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
8 |
| auto[1] |
9731823 |
1 |
|
|
T11 |
4 |
|
T12 |
3 |
|
T13 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15831170 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5832301 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T51 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11988850 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9674621 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T51 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1913061 |
1 |
|
|
T51 |
1 |
|
T23 |
4 |
|
T5 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2912177 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T51 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1929259 |
1 |
|
|
T23 |
1 |
|
T100 |
1 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2920124 |
1 |
|
|
T24 |
1 |
|
T6 |
1 |
|
T26 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11965763 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
4 |
| auto[1] |
9697708 |
1 |
|
|
T1 |
11 |
|
T11 |
8 |
|
T12 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15850052 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5813419 |
1 |
|
|
T22 |
3 |
|
T51 |
4 |
|
T23 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12013937 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9649534 |
1 |
|
|
T14 |
1 |
|
T22 |
5 |
|
T51 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1917295 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T23 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2908831 |
1 |
|
|
T22 |
1 |
|
T23 |
6 |
|
T111 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1918820 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T8 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2904588 |
1 |
|
|
T22 |
2 |
|
T51 |
4 |
|
T23 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11981896 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
8 |
| auto[1] |
9681575 |
1 |
|
|
T11 |
4 |
|
T12 |
2 |
|
T13 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15850528 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5812943 |
1 |
|
|
T17 |
1 |
|
T22 |
4 |
|
T51 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12012553 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9650918 |
1 |
|
|
T17 |
1 |
|
T22 |
4 |
|
T51 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1915084 |
1 |
|
|
T23 |
2 |
|
T111 |
1 |
|
T24 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2910951 |
1 |
|
|
T22 |
2 |
|
T23 |
5 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1922891 |
1 |
|
|
T23 |
1 |
|
T75 |
1 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2901992 |
1 |
|
|
T17 |
1 |
|
T22 |
2 |
|
T51 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12007927 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
2 |
| auto[1] |
9655544 |
1 |
|
|
T11 |
10 |
|
T12 |
5 |
|
T13 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15849232 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
5814239 |
1 |
|
|
T1 |
11 |
|
T22 |
2 |
|
T51 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12005850 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9657621 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1921374 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T75 |
3 |
| auto[1] |
auto[0] |
auto[1] |
2908712 |
1 |
|
|
T1 |
11 |
|
T22 |
2 |
|
T23 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1922008 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T4 |
4 |
| auto[1] |
auto[1] |
auto[1] |
2905527 |
1 |
|
|
T51 |
3 |
|
T23 |
2 |
|
T4 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12032139 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
6 |
| auto[1] |
9631332 |
1 |
|
|
T11 |
6 |
|
T12 |
5 |
|
T13 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15786081 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5877390 |
1 |
|
|
T22 |
2 |
|
T51 |
3 |
|
T23 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11913774 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9749697 |
1 |
|
|
T22 |
4 |
|
T51 |
3 |
|
T23 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1954658 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T4 |
6 |
| auto[1] |
auto[0] |
auto[1] |
2971033 |
1 |
|
|
T23 |
4 |
|
T111 |
1 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1917649 |
1 |
|
|
T23 |
2 |
|
T35 |
2 |
|
T9 |
3 |
| auto[1] |
auto[1] |
auto[1] |
2906357 |
1 |
|
|
T22 |
2 |
|
T51 |
3 |
|
T23 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11937765 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
8 |
| auto[1] |
9725706 |
1 |
|
|
T11 |
4 |
|
T12 |
8 |
|
T13 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15834078 |
1 |
|
|
T21 |
1 |
|
T1 |
6 |
|
T11 |
12 |
| auto[1] |
5829393 |
1 |
|
|
T1 |
7 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11988260 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9675211 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1916933 |
1 |
|
|
T1 |
4 |
|
T23 |
2 |
|
T3 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2902136 |
1 |
|
|
T1 |
7 |
|
T14 |
1 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1928885 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2927257 |
1 |
|
|
T51 |
1 |
|
T23 |
2 |
|
T100 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11961972 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
2 |
| auto[1] |
9701499 |
1 |
|
|
T1 |
11 |
|
T11 |
10 |
|
T12 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15830336 |
1 |
|
|
T21 |
1 |
|
T1 |
6 |
|
T11 |
12 |
| auto[1] |
5833135 |
1 |
|
|
T1 |
7 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11982434 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9681037 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1919180 |
1 |
|
|
T51 |
1 |
|
T75 |
1 |
|
T5 |
3 |
| auto[1] |
auto[0] |
auto[1] |
2907070 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1928722 |
1 |
|
|
T1 |
4 |
|
T24 |
1 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2926065 |
1 |
|
|
T1 |
7 |
|
T22 |
3 |
|
T51 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11959937 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9703534 |
1 |
|
|
T12 |
3 |
|
T13 |
20 |
|
T15 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15874066 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5789405 |
1 |
|
|
T17 |
1 |
|
T22 |
4 |
|
T23 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12056193 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9607278 |
1 |
|
|
T17 |
1 |
|
T22 |
5 |
|
T23 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1908861 |
1 |
|
|
T23 |
1 |
|
T100 |
2 |
|
T111 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2875486 |
1 |
|
|
T17 |
1 |
|
T22 |
1 |
|
T23 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1909012 |
1 |
|
|
T22 |
1 |
|
T4 |
4 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2913919 |
1 |
|
|
T22 |
3 |
|
T23 |
3 |
|
T4 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12013892 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
2 |
| auto[1] |
9649579 |
1 |
|
|
T1 |
11 |
|
T11 |
10 |
|
T12 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15835486 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
5827985 |
1 |
|
|
T1 |
11 |
|
T22 |
2 |
|
T51 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11989074 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9674397 |
1 |
|
|
T1 |
11 |
|
T22 |
2 |
|
T51 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1926077 |
1 |
|
|
T23 |
6 |
|
T24 |
1 |
|
T5 |
3 |
| auto[1] |
auto[0] |
auto[1] |
2917212 |
1 |
|
|
T22 |
1 |
|
T51 |
2 |
|
T23 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1920335 |
1 |
|
|
T100 |
1 |
|
T24 |
2 |
|
T26 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2910773 |
1 |
|
|
T1 |
11 |
|
T22 |
1 |
|
T3 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11970150 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9693321 |
1 |
|
|
T1 |
11 |
|
T12 |
5 |
|
T13 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15828300 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5835171 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11976326 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9687145 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1921907 |
1 |
|
|
T23 |
2 |
|
T100 |
1 |
|
T26 |
3 |
| auto[1] |
auto[0] |
auto[1] |
2919788 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T51 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1930067 |
1 |
|
|
T23 |
1 |
|
T110 |
1 |
|
T26 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2915383 |
1 |
|
|
T17 |
1 |
|
T22 |
1 |
|
T51 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11951388 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
2 |
| auto[1] |
9712083 |
1 |
|
|
T11 |
10 |
|
T12 |
10 |
|
T13 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15827416 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5836055 |
1 |
|
|
T22 |
4 |
|
T51 |
3 |
|
T23 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11984331 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9679140 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1915920 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T23 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2909915 |
1 |
|
|
T22 |
3 |
|
T51 |
1 |
|
T23 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1927165 |
1 |
|
|
T51 |
2 |
|
T4 |
2 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2926140 |
1 |
|
|
T22 |
1 |
|
T51 |
2 |
|
T23 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12022025 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
10 |
| auto[1] |
9641446 |
1 |
|
|
T11 |
2 |
|
T12 |
7 |
|
T13 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15834873 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5828598 |
1 |
|
|
T14 |
1 |
|
T22 |
3 |
|
T23 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11991428 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9672043 |
1 |
|
|
T14 |
1 |
|
T22 |
5 |
|
T51 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1926269 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2924613 |
1 |
|
|
T14 |
1 |
|
T22 |
3 |
|
T23 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1917176 |
1 |
|
|
T22 |
1 |
|
T23 |
1 |
|
T35 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2903985 |
1 |
|
|
T23 |
2 |
|
T110 |
1 |
|
T74 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11976484 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
10 |
| auto[1] |
9686987 |
1 |
|
|
T1 |
11 |
|
T11 |
2 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15855365 |
1 |
|
|
T21 |
1 |
|
T1 |
9 |
|
T11 |
12 |
| auto[1] |
5808106 |
1 |
|
|
T1 |
4 |
|
T22 |
3 |
|
T51 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12023636 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9639835 |
1 |
|
|
T1 |
11 |
|
T22 |
3 |
|
T51 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1908746 |
1 |
|
|
T23 |
2 |
|
T100 |
1 |
|
T111 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2897655 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1922983 |
1 |
|
|
T1 |
7 |
|
T3 |
1 |
|
T26 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2910451 |
1 |
|
|
T1 |
4 |
|
T22 |
2 |
|
T51 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11977910 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9685561 |
1 |
|
|
T1 |
11 |
|
T12 |
7 |
|
T13 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15797007 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
5866464 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11938622 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9724849 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1928496 |
1 |
|
|
T22 |
1 |
|
T23 |
4 |
|
T4 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2932581 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1929889 |
1 |
|
|
T51 |
2 |
|
T24 |
2 |
|
T5 |
3 |
| auto[1] |
auto[1] |
auto[1] |
2933883 |
1 |
|
|
T1 |
11 |
|
T22 |
1 |
|
T51 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11962083 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
2 |
| auto[1] |
9701388 |
1 |
|
|
T1 |
11 |
|
T11 |
10 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15821972 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5841499 |
1 |
|
|
T14 |
1 |
|
T22 |
1 |
|
T23 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11972261 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9691210 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T23 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1931941 |
1 |
|
|
T22 |
1 |
|
T23 |
5 |
|
T24 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2929095 |
1 |
|
|
T14 |
1 |
|
T23 |
5 |
|
T100 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1917770 |
1 |
|
|
T23 |
1 |
|
T6 |
1 |
|
T35 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2912404 |
1 |
|
|
T22 |
1 |
|
T23 |
1 |
|
T3 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |