Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11956252 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
4 |
| auto[1] |
9707219 |
1 |
|
|
T1 |
11 |
|
T11 |
8 |
|
T12 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15774010 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5889461 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T23 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11902215 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9761256 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T51 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1937434 |
1 |
|
|
T23 |
2 |
|
T24 |
1 |
|
T35 |
3 |
| auto[1] |
auto[0] |
auto[1] |
2937529 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T23 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1934361 |
1 |
|
|
T51 |
1 |
|
T23 |
1 |
|
T35 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2951932 |
1 |
|
|
T23 |
3 |
|
T100 |
1 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11970684 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
2 |
| auto[1] |
9692787 |
1 |
|
|
T1 |
11 |
|
T11 |
10 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15827808 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
5835663 |
1 |
|
|
T1 |
11 |
|
T22 |
3 |
|
T51 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11978468 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9685003 |
1 |
|
|
T1 |
11 |
|
T22 |
3 |
|
T51 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1929613 |
1 |
|
|
T23 |
3 |
|
T4 |
5 |
|
T24 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2933914 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1919727 |
1 |
|
|
T23 |
1 |
|
T26 |
1 |
|
T35 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2901749 |
1 |
|
|
T1 |
11 |
|
T22 |
2 |
|
T23 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11971600 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
4 |
| auto[1] |
9691871 |
1 |
|
|
T11 |
8 |
|
T12 |
5 |
|
T13 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15848154 |
1 |
|
|
T21 |
1 |
|
T1 |
7 |
|
T11 |
12 |
| auto[1] |
5815317 |
1 |
|
|
T1 |
6 |
|
T14 |
1 |
|
T22 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12016857 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9646614 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T22 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1911287 |
1 |
|
|
T1 |
5 |
|
T22 |
1 |
|
T23 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2906332 |
1 |
|
|
T1 |
6 |
|
T14 |
1 |
|
T22 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1920010 |
1 |
|
|
T23 |
2 |
|
T100 |
1 |
|
T35 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2908985 |
1 |
|
|
T22 |
1 |
|
T23 |
4 |
|
T100 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11988718 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
6 |
| auto[1] |
9674753 |
1 |
|
|
T1 |
11 |
|
T11 |
6 |
|
T12 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15826253 |
1 |
|
|
T21 |
1 |
|
T1 |
7 |
|
T11 |
12 |
| auto[1] |
5837218 |
1 |
|
|
T1 |
6 |
|
T14 |
1 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11984680 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9678791 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T22 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1917601 |
1 |
|
|
T22 |
1 |
|
T23 |
3 |
|
T5 |
5 |
| auto[1] |
auto[0] |
auto[1] |
2915567 |
1 |
|
|
T14 |
1 |
|
T22 |
1 |
|
T51 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1923972 |
1 |
|
|
T1 |
5 |
|
T23 |
1 |
|
T4 |
4 |
| auto[1] |
auto[1] |
auto[1] |
2921651 |
1 |
|
|
T1 |
6 |
|
T51 |
4 |
|
T23 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11967157 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
6 |
| auto[1] |
9696314 |
1 |
|
|
T11 |
6 |
|
T12 |
5 |
|
T13 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15855058 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5808413 |
1 |
|
|
T22 |
3 |
|
T23 |
6 |
|
T111 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12018587 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9644884 |
1 |
|
|
T14 |
1 |
|
T22 |
4 |
|
T23 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1923040 |
1 |
|
|
T14 |
1 |
|
T22 |
1 |
|
T23 |
4 |
| auto[1] |
auto[0] |
auto[1] |
2906630 |
1 |
|
|
T22 |
2 |
|
T23 |
6 |
|
T111 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1913431 |
1 |
|
|
T26 |
1 |
|
T35 |
1 |
|
T7 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2901783 |
1 |
|
|
T22 |
1 |
|
T24 |
3 |
|
T110 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12001508 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
10 |
| auto[1] |
9661963 |
1 |
|
|
T11 |
2 |
|
T12 |
5 |
|
T13 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15827770 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5835701 |
1 |
|
|
T17 |
1 |
|
T22 |
3 |
|
T51 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11984016 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9679455 |
1 |
|
|
T17 |
1 |
|
T22 |
4 |
|
T51 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1930479 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2933516 |
1 |
|
|
T17 |
1 |
|
T22 |
3 |
|
T51 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1913275 |
1 |
|
|
T23 |
2 |
|
T24 |
2 |
|
T5 |
4 |
| auto[1] |
auto[1] |
auto[1] |
2902185 |
1 |
|
|
T51 |
1 |
|
T23 |
3 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12014439 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
8 |
| auto[1] |
9649032 |
1 |
|
|
T11 |
4 |
|
T12 |
8 |
|
T13 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15778802 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5884669 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11915677 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9747794 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1940540 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T5 |
6 |
| auto[1] |
auto[0] |
auto[1] |
2961960 |
1 |
|
|
T14 |
1 |
|
T22 |
3 |
|
T23 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1922585 |
1 |
|
|
T23 |
1 |
|
T100 |
1 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2922709 |
1 |
|
|
T17 |
1 |
|
T51 |
1 |
|
T23 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11967879 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
6 |
| auto[1] |
9695592 |
1 |
|
|
T1 |
11 |
|
T11 |
6 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15829841 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5833630 |
1 |
|
|
T14 |
1 |
|
T22 |
4 |
|
T23 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11992982 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9670489 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1925183 |
1 |
|
|
T23 |
1 |
|
T4 |
1 |
|
T26 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2931698 |
1 |
|
|
T14 |
1 |
|
T22 |
3 |
|
T23 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1911676 |
1 |
|
|
T17 |
1 |
|
T51 |
2 |
|
T75 |
4 |
| auto[1] |
auto[1] |
auto[1] |
2901932 |
1 |
|
|
T22 |
1 |
|
T23 |
4 |
|
T75 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11982744 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
6 |
| auto[1] |
9680727 |
1 |
|
|
T1 |
11 |
|
T11 |
6 |
|
T12 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15839374 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5824097 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11998390 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9665081 |
1 |
|
|
T22 |
6 |
|
T51 |
1 |
|
T23 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1924797 |
1 |
|
|
T22 |
3 |
|
T23 |
2 |
|
T100 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2914745 |
1 |
|
|
T23 |
7 |
|
T75 |
5 |
|
T100 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1916187 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T4 |
5 |
| auto[1] |
auto[1] |
auto[1] |
2909352 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11945224 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
10 |
| auto[1] |
9718247 |
1 |
|
|
T1 |
11 |
|
T11 |
2 |
|
T12 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15836012 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
5827459 |
1 |
|
|
T1 |
11 |
|
T22 |
4 |
|
T51 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11995915 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9667556 |
1 |
|
|
T1 |
11 |
|
T22 |
4 |
|
T51 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1913450 |
1 |
|
|
T23 |
4 |
|
T26 |
1 |
|
T35 |
3 |
| auto[1] |
auto[0] |
auto[1] |
2896314 |
1 |
|
|
T22 |
3 |
|
T51 |
1 |
|
T23 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1926647 |
1 |
|
|
T23 |
1 |
|
T75 |
3 |
|
T4 |
4 |
| auto[1] |
auto[1] |
auto[1] |
2931145 |
1 |
|
|
T1 |
11 |
|
T22 |
1 |
|
T51 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11983655 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
4 |
| auto[1] |
9679816 |
1 |
|
|
T11 |
8 |
|
T12 |
8 |
|
T13 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15853607 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5809864 |
1 |
|
|
T22 |
5 |
|
T51 |
1 |
|
T23 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12017268 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9646203 |
1 |
|
|
T22 |
6 |
|
T51 |
2 |
|
T23 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1927650 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2923147 |
1 |
|
|
T22 |
2 |
|
T51 |
1 |
|
T23 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1908689 |
1 |
|
|
T23 |
1 |
|
T4 |
5 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2886717 |
1 |
|
|
T22 |
3 |
|
T23 |
2 |
|
T4 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12006180 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
2 |
| auto[1] |
9657291 |
1 |
|
|
T11 |
10 |
|
T12 |
7 |
|
T13 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15822974 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5840497 |
1 |
|
|
T22 |
3 |
|
T51 |
3 |
|
T23 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11977617 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9685854 |
1 |
|
|
T14 |
1 |
|
T22 |
5 |
|
T51 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1927289 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T51 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2933053 |
1 |
|
|
T22 |
1 |
|
T51 |
3 |
|
T23 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1918068 |
1 |
|
|
T3 |
1 |
|
T26 |
1 |
|
T35 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2907444 |
1 |
|
|
T22 |
2 |
|
T23 |
4 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12002445 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
10 |
| auto[1] |
9661026 |
1 |
|
|
T11 |
2 |
|
T13 |
8 |
|
T17 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15822886 |
1 |
|
|
T21 |
1 |
|
T1 |
8 |
|
T11 |
12 |
| auto[1] |
5840585 |
1 |
|
|
T1 |
5 |
|
T14 |
1 |
|
T22 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11971178 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9692293 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1931120 |
1 |
|
|
T1 |
6 |
|
T51 |
1 |
|
T23 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2945183 |
1 |
|
|
T1 |
5 |
|
T14 |
1 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1920588 |
1 |
|
|
T17 |
1 |
|
T23 |
1 |
|
T75 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2895402 |
1 |
|
|
T22 |
2 |
|
T51 |
1 |
|
T23 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11956862 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
6 |
| auto[1] |
9706609 |
1 |
|
|
T11 |
6 |
|
T12 |
3 |
|
T13 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15831417 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
5832054 |
1 |
|
|
T22 |
3 |
|
T51 |
5 |
|
T23 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11997983 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
| auto[1] |
9665488 |
1 |
|
|
T14 |
1 |
|
T22 |
4 |
|
T51 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1914598 |
1 |
|
|
T14 |
1 |
|
T22 |
1 |
|
T23 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2910345 |
1 |
|
|
T22 |
2 |
|
T51 |
2 |
|
T23 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1918836 |
1 |
|
|
T23 |
1 |
|
T26 |
1 |
|
T116 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2921709 |
1 |
|
|
T22 |
1 |
|
T51 |
3 |
|
T23 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11942393 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
6 |
| auto[1] |
9721078 |
1 |
|
|
T11 |
6 |
|
T12 |
8 |
|
T13 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15806580 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
5856891 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11961488 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
| auto[1] |
9701983 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1919598 |
1 |
|
|
T23 |
3 |
|
T26 |
1 |
|
T35 |
4 |
| auto[1] |
auto[0] |
auto[1] |
2914605 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1925494 |
1 |
|
|
T22 |
1 |
|
T75 |
3 |
|
T4 |
5 |
| auto[1] |
auto[1] |
auto[1] |
2942286 |
1 |
|
|
T17 |
1 |
|
T22 |
2 |
|
T23 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |