Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11987866 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
10 |
auto[1] |
9675605 |
1 |
|
|
T11 |
2 |
|
T13 |
19 |
|
T15 |
11 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
15853185 |
1 |
|
|
T21 |
1 |
|
T1 |
6 |
|
T11 |
12 |
auto[1] |
5810286 |
1 |
|
|
T1 |
7 |
|
T17 |
1 |
|
T22 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12015615 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
auto[1] |
9647856 |
1 |
|
|
T1 |
11 |
|
T17 |
1 |
|
T22 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1915411 |
1 |
|
|
T1 |
4 |
|
T51 |
1 |
|
T23 |
3 |
auto[1] |
auto[0] |
auto[1] |
2898729 |
1 |
|
|
T1 |
7 |
|
T22 |
1 |
|
T51 |
1 |
auto[1] |
auto[1] |
auto[0] |
1922159 |
1 |
|
|
T23 |
2 |
|
T5 |
1 |
|
T26 |
1 |
auto[1] |
auto[1] |
auto[1] |
2911557 |
1 |
|
|
T17 |
1 |
|
T22 |
1 |
|
T3 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11958648 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
10 |
auto[1] |
9704823 |
1 |
|
|
T1 |
11 |
|
T11 |
2 |
|
T12 |
5 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20420910 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
1242561 |
1 |
|
|
T19 |
1 |
|
T22 |
3 |
|
T23 |
4 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12011317 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
9652154 |
1 |
|
|
T19 |
1 |
|
T22 |
4 |
|
T51 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4194006 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
7 |
auto[1] |
auto[0] |
auto[1] |
619530 |
1 |
|
|
T22 |
2 |
|
T23 |
3 |
|
T24 |
1 |
auto[1] |
auto[1] |
auto[0] |
4215587 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T5 |
4 |
auto[1] |
auto[1] |
auto[1] |
623031 |
1 |
|
|
T19 |
1 |
|
T22 |
1 |
|
T23 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11931648 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
8 |
auto[1] |
9731823 |
1 |
|
|
T11 |
4 |
|
T12 |
3 |
|
T13 |
18 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20416085 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
1247386 |
1 |
|
|
T51 |
2 |
|
T23 |
4 |
|
T75 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11986708 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
9676763 |
1 |
|
|
T14 |
1 |
|
T22 |
1 |
|
T51 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4208194 |
1 |
|
|
T14 |
1 |
|
T51 |
3 |
|
T23 |
5 |
auto[1] |
auto[0] |
auto[1] |
620299 |
1 |
|
|
T51 |
2 |
|
T23 |
3 |
|
T26 |
3 |
auto[1] |
auto[1] |
auto[0] |
4221183 |
1 |
|
|
T22 |
1 |
|
T23 |
1 |
|
T75 |
4 |
auto[1] |
auto[1] |
auto[1] |
627087 |
1 |
|
|
T23 |
1 |
|
T75 |
1 |
|
T4 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11965763 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
4 |
auto[1] |
9697708 |
1 |
|
|
T1 |
11 |
|
T11 |
8 |
|
T12 |
10 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20408101 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
1255370 |
1 |
|
|
T17 |
1 |
|
T23 |
6 |
|
T24 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11936144 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
9727327 |
1 |
|
|
T17 |
1 |
|
T22 |
2 |
|
T51 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4217599 |
1 |
|
|
T22 |
2 |
|
T23 |
6 |
|
T4 |
8 |
auto[1] |
auto[0] |
auto[1] |
625449 |
1 |
|
|
T17 |
1 |
|
T23 |
5 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[0] |
4254358 |
1 |
|
|
T51 |
3 |
|
T23 |
2 |
|
T75 |
5 |
auto[1] |
auto[1] |
auto[1] |
629921 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T7 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11981896 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
8 |
auto[1] |
9681575 |
1 |
|
|
T11 |
4 |
|
T12 |
2 |
|
T13 |
27 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20413134 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
1250337 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T111 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11979771 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
9683700 |
1 |
|
|
T22 |
3 |
|
T51 |
2 |
|
T23 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4223621 |
1 |
|
|
T22 |
2 |
|
T51 |
2 |
|
T23 |
7 |
auto[1] |
auto[0] |
auto[1] |
624798 |
1 |
|
|
T23 |
1 |
|
T111 |
1 |
|
T4 |
2 |
auto[1] |
auto[1] |
auto[0] |
4209742 |
1 |
|
|
T23 |
2 |
|
T4 |
7 |
|
T24 |
1 |
auto[1] |
auto[1] |
auto[1] |
625539 |
1 |
|
|
T22 |
1 |
|
T23 |
1 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12007927 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
2 |
auto[1] |
9655544 |
1 |
|
|
T11 |
10 |
|
T12 |
5 |
|
T13 |
11 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20407566 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
1255905 |
1 |
|
|
T19 |
1 |
|
T22 |
2 |
|
T23 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11953906 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
auto[1] |
9709565 |
1 |
|
|
T1 |
11 |
|
T19 |
1 |
|
T22 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4226803 |
1 |
|
|
T1 |
11 |
|
T22 |
1 |
|
T23 |
7 |
auto[1] |
auto[0] |
auto[1] |
626991 |
1 |
|
|
T23 |
1 |
|
T75 |
2 |
|
T24 |
1 |
auto[1] |
auto[1] |
auto[0] |
4226857 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T4 |
5 |
auto[1] |
auto[1] |
auto[1] |
628914 |
1 |
|
|
T19 |
1 |
|
T22 |
2 |
|
T23 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12032139 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
6 |
auto[1] |
9631332 |
1 |
|
|
T11 |
6 |
|
T12 |
5 |
|
T13 |
19 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20418464 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
1245007 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12010556 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
auto[1] |
9652915 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T19 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4224825 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T23 |
4 |
auto[1] |
auto[0] |
auto[1] |
625998 |
1 |
|
|
T4 |
2 |
|
T26 |
3 |
|
T35 |
1 |
auto[1] |
auto[1] |
auto[0] |
4183083 |
1 |
|
|
T19 |
1 |
|
T51 |
1 |
|
T23 |
2 |
auto[1] |
auto[1] |
auto[1] |
619009 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11937765 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
8 |
auto[1] |
9725706 |
1 |
|
|
T11 |
4 |
|
T12 |
8 |
|
T13 |
13 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20417907 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
1245564 |
1 |
|
|
T22 |
1 |
|
T51 |
1 |
|
T23 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12004508 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
9658963 |
1 |
|
|
T17 |
1 |
|
T19 |
1 |
|
T22 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4198439 |
1 |
|
|
T17 |
1 |
|
T19 |
1 |
|
T51 |
1 |
auto[1] |
auto[0] |
auto[1] |
621424 |
1 |
|
|
T22 |
1 |
|
T3 |
1 |
|
T5 |
5 |
auto[1] |
auto[1] |
auto[0] |
4214960 |
1 |
|
|
T51 |
1 |
|
T23 |
1 |
|
T100 |
2 |
auto[1] |
auto[1] |
auto[1] |
624140 |
1 |
|
|
T51 |
1 |
|
T23 |
2 |
|
T24 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11961972 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
2 |
auto[1] |
9701499 |
1 |
|
|
T1 |
11 |
|
T11 |
10 |
|
T12 |
2 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20415812 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
1247659 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T3 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11977466 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
9686005 |
1 |
|
|
T14 |
1 |
|
T19 |
1 |
|
T22 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4203244 |
1 |
|
|
T14 |
1 |
|
T19 |
1 |
|
T23 |
5 |
auto[1] |
auto[0] |
auto[1] |
620720 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T26 |
2 |
auto[1] |
auto[1] |
auto[0] |
4235102 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T4 |
7 |
auto[1] |
auto[1] |
auto[1] |
626939 |
1 |
|
|
T3 |
1 |
|
T24 |
1 |
|
T6 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11959937 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
9703534 |
1 |
|
|
T12 |
3 |
|
T13 |
20 |
|
T15 |
12 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20417634 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
1245837 |
1 |
|
|
T23 |
2 |
|
T100 |
1 |
|
T4 |
3 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12005380 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
9658091 |
1 |
|
|
T22 |
2 |
|
T51 |
2 |
|
T23 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4197003 |
1 |
|
|
T22 |
1 |
|
T23 |
4 |
|
T100 |
1 |
auto[1] |
auto[0] |
auto[1] |
622178 |
1 |
|
|
T23 |
1 |
|
T100 |
1 |
|
T24 |
1 |
auto[1] |
auto[1] |
auto[0] |
4215251 |
1 |
|
|
T22 |
1 |
|
T51 |
2 |
|
T23 |
2 |
auto[1] |
auto[1] |
auto[1] |
623659 |
1 |
|
|
T23 |
1 |
|
T4 |
3 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12013892 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
2 |
auto[1] |
9649579 |
1 |
|
|
T1 |
11 |
|
T11 |
10 |
|
T12 |
8 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20416472 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
1246999 |
1 |
|
|
T51 |
1 |
|
T23 |
3 |
|
T4 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12001079 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
auto[1] |
9662392 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T22 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4218310 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T51 |
4 |
auto[1] |
auto[0] |
auto[1] |
625246 |
1 |
|
|
T51 |
1 |
|
T23 |
3 |
|
T24 |
1 |
auto[1] |
auto[1] |
auto[0] |
4197083 |
1 |
|
|
T1 |
11 |
|
T22 |
1 |
|
T3 |
1 |
auto[1] |
auto[1] |
auto[1] |
621753 |
1 |
|
|
T4 |
2 |
|
T24 |
2 |
|
T101 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11970150 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
auto[1] |
9693321 |
1 |
|
|
T1 |
11 |
|
T12 |
5 |
|
T13 |
12 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20415230 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
1248241 |
1 |
|
|
T23 |
4 |
|
T101 |
1 |
|
T6 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11995215 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
9668256 |
1 |
|
|
T17 |
1 |
|
T19 |
1 |
|
T22 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4191926 |
1 |
|
|
T19 |
1 |
|
T22 |
2 |
|
T23 |
6 |
auto[1] |
auto[0] |
auto[1] |
619495 |
1 |
|
|
T23 |
4 |
|
T101 |
1 |
|
T6 |
2 |
auto[1] |
auto[1] |
auto[0] |
4228089 |
1 |
|
|
T17 |
1 |
|
T22 |
1 |
|
T51 |
2 |
auto[1] |
auto[1] |
auto[1] |
628746 |
1 |
|
|
T26 |
1 |
|
T35 |
3 |
|
T116 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11951388 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
2 |
auto[1] |
9712083 |
1 |
|
|
T11 |
10 |
|
T12 |
10 |
|
T13 |
12 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20411387 |
1 |
|
|
T21 |
1 |
|
T1 |
9 |
|
T11 |
12 |
auto[1] |
1252084 |
1 |
|
|
T1 |
4 |
|
T17 |
1 |
|
T23 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11963589 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
auto[1] |
9699882 |
1 |
|
|
T1 |
11 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4206158 |
1 |
|
|
T1 |
7 |
|
T19 |
1 |
|
T22 |
3 |
auto[1] |
auto[0] |
auto[1] |
623513 |
1 |
|
|
T1 |
4 |
|
T17 |
1 |
|
T23 |
1 |
auto[1] |
auto[1] |
auto[0] |
4241640 |
1 |
|
|
T51 |
1 |
|
T23 |
1 |
|
T100 |
2 |
auto[1] |
auto[1] |
auto[1] |
628571 |
1 |
|
|
T23 |
1 |
|
T4 |
2 |
|
T5 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12022025 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
10 |
auto[1] |
9641446 |
1 |
|
|
T11 |
2 |
|
T12 |
7 |
|
T13 |
11 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20413605 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
1249866 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T75 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11991432 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
12 |
auto[1] |
9672039 |
1 |
|
|
T17 |
1 |
|
T19 |
1 |
|
T22 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4250704 |
1 |
|
|
T17 |
1 |
|
T22 |
1 |
|
T51 |
1 |
auto[1] |
auto[0] |
auto[1] |
631800 |
1 |
|
|
T23 |
1 |
|
T100 |
1 |
|
T24 |
1 |
auto[1] |
auto[1] |
auto[0] |
4171469 |
1 |
|
|
T19 |
1 |
|
T22 |
1 |
|
T51 |
2 |
auto[1] |
auto[1] |
auto[1] |
618066 |
1 |
|
|
T22 |
2 |
|
T23 |
1 |
|
T75 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11976484 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
10 |
auto[1] |
9686987 |
1 |
|
|
T1 |
11 |
|
T11 |
2 |
|
T12 |
5 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20415958 |
1 |
|
|
T21 |
1 |
|
T1 |
9 |
|
T11 |
12 |
auto[1] |
1247513 |
1 |
|
|
T1 |
4 |
|
T19 |
1 |
|
T51 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11993201 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
12 |
auto[1] |
9670270 |
1 |
|
|
T1 |
11 |
|
T14 |
1 |
|
T19 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4209644 |
1 |
|
|
T14 |
1 |
|
T22 |
2 |
|
T51 |
1 |
auto[1] |
auto[0] |
auto[1] |
621928 |
1 |
|
|
T23 |
1 |
|
T100 |
1 |
|
T101 |
1 |
auto[1] |
auto[1] |
auto[0] |
4213113 |
1 |
|
|
T1 |
7 |
|
T51 |
3 |
|
T23 |
1 |
auto[1] |
auto[1] |
auto[1] |
625585 |
1 |
|
|
T1 |
4 |
|
T19 |
1 |
|
T51 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |