Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.06 99.10 100.00 99.80 99.68 100.00


Total test records in report: 970
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T767 /workspace/coverage/default/37.gpio_filter_stress.2826986840 Jan 14 01:43:27 PM PST 24 Jan 14 01:43:55 PM PST 24 3569696990 ps
T768 /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2065494635 Jan 14 01:44:14 PM PST 24 Jan 14 01:44:16 PM PST 24 29364565 ps
T769 /workspace/coverage/default/28.gpio_random_dout_din.3944762193 Jan 14 01:42:58 PM PST 24 Jan 14 01:43:00 PM PST 24 70461130 ps
T770 /workspace/coverage/default/46.gpio_smoke.1894117311 Jan 14 01:44:08 PM PST 24 Jan 14 01:44:10 PM PST 24 133011461 ps
T771 /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2227859394 Jan 14 01:41:46 PM PST 24 Jan 14 01:41:48 PM PST 24 120540328 ps
T772 /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2823879639 Jan 14 01:43:27 PM PST 24 Jan 14 02:01:01 PM PST 24 76213230189 ps
T773 /workspace/coverage/default/14.gpio_filter_stress.2916409902 Jan 14 01:41:46 PM PST 24 Jan 14 01:42:00 PM PST 24 1833638656 ps
T774 /workspace/coverage/default/36.gpio_alert_test.2195638613 Jan 14 01:43:30 PM PST 24 Jan 14 01:43:32 PM PST 24 197414029 ps
T775 /workspace/coverage/default/34.gpio_alert_test.2331646494 Jan 14 01:43:18 PM PST 24 Jan 14 01:43:20 PM PST 24 44341116 ps
T776 /workspace/coverage/default/41.gpio_alert_test.2302285594 Jan 14 01:43:54 PM PST 24 Jan 14 01:43:56 PM PST 24 25482214 ps
T777 /workspace/coverage/default/39.gpio_rand_intr_trigger.2211047389 Jan 14 01:43:34 PM PST 24 Jan 14 01:43:37 PM PST 24 310098115 ps
T778 /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3465415841 Jan 14 01:40:38 PM PST 24 Jan 14 02:15:58 PM PST 24 63957754693 ps
T779 /workspace/coverage/default/35.gpio_filter_stress.2351837898 Jan 14 01:43:21 PM PST 24 Jan 14 01:43:43 PM PST 24 2335294533 ps
T780 /workspace/coverage/default/28.gpio_stress_all.3347489046 Jan 14 01:43:06 PM PST 24 Jan 14 01:45:59 PM PST 24 13812191224 ps
T781 /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2675746547 Jan 14 01:42:41 PM PST 24 Jan 14 01:42:46 PM PST 24 264727335 ps
T782 /workspace/coverage/default/7.gpio_alert_test.3935387443 Jan 14 01:41:09 PM PST 24 Jan 14 01:41:11 PM PST 24 15049224 ps
T783 /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.964693376 Jan 14 01:42:30 PM PST 24 Jan 14 01:42:34 PM PST 24 697859713 ps
T784 /workspace/coverage/default/21.gpio_intr_rand_pgm.2304950229 Jan 14 01:42:28 PM PST 24 Jan 14 01:42:30 PM PST 24 119990568 ps
T785 /workspace/coverage/default/35.gpio_intr_rand_pgm.1980645630 Jan 14 01:43:20 PM PST 24 Jan 14 01:43:23 PM PST 24 111872819 ps
T786 /workspace/coverage/default/48.gpio_alert_test.4076654660 Jan 14 01:44:03 PM PST 24 Jan 14 01:44:05 PM PST 24 14361451 ps
T787 /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2510568856 Jan 14 01:43:47 PM PST 24 Jan 14 01:43:51 PM PST 24 1385193490 ps
T788 /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.3994008021 Jan 14 01:44:08 PM PST 24 Jan 14 02:02:49 PM PST 24 828250558562 ps
T789 /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1533290998 Jan 14 01:43:58 PM PST 24 Jan 14 01:44:01 PM PST 24 167030049 ps
T790 /workspace/coverage/default/23.gpio_stress_all.1346487093 Jan 14 01:42:30 PM PST 24 Jan 14 01:44:38 PM PST 24 16762831973 ps
T791 /workspace/coverage/default/13.gpio_alert_test.1524252301 Jan 14 01:41:46 PM PST 24 Jan 14 01:41:47 PM PST 24 18398731 ps
T792 /workspace/coverage/default/28.gpio_rand_intr_trigger.3784816077 Jan 14 01:43:03 PM PST 24 Jan 14 01:43:05 PM PST 24 36460106 ps
T793 /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.4009205536 Jan 14 01:42:50 PM PST 24 Jan 14 01:42:53 PM PST 24 56897093 ps
T794 /workspace/coverage/default/29.gpio_intr_rand_pgm.3478666767 Jan 14 01:43:07 PM PST 24 Jan 14 01:43:10 PM PST 24 79446225 ps
T795 /workspace/coverage/default/13.gpio_rand_intr_trigger.855128956 Jan 14 01:41:46 PM PST 24 Jan 14 01:41:49 PM PST 24 541515882 ps
T796 /workspace/coverage/default/38.gpio_alert_test.3441203721 Jan 14 01:43:32 PM PST 24 Jan 14 01:43:34 PM PST 24 22153588 ps
T797 /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3557903691 Jan 14 01:41:30 PM PST 24 Jan 14 01:41:33 PM PST 24 69104221 ps
T798 /workspace/coverage/default/32.gpio_full_random.431967238 Jan 14 01:43:12 PM PST 24 Jan 14 01:43:15 PM PST 24 179075227 ps
T799 /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1773056459 Jan 14 01:42:13 PM PST 24 Jan 14 01:42:21 PM PST 24 110883643 ps
T800 /workspace/coverage/default/40.gpio_stress_all.3841007621 Jan 14 01:43:46 PM PST 24 Jan 14 01:45:12 PM PST 24 12666665196 ps
T801 /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.897990994 Jan 14 01:40:23 PM PST 24 Jan 14 01:58:09 PM PST 24 318565648792 ps
T802 /workspace/coverage/default/48.gpio_filter_stress.3539966456 Jan 14 01:44:04 PM PST 24 Jan 14 01:44:13 PM PST 24 159872749 ps
T803 /workspace/coverage/default/45.gpio_alert_test.2266082867 Jan 14 01:44:04 PM PST 24 Jan 14 01:44:06 PM PST 24 38947340 ps
T804 /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1084804809 Jan 14 01:42:33 PM PST 24 Jan 14 01:42:37 PM PST 24 543479700 ps
T805 /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.883053241 Jan 14 01:41:05 PM PST 24 Jan 14 01:41:06 PM PST 24 30694977 ps
T806 /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.4049490165 Jan 14 01:42:16 PM PST 24 Jan 14 01:42:22 PM PST 24 64567017 ps
T807 /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2396046598 Jan 14 01:42:28 PM PST 24 Jan 14 01:42:30 PM PST 24 13620054 ps
T808 /workspace/coverage/default/29.gpio_full_random.2888553066 Jan 14 01:43:07 PM PST 24 Jan 14 01:43:10 PM PST 24 163832234 ps
T809 /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1969785853 Jan 14 01:42:08 PM PST 24 Jan 14 01:42:12 PM PST 24 48402055 ps
T810 /workspace/coverage/default/1.gpio_full_random.4276160329 Jan 14 01:40:23 PM PST 24 Jan 14 01:40:24 PM PST 24 19978268 ps
T811 /workspace/coverage/default/49.gpio_full_random.2219904962 Jan 14 01:44:17 PM PST 24 Jan 14 01:44:18 PM PST 24 50936214 ps
T812 /workspace/coverage/default/16.gpio_stress_all.1550464453 Jan 14 01:42:06 PM PST 24 Jan 14 01:42:59 PM PST 24 8061385068 ps
T813 /workspace/coverage/default/39.gpio_filter_stress.2997040369 Jan 14 01:43:42 PM PST 24 Jan 14 01:44:08 PM PST 24 2739771285 ps
T814 /workspace/coverage/default/46.gpio_alert_test.987432651 Jan 14 01:44:12 PM PST 24 Jan 14 01:44:13 PM PST 24 13005792 ps
T815 /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3447364867 Jan 14 01:43:11 PM PST 24 Jan 14 01:43:14 PM PST 24 55744393 ps
T816 /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.883918116 Jan 14 01:42:11 PM PST 24 Jan 14 02:05:13 PM PST 24 134159634383 ps
T817 /workspace/coverage/default/0.gpio_random_dout_din.1681710727 Jan 14 01:40:10 PM PST 24 Jan 14 01:40:15 PM PST 24 90747041 ps
T818 /workspace/coverage/default/1.gpio_rand_intr_trigger.2705141544 Jan 14 01:40:24 PM PST 24 Jan 14 01:40:29 PM PST 24 173853674 ps
T819 /workspace/coverage/default/37.gpio_full_random.3044958966 Jan 14 01:43:36 PM PST 24 Jan 14 01:43:37 PM PST 24 27656730 ps
T820 /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3206260225 Jan 14 01:42:36 PM PST 24 Jan 14 01:42:39 PM PST 24 293408828 ps
T821 /workspace/coverage/default/12.gpio_intr_rand_pgm.29818323 Jan 14 01:41:36 PM PST 24 Jan 14 01:41:37 PM PST 24 57734233 ps
T822 /workspace/coverage/default/3.gpio_filter_stress.1895524447 Jan 14 01:40:41 PM PST 24 Jan 14 01:40:52 PM PST 24 6504539153 ps
T823 /workspace/coverage/default/28.gpio_alert_test.1748631979 Jan 14 01:43:06 PM PST 24 Jan 14 01:43:08 PM PST 24 14332975 ps
T824 /workspace/coverage/default/46.gpio_random_dout_din.1101164706 Jan 14 01:44:09 PM PST 24 Jan 14 01:44:11 PM PST 24 30406210 ps
T825 /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.945067561 Jan 14 01:41:37 PM PST 24 Jan 14 01:46:18 PM PST 24 22293748406 ps
T826 /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3806042405 Jan 14 01:42:41 PM PST 24 Jan 14 01:42:44 PM PST 24 102242692 ps
T827 /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3222315566 Jan 14 01:43:07 PM PST 24 Jan 14 01:43:10 PM PST 24 25781532 ps
T828 /workspace/coverage/default/40.gpio_smoke.4036592602 Jan 14 01:43:43 PM PST 24 Jan 14 01:43:45 PM PST 24 54878320 ps
T829 /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3970063600 Jan 14 01:42:26 PM PST 24 Jan 14 01:42:29 PM PST 24 35532598 ps
T830 /workspace/coverage/default/33.gpio_intr_rand_pgm.2464154479 Jan 14 01:43:18 PM PST 24 Jan 14 01:43:21 PM PST 24 90304005 ps
T831 /workspace/coverage/default/7.gpio_random_dout_din.256608515 Jan 14 01:41:11 PM PST 24 Jan 14 01:41:13 PM PST 24 141672231 ps
T832 /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3049591945 Jan 14 01:42:42 PM PST 24 Jan 14 01:42:46 PM PST 24 221208677 ps
T833 /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3167259837 Jan 14 01:44:00 PM PST 24 Jan 14 01:44:02 PM PST 24 255474890 ps
T834 /workspace/coverage/default/11.gpio_smoke.2365577882 Jan 14 01:41:30 PM PST 24 Jan 14 01:41:32 PM PST 24 58832561 ps
T835 /workspace/coverage/default/15.gpio_full_random.4057013878 Jan 14 01:41:54 PM PST 24 Jan 14 01:41:55 PM PST 24 55323539 ps
T836 /workspace/coverage/default/23.gpio_alert_test.2403399217 Jan 14 01:42:34 PM PST 24 Jan 14 01:42:36 PM PST 24 38867755 ps
T837 /workspace/coverage/default/14.gpio_stress_all.3375821553 Jan 14 01:41:46 PM PST 24 Jan 14 01:43:24 PM PST 24 8279483158 ps
T838 /workspace/coverage/default/27.gpio_rand_intr_trigger.11093301 Jan 14 01:42:42 PM PST 24 Jan 14 01:42:47 PM PST 24 58530438 ps
T839 /workspace/coverage/default/4.gpio_stress_all.3427952312 Jan 14 01:40:58 PM PST 24 Jan 14 01:43:16 PM PST 24 12913829565 ps
T840 /workspace/coverage/default/24.gpio_stress_all.3620986116 Jan 14 01:42:32 PM PST 24 Jan 14 01:43:47 PM PST 24 2972576689 ps
T841 /workspace/coverage/default/40.gpio_random_dout_din.46796008 Jan 14 01:43:36 PM PST 24 Jan 14 01:43:38 PM PST 24 38828667 ps
T842 /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2102249627 Jan 14 01:43:12 PM PST 24 Jan 14 01:52:11 PM PST 24 39039259413 ps
T843 /workspace/coverage/default/44.gpio_full_random.272225809 Jan 14 01:44:03 PM PST 24 Jan 14 01:44:04 PM PST 24 149002443 ps
T844 /workspace/coverage/default/34.gpio_stress_all.746264132 Jan 14 01:43:18 PM PST 24 Jan 14 01:45:35 PM PST 24 5452305057 ps
T845 /workspace/coverage/default/33.gpio_filter_stress.852781516 Jan 14 01:43:19 PM PST 24 Jan 14 01:43:24 PM PST 24 256068301 ps
T846 /workspace/coverage/default/47.gpio_alert_test.560844269 Jan 14 01:44:11 PM PST 24 Jan 14 01:44:12 PM PST 24 40020557 ps
T847 /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.104110333 Jan 14 01:43:19 PM PST 24 Jan 14 02:07:40 PM PST 24 51603662533 ps
T848 /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3636669170 Jan 14 01:41:38 PM PST 24 Jan 14 01:41:40 PM PST 24 97416734 ps
T849 /workspace/coverage/default/49.gpio_smoke.3387218025 Jan 14 01:44:16 PM PST 24 Jan 14 01:44:18 PM PST 24 467048634 ps
T850 /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2873693906 Jan 14 01:40:50 PM PST 24 Jan 14 01:40:52 PM PST 24 32495787 ps
T851 /workspace/coverage/default/15.gpio_intr_rand_pgm.2264681568 Jan 14 01:41:53 PM PST 24 Jan 14 01:41:54 PM PST 24 68090548 ps
T852 /workspace/coverage/default/14.gpio_rand_intr_trigger.2324402618 Jan 14 01:41:44 PM PST 24 Jan 14 01:41:46 PM PST 24 32720702 ps
T853 /workspace/coverage/default/26.gpio_stress_all.3442505653 Jan 14 01:42:40 PM PST 24 Jan 14 01:45:46 PM PST 24 29255299248 ps
T854 /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1984045581 Jan 14 01:43:57 PM PST 24 Jan 14 01:43:59 PM PST 24 103995478 ps
T855 /workspace/coverage/default/23.gpio_random_dout_din.1082216797 Jan 14 01:42:29 PM PST 24 Jan 14 01:42:32 PM PST 24 324807201 ps
T856 /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1547342581 Jan 14 01:41:11 PM PST 24 Jan 14 01:41:14 PM PST 24 193054672 ps
T857 /workspace/coverage/default/15.gpio_alert_test.3234195450 Jan 14 01:41:54 PM PST 24 Jan 14 01:41:55 PM PST 24 33848013 ps
T858 /workspace/coverage/default/7.gpio_smoke.497440587 Jan 14 01:41:11 PM PST 24 Jan 14 01:41:13 PM PST 24 42412591 ps
T859 /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.4096324865 Jan 14 01:42:48 PM PST 24 Jan 14 02:09:24 PM PST 24 314587337033 ps
T860 /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3310061845 Jan 14 01:41:44 PM PST 24 Jan 14 01:41:45 PM PST 24 160931113 ps
T861 /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2601801728 Jan 14 01:41:32 PM PST 24 Jan 14 01:41:35 PM PST 24 48143471 ps
T862 /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1889966362 Jan 14 01:41:04 PM PST 24 Jan 14 01:41:06 PM PST 24 42433631 ps
T863 /workspace/coverage/default/29.gpio_stress_all.196572021 Jan 14 01:43:06 PM PST 24 Jan 14 01:46:48 PM PST 24 30639933707 ps
T864 /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.510503273 Jan 14 01:43:50 PM PST 24 Jan 14 01:43:52 PM PST 24 45669567 ps
T865 /workspace/coverage/default/11.gpio_full_random.1487171375 Jan 14 01:41:34 PM PST 24 Jan 14 01:41:36 PM PST 24 71290212 ps
T866 /workspace/coverage/default/21.gpio_random_dout_din.36422308 Jan 14 01:42:20 PM PST 24 Jan 14 01:42:25 PM PST 24 49430513 ps
T867 /workspace/coverage/default/49.gpio_stress_all.2034073468 Jan 14 01:44:15 PM PST 24 Jan 14 01:47:25 PM PST 24 68500936889 ps
T868 /workspace/coverage/default/30.gpio_alert_test.3177013100 Jan 14 01:43:09 PM PST 24 Jan 14 01:43:11 PM PST 24 14057416 ps
T869 /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.385700971 Jan 14 01:43:15 PM PST 24 Jan 14 01:43:18 PM PST 24 51298042 ps
T870 /workspace/coverage/default/33.gpio_stress_all.4260582942 Jan 14 01:43:14 PM PST 24 Jan 14 01:44:32 PM PST 24 3044664574 ps
T871 /workspace/coverage/default/35.gpio_alert_test.1596491318 Jan 14 01:43:20 PM PST 24 Jan 14 01:43:22 PM PST 24 47522989 ps
T872 /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3754764437 Jan 14 01:43:57 PM PST 24 Jan 14 01:44:03 PM PST 24 442868668 ps
T873 /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.4035277221 Jan 14 01:43:11 PM PST 24 Jan 14 01:43:15 PM PST 24 47134251 ps
T874 /workspace/coverage/default/4.gpio_rand_intr_trigger.2507386357 Jan 14 01:41:00 PM PST 24 Jan 14 01:41:04 PM PST 24 788227046 ps
T875 /workspace/coverage/default/45.gpio_rand_intr_trigger.3538780746 Jan 14 01:44:05 PM PST 24 Jan 14 01:44:09 PM PST 24 83064449 ps
T876 /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3014263537 Jan 14 01:41:04 PM PST 24 Jan 14 01:41:09 PM PST 24 259642436 ps
T877 /workspace/coverage/default/47.gpio_full_random.3326553683 Jan 14 01:44:09 PM PST 24 Jan 14 01:44:11 PM PST 24 176279964 ps
T878 /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.4169773949 Jan 14 01:43:27 PM PST 24 Jan 14 01:43:32 PM PST 24 176312218 ps
T879 /workspace/coverage/default/3.gpio_alert_test.1651559565 Jan 14 01:40:53 PM PST 24 Jan 14 01:40:54 PM PST 24 15321888 ps
T880 /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2984857399 Jan 14 01:42:37 PM PST 24 Jan 14 01:42:39 PM PST 24 49154100 ps
T881 /workspace/coverage/default/11.gpio_filter_stress.340346210 Jan 14 01:41:36 PM PST 24 Jan 14 01:41:53 PM PST 24 986061472 ps
T882 /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4150804475 Jan 14 01:41:15 PM PST 24 Jan 14 01:41:17 PM PST 24 20674079 ps
T883 /workspace/coverage/default/40.gpio_full_random.2741118645 Jan 14 01:43:52 PM PST 24 Jan 14 01:43:53 PM PST 24 64102856 ps
T884 /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2715255374 Jan 14 01:42:24 PM PST 24 Jan 14 01:42:28 PM PST 24 88337360 ps
T885 /workspace/coverage/default/41.gpio_smoke.1431385410 Jan 14 01:43:48 PM PST 24 Jan 14 01:43:50 PM PST 24 363870269 ps
T886 /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3437629980 Jan 14 01:44:06 PM PST 24 Jan 14 01:44:08 PM PST 24 120466017 ps
T887 /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1108762349 Jan 14 01:42:32 PM PST 24 Jan 14 01:54:53 PM PST 24 48445399856 ps
T888 /workspace/coverage/default/30.gpio_full_random.1425491922 Jan 14 01:43:11 PM PST 24 Jan 14 01:43:14 PM PST 24 151281082 ps
T889 /workspace/coverage/default/16.gpio_smoke.3169325559 Jan 14 01:41:55 PM PST 24 Jan 14 01:41:57 PM PST 24 67779887 ps
T890 /workspace/coverage/default/36.gpio_intr_rand_pgm.1590006297 Jan 14 01:43:22 PM PST 24 Jan 14 01:43:25 PM PST 24 122943584 ps
T891 /workspace/coverage/default/23.gpio_smoke.656592124 Jan 14 01:42:27 PM PST 24 Jan 14 01:42:29 PM PST 24 31998115 ps
T892 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2418307890 Jan 14 01:10:03 PM PST 24 Jan 14 01:10:12 PM PST 24 365504365 ps
T893 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3437332701 Jan 14 01:09:45 PM PST 24 Jan 14 01:09:55 PM PST 24 81861325 ps
T88 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2855251295 Jan 14 01:09:43 PM PST 24 Jan 14 01:09:45 PM PST 24 39478414 ps
T894 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2779004139 Jan 14 01:09:44 PM PST 24 Jan 14 01:09:47 PM PST 24 176299291 ps
T895 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3427205002 Jan 14 01:10:24 PM PST 24 Jan 14 01:10:26 PM PST 24 14442556 ps
T896 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1562961389 Jan 14 01:09:39 PM PST 24 Jan 14 01:09:41 PM PST 24 14099042 ps
T897 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2461258091 Jan 14 01:09:51 PM PST 24 Jan 14 01:09:55 PM PST 24 69870081 ps
T89 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2069198744 Jan 14 01:09:47 PM PST 24 Jan 14 01:09:54 PM PST 24 85568429 ps
T898 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1443288149 Jan 14 01:10:20 PM PST 24 Jan 14 01:10:23 PM PST 24 347476795 ps
T899 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3467548643 Jan 14 01:10:18 PM PST 24 Jan 14 01:10:20 PM PST 24 25192660 ps
T900 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.909532307 Jan 14 01:10:22 PM PST 24 Jan 14 01:10:24 PM PST 24 20995125 ps
T901 /workspace/coverage/cover_reg_top/29.gpio_intr_test.1651999911 Jan 14 01:10:25 PM PST 24 Jan 14 01:10:27 PM PST 24 19078616 ps
T90 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3767040509 Jan 14 01:10:04 PM PST 24 Jan 14 01:10:12 PM PST 24 109737026 ps
T34 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3111414417 Jan 14 01:10:11 PM PST 24 Jan 14 01:10:16 PM PST 24 42557665 ps
T91 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2290537842 Jan 14 01:09:37 PM PST 24 Jan 14 01:09:39 PM PST 24 46263813 ps
T902 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3740969316 Jan 14 01:10:13 PM PST 24 Jan 14 01:10:16 PM PST 24 26194355 ps
T98 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2012552901 Jan 14 01:09:52 PM PST 24 Jan 14 01:09:55 PM PST 24 52701755 ps
T903 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3853031972 Jan 14 01:10:27 PM PST 24 Jan 14 01:10:29 PM PST 24 30400583 ps
T904 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3434968090 Jan 14 01:09:54 PM PST 24 Jan 14 01:09:58 PM PST 24 11862143 ps
T92 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3624007067 Jan 14 01:10:23 PM PST 24 Jan 14 01:10:25 PM PST 24 13332236 ps
T905 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1592421880 Jan 14 01:09:47 PM PST 24 Jan 14 01:09:54 PM PST 24 31498141 ps
T99 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2877559748 Jan 14 01:09:45 PM PST 24 Jan 14 01:09:53 PM PST 24 35185845 ps
T906 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1611996287 Jan 14 01:10:01 PM PST 24 Jan 14 01:10:10 PM PST 24 482981633 ps
T907 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1385253676 Jan 14 01:10:27 PM PST 24 Jan 14 01:10:29 PM PST 24 17886107 ps
T908 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.186793334 Jan 14 01:09:49 PM PST 24 Jan 14 01:09:54 PM PST 24 19781609 ps
T909 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.380871488 Jan 14 01:09:56 PM PST 24 Jan 14 01:09:59 PM PST 24 25445806 ps
T910 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3307019654 Jan 14 01:10:16 PM PST 24 Jan 14 01:10:20 PM PST 24 188910891 ps
T93 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1499426117 Jan 14 01:09:47 PM PST 24 Jan 14 01:09:54 PM PST 24 14688775 ps
T94 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.303265994 Jan 14 01:10:12 PM PST 24 Jan 14 01:10:16 PM PST 24 20458323 ps
T911 /workspace/coverage/cover_reg_top/4.gpio_intr_test.198735211 Jan 14 01:09:55 PM PST 24 Jan 14 01:09:58 PM PST 24 18178000 ps
T912 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2502569892 Jan 14 01:10:01 PM PST 24 Jan 14 01:10:09 PM PST 24 12945354 ps
T95 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2375714950 Jan 14 01:09:41 PM PST 24 Jan 14 01:09:45 PM PST 24 148276836 ps
T913 /workspace/coverage/cover_reg_top/28.gpio_intr_test.3138611925 Jan 14 01:10:23 PM PST 24 Jan 14 01:10:25 PM PST 24 18720635 ps
T914 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1654714776 Jan 14 01:09:58 PM PST 24 Jan 14 01:10:01 PM PST 24 639329946 ps
T97 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.911173036 Jan 14 01:09:43 PM PST 24 Jan 14 01:09:45 PM PST 24 10818191 ps
T915 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1511007247 Jan 14 01:09:52 PM PST 24 Jan 14 01:09:55 PM PST 24 30327492 ps
T916 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3357781644 Jan 14 01:10:08 PM PST 24 Jan 14 01:10:12 PM PST 24 40509162 ps
T917 /workspace/coverage/cover_reg_top/38.gpio_intr_test.87631826 Jan 14 01:10:29 PM PST 24 Jan 14 01:10:31 PM PST 24 37029480 ps
T106 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1516001734 Jan 14 01:10:24 PM PST 24 Jan 14 01:10:26 PM PST 24 88664371 ps
T107 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1972422522 Jan 14 01:10:11 PM PST 24 Jan 14 01:10:15 PM PST 24 79838334 ps
T918 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.119819924 Jan 14 01:10:06 PM PST 24 Jan 14 01:10:13 PM PST 24 33320337 ps
T919 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2577233662 Jan 14 01:10:25 PM PST 24 Jan 14 01:10:28 PM PST 24 52710517 ps
T920 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2640188627 Jan 14 01:10:16 PM PST 24 Jan 14 01:10:18 PM PST 24 25174286 ps
T921 /workspace/coverage/cover_reg_top/21.gpio_intr_test.286715318 Jan 14 01:10:22 PM PST 24 Jan 14 01:10:23 PM PST 24 57128890 ps
T922 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.561350672 Jan 14 01:10:09 PM PST 24 Jan 14 01:10:15 PM PST 24 47566155 ps
T923 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1300751796 Jan 14 01:10:10 PM PST 24 Jan 14 01:10:15 PM PST 24 28910447 ps
T924 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3122477421 Jan 14 01:10:13 PM PST 24 Jan 14 01:10:16 PM PST 24 16163654 ps
T925 /workspace/coverage/cover_reg_top/47.gpio_intr_test.1031332124 Jan 14 01:10:27 PM PST 24 Jan 14 01:10:29 PM PST 24 22658378 ps
T926 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.131189379 Jan 14 01:10:11 PM PST 24 Jan 14 01:10:15 PM PST 24 115314418 ps
T927 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1448174360 Jan 14 01:09:38 PM PST 24 Jan 14 01:09:40 PM PST 24 15584239 ps
T928 /workspace/coverage/cover_reg_top/25.gpio_intr_test.690659295 Jan 14 01:10:27 PM PST 24 Jan 14 01:10:29 PM PST 24 51662288 ps
T929 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2442355035 Jan 14 01:10:13 PM PST 24 Jan 14 01:10:16 PM PST 24 23318485 ps
T930 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2924622758 Jan 14 01:10:25 PM PST 24 Jan 14 01:10:27 PM PST 24 29260156 ps
T931 /workspace/coverage/cover_reg_top/19.gpio_intr_test.2682920296 Jan 14 01:10:24 PM PST 24 Jan 14 01:10:26 PM PST 24 48635838 ps
T932 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1967663979 Jan 14 01:10:12 PM PST 24 Jan 14 01:10:16 PM PST 24 26204675 ps
T933 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.133742637 Jan 14 01:09:42 PM PST 24 Jan 14 01:09:47 PM PST 24 173404880 ps
T934 /workspace/coverage/cover_reg_top/27.gpio_intr_test.453813641 Jan 14 01:10:24 PM PST 24 Jan 14 01:10:26 PM PST 24 17563921 ps
T935 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3904302043 Jan 14 01:09:53 PM PST 24 Jan 14 01:09:58 PM PST 24 23975087 ps
T936 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3196206263 Jan 14 01:10:09 PM PST 24 Jan 14 01:10:15 PM PST 24 49630902 ps
T937 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1085329286 Jan 14 01:10:23 PM PST 24 Jan 14 01:10:25 PM PST 24 48822767 ps
T938 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3734761633 Jan 14 01:10:07 PM PST 24 Jan 14 01:10:13 PM PST 24 33320202 ps
T939 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3307413476 Jan 14 01:09:43 PM PST 24 Jan 14 01:09:45 PM PST 24 17966289 ps
T940 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2940649450 Jan 14 01:10:01 PM PST 24 Jan 14 01:10:09 PM PST 24 124221005 ps
T941 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2399088455 Jan 14 01:09:36 PM PST 24 Jan 14 01:09:39 PM PST 24 174748218 ps
T942 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3215733704 Jan 14 01:10:27 PM PST 24 Jan 14 01:10:29 PM PST 24 13544449 ps
T943 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1110929215 Jan 14 01:10:29 PM PST 24 Jan 14 01:10:31 PM PST 24 41424190 ps
T944 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3296159510 Jan 14 01:10:19 PM PST 24 Jan 14 01:10:20 PM PST 24 37616839 ps
T945 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1236346474 Jan 14 01:10:07 PM PST 24 Jan 14 01:10:12 PM PST 24 12470662 ps
T946 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2272501002 Jan 14 01:10:08 PM PST 24 Jan 14 01:10:14 PM PST 24 85024863 ps
T40 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2366867111 Jan 14 01:10:16 PM PST 24 Jan 14 01:10:18 PM PST 24 51178225 ps
T947 /workspace/coverage/cover_reg_top/37.gpio_intr_test.868289696 Jan 14 01:10:28 PM PST 24 Jan 14 01:10:31 PM PST 24 21243538 ps
T948 /workspace/coverage/cover_reg_top/34.gpio_intr_test.4093997031 Jan 14 01:10:27 PM PST 24 Jan 14 01:10:29 PM PST 24 15513552 ps
T949 /workspace/coverage/cover_reg_top/6.gpio_intr_test.166393551 Jan 14 01:10:08 PM PST 24 Jan 14 01:10:12 PM PST 24 13930067 ps
T950 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1197762390 Jan 14 01:10:23 PM PST 24 Jan 14 01:10:25 PM PST 24 17652684 ps
T951 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1829012270 Jan 14 01:09:59 PM PST 24 Jan 14 01:10:03 PM PST 24 18429928 ps
T952 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2417244717 Jan 14 01:10:02 PM PST 24 Jan 14 01:10:10 PM PST 24 74817343 ps
T953 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1742845512 Jan 14 01:10:07 PM PST 24 Jan 14 01:10:13 PM PST 24 247954283 ps
T954 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.574272524 Jan 14 01:10:26 PM PST 24 Jan 14 01:10:28 PM PST 24 80115418 ps
T955 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.433549451 Jan 14 01:10:11 PM PST 24 Jan 14 01:10:15 PM PST 24 21843802 ps
T956 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1421633681 Jan 14 01:10:11 PM PST 24 Jan 14 01:10:15 PM PST 24 13906253 ps
T957 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.96190588 Jan 14 01:10:22 PM PST 24 Jan 14 01:10:25 PM PST 24 232918345 ps
T958 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1814481243 Jan 14 01:10:21 PM PST 24 Jan 14 01:10:23 PM PST 24 50064837 ps
T959 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1480300394 Jan 14 01:10:07 PM PST 24 Jan 14 01:10:12 PM PST 24 22879209 ps
T960 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1411164510 Jan 14 01:09:50 PM PST 24 Jan 14 01:09:55 PM PST 24 302525614 ps
T961 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1974468831 Jan 14 01:10:26 PM PST 24 Jan 14 01:10:28 PM PST 24 13013602 ps
T962 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3698150792 Jan 14 01:10:15 PM PST 24 Jan 14 01:10:18 PM PST 24 550555589 ps
T963 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3947349132 Jan 14 01:09:42 PM PST 24 Jan 14 01:09:44 PM PST 24 171838098 ps
T964 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3444094023 Jan 14 01:10:03 PM PST 24 Jan 14 01:10:10 PM PST 24 41262519 ps
T96 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2044831677 Jan 14 01:09:44 PM PST 24 Jan 14 01:09:46 PM PST 24 14769851 ps
T965 /workspace/coverage/cover_reg_top/44.gpio_intr_test.2694969714 Jan 14 01:10:25 PM PST 24 Jan 14 01:10:27 PM PST 24 84662805 ps
T966 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3905949952 Jan 14 01:10:21 PM PST 24 Jan 14 01:10:22 PM PST 24 70319795 ps
T967 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.4051252527 Jan 14 01:10:10 PM PST 24 Jan 14 01:10:15 PM PST 24 60078206 ps
T968 /workspace/coverage/cover_reg_top/42.gpio_intr_test.507867065 Jan 14 01:10:27 PM PST 24 Jan 14 01:10:30 PM PST 24 12585353 ps
T969 /workspace/coverage/cover_reg_top/40.gpio_intr_test.233693650 Jan 14 01:10:27 PM PST 24 Jan 14 01:10:29 PM PST 24 34801238 ps
T970 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2297274525 Jan 14 01:10:14 PM PST 24 Jan 14 01:10:16 PM PST 24 17918553 ps

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3676786315
Short name T21
Test name
Test status
Simulation time 644992391 ps
CPU time 3.02 seconds
Started Jan 14 01:09:51 PM PST 24
Finished Jan 14 01:09:57 PM PST 24
Peak memory 198312 kb
Host smart-7b03cdfe-3914-48b7-8a04-acfb515eb858
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676786315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3676786315
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.491365878
Short name T42
Test name
Test status
Simulation time 133045322 ps
CPU time 1.23 seconds
Started Jan 14 01:00:10 PM PST 24
Finished Jan 14 01:00:12 PM PST 24
Peak memory 197684 kb
Host smart-50186657-26fa-4a58-83ba-05f2c7a7b1ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491365878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.491365878
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2511671520
Short name T45
Test name
Test status
Simulation time 95271288 ps
CPU time 2.23 seconds
Started Jan 14 01:42:40 PM PST 24
Finished Jan 14 01:42:44 PM PST 24
Peak memory 198264 kb
Host smart-ed7a8803-d3e6-4cf3-bfb5-0639dc317f41
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511671520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2511671520
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3751185251
Short name T23
Test name
Test status
Simulation time 400959889 ps
CPU time 1.39 seconds
Started Jan 14 01:09:44 PM PST 24
Finished Jan 14 01:09:54 PM PST 24
Peak memory 198248 kb
Host smart-8e8dfde5-4003-40cc-ad83-6eb42eefaf7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751185251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3751185251
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.712012202
Short name T52
Test name
Test status
Simulation time 64786244941 ps
CPU time 822.78 seconds
Started Jan 14 01:40:51 PM PST 24
Finished Jan 14 01:54:35 PM PST 24
Peak memory 198392 kb
Host smart-ca540dc6-8afa-48f4-bd4e-93a0a03f70c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=712012202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.712012202
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3729034843
Short name T25
Test name
Test status
Simulation time 115425932 ps
CPU time 1.45 seconds
Started Jan 14 01:10:27 PM PST 24
Finished Jan 14 01:10:30 PM PST 24
Peak memory 198328 kb
Host smart-1bab594d-731b-49eb-9cdf-42c39009c2ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729034843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3729034843
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1608105512
Short name T3
Test name
Test status
Simulation time 28395131 ps
CPU time 0.64 seconds
Started Jan 14 01:10:12 PM PST 24
Finished Jan 14 01:10:16 PM PST 24
Peak memory 197328 kb
Host smart-97d9dd73-0e32-4667-9f54-17be69f16f47
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608105512 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1608105512
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2799959994
Short name T13
Test name
Test status
Simulation time 15663853 ps
CPU time 0.62 seconds
Started Jan 14 01:10:08 PM PST 24
Finished Jan 14 01:10:12 PM PST 24
Peak memory 194740 kb
Host smart-0a4aba64-bc64-4b41-bec3-44270615a8fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799959994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2799959994
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2091825961
Short name T27
Test name
Test status
Simulation time 51256326 ps
CPU time 0.77 seconds
Started Jan 14 01:40:23 PM PST 24
Finished Jan 14 01:40:24 PM PST 24
Peak memory 213552 kb
Host smart-9c2a5c04-03f3-411f-8401-8db0453d4fc1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091825961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2091825961
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2310793372
Short name T77
Test name
Test status
Simulation time 102637983 ps
CPU time 0.72 seconds
Started Jan 14 01:09:47 PM PST 24
Finished Jan 14 01:09:55 PM PST 24
Peak memory 195980 kb
Host smart-2d2e725f-5f8c-4bb3-a6e8-e23582aa21d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310793372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2310793372
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3443839449
Short name T24
Test name
Test status
Simulation time 137284644 ps
CPU time 0.81 seconds
Started Jan 14 01:09:41 PM PST 24
Finished Jan 14 01:09:42 PM PST 24
Peak memory 197604 kb
Host smart-bc050245-d647-4ce9-968e-aac5b73f2cb5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443839449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3443839449
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3226644827
Short name T59
Test name
Test status
Simulation time 37891697 ps
CPU time 1.1 seconds
Started Jan 14 12:59:49 PM PST 24
Finished Jan 14 12:59:51 PM PST 24
Peak memory 196172 kb
Host smart-a58e2e87-4632-4dcb-9fc2-99cb413c5231
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3226644827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3226644827
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1414533276
Short name T4
Test name
Test status
Simulation time 28271936 ps
CPU time 0.77 seconds
Started Jan 14 01:10:11 PM PST 24
Finished Jan 14 01:10:15 PM PST 24
Peak memory 195276 kb
Host smart-898ec02c-5b2e-4a82-b8e2-c7948d2bbdde
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414533276 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1414533276
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1677851136
Short name T39
Test name
Test status
Simulation time 124269477 ps
CPU time 1.43 seconds
Started Jan 14 01:09:38 PM PST 24
Finished Jan 14 01:09:40 PM PST 24
Peak memory 198260 kb
Host smart-48ccdc0f-b5f0-4103-8ca5-8c4b497640e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677851136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1677851136
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1280802454
Short name T235
Test name
Test status
Simulation time 14457656 ps
CPU time 0.55 seconds
Started Jan 14 01:41:35 PM PST 24
Finished Jan 14 01:41:36 PM PST 24
Peak memory 194012 kb
Host smart-ca90f222-c642-45db-9a80-df1a12ef5d41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280802454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1280802454
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2877182535
Short name T31
Test name
Test status
Simulation time 119369713 ps
CPU time 1.73 seconds
Started Jan 14 01:09:45 PM PST 24
Finished Jan 14 01:09:55 PM PST 24
Peak memory 198280 kb
Host smart-d14c46c9-afad-43a8-8a54-7e523d68885d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877182535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2877182535
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1311791615
Short name T119
Test name
Test status
Simulation time 42187530 ps
CPU time 0.62 seconds
Started Jan 14 01:09:45 PM PST 24
Finished Jan 14 01:09:53 PM PST 24
Peak memory 193952 kb
Host smart-ef87433d-c35d-4508-bbc3-1169543c79b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311791615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1311791615
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2044831677
Short name T96
Test name
Test status
Simulation time 14769851 ps
CPU time 0.71 seconds
Started Jan 14 01:09:44 PM PST 24
Finished Jan 14 01:09:46 PM PST 24
Peak memory 195864 kb
Host smart-d9c967c7-d3de-49df-ae57-06f6e23bf119
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044831677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2044831677
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1588398322
Short name T122
Test name
Test status
Simulation time 1262238444 ps
CPU time 3.27 seconds
Started Jan 14 01:09:36 PM PST 24
Finished Jan 14 01:09:39 PM PST 24
Peak memory 198240 kb
Host smart-30abacf2-794c-42ef-8050-69fbc9ac7ae8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588398322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1588398322
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1499426117
Short name T93
Test name
Test status
Simulation time 14688775 ps
CPU time 0.63 seconds
Started Jan 14 01:09:47 PM PST 24
Finished Jan 14 01:09:54 PM PST 24
Peak memory 194536 kb
Host smart-650353b9-3b03-45bf-a312-9e346fe29615
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499426117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1499426117
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3617434912
Short name T10
Test name
Test status
Simulation time 64172799 ps
CPU time 0.64 seconds
Started Jan 14 01:09:35 PM PST 24
Finished Jan 14 01:09:36 PM PST 24
Peak memory 197024 kb
Host smart-22a91cfd-1814-4f9c-9d59-be5ecafbd3e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617434912 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3617434912
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1938265637
Short name T78
Test name
Test status
Simulation time 12200334 ps
CPU time 0.64 seconds
Started Jan 14 01:09:38 PM PST 24
Finished Jan 14 01:09:40 PM PST 24
Peak memory 194992 kb
Host smart-3697a402-e057-4ca7-86e1-754f68afd51e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938265637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1938265637
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3307413476
Short name T939
Test name
Test status
Simulation time 17966289 ps
CPU time 0.65 seconds
Started Jan 14 01:09:43 PM PST 24
Finished Jan 14 01:09:45 PM PST 24
Peak memory 195844 kb
Host smart-f3ca773e-446b-4d3b-a9a3-38ee4ce7f407
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307413476 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3307413476
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2290537842
Short name T91
Test name
Test status
Simulation time 46263813 ps
CPU time 0.72 seconds
Started Jan 14 01:09:37 PM PST 24
Finished Jan 14 01:09:39 PM PST 24
Peak memory 196212 kb
Host smart-4d4f9bc6-e377-4215-a554-54523b8da0ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290537842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2290537842
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2399088455
Short name T941
Test name
Test status
Simulation time 174748218 ps
CPU time 2.37 seconds
Started Jan 14 01:09:36 PM PST 24
Finished Jan 14 01:09:39 PM PST 24
Peak memory 197292 kb
Host smart-c970f321-974a-4dca-bdff-81ab51d385cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399088455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2399088455
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2069198744
Short name T89
Test name
Test status
Simulation time 85568429 ps
CPU time 0.63 seconds
Started Jan 14 01:09:47 PM PST 24
Finished Jan 14 01:09:54 PM PST 24
Peak memory 193976 kb
Host smart-af7035f9-935b-42a3-9862-5181dac5c837
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069198744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2069198744
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3437332701
Short name T893
Test name
Test status
Simulation time 81861325 ps
CPU time 0.8 seconds
Started Jan 14 01:09:45 PM PST 24
Finished Jan 14 01:09:55 PM PST 24
Peak memory 198120 kb
Host smart-33c8c61b-4e6a-4659-a31c-63954fd92824
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437332701 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3437332701
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1592421880
Short name T905
Test name
Test status
Simulation time 31498141 ps
CPU time 0.57 seconds
Started Jan 14 01:09:47 PM PST 24
Finished Jan 14 01:09:54 PM PST 24
Peak memory 194716 kb
Host smart-2fecd8f2-c3b0-490a-ab38-4b4231032ce1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592421880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1592421880
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1236376251
Short name T118
Test name
Test status
Simulation time 15084494 ps
CPU time 0.58 seconds
Started Jan 14 01:09:47 PM PST 24
Finished Jan 14 01:09:54 PM PST 24
Peak memory 194024 kb
Host smart-06930b72-4960-4c8e-a826-39383986880a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236376251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1236376251
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2877559748
Short name T99
Test name
Test status
Simulation time 35185845 ps
CPU time 0.63 seconds
Started Jan 14 01:09:45 PM PST 24
Finished Jan 14 01:09:53 PM PST 24
Peak memory 194920 kb
Host smart-0c857eda-3dc5-416f-b346-80d7528ddc58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877559748 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2877559748
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2779004139
Short name T894
Test name
Test status
Simulation time 176299291 ps
CPU time 1.43 seconds
Started Jan 14 01:09:44 PM PST 24
Finished Jan 14 01:09:47 PM PST 24
Peak memory 198304 kb
Host smart-85c42545-56c6-4a7f-a683-d4ebf420e87b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779004139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2779004139
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2842538095
Short name T74
Test name
Test status
Simulation time 21993137 ps
CPU time 1.05 seconds
Started Jan 14 01:10:12 PM PST 24
Finished Jan 14 01:10:16 PM PST 24
Peak memory 198376 kb
Host smart-2145aa12-37f0-47e9-a504-f2bb25b33190
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842538095 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2842538095
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3357781644
Short name T916
Test name
Test status
Simulation time 40509162 ps
CPU time 0.58 seconds
Started Jan 14 01:10:08 PM PST 24
Finished Jan 14 01:10:12 PM PST 24
Peak memory 195468 kb
Host smart-11989942-6947-4ac3-9189-2ed7300495d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357781644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3357781644
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1236346474
Short name T945
Test name
Test status
Simulation time 12470662 ps
CPU time 0.57 seconds
Started Jan 14 01:10:07 PM PST 24
Finished Jan 14 01:10:12 PM PST 24
Peak memory 194692 kb
Host smart-d84d5f51-3f58-4a63-ba3c-397e4105af5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236346474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1236346474
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1300751796
Short name T923
Test name
Test status
Simulation time 28910447 ps
CPU time 0.79 seconds
Started Jan 14 01:10:10 PM PST 24
Finished Jan 14 01:10:15 PM PST 24
Peak memory 196456 kb
Host smart-ad1dbb8e-0c70-4682-8d2a-169566a2647a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300751796 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1300751796
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3029402044
Short name T41
Test name
Test status
Simulation time 131821509 ps
CPU time 1.98 seconds
Started Jan 14 01:10:07 PM PST 24
Finished Jan 14 01:10:14 PM PST 24
Peak memory 198312 kb
Host smart-b3991d42-7a36-4d68-ab59-3fd92041ff43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029402044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3029402044
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1972422522
Short name T107
Test name
Test status
Simulation time 79838334 ps
CPU time 0.85 seconds
Started Jan 14 01:10:11 PM PST 24
Finished Jan 14 01:10:15 PM PST 24
Peak memory 197248 kb
Host smart-3b3c3723-1f63-4560-b824-07ca995b5624
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972422522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1972422522
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3734761633
Short name T938
Test name
Test status
Simulation time 33320202 ps
CPU time 1 seconds
Started Jan 14 01:10:07 PM PST 24
Finished Jan 14 01:10:13 PM PST 24
Peak memory 198208 kb
Host smart-fcd7ec6c-f008-4210-8b9d-3cce01cae106
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734761633 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3734761633
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.433549451
Short name T955
Test name
Test status
Simulation time 21843802 ps
CPU time 0.58 seconds
Started Jan 14 01:10:11 PM PST 24
Finished Jan 14 01:10:15 PM PST 24
Peak memory 194880 kb
Host smart-3ae0a5c5-84e5-4b28-b730-8cc1001cb6b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433549451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.433549451
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2442355035
Short name T929
Test name
Test status
Simulation time 23318485 ps
CPU time 0.59 seconds
Started Jan 14 01:10:13 PM PST 24
Finished Jan 14 01:10:16 PM PST 24
Peak memory 194028 kb
Host smart-10202f4f-5bcc-4254-96bf-dd8cca3976e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442355035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2442355035
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.631423600
Short name T132
Test name
Test status
Simulation time 290978307 ps
CPU time 2.59 seconds
Started Jan 14 01:10:09 PM PST 24
Finished Jan 14 01:10:14 PM PST 24
Peak memory 198488 kb
Host smart-fd74b6ec-70e2-46b1-be42-8b3f4df97f82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631423600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.631423600
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2366867111
Short name T40
Test name
Test status
Simulation time 51178225 ps
CPU time 0.88 seconds
Started Jan 14 01:10:16 PM PST 24
Finished Jan 14 01:10:18 PM PST 24
Peak memory 197504 kb
Host smart-e5b40d75-07de-41a5-9be3-19dabc12781a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366867111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2366867111
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.303265994
Short name T94
Test name
Test status
Simulation time 20458323 ps
CPU time 0.61 seconds
Started Jan 14 01:10:12 PM PST 24
Finished Jan 14 01:10:16 PM PST 24
Peak memory 195072 kb
Host smart-d56d9a53-d064-402c-a1f0-ab21c4743e0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303265994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.303265994
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1421633681
Short name T956
Test name
Test status
Simulation time 13906253 ps
CPU time 0.57 seconds
Started Jan 14 01:10:11 PM PST 24
Finished Jan 14 01:10:15 PM PST 24
Peak memory 194656 kb
Host smart-71f0f2c8-9f14-4b6f-8566-8f873a920ca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421633681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1421633681
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.131189379
Short name T926
Test name
Test status
Simulation time 115314418 ps
CPU time 0.8 seconds
Started Jan 14 01:10:11 PM PST 24
Finished Jan 14 01:10:15 PM PST 24
Peak memory 196572 kb
Host smart-f1707b12-3ff4-4898-8a47-57ca95b2b5e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131189379 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.131189379
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3307019654
Short name T910
Test name
Test status
Simulation time 188910891 ps
CPU time 3.11 seconds
Started Jan 14 01:10:16 PM PST 24
Finished Jan 14 01:10:20 PM PST 24
Peak memory 198408 kb
Host smart-8258ef4d-63a0-46a8-b446-cd4a96471932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307019654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3307019654
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2635491208
Short name T35
Test name
Test status
Simulation time 231224169 ps
CPU time 1.37 seconds
Started Jan 14 01:10:17 PM PST 24
Finished Jan 14 01:10:19 PM PST 24
Peak memory 198392 kb
Host smart-9637068f-08e4-44a3-aa6a-aad8b5434f95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635491208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2635491208
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2640188627
Short name T920
Test name
Test status
Simulation time 25174286 ps
CPU time 0.78 seconds
Started Jan 14 01:10:16 PM PST 24
Finished Jan 14 01:10:18 PM PST 24
Peak memory 198144 kb
Host smart-b8915ed4-ffc1-487f-9df8-60131209f48c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640188627 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2640188627
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3122477421
Short name T924
Test name
Test status
Simulation time 16163654 ps
CPU time 0.59 seconds
Started Jan 14 01:10:13 PM PST 24
Finished Jan 14 01:10:16 PM PST 24
Peak memory 195128 kb
Host smart-0600f550-5290-418e-b57c-1f4d57b44755
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122477421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3122477421
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1967663979
Short name T932
Test name
Test status
Simulation time 26204675 ps
CPU time 0.62 seconds
Started Jan 14 01:10:12 PM PST 24
Finished Jan 14 01:10:16 PM PST 24
Peak memory 194116 kb
Host smart-0e3461e0-f6a9-4622-9fdc-d61433a5dcbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967663979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1967663979
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1725291453
Short name T8
Test name
Test status
Simulation time 92297314 ps
CPU time 0.72 seconds
Started Jan 14 01:10:12 PM PST 24
Finished Jan 14 01:10:16 PM PST 24
Peak memory 195256 kb
Host smart-a22b909c-6e16-48ac-86d5-90b8a03f263b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725291453 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1725291453
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1913834258
Short name T16
Test name
Test status
Simulation time 96530869 ps
CPU time 1.5 seconds
Started Jan 14 01:10:18 PM PST 24
Finished Jan 14 01:10:20 PM PST 24
Peak memory 198456 kb
Host smart-b6446852-0265-4071-a4db-787dedccc23c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913834258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1913834258
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3698150792
Short name T962
Test name
Test status
Simulation time 550555589 ps
CPU time 1.39 seconds
Started Jan 14 01:10:15 PM PST 24
Finished Jan 14 01:10:18 PM PST 24
Peak memory 198268 kb
Host smart-e34f803b-fc92-4ead-b3d1-50e1b840fa15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698150792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3698150792
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3905949952
Short name T966
Test name
Test status
Simulation time 70319795 ps
CPU time 0.74 seconds
Started Jan 14 01:10:21 PM PST 24
Finished Jan 14 01:10:22 PM PST 24
Peak memory 197940 kb
Host smart-ef1e1cbf-76d3-4f27-adb2-841b3bb900bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905949952 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3905949952
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3740969316
Short name T902
Test name
Test status
Simulation time 26194355 ps
CPU time 0.61 seconds
Started Jan 14 01:10:13 PM PST 24
Finished Jan 14 01:10:16 PM PST 24
Peak memory 195136 kb
Host smart-4d93928c-8ec2-47f9-a001-7d30b5e9a534
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740969316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3740969316
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1415921092
Short name T129
Test name
Test status
Simulation time 26984233 ps
CPU time 0.6 seconds
Started Jan 14 01:10:23 PM PST 24
Finished Jan 14 01:10:25 PM PST 24
Peak memory 194772 kb
Host smart-78b35ce6-4c92-40b4-9b4a-ad950e67d794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415921092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1415921092
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2297274525
Short name T970
Test name
Test status
Simulation time 17918553 ps
CPU time 0.82 seconds
Started Jan 14 01:10:14 PM PST 24
Finished Jan 14 01:10:16 PM PST 24
Peak memory 196632 kb
Host smart-3f04dda5-5234-47dd-bcee-3a1c39289da4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297274525 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2297274525
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3428248398
Short name T20
Test name
Test status
Simulation time 551846857 ps
CPU time 1.75 seconds
Started Jan 14 01:10:21 PM PST 24
Finished Jan 14 01:10:24 PM PST 24
Peak memory 198312 kb
Host smart-3070946a-8e7d-4edd-a224-1e45da56c9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428248398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3428248398
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2652792099
Short name T26
Test name
Test status
Simulation time 132233826 ps
CPU time 1.44 seconds
Started Jan 14 01:10:13 PM PST 24
Finished Jan 14 01:10:17 PM PST 24
Peak memory 198260 kb
Host smart-fc3e96aa-64a4-449b-8d1f-ddc3e8e2d268
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652792099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2652792099
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3467548643
Short name T899
Test name
Test status
Simulation time 25192660 ps
CPU time 0.79 seconds
Started Jan 14 01:10:18 PM PST 24
Finished Jan 14 01:10:20 PM PST 24
Peak memory 198196 kb
Host smart-5c680a17-9ae2-46bc-945c-44246197d0a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467548643 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3467548643
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3674629545
Short name T51
Test name
Test status
Simulation time 82181162 ps
CPU time 0.63 seconds
Started Jan 14 01:10:17 PM PST 24
Finished Jan 14 01:10:18 PM PST 24
Peak memory 195176 kb
Host smart-902afe61-38ad-4ab7-8888-37e9ff1c1a9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674629545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3674629545
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3296159510
Short name T944
Test name
Test status
Simulation time 37616839 ps
CPU time 0.56 seconds
Started Jan 14 01:10:19 PM PST 24
Finished Jan 14 01:10:20 PM PST 24
Peak memory 194040 kb
Host smart-b25ea357-82e1-49c4-a005-d776769b7f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296159510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3296159510
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3099925746
Short name T80
Test name
Test status
Simulation time 147662403 ps
CPU time 0.85 seconds
Started Jan 14 01:10:14 PM PST 24
Finished Jan 14 01:10:17 PM PST 24
Peak memory 197832 kb
Host smart-ffa44c34-7d33-49f5-8382-fcf3cdaf8462
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099925746 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3099925746
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.304673526
Short name T2
Test name
Test status
Simulation time 98783929 ps
CPU time 1.22 seconds
Started Jan 14 01:10:21 PM PST 24
Finished Jan 14 01:10:24 PM PST 24
Peak memory 198368 kb
Host smart-ed530192-c6d4-455c-a130-6aa723d57840
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304673526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.304673526
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3884361274
Short name T7
Test name
Test status
Simulation time 87069233 ps
CPU time 1.16 seconds
Started Jan 14 01:10:16 PM PST 24
Finished Jan 14 01:10:18 PM PST 24
Peak memory 198316 kb
Host smart-64b808de-63c7-4734-bce6-a8cf034638dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884361274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3884361274
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2203966441
Short name T17
Test name
Test status
Simulation time 34168029 ps
CPU time 0.78 seconds
Started Jan 14 01:10:22 PM PST 24
Finished Jan 14 01:10:23 PM PST 24
Peak memory 198280 kb
Host smart-d8df5330-73a4-4f7f-ac69-287189cc50e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203966441 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2203966441
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3533365188
Short name T100
Test name
Test status
Simulation time 22106768 ps
CPU time 0.65 seconds
Started Jan 14 01:10:20 PM PST 24
Finished Jan 14 01:10:21 PM PST 24
Peak memory 195060 kb
Host smart-c105ab4a-a204-476e-98fb-365291e057f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533365188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3533365188
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1758111936
Short name T15
Test name
Test status
Simulation time 93177633 ps
CPU time 0.62 seconds
Started Jan 14 01:10:22 PM PST 24
Finished Jan 14 01:10:23 PM PST 24
Peak memory 193996 kb
Host smart-5b5392f0-7222-4634-8ffd-372b40c978ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758111936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1758111936
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3198412348
Short name T75
Test name
Test status
Simulation time 47021066 ps
CPU time 0.64 seconds
Started Jan 14 01:10:16 PM PST 24
Finished Jan 14 01:10:18 PM PST 24
Peak memory 194984 kb
Host smart-2d90ca8e-fd32-4661-b66c-d778ccd7e02b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198412348 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3198412348
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3014186613
Short name T128
Test name
Test status
Simulation time 26085009 ps
CPU time 1.28 seconds
Started Jan 14 01:10:23 PM PST 24
Finished Jan 14 01:10:26 PM PST 24
Peak memory 198308 kb
Host smart-3cc764bc-c2e0-463c-8d12-c6512dcb3e73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014186613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3014186613
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.574272524
Short name T954
Test name
Test status
Simulation time 80115418 ps
CPU time 0.87 seconds
Started Jan 14 01:10:26 PM PST 24
Finished Jan 14 01:10:28 PM PST 24
Peak memory 197220 kb
Host smart-fdc17e57-331e-4c02-918d-f03cded627ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574272524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.574272524
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.4239342143
Short name T83
Test name
Test status
Simulation time 29890182 ps
CPU time 1.22 seconds
Started Jan 14 01:10:19 PM PST 24
Finished Jan 14 01:10:21 PM PST 24
Peak memory 198432 kb
Host smart-d4111ce8-8b8d-47fa-9c6c-24c03b91f6bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239342143 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.4239342143
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3624007067
Short name T92
Test name
Test status
Simulation time 13332236 ps
CPU time 0.62 seconds
Started Jan 14 01:10:23 PM PST 24
Finished Jan 14 01:10:25 PM PST 24
Peak memory 195628 kb
Host smart-cb661b4b-e385-46b4-8483-739a05dbb620
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624007067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3624007067
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1085329286
Short name T937
Test name
Test status
Simulation time 48822767 ps
CPU time 0.62 seconds
Started Jan 14 01:10:23 PM PST 24
Finished Jan 14 01:10:25 PM PST 24
Peak memory 193992 kb
Host smart-05c24b21-af5c-4170-afe9-b33f0cd0c33f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085329286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1085329286
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2078466971
Short name T84
Test name
Test status
Simulation time 101591556 ps
CPU time 0.68 seconds
Started Jan 14 01:10:21 PM PST 24
Finished Jan 14 01:10:23 PM PST 24
Peak memory 195680 kb
Host smart-36323246-bd97-41a4-9182-7f57ad3f2cb4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078466971 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2078466971
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1443288149
Short name T898
Test name
Test status
Simulation time 347476795 ps
CPU time 2.11 seconds
Started Jan 14 01:10:20 PM PST 24
Finished Jan 14 01:10:23 PM PST 24
Peak memory 198412 kb
Host smart-6fa2e60e-e84b-4802-943a-708c02587be1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443288149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1443288149
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.96190588
Short name T957
Test name
Test status
Simulation time 232918345 ps
CPU time 1.53 seconds
Started Jan 14 01:10:22 PM PST 24
Finished Jan 14 01:10:25 PM PST 24
Peak memory 198332 kb
Host smart-271ef036-ad60-449e-9f84-f0bc47104b92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96190588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
17.gpio_tl_intg_err.96190588
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.491852318
Short name T111
Test name
Test status
Simulation time 14949551 ps
CPU time 0.76 seconds
Started Jan 14 01:10:24 PM PST 24
Finished Jan 14 01:10:26 PM PST 24
Peak memory 198144 kb
Host smart-79d7e705-d4bb-48aa-a346-718db384f59e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491852318 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.491852318
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2690475724
Short name T101
Test name
Test status
Simulation time 13998364 ps
CPU time 0.58 seconds
Started Jan 14 01:10:26 PM PST 24
Finished Jan 14 01:10:28 PM PST 24
Peak memory 193704 kb
Host smart-79995101-45ba-49e0-8aa4-2bf5a43e36a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690475724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2690475724
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2566002276
Short name T82
Test name
Test status
Simulation time 43407373 ps
CPU time 0.58 seconds
Started Jan 14 01:10:26 PM PST 24
Finished Jan 14 01:10:28 PM PST 24
Peak memory 193980 kb
Host smart-037d045e-ce5e-47fe-bd68-923d71b32f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566002276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2566002276
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2021757869
Short name T5
Test name
Test status
Simulation time 142343570 ps
CPU time 0.84 seconds
Started Jan 14 01:10:24 PM PST 24
Finished Jan 14 01:10:27 PM PST 24
Peak memory 196452 kb
Host smart-daf4d7e4-3848-4e0a-954b-96844916479b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021757869 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2021757869
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.4039607936
Short name T81
Test name
Test status
Simulation time 120869575 ps
CPU time 1.51 seconds
Started Jan 14 01:10:19 PM PST 24
Finished Jan 14 01:10:21 PM PST 24
Peak memory 198400 kb
Host smart-e22a164b-1edb-46fd-86e2-b3758a75b61c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039607936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.4039607936
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1516001734
Short name T106
Test name
Test status
Simulation time 88664371 ps
CPU time 1.18 seconds
Started Jan 14 01:10:24 PM PST 24
Finished Jan 14 01:10:26 PM PST 24
Peak memory 198276 kb
Host smart-541ec5ae-3cbd-4ef0-b2b9-a227020c5648
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516001734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1516001734
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.909532307
Short name T900
Test name
Test status
Simulation time 20995125 ps
CPU time 0.66 seconds
Started Jan 14 01:10:22 PM PST 24
Finished Jan 14 01:10:24 PM PST 24
Peak memory 197340 kb
Host smart-bac47195-52ff-4a92-ac39-f15f6e6081f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909532307 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.909532307
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3427205002
Short name T895
Test name
Test status
Simulation time 14442556 ps
CPU time 0.62 seconds
Started Jan 14 01:10:24 PM PST 24
Finished Jan 14 01:10:26 PM PST 24
Peak memory 195008 kb
Host smart-f1ce333b-97e9-42d8-afa3-abd76a2f753b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427205002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3427205002
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2682920296
Short name T931
Test name
Test status
Simulation time 48635838 ps
CPU time 0.61 seconds
Started Jan 14 01:10:24 PM PST 24
Finished Jan 14 01:10:26 PM PST 24
Peak memory 194092 kb
Host smart-8b1b90bf-ab38-4307-afbe-fe1d9fe7c74f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682920296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2682920296
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1814481243
Short name T958
Test name
Test status
Simulation time 50064837 ps
CPU time 0.7 seconds
Started Jan 14 01:10:21 PM PST 24
Finished Jan 14 01:10:23 PM PST 24
Peak memory 196272 kb
Host smart-6f689ec2-82c7-456f-86ad-678ebe3db921
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814481243 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1814481243
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2577233662
Short name T919
Test name
Test status
Simulation time 52710517 ps
CPU time 0.86 seconds
Started Jan 14 01:10:25 PM PST 24
Finished Jan 14 01:10:28 PM PST 24
Peak memory 197276 kb
Host smart-88314d38-fcaa-46e8-865f-4385ad8ce7c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577233662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2577233662
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2375714950
Short name T95
Test name
Test status
Simulation time 148276836 ps
CPU time 3.03 seconds
Started Jan 14 01:09:41 PM PST 24
Finished Jan 14 01:09:45 PM PST 24
Peak memory 198332 kb
Host smart-de9ef2d4-02bb-4fe9-9855-3f6980375f70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375714950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2375714950
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2855251295
Short name T88
Test name
Test status
Simulation time 39478414 ps
CPU time 0.58 seconds
Started Jan 14 01:09:43 PM PST 24
Finished Jan 14 01:09:45 PM PST 24
Peak memory 194996 kb
Host smart-bd8a40e0-e839-4f83-b438-05043d8fd3ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855251295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2855251295
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3947349132
Short name T963
Test name
Test status
Simulation time 171838098 ps
CPU time 0.87 seconds
Started Jan 14 01:09:42 PM PST 24
Finished Jan 14 01:09:44 PM PST 24
Peak memory 198272 kb
Host smart-baaad9e1-a015-4b58-ac6d-fbd44d1138df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947349132 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3947349132
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1448174360
Short name T927
Test name
Test status
Simulation time 15584239 ps
CPU time 0.61 seconds
Started Jan 14 01:09:38 PM PST 24
Finished Jan 14 01:09:40 PM PST 24
Peak memory 195000 kb
Host smart-15f620fb-b147-4dce-806c-558116ac6229
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448174360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1448174360
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1562961389
Short name T896
Test name
Test status
Simulation time 14099042 ps
CPU time 0.58 seconds
Started Jan 14 01:09:39 PM PST 24
Finished Jan 14 01:09:41 PM PST 24
Peak memory 193864 kb
Host smart-63871bac-a86a-4071-b1d8-c087d5914ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562961389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1562961389
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3427798872
Short name T9
Test name
Test status
Simulation time 39091535 ps
CPU time 0.86 seconds
Started Jan 14 01:09:39 PM PST 24
Finished Jan 14 01:09:40 PM PST 24
Peak memory 197152 kb
Host smart-75f1a2a4-0aa2-43b9-b8ca-fb206c5287bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427798872 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3427798872
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.133742637
Short name T933
Test name
Test status
Simulation time 173404880 ps
CPU time 2.93 seconds
Started Jan 14 01:09:42 PM PST 24
Finished Jan 14 01:09:47 PM PST 24
Peak memory 198492 kb
Host smart-070ff2cb-5381-4026-929f-324403fcfcbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133742637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.133742637
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3863788237
Short name T123
Test name
Test status
Simulation time 28752755 ps
CPU time 0.61 seconds
Started Jan 14 01:10:23 PM PST 24
Finished Jan 14 01:10:25 PM PST 24
Peak memory 193944 kb
Host smart-beda587f-8ee2-4d37-9019-6c1091ff8adb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863788237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3863788237
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.286715318
Short name T921
Test name
Test status
Simulation time 57128890 ps
CPU time 0.6 seconds
Started Jan 14 01:10:22 PM PST 24
Finished Jan 14 01:10:23 PM PST 24
Peak memory 194008 kb
Host smart-3da82024-c9f1-4269-b6e0-76f40c63abc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286715318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.286715318
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1931536622
Short name T121
Test name
Test status
Simulation time 23330127 ps
CPU time 0.57 seconds
Started Jan 14 01:10:24 PM PST 24
Finished Jan 14 01:10:26 PM PST 24
Peak memory 194668 kb
Host smart-82f09a51-83ae-455a-8133-d93c8a79a826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931536622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1931536622
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1197762390
Short name T950
Test name
Test status
Simulation time 17652684 ps
CPU time 0.63 seconds
Started Jan 14 01:10:23 PM PST 24
Finished Jan 14 01:10:25 PM PST 24
Peak memory 194124 kb
Host smart-a05757ca-3c7c-4100-9a0c-2a0a4a92a3c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197762390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1197762390
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1526450763
Short name T131
Test name
Test status
Simulation time 14462205 ps
CPU time 0.56 seconds
Started Jan 14 01:10:26 PM PST 24
Finished Jan 14 01:10:28 PM PST 24
Peak memory 193876 kb
Host smart-fd3676f1-d3f4-4b5d-afd2-b148e219ee96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526450763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1526450763
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.690659295
Short name T928
Test name
Test status
Simulation time 51662288 ps
CPU time 0.59 seconds
Started Jan 14 01:10:27 PM PST 24
Finished Jan 14 01:10:29 PM PST 24
Peak memory 193912 kb
Host smart-f03f7e40-414f-4437-803c-7f50b6dca999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690659295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.690659295
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3853031972
Short name T903
Test name
Test status
Simulation time 30400583 ps
CPU time 0.61 seconds
Started Jan 14 01:10:27 PM PST 24
Finished Jan 14 01:10:29 PM PST 24
Peak memory 194144 kb
Host smart-079215f6-11b1-414e-8a5c-b164baf60b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853031972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3853031972
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.453813641
Short name T934
Test name
Test status
Simulation time 17563921 ps
CPU time 0.63 seconds
Started Jan 14 01:10:24 PM PST 24
Finished Jan 14 01:10:26 PM PST 24
Peak memory 194696 kb
Host smart-27966162-5d73-4aac-b76f-48a3ff7bc2d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453813641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.453813641
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3138611925
Short name T913
Test name
Test status
Simulation time 18720635 ps
CPU time 0.59 seconds
Started Jan 14 01:10:23 PM PST 24
Finished Jan 14 01:10:25 PM PST 24
Peak memory 194700 kb
Host smart-647fb50a-6cd2-4295-a54b-f9d8f4107046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138611925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3138611925
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1651999911
Short name T901
Test name
Test status
Simulation time 19078616 ps
CPU time 0.59 seconds
Started Jan 14 01:10:25 PM PST 24
Finished Jan 14 01:10:27 PM PST 24
Peak memory 194708 kb
Host smart-18176284-e619-4c61-b1b2-3d7abe17e651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651999911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1651999911
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1511007247
Short name T915
Test name
Test status
Simulation time 30327492 ps
CPU time 0.83 seconds
Started Jan 14 01:09:52 PM PST 24
Finished Jan 14 01:09:55 PM PST 24
Peak memory 195824 kb
Host smart-d9ba45f9-2ad1-4137-bbe1-03d4c43d1d7c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511007247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1511007247
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3434968090
Short name T904
Test name
Test status
Simulation time 11862143 ps
CPU time 0.6 seconds
Started Jan 14 01:09:54 PM PST 24
Finished Jan 14 01:09:58 PM PST 24
Peak memory 194784 kb
Host smart-704f3eb8-549a-4c21-a8f4-074a40f1070c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434968090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3434968090
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3575628858
Short name T18
Test name
Test status
Simulation time 71169597 ps
CPU time 0.73 seconds
Started Jan 14 01:09:50 PM PST 24
Finished Jan 14 01:09:55 PM PST 24
Peak memory 198152 kb
Host smart-b3b421bf-6503-4eb1-b604-ca0fc804d8c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575628858 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3575628858
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.911173036
Short name T97
Test name
Test status
Simulation time 10818191 ps
CPU time 0.59 seconds
Started Jan 14 01:09:43 PM PST 24
Finished Jan 14 01:09:45 PM PST 24
Peak memory 194956 kb
Host smart-da489afa-4835-4d9d-b8bc-41721ce1d640
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911173036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.911173036
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2461258091
Short name T897
Test name
Test status
Simulation time 69870081 ps
CPU time 0.59 seconds
Started Jan 14 01:09:51 PM PST 24
Finished Jan 14 01:09:55 PM PST 24
Peak memory 193936 kb
Host smart-2f4b5579-03a0-453f-9927-eedfa0cdd68f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461258091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2461258091
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2012552901
Short name T98
Test name
Test status
Simulation time 52701755 ps
CPU time 0.71 seconds
Started Jan 14 01:09:52 PM PST 24
Finished Jan 14 01:09:55 PM PST 24
Peak memory 195304 kb
Host smart-d1a87280-a989-4ec3-a341-e4e03e469e1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012552901 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2012552901
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3627953765
Short name T33
Test name
Test status
Simulation time 144477729 ps
CPU time 1.31 seconds
Started Jan 14 01:09:49 PM PST 24
Finished Jan 14 01:09:56 PM PST 24
Peak memory 198312 kb
Host smart-d4539a0c-9795-4534-8fd1-4bc77cb54ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627953765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3627953765
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1882787726
Short name T116
Test name
Test status
Simulation time 74553849 ps
CPU time 1.22 seconds
Started Jan 14 01:09:50 PM PST 24
Finished Jan 14 01:09:55 PM PST 24
Peak memory 198464 kb
Host smart-cbe894ef-c0e6-4bec-9246-b2f736e57e7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882787726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1882787726
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1974468831
Short name T961
Test name
Test status
Simulation time 13013602 ps
CPU time 0.64 seconds
Started Jan 14 01:10:26 PM PST 24
Finished Jan 14 01:10:28 PM PST 24
Peak memory 194156 kb
Host smart-595116f4-525a-472b-af15-cda40046eaee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974468831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1974468831
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.959873324
Short name T124
Test name
Test status
Simulation time 50344505 ps
CPU time 0.63 seconds
Started Jan 14 01:10:29 PM PST 24
Finished Jan 14 01:10:31 PM PST 24
Peak memory 194216 kb
Host smart-6a50e660-029c-4599-ad25-be050965e186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959873324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.959873324
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2962091509
Short name T73
Test name
Test status
Simulation time 73494291 ps
CPU time 0.58 seconds
Started Jan 14 01:10:26 PM PST 24
Finished Jan 14 01:10:28 PM PST 24
Peak memory 193920 kb
Host smart-88a6c35f-8a21-4e6f-a097-51b5cd83bd69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962091509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2962091509
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3215733704
Short name T942
Test name
Test status
Simulation time 13544449 ps
CPU time 0.62 seconds
Started Jan 14 01:10:27 PM PST 24
Finished Jan 14 01:10:29 PM PST 24
Peak memory 194744 kb
Host smart-882bf642-aa1e-4b46-83c8-8ade752bab01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215733704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3215733704
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.4093997031
Short name T948
Test name
Test status
Simulation time 15513552 ps
CPU time 0.59 seconds
Started Jan 14 01:10:27 PM PST 24
Finished Jan 14 01:10:29 PM PST 24
Peak memory 193992 kb
Host smart-eeceb7f6-de56-4c4d-9df5-8549c29b1d1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093997031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.4093997031
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1845022729
Short name T102
Test name
Test status
Simulation time 26174565 ps
CPU time 0.64 seconds
Started Jan 14 01:10:25 PM PST 24
Finished Jan 14 01:10:27 PM PST 24
Peak memory 194804 kb
Host smart-6c1d2916-864f-49b8-aa2a-fed9c256734b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845022729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1845022729
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3125912539
Short name T11
Test name
Test status
Simulation time 28419218 ps
CPU time 0.57 seconds
Started Jan 14 01:10:26 PM PST 24
Finished Jan 14 01:10:28 PM PST 24
Peak memory 194524 kb
Host smart-1af1d1d3-971f-4925-a1ae-80c6da49698d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125912539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3125912539
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.868289696
Short name T947
Test name
Test status
Simulation time 21243538 ps
CPU time 0.57 seconds
Started Jan 14 01:10:28 PM PST 24
Finished Jan 14 01:10:31 PM PST 24
Peak memory 194040 kb
Host smart-eec101a4-308e-4587-829f-b93273342135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868289696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.868289696
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.87631826
Short name T917
Test name
Test status
Simulation time 37029480 ps
CPU time 0.57 seconds
Started Jan 14 01:10:29 PM PST 24
Finished Jan 14 01:10:31 PM PST 24
Peak memory 194736 kb
Host smart-11f57968-e6a2-405f-b404-4c7d3603b9cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87631826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.87631826
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1110929215
Short name T943
Test name
Test status
Simulation time 41424190 ps
CPU time 0.6 seconds
Started Jan 14 01:10:29 PM PST 24
Finished Jan 14 01:10:31 PM PST 24
Peak memory 193960 kb
Host smart-05e5b9b6-1a64-4dfe-89d9-6a25f8d5237d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110929215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1110929215
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3266510954
Short name T19
Test name
Test status
Simulation time 93866413 ps
CPU time 0.63 seconds
Started Jan 14 01:09:48 PM PST 24
Finished Jan 14 01:09:55 PM PST 24
Peak memory 194620 kb
Host smart-ca9bf36a-98c6-449e-b9db-60df0a409fce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266510954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3266510954
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2418307890
Short name T892
Test name
Test status
Simulation time 365504365 ps
CPU time 1.47 seconds
Started Jan 14 01:10:03 PM PST 24
Finished Jan 14 01:10:12 PM PST 24
Peak memory 196952 kb
Host smart-e1f27f5c-d99f-4b53-ba2b-d898bcbb69f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418307890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2418307890
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1127745097
Short name T36
Test name
Test status
Simulation time 55006922 ps
CPU time 0.63 seconds
Started Jan 14 01:09:57 PM PST 24
Finished Jan 14 01:09:59 PM PST 24
Peak memory 194916 kb
Host smart-8f376426-501f-43cb-abc9-43db5dbe67da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127745097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1127745097
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.380871488
Short name T909
Test name
Test status
Simulation time 25445806 ps
CPU time 0.86 seconds
Started Jan 14 01:09:56 PM PST 24
Finished Jan 14 01:09:59 PM PST 24
Peak memory 198304 kb
Host smart-ebfaa076-b806-4bbb-ae96-059211b5a2ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380871488 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.380871488
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.186793334
Short name T908
Test name
Test status
Simulation time 19781609 ps
CPU time 0.57 seconds
Started Jan 14 01:09:49 PM PST 24
Finished Jan 14 01:09:54 PM PST 24
Peak memory 193520 kb
Host smart-7abb24c9-9441-4721-a256-e4d7dd4e140d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186793334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.186793334
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.198735211
Short name T911
Test name
Test status
Simulation time 18178000 ps
CPU time 0.61 seconds
Started Jan 14 01:09:55 PM PST 24
Finished Jan 14 01:09:58 PM PST 24
Peak memory 193968 kb
Host smart-b9a0502a-3128-4e3b-abcd-ba040acd87f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198735211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.198735211
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3904302043
Short name T935
Test name
Test status
Simulation time 23975087 ps
CPU time 0.72 seconds
Started Jan 14 01:09:53 PM PST 24
Finished Jan 14 01:09:58 PM PST 24
Peak memory 195872 kb
Host smart-1d0e6de7-9da4-455d-9387-5f7e2ac9ddc9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904302043 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3904302043
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2974957148
Short name T130
Test name
Test status
Simulation time 205223018 ps
CPU time 2.67 seconds
Started Jan 14 01:09:50 PM PST 24
Finished Jan 14 01:09:57 PM PST 24
Peak memory 198312 kb
Host smart-b79e2694-08d1-47fa-ac1c-7505c0923ce3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974957148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2974957148
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1411164510
Short name T960
Test name
Test status
Simulation time 302525614 ps
CPU time 1.15 seconds
Started Jan 14 01:09:50 PM PST 24
Finished Jan 14 01:09:55 PM PST 24
Peak memory 198400 kb
Host smart-4d42fdc1-6b94-4dc9-9b1e-92f6a338040d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411164510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1411164510
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.233693650
Short name T969
Test name
Test status
Simulation time 34801238 ps
CPU time 0.63 seconds
Started Jan 14 01:10:27 PM PST 24
Finished Jan 14 01:10:29 PM PST 24
Peak memory 194692 kb
Host smart-24f836df-1455-4b97-ba0a-a0da4278b71e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233693650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.233693650
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1298228188
Short name T126
Test name
Test status
Simulation time 42787531 ps
CPU time 0.62 seconds
Started Jan 14 01:10:26 PM PST 24
Finished Jan 14 01:10:29 PM PST 24
Peak memory 194012 kb
Host smart-52b78d24-2a7d-4594-8872-3e287c9a3015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298228188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1298228188
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.507867065
Short name T968
Test name
Test status
Simulation time 12585353 ps
CPU time 0.58 seconds
Started Jan 14 01:10:27 PM PST 24
Finished Jan 14 01:10:30 PM PST 24
Peak memory 194708 kb
Host smart-d6ec2286-1e7f-405b-b1bb-1527d02cbda6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507867065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.507867065
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.950963998
Short name T120
Test name
Test status
Simulation time 15927417 ps
CPU time 0.61 seconds
Started Jan 14 01:10:31 PM PST 24
Finished Jan 14 01:10:33 PM PST 24
Peak memory 194044 kb
Host smart-dab2f936-0211-4a9e-9239-df1ba8b84128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950963998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.950963998
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2694969714
Short name T965
Test name
Test status
Simulation time 84662805 ps
CPU time 0.6 seconds
Started Jan 14 01:10:25 PM PST 24
Finished Jan 14 01:10:27 PM PST 24
Peak memory 194720 kb
Host smart-ae1648ff-6f21-4a24-ae93-ea9873e3f5f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694969714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2694969714
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.445175346
Short name T12
Test name
Test status
Simulation time 14363768 ps
CPU time 0.58 seconds
Started Jan 14 01:10:29 PM PST 24
Finished Jan 14 01:10:31 PM PST 24
Peak memory 193944 kb
Host smart-b5be0ba0-6d79-4f5a-b769-8bd8f04d5cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445175346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.445175346
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1385253676
Short name T907
Test name
Test status
Simulation time 17886107 ps
CPU time 0.64 seconds
Started Jan 14 01:10:27 PM PST 24
Finished Jan 14 01:10:29 PM PST 24
Peak memory 194152 kb
Host smart-d4974a0f-39d6-4547-bfba-ea8f20eacad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385253676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1385253676
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1031332124
Short name T925
Test name
Test status
Simulation time 22658378 ps
CPU time 0.64 seconds
Started Jan 14 01:10:27 PM PST 24
Finished Jan 14 01:10:29 PM PST 24
Peak memory 194124 kb
Host smart-6246f5cb-d822-41cb-83e0-70696a465583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031332124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1031332124
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2562659355
Short name T108
Test name
Test status
Simulation time 31052473 ps
CPU time 0.6 seconds
Started Jan 14 01:10:27 PM PST 24
Finished Jan 14 01:10:30 PM PST 24
Peak memory 194040 kb
Host smart-b2318250-cf49-4772-964a-bb84020ed2a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562659355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2562659355
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2924622758
Short name T930
Test name
Test status
Simulation time 29260156 ps
CPU time 0.61 seconds
Started Jan 14 01:10:25 PM PST 24
Finished Jan 14 01:10:27 PM PST 24
Peak memory 194648 kb
Host smart-93ded3ac-1cbd-416c-8290-9e7ca25366f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924622758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2924622758
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.445799571
Short name T110
Test name
Test status
Simulation time 21411909 ps
CPU time 0.79 seconds
Started Jan 14 01:10:02 PM PST 24
Finished Jan 14 01:10:10 PM PST 24
Peak memory 198152 kb
Host smart-a69c460e-6462-44e1-b970-ab1ba538478e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445799571 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.445799571
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.382958874
Short name T76
Test name
Test status
Simulation time 18160335 ps
CPU time 0.58 seconds
Started Jan 14 01:10:00 PM PST 24
Finished Jan 14 01:10:03 PM PST 24
Peak memory 194780 kb
Host smart-0131cb43-6890-4423-a4c3-91201c0a6249
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382958874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.382958874
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1829012270
Short name T951
Test name
Test status
Simulation time 18429928 ps
CPU time 0.6 seconds
Started Jan 14 01:09:59 PM PST 24
Finished Jan 14 01:10:03 PM PST 24
Peak memory 194700 kb
Host smart-69517fb8-c226-40d8-b22c-5f576bd9923c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829012270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1829012270
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2940649450
Short name T940
Test name
Test status
Simulation time 124221005 ps
CPU time 0.71 seconds
Started Jan 14 01:10:01 PM PST 24
Finished Jan 14 01:10:09 PM PST 24
Peak memory 196896 kb
Host smart-382426a4-7a14-4780-a47a-10d1779c828c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940649450 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2940649450
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3675596525
Short name T32
Test name
Test status
Simulation time 81975342 ps
CPU time 1.16 seconds
Started Jan 14 01:10:00 PM PST 24
Finished Jan 14 01:10:04 PM PST 24
Peak memory 198424 kb
Host smart-bae5278b-d1fc-48d3-92bf-0fb24ec83dce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675596525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3675596525
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1654714776
Short name T914
Test name
Test status
Simulation time 639329946 ps
CPU time 1.34 seconds
Started Jan 14 01:09:58 PM PST 24
Finished Jan 14 01:10:01 PM PST 24
Peak memory 198376 kb
Host smart-19202ea3-aa95-4452-9fb2-032514b3a973
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654714776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1654714776
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2417244717
Short name T952
Test name
Test status
Simulation time 74817343 ps
CPU time 0.76 seconds
Started Jan 14 01:10:02 PM PST 24
Finished Jan 14 01:10:10 PM PST 24
Peak memory 198132 kb
Host smart-a394d93b-5d4f-46f0-ae8f-688617290c62
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417244717 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2417244717
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3767040509
Short name T90
Test name
Test status
Simulation time 109737026 ps
CPU time 0.65 seconds
Started Jan 14 01:10:04 PM PST 24
Finished Jan 14 01:10:12 PM PST 24
Peak memory 195068 kb
Host smart-f9fddbb6-25f8-49c1-8049-4a2c7ad0a34d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767040509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3767040509
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.166393551
Short name T949
Test name
Test status
Simulation time 13930067 ps
CPU time 0.62 seconds
Started Jan 14 01:10:08 PM PST 24
Finished Jan 14 01:10:12 PM PST 24
Peak memory 194796 kb
Host smart-286560ad-8080-435b-9bd9-2a6f512b9719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166393551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.166393551
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.119819924
Short name T918
Test name
Test status
Simulation time 33320337 ps
CPU time 0.88 seconds
Started Jan 14 01:10:06 PM PST 24
Finished Jan 14 01:10:13 PM PST 24
Peak memory 196536 kb
Host smart-727143bc-ade4-4219-8f22-375de37dcb9d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119819924 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.119819924
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1611996287
Short name T906
Test name
Test status
Simulation time 482981633 ps
CPU time 2.05 seconds
Started Jan 14 01:10:01 PM PST 24
Finished Jan 14 01:10:10 PM PST 24
Peak memory 198512 kb
Host smart-909a3055-ae01-45ec-bb26-89996ea01c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611996287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1611996287
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1742845512
Short name T953
Test name
Test status
Simulation time 247954283 ps
CPU time 0.9 seconds
Started Jan 14 01:10:07 PM PST 24
Finished Jan 14 01:10:13 PM PST 24
Peak memory 198156 kb
Host smart-059c949b-ce8e-4a4a-bc83-56ffe216a45e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742845512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1742845512
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3353267039
Short name T14
Test name
Test status
Simulation time 21449588 ps
CPU time 0.65 seconds
Started Jan 14 01:10:08 PM PST 24
Finished Jan 14 01:10:12 PM PST 24
Peak memory 196976 kb
Host smart-73f31ef7-6e1c-4169-aebb-a05b23b73f7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353267039 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3353267039
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2502569892
Short name T912
Test name
Test status
Simulation time 12945354 ps
CPU time 0.59 seconds
Started Jan 14 01:10:01 PM PST 24
Finished Jan 14 01:10:09 PM PST 24
Peak memory 195620 kb
Host smart-10c5b049-f882-4af2-9423-b3eeb6045219
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502569892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2502569892
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3444094023
Short name T964
Test name
Test status
Simulation time 41262519 ps
CPU time 0.59 seconds
Started Jan 14 01:10:03 PM PST 24
Finished Jan 14 01:10:10 PM PST 24
Peak memory 193920 kb
Host smart-ad73cbfa-41f5-4dde-8831-7d2edd5440a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444094023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3444094023
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1480300394
Short name T959
Test name
Test status
Simulation time 22879209 ps
CPU time 0.69 seconds
Started Jan 14 01:10:07 PM PST 24
Finished Jan 14 01:10:12 PM PST 24
Peak memory 195132 kb
Host smart-787991b8-34aa-45b7-8e76-da0c0f77bdb9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480300394 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1480300394
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.890943150
Short name T125
Test name
Test status
Simulation time 63302054 ps
CPU time 1.66 seconds
Started Jan 14 01:10:02 PM PST 24
Finished Jan 14 01:10:11 PM PST 24
Peak memory 198376 kb
Host smart-81c78da2-72b8-495c-bf99-bf1d9a703e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890943150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.890943150
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3070622863
Short name T22
Test name
Test status
Simulation time 378230058 ps
CPU time 0.82 seconds
Started Jan 14 01:10:02 PM PST 24
Finished Jan 14 01:10:10 PM PST 24
Peak memory 198024 kb
Host smart-6a0fa779-3cd4-4990-8a89-ff4b1aee6268
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070622863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3070622863
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.4051252527
Short name T967
Test name
Test status
Simulation time 60078206 ps
CPU time 0.77 seconds
Started Jan 14 01:10:10 PM PST 24
Finished Jan 14 01:10:15 PM PST 24
Peak memory 198156 kb
Host smart-a30d7e39-63da-48d0-b493-523b59320165
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051252527 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.4051252527
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1943592020
Short name T115
Test name
Test status
Simulation time 11617045 ps
CPU time 0.62 seconds
Started Jan 14 01:10:03 PM PST 24
Finished Jan 14 01:10:10 PM PST 24
Peak memory 195776 kb
Host smart-77d44a1a-fd3a-48e7-acb9-ad1c61f26d82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943592020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1943592020
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3196206263
Short name T936
Test name
Test status
Simulation time 49630902 ps
CPU time 0.67 seconds
Started Jan 14 01:10:09 PM PST 24
Finished Jan 14 01:10:15 PM PST 24
Peak memory 194808 kb
Host smart-0f3160d1-a884-4f6d-8687-197d1ac451aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196206263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3196206263
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.561350672
Short name T922
Test name
Test status
Simulation time 47566155 ps
CPU time 0.77 seconds
Started Jan 14 01:10:09 PM PST 24
Finished Jan 14 01:10:15 PM PST 24
Peak memory 196200 kb
Host smart-5eacc3e5-56ae-46ba-baca-95504454b0a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561350672 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.561350672
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.346253899
Short name T30
Test name
Test status
Simulation time 71128782 ps
CPU time 2.04 seconds
Started Jan 14 01:10:12 PM PST 24
Finished Jan 14 01:10:17 PM PST 24
Peak memory 198456 kb
Host smart-74362110-0ccc-41bd-800e-b8c3467073ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346253899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.346253899
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3111414417
Short name T34
Test name
Test status
Simulation time 42557665 ps
CPU time 0.86 seconds
Started Jan 14 01:10:11 PM PST 24
Finished Jan 14 01:10:16 PM PST 24
Peak memory 198168 kb
Host smart-f2f7e1cb-2962-46cc-9142-19d2e2e044d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111414417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3111414417
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3276218209
Short name T127
Test name
Test status
Simulation time 27785522 ps
CPU time 1.38 seconds
Started Jan 14 01:10:07 PM PST 24
Finished Jan 14 01:10:13 PM PST 24
Peak memory 198396 kb
Host smart-877b1f06-ddd9-4b86-acaa-c63b017e05aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276218209 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3276218209
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.478940265
Short name T79
Test name
Test status
Simulation time 166551323 ps
CPU time 0.59 seconds
Started Jan 14 01:10:12 PM PST 24
Finished Jan 14 01:10:16 PM PST 24
Peak memory 194684 kb
Host smart-c9e5ecf2-3688-4cb3-b37b-6f3ede428b3a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478940265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.478940265
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3850229305
Short name T1
Test name
Test status
Simulation time 123775869 ps
CPU time 0.76 seconds
Started Jan 14 01:10:10 PM PST 24
Finished Jan 14 01:10:15 PM PST 24
Peak memory 196280 kb
Host smart-b4b5f475-df0a-4681-9df3-28efa6c6919f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850229305 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3850229305
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2272501002
Short name T946
Test name
Test status
Simulation time 85024863 ps
CPU time 2.23 seconds
Started Jan 14 01:10:08 PM PST 24
Finished Jan 14 01:10:14 PM PST 24
Peak memory 198476 kb
Host smart-08805382-d9f6-4acf-9da2-107954ac7e57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272501002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2272501002
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1692214411
Short name T6
Test name
Test status
Simulation time 181558578 ps
CPU time 0.87 seconds
Started Jan 14 01:10:10 PM PST 24
Finished Jan 14 01:10:15 PM PST 24
Peak memory 197144 kb
Host smart-bd85257c-c5e9-4d24-9309-88ca3c7cdba2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692214411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1692214411
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1669376365
Short name T657
Test name
Test status
Simulation time 13570570 ps
CPU time 0.54 seconds
Started Jan 14 01:40:25 PM PST 24
Finished Jan 14 01:40:27 PM PST 24
Peak memory 194088 kb
Host smart-941d039e-08b4-4661-8ff7-8a9b33f709be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669376365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1669376365
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.251911409
Short name T334
Test name
Test status
Simulation time 299725090 ps
CPU time 0.87 seconds
Started Jan 14 01:40:04 PM PST 24
Finished Jan 14 01:40:11 PM PST 24
Peak memory 196596 kb
Host smart-bbfbf7f4-1f11-454b-b191-6c6018a71806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251911409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.251911409
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2164825595
Short name T530
Test name
Test status
Simulation time 3511357941 ps
CPU time 14.54 seconds
Started Jan 14 01:40:23 PM PST 24
Finished Jan 14 01:40:38 PM PST 24
Peak memory 196984 kb
Host smart-fe32fa8e-29fe-4cc0-9b63-19f29533f4f1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164825595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2164825595
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1110412551
Short name T694
Test name
Test status
Simulation time 84745965 ps
CPU time 0.98 seconds
Started Jan 14 01:40:22 PM PST 24
Finished Jan 14 01:40:24 PM PST 24
Peak memory 196744 kb
Host smart-e266836d-9e99-499c-aefd-e0ffd51a270b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110412551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1110412551
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2351862066
Short name T598
Test name
Test status
Simulation time 1200033226 ps
CPU time 1.13 seconds
Started Jan 14 01:40:06 PM PST 24
Finished Jan 14 01:40:11 PM PST 24
Peak memory 196120 kb
Host smart-09173361-6188-4f82-9bce-fe4c61d53a23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351862066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2351862066
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3687223318
Short name T47
Test name
Test status
Simulation time 74006057 ps
CPU time 2.79 seconds
Started Jan 14 01:40:24 PM PST 24
Finished Jan 14 01:40:28 PM PST 24
Peak memory 196636 kb
Host smart-711ee275-33cf-4ea6-ba19-370916bc5561
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687223318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3687223318
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3896511733
Short name T651
Test name
Test status
Simulation time 234031727 ps
CPU time 2.29 seconds
Started Jan 14 01:40:19 PM PST 24
Finished Jan 14 01:40:22 PM PST 24
Peak memory 197128 kb
Host smart-7dd25d14-1953-4e31-b07d-3e433533b9d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896511733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3896511733
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1681710727
Short name T817
Test name
Test status
Simulation time 90747041 ps
CPU time 0.73 seconds
Started Jan 14 01:40:10 PM PST 24
Finished Jan 14 01:40:15 PM PST 24
Peak memory 195512 kb
Host smart-52c64bf2-d06f-4420-a928-346570bfab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681710727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1681710727
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.643762935
Short name T548
Test name
Test status
Simulation time 32671704 ps
CPU time 0.87 seconds
Started Jan 14 01:40:07 PM PST 24
Finished Jan 14 01:40:11 PM PST 24
Peak memory 195976 kb
Host smart-d069f4ca-d6e5-4dd9-9046-ef2d3ed30fed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643762935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.643762935
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1640893036
Short name T487
Test name
Test status
Simulation time 399584270 ps
CPU time 3.33 seconds
Started Jan 14 01:40:26 PM PST 24
Finished Jan 14 01:40:32 PM PST 24
Peak memory 196564 kb
Host smart-2d6c6c4b-c72a-43fa-ab10-76459c8ecd0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640893036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1640893036
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.2838102445
Short name T424
Test name
Test status
Simulation time 42212657 ps
CPU time 0.96 seconds
Started Jan 14 01:40:07 PM PST 24
Finished Jan 14 01:40:11 PM PST 24
Peak memory 195856 kb
Host smart-41b2c827-1c16-40cb-8ce3-0723fc70802e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838102445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2838102445
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3914599836
Short name T226
Test name
Test status
Simulation time 83922256 ps
CPU time 0.66 seconds
Started Jan 14 01:40:07 PM PST 24
Finished Jan 14 01:40:11 PM PST 24
Peak memory 194180 kb
Host smart-4a0197e9-e0d0-4454-8b7a-fd836e3d4a35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914599836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3914599836
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.4212658625
Short name T558
Test name
Test status
Simulation time 4674703677 ps
CPU time 130.99 seconds
Started Jan 14 01:40:25 PM PST 24
Finished Jan 14 01:42:37 PM PST 24
Peak memory 198280 kb
Host smart-8e90d87a-2f07-4f2d-b3db-2315c40e68e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212658625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.4212658625
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.897990994
Short name T801
Test name
Test status
Simulation time 318565648792 ps
CPU time 1064.67 seconds
Started Jan 14 01:40:23 PM PST 24
Finished Jan 14 01:58:09 PM PST 24
Peak memory 206648 kb
Host smart-01b4c24b-689b-400a-bbb4-2957836b3c0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=897990994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.897990994
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3071843389
Short name T447
Test name
Test status
Simulation time 30658585 ps
CPU time 0.57 seconds
Started Jan 14 01:40:42 PM PST 24
Finished Jan 14 01:40:43 PM PST 24
Peak memory 194784 kb
Host smart-baa5ed35-350c-473e-b8fc-53e3529a4163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071843389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3071843389
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.438628254
Short name T367
Test name
Test status
Simulation time 81235199 ps
CPU time 0.8 seconds
Started Jan 14 01:40:24 PM PST 24
Finished Jan 14 01:40:26 PM PST 24
Peak memory 195452 kb
Host smart-28b3d6b9-b6ee-4aa3-b8f0-9d8756c0dca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438628254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.438628254
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.807559389
Short name T227
Test name
Test status
Simulation time 547981210 ps
CPU time 7.07 seconds
Started Jan 14 01:40:24 PM PST 24
Finished Jan 14 01:40:32 PM PST 24
Peak memory 196996 kb
Host smart-393f5f97-cae5-470b-87fe-3cbee1f6d009
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807559389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.807559389
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.4276160329
Short name T810
Test name
Test status
Simulation time 19978268 ps
CPU time 0.61 seconds
Started Jan 14 01:40:23 PM PST 24
Finished Jan 14 01:40:24 PM PST 24
Peak memory 195280 kb
Host smart-94c3e285-1af6-44da-a0f6-e43968460223
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276160329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.4276160329
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3312713608
Short name T401
Test name
Test status
Simulation time 33449090 ps
CPU time 0.64 seconds
Started Jan 14 01:40:25 PM PST 24
Finished Jan 14 01:40:29 PM PST 24
Peak memory 195040 kb
Host smart-fc52f1c0-d19c-4860-b957-fe8e01a745f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312713608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3312713608
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.807298652
Short name T630
Test name
Test status
Simulation time 212683723 ps
CPU time 2.07 seconds
Started Jan 14 01:40:22 PM PST 24
Finished Jan 14 01:40:25 PM PST 24
Peak memory 198196 kb
Host smart-cdac0ad5-9c17-4d54-8262-d3bc39b01cc0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807298652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.807298652
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2705141544
Short name T818
Test name
Test status
Simulation time 173853674 ps
CPU time 3.28 seconds
Started Jan 14 01:40:24 PM PST 24
Finished Jan 14 01:40:29 PM PST 24
Peak memory 198188 kb
Host smart-2535b4ed-4ef7-4767-86b3-a2002d6af07f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705141544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2705141544
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.4083208123
Short name T445
Test name
Test status
Simulation time 32034323 ps
CPU time 1.19 seconds
Started Jan 14 01:40:26 PM PST 24
Finished Jan 14 01:40:29 PM PST 24
Peak memory 196700 kb
Host smart-effa3db1-f80a-4571-8774-0af3a17ffb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083208123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.4083208123
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1212302738
Short name T537
Test name
Test status
Simulation time 68738450 ps
CPU time 0.96 seconds
Started Jan 14 01:40:23 PM PST 24
Finished Jan 14 01:40:25 PM PST 24
Peak memory 196804 kb
Host smart-a8f3b75e-ff32-4f3d-b16b-3b0492909927
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212302738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1212302738
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.103702911
Short name T434
Test name
Test status
Simulation time 174119440 ps
CPU time 4.29 seconds
Started Jan 14 01:40:25 PM PST 24
Finished Jan 14 01:40:31 PM PST 24
Peak memory 198088 kb
Host smart-79e82269-d7a9-4b64-8b1c-112d8ff21145
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103702911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.103702911
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1391258677
Short name T29
Test name
Test status
Simulation time 34528450 ps
CPU time 0.76 seconds
Started Jan 14 01:40:36 PM PST 24
Finished Jan 14 01:40:38 PM PST 24
Peak memory 213596 kb
Host smart-b6e00f06-236e-4ab7-88b3-6d0f138cd819
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391258677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1391258677
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.895052957
Short name T520
Test name
Test status
Simulation time 57554067 ps
CPU time 1.05 seconds
Started Jan 14 01:40:26 PM PST 24
Finished Jan 14 01:40:29 PM PST 24
Peak memory 195820 kb
Host smart-934d96a1-0e02-448e-b370-05cbe94a9d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895052957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.895052957
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3003499137
Short name T645
Test name
Test status
Simulation time 362345909 ps
CPU time 1.04 seconds
Started Jan 14 01:40:24 PM PST 24
Finished Jan 14 01:40:26 PM PST 24
Peak memory 196396 kb
Host smart-e38a64ec-4856-4e80-917b-67ce62dc3a7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003499137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3003499137
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2549679588
Short name T459
Test name
Test status
Simulation time 4237983214 ps
CPU time 102.1 seconds
Started Jan 14 01:40:25 PM PST 24
Finished Jan 14 01:42:10 PM PST 24
Peak memory 198224 kb
Host smart-f04c77f4-f94e-4f6f-ab9b-148f40642131
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549679588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2549679588
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3465415841
Short name T778
Test name
Test status
Simulation time 63957754693 ps
CPU time 2118.94 seconds
Started Jan 14 01:40:38 PM PST 24
Finished Jan 14 02:15:58 PM PST 24
Peak memory 198416 kb
Host smart-23c7f90a-007c-474c-9669-db4d9807ba59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3465415841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.3465415841
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2230700559
Short name T749
Test name
Test status
Simulation time 15577753 ps
CPU time 0.57 seconds
Started Jan 14 01:41:31 PM PST 24
Finished Jan 14 01:41:33 PM PST 24
Peak memory 194960 kb
Host smart-dcf317e8-b8b1-4c37-b3a4-516755354b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230700559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2230700559
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.651459467
Short name T670
Test name
Test status
Simulation time 36945233 ps
CPU time 0.84 seconds
Started Jan 14 01:41:31 PM PST 24
Finished Jan 14 01:41:33 PM PST 24
Peak memory 195292 kb
Host smart-91071844-2978-4ff9-9179-8b2d3fbc0c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651459467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.651459467
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1206973207
Short name T690
Test name
Test status
Simulation time 281787283 ps
CPU time 8.47 seconds
Started Jan 14 01:41:31 PM PST 24
Finished Jan 14 01:41:41 PM PST 24
Peak memory 198168 kb
Host smart-ccc566aa-ea26-4d22-9cef-9dbac6b8497c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206973207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1206973207
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.341444658
Short name T307
Test name
Test status
Simulation time 84563132 ps
CPU time 0.61 seconds
Started Jan 14 01:41:32 PM PST 24
Finished Jan 14 01:41:33 PM PST 24
Peak memory 194672 kb
Host smart-f07c212c-d793-4125-8821-08c5c78816cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341444658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.341444658
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2773694014
Short name T319
Test name
Test status
Simulation time 59531570 ps
CPU time 1.16 seconds
Started Jan 14 01:41:31 PM PST 24
Finished Jan 14 01:41:34 PM PST 24
Peak memory 196116 kb
Host smart-9d5a49cd-a7c6-4924-ade3-a2cc50de9e74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773694014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2773694014
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2601801728
Short name T861
Test name
Test status
Simulation time 48143471 ps
CPU time 1.88 seconds
Started Jan 14 01:41:32 PM PST 24
Finished Jan 14 01:41:35 PM PST 24
Peak memory 198176 kb
Host smart-dddbc3a7-f68d-4376-92fa-0c7d473cd6bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601801728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2601801728
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2537142210
Short name T248
Test name
Test status
Simulation time 97250982 ps
CPU time 2.13 seconds
Started Jan 14 01:41:30 PM PST 24
Finished Jan 14 01:41:33 PM PST 24
Peak memory 196004 kb
Host smart-a687f779-54f3-4a40-a866-43b8d0aa00fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537142210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2537142210
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3183577787
Short name T742
Test name
Test status
Simulation time 57613914 ps
CPU time 0.89 seconds
Started Jan 14 01:41:35 PM PST 24
Finished Jan 14 01:41:36 PM PST 24
Peak memory 197192 kb
Host smart-a1129835-4c83-4a5b-8b1a-a81abe5cca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183577787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3183577787
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3554282907
Short name T388
Test name
Test status
Simulation time 32847002 ps
CPU time 0.86 seconds
Started Jan 14 01:41:35 PM PST 24
Finished Jan 14 01:41:37 PM PST 24
Peak memory 197376 kb
Host smart-3cc7c16b-6261-4cc4-ba7c-68ac35640768
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554282907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3554282907
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1834282893
Short name T479
Test name
Test status
Simulation time 277240511 ps
CPU time 4.56 seconds
Started Jan 14 01:41:32 PM PST 24
Finished Jan 14 01:41:38 PM PST 24
Peak memory 197156 kb
Host smart-72cf3c12-9f9e-45e6-b106-db74843d3458
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834282893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1834282893
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.427543684
Short name T336
Test name
Test status
Simulation time 162499309 ps
CPU time 1.16 seconds
Started Jan 14 01:41:29 PM PST 24
Finished Jan 14 01:41:30 PM PST 24
Peak memory 196876 kb
Host smart-d965f737-19c8-48cc-8c2b-64e75f8327cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427543684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.427543684
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.857909788
Short name T63
Test name
Test status
Simulation time 480771220 ps
CPU time 0.85 seconds
Started Jan 14 01:41:39 PM PST 24
Finished Jan 14 01:41:40 PM PST 24
Peak memory 195292 kb
Host smart-6c3b91b2-1995-45b9-8f33-4b095c18ae3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857909788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.857909788
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.836582335
Short name T725
Test name
Test status
Simulation time 6590846925 ps
CPU time 62.63 seconds
Started Jan 14 01:41:33 PM PST 24
Finished Jan 14 01:42:37 PM PST 24
Peak memory 198120 kb
Host smart-648a1f1f-dd2f-4462-90c3-bd9fafedd0c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836582335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.836582335
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1508248886
Short name T276
Test name
Test status
Simulation time 39085716285 ps
CPU time 506.58 seconds
Started Jan 14 01:41:33 PM PST 24
Finished Jan 14 01:50:00 PM PST 24
Peak memory 198440 kb
Host smart-906a4c25-342a-4504-95cd-ccc1f0cc1a37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1508248886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1508248886
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2675735557
Short name T441
Test name
Test status
Simulation time 48605133 ps
CPU time 0.53 seconds
Started Jan 14 01:41:34 PM PST 24
Finished Jan 14 01:41:35 PM PST 24
Peak memory 193544 kb
Host smart-4cac3127-6f3d-44be-a603-007966eef148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675735557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2675735557
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.4051890134
Short name T542
Test name
Test status
Simulation time 182006048 ps
CPU time 0.75 seconds
Started Jan 14 01:41:36 PM PST 24
Finished Jan 14 01:41:38 PM PST 24
Peak memory 196128 kb
Host smart-c7078464-d446-4a41-a419-187c93999bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051890134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.4051890134
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.340346210
Short name T881
Test name
Test status
Simulation time 986061472 ps
CPU time 16.63 seconds
Started Jan 14 01:41:36 PM PST 24
Finished Jan 14 01:41:53 PM PST 24
Peak memory 196448 kb
Host smart-c9f47a15-8b44-49e9-be97-f37b0b4472ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340346210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.340346210
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1487171375
Short name T865
Test name
Test status
Simulation time 71290212 ps
CPU time 1.05 seconds
Started Jan 14 01:41:34 PM PST 24
Finished Jan 14 01:41:36 PM PST 24
Peak memory 196788 kb
Host smart-04143eb9-9642-46fc-adec-0cf81b6c4e2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487171375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1487171375
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.992984759
Short name T721
Test name
Test status
Simulation time 209084089 ps
CPU time 1.17 seconds
Started Jan 14 01:41:37 PM PST 24
Finished Jan 14 01:41:38 PM PST 24
Peak memory 196068 kb
Host smart-d1fe689a-49ab-48d8-9280-7d399261a3d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992984759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.992984759
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2084510127
Short name T482
Test name
Test status
Simulation time 74449679 ps
CPU time 2.71 seconds
Started Jan 14 01:41:35 PM PST 24
Finished Jan 14 01:41:38 PM PST 24
Peak memory 196476 kb
Host smart-e56abaaa-9b16-4c03-a146-a9a7aaf63b62
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084510127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2084510127
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1570026009
Short name T287
Test name
Test status
Simulation time 254691549 ps
CPU time 1.59 seconds
Started Jan 14 01:41:37 PM PST 24
Finished Jan 14 01:41:39 PM PST 24
Peak memory 196092 kb
Host smart-be57dd85-644b-4025-ba0f-ffb10bcd51e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570026009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1570026009
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3429806912
Short name T529
Test name
Test status
Simulation time 85794371 ps
CPU time 0.77 seconds
Started Jan 14 01:41:32 PM PST 24
Finished Jan 14 01:41:34 PM PST 24
Peak memory 195500 kb
Host smart-cc59eb15-9057-4a29-bce8-7ecd7eb1facd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429806912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3429806912
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3636669170
Short name T848
Test name
Test status
Simulation time 97416734 ps
CPU time 1.07 seconds
Started Jan 14 01:41:38 PM PST 24
Finished Jan 14 01:41:40 PM PST 24
Peak memory 196888 kb
Host smart-8d816f93-b9a0-4818-b12f-415ea199d7b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636669170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3636669170
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2405234337
Short name T652
Test name
Test status
Simulation time 87830273 ps
CPU time 3.85 seconds
Started Jan 14 01:41:37 PM PST 24
Finished Jan 14 01:41:41 PM PST 24
Peak memory 198120 kb
Host smart-ccedf277-96a5-4d2c-8106-62044ac3cea1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405234337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2405234337
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2365577882
Short name T834
Test name
Test status
Simulation time 58832561 ps
CPU time 1.09 seconds
Started Jan 14 01:41:30 PM PST 24
Finished Jan 14 01:41:32 PM PST 24
Peak memory 195904 kb
Host smart-1ff0c8d2-38bf-4326-b9e5-dd525d1af977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365577882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2365577882
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1074675467
Short name T614
Test name
Test status
Simulation time 227048222 ps
CPU time 1.01 seconds
Started Jan 14 01:41:34 PM PST 24
Finished Jan 14 01:41:35 PM PST 24
Peak memory 195748 kb
Host smart-34204b63-ef19-4f27-9748-c542f67058f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074675467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1074675467
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2632459367
Short name T458
Test name
Test status
Simulation time 31338898468 ps
CPU time 191.88 seconds
Started Jan 14 01:41:37 PM PST 24
Finished Jan 14 01:44:50 PM PST 24
Peak memory 198284 kb
Host smart-4633f963-d063-46e2-8f13-b5006f064ad3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632459367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2632459367
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.945067561
Short name T825
Test name
Test status
Simulation time 22293748406 ps
CPU time 281.01 seconds
Started Jan 14 01:41:37 PM PST 24
Finished Jan 14 01:46:18 PM PST 24
Peak memory 198404 kb
Host smart-ca99f6b2-f5a0-408a-bb67-1170378d508a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=945067561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.945067561
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1381287616
Short name T483
Test name
Test status
Simulation time 91367505 ps
CPU time 0.92 seconds
Started Jan 14 01:41:40 PM PST 24
Finished Jan 14 01:41:41 PM PST 24
Peak memory 196584 kb
Host smart-9a58d58f-5737-4a69-b252-de68709190ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381287616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1381287616
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.793085619
Short name T46
Test name
Test status
Simulation time 190174806 ps
CPU time 9.74 seconds
Started Jan 14 01:41:39 PM PST 24
Finished Jan 14 01:41:49 PM PST 24
Peak memory 197120 kb
Host smart-ecda8bcc-af45-4d4e-a120-5701388a6980
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793085619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.793085619
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2471396375
Short name T342
Test name
Test status
Simulation time 102653027 ps
CPU time 1.07 seconds
Started Jan 14 01:41:41 PM PST 24
Finished Jan 14 01:41:43 PM PST 24
Peak memory 196732 kb
Host smart-762e20be-baec-46fa-9a90-dcb0b14fbfe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471396375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2471396375
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.29818323
Short name T821
Test name
Test status
Simulation time 57734233 ps
CPU time 1.01 seconds
Started Jan 14 01:41:36 PM PST 24
Finished Jan 14 01:41:37 PM PST 24
Peak memory 196976 kb
Host smart-172f8985-a140-4450-a600-7cb121bcfc21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29818323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.29818323
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3567578634
Short name T343
Test name
Test status
Simulation time 32785651 ps
CPU time 1.28 seconds
Started Jan 14 01:41:40 PM PST 24
Finished Jan 14 01:41:42 PM PST 24
Peak memory 196780 kb
Host smart-72b1da69-c87f-4ebf-b722-b4c5aac19623
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567578634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3567578634
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1829824344
Short name T426
Test name
Test status
Simulation time 62867988 ps
CPU time 1.49 seconds
Started Jan 14 01:41:40 PM PST 24
Finished Jan 14 01:41:42 PM PST 24
Peak memory 195952 kb
Host smart-ad5ca674-6145-4201-9ed1-a28f5525676f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829824344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1829824344
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.4279715612
Short name T308
Test name
Test status
Simulation time 69572411 ps
CPU time 1.26 seconds
Started Jan 14 01:41:36 PM PST 24
Finished Jan 14 01:41:38 PM PST 24
Peak memory 198180 kb
Host smart-1e033bf7-993d-449a-8e4e-7000f88451be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279715612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.4279715612
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3923433628
Short name T38
Test name
Test status
Simulation time 48420600 ps
CPU time 1.14 seconds
Started Jan 14 01:41:39 PM PST 24
Finished Jan 14 01:41:40 PM PST 24
Peak memory 196252 kb
Host smart-8eac9738-8f57-4bc6-a2e6-55fa009c67b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923433628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3923433628
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2011214510
Short name T277
Test name
Test status
Simulation time 475898487 ps
CPU time 2.61 seconds
Started Jan 14 01:41:36 PM PST 24
Finished Jan 14 01:41:39 PM PST 24
Peak memory 198080 kb
Host smart-4d01aa21-5e25-4900-899e-466e12900d2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011214510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2011214510
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.4280802339
Short name T325
Test name
Test status
Simulation time 39270214 ps
CPU time 0.9 seconds
Started Jan 14 01:41:38 PM PST 24
Finished Jan 14 01:41:39 PM PST 24
Peak memory 197164 kb
Host smart-aad14a0f-ce41-47c4-8dc9-003a7c59fe40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280802339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.4280802339
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2987255619
Short name T733
Test name
Test status
Simulation time 22745940 ps
CPU time 0.81 seconds
Started Jan 14 01:41:34 PM PST 24
Finished Jan 14 01:41:35 PM PST 24
Peak memory 195308 kb
Host smart-0034111f-c22d-4efb-bff4-f07ded0b2c71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987255619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2987255619
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3287860093
Short name T436
Test name
Test status
Simulation time 4193201493 ps
CPU time 103.95 seconds
Started Jan 14 01:41:36 PM PST 24
Finished Jan 14 01:43:21 PM PST 24
Peak memory 198240 kb
Host smart-4e0f1166-c22b-41f1-b5a2-b0438ac9fe4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287860093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3287860093
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.663551554
Short name T450
Test name
Test status
Simulation time 117587754691 ps
CPU time 753.4 seconds
Started Jan 14 01:41:40 PM PST 24
Finished Jan 14 01:54:14 PM PST 24
Peak memory 198412 kb
Host smart-53884196-c480-49f2-8bfa-9fea332fa3d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=663551554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.663551554
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1524252301
Short name T791
Test name
Test status
Simulation time 18398731 ps
CPU time 0.58 seconds
Started Jan 14 01:41:46 PM PST 24
Finished Jan 14 01:41:47 PM PST 24
Peak memory 194068 kb
Host smart-69d8b89d-31d7-4317-8215-8ca036a4abfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524252301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1524252301
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3310061845
Short name T860
Test name
Test status
Simulation time 160931113 ps
CPU time 0.71 seconds
Started Jan 14 01:41:44 PM PST 24
Finished Jan 14 01:41:45 PM PST 24
Peak memory 195144 kb
Host smart-078642d3-1e0b-4c3e-a4a1-e31175a2cd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310061845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3310061845
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1989707530
Short name T611
Test name
Test status
Simulation time 390729686 ps
CPU time 19.85 seconds
Started Jan 14 01:41:45 PM PST 24
Finished Jan 14 01:42:05 PM PST 24
Peak memory 198188 kb
Host smart-f850c699-07cf-4789-8597-f13da8a48c7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989707530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1989707530
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.4253507631
Short name T302
Test name
Test status
Simulation time 299367163 ps
CPU time 0.78 seconds
Started Jan 14 01:41:42 PM PST 24
Finished Jan 14 01:41:43 PM PST 24
Peak memory 196124 kb
Host smart-27dd1fce-64a9-4aee-bad2-758e7eb05bb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253507631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.4253507631
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.113936167
Short name T472
Test name
Test status
Simulation time 51074824 ps
CPU time 1.26 seconds
Started Jan 14 01:41:43 PM PST 24
Finished Jan 14 01:41:45 PM PST 24
Peak memory 197232 kb
Host smart-4a446e35-ac19-4bb0-b636-bf4f428f2aaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113936167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.113936167
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1442232183
Short name T578
Test name
Test status
Simulation time 58526508 ps
CPU time 2.37 seconds
Started Jan 14 01:41:45 PM PST 24
Finished Jan 14 01:41:48 PM PST 24
Peak memory 198224 kb
Host smart-bdd39a8a-400b-45b5-b9f1-24973ee03313
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442232183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1442232183
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.855128956
Short name T795
Test name
Test status
Simulation time 541515882 ps
CPU time 2.49 seconds
Started Jan 14 01:41:46 PM PST 24
Finished Jan 14 01:41:49 PM PST 24
Peak memory 197328 kb
Host smart-004487fa-9858-4e38-bb3e-de1019607a6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855128956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
855128956
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.655136096
Short name T262
Test name
Test status
Simulation time 982432981 ps
CPU time 1.17 seconds
Started Jan 14 01:41:43 PM PST 24
Finished Jan 14 01:41:45 PM PST 24
Peak memory 197068 kb
Host smart-b6127630-c96a-4ff7-bb2d-d4c35931455e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655136096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.655136096
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3508013463
Short name T484
Test name
Test status
Simulation time 214680378 ps
CPU time 1.03 seconds
Started Jan 14 01:41:43 PM PST 24
Finished Jan 14 01:41:44 PM PST 24
Peak memory 196056 kb
Host smart-a6d6688a-3268-4ec8-b253-ed432cdb81bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508013463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3508013463
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1209890227
Short name T557
Test name
Test status
Simulation time 1203022957 ps
CPU time 5.27 seconds
Started Jan 14 01:41:44 PM PST 24
Finished Jan 14 01:41:50 PM PST 24
Peak memory 197988 kb
Host smart-015ae070-7418-465c-88f5-a103e623493e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209890227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1209890227
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1117390319
Short name T228
Test name
Test status
Simulation time 262997553 ps
CPU time 1.09 seconds
Started Jan 14 01:41:42 PM PST 24
Finished Jan 14 01:41:44 PM PST 24
Peak memory 195652 kb
Host smart-1eed4f12-14e4-4ce0-8333-1ced74d68a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117390319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1117390319
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2037348695
Short name T223
Test name
Test status
Simulation time 174417760 ps
CPU time 1.1 seconds
Started Jan 14 01:41:42 PM PST 24
Finished Jan 14 01:41:44 PM PST 24
Peak memory 196640 kb
Host smart-1672e95c-6577-4e64-b70d-b2a8b6d64d57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037348695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2037348695
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3094180981
Short name T417
Test name
Test status
Simulation time 5472219728 ps
CPU time 124.54 seconds
Started Jan 14 01:41:44 PM PST 24
Finished Jan 14 01:43:49 PM PST 24
Peak memory 198272 kb
Host smart-8808f474-c7de-4a1c-b4c5-6142864bd175
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094180981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3094180981
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3339412180
Short name T766
Test name
Test status
Simulation time 20270099535 ps
CPU time 260.01 seconds
Started Jan 14 01:41:44 PM PST 24
Finished Jan 14 01:46:05 PM PST 24
Peak memory 198308 kb
Host smart-4ba4e41d-35f1-4540-a4ce-1a4958215168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3339412180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3339412180
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.79221753
Short name T296
Test name
Test status
Simulation time 11738395 ps
CPU time 0.58 seconds
Started Jan 14 01:41:56 PM PST 24
Finished Jan 14 01:41:58 PM PST 24
Peak memory 194124 kb
Host smart-8bd9ea36-d4a3-482d-8f8b-35f9f312820b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79221753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.79221753
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1838066555
Short name T602
Test name
Test status
Simulation time 36633625 ps
CPU time 0.8 seconds
Started Jan 14 01:41:44 PM PST 24
Finished Jan 14 01:41:46 PM PST 24
Peak memory 196124 kb
Host smart-05055533-b6c4-4502-9559-0811eeb3fb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838066555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1838066555
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2916409902
Short name T773
Test name
Test status
Simulation time 1833638656 ps
CPU time 13.64 seconds
Started Jan 14 01:41:46 PM PST 24
Finished Jan 14 01:42:00 PM PST 24
Peak memory 198060 kb
Host smart-a4031d34-dee5-4cab-bec8-cb74e8dfcc49
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916409902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2916409902
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.97291508
Short name T346
Test name
Test status
Simulation time 131208093 ps
CPU time 0.76 seconds
Started Jan 14 01:41:48 PM PST 24
Finished Jan 14 01:41:49 PM PST 24
Peak memory 195916 kb
Host smart-d1296ddf-dc7d-406c-9750-5d4ab280025e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97291508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.97291508
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2567160305
Short name T402
Test name
Test status
Simulation time 140885508 ps
CPU time 1.28 seconds
Started Jan 14 01:41:45 PM PST 24
Finished Jan 14 01:41:47 PM PST 24
Peak memory 196860 kb
Host smart-ad9f4df0-ec83-4240-ab0a-8fc4fb9b161a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567160305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2567160305
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3738000509
Short name T587
Test name
Test status
Simulation time 167073686 ps
CPU time 3.31 seconds
Started Jan 14 01:41:46 PM PST 24
Finished Jan 14 01:41:50 PM PST 24
Peak memory 196648 kb
Host smart-23d58f7a-56a6-40f7-b5b0-d1382a47a4d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738000509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3738000509
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2324402618
Short name T852
Test name
Test status
Simulation time 32720702 ps
CPU time 0.88 seconds
Started Jan 14 01:41:44 PM PST 24
Finished Jan 14 01:41:46 PM PST 24
Peak memory 195696 kb
Host smart-057ff6eb-116b-4a2f-81d4-ec4c009b597d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324402618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2324402618
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1337157966
Short name T489
Test name
Test status
Simulation time 434523658 ps
CPU time 1.16 seconds
Started Jan 14 01:41:43 PM PST 24
Finished Jan 14 01:41:45 PM PST 24
Peak memory 197040 kb
Host smart-56ef3c0a-d0e9-4dfd-a997-6227864849e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337157966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1337157966
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2227859394
Short name T771
Test name
Test status
Simulation time 120540328 ps
CPU time 1.1 seconds
Started Jan 14 01:41:46 PM PST 24
Finished Jan 14 01:41:48 PM PST 24
Peak memory 197240 kb
Host smart-23018700-dfb3-4c34-a193-c52447d84b5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227859394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2227859394
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3540225773
Short name T236
Test name
Test status
Simulation time 54546592 ps
CPU time 2.44 seconds
Started Jan 14 01:41:45 PM PST 24
Finished Jan 14 01:41:48 PM PST 24
Peak memory 198100 kb
Host smart-32487795-3d3f-47cf-9742-9527dcdefbd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540225773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3540225773
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.989909441
Short name T428
Test name
Test status
Simulation time 119281923 ps
CPU time 0.82 seconds
Started Jan 14 01:41:47 PM PST 24
Finished Jan 14 01:41:48 PM PST 24
Peak memory 195976 kb
Host smart-5b7f0fc4-d4ea-4b94-98e0-38cd5623d1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989909441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.989909441
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1587137358
Short name T408
Test name
Test status
Simulation time 155287502 ps
CPU time 1.22 seconds
Started Jan 14 01:41:48 PM PST 24
Finished Jan 14 01:41:50 PM PST 24
Peak memory 195944 kb
Host smart-fb32c5ca-0262-4ed9-a2b3-3e7c1f0e14a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587137358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1587137358
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3375821553
Short name T837
Test name
Test status
Simulation time 8279483158 ps
CPU time 98.25 seconds
Started Jan 14 01:41:46 PM PST 24
Finished Jan 14 01:43:24 PM PST 24
Peak memory 198244 kb
Host smart-7a3c4f35-2b24-419e-bfd7-7f04fa0cb504
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375821553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3375821553
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2709207788
Short name T679
Test name
Test status
Simulation time 29621670871 ps
CPU time 863.47 seconds
Started Jan 14 01:41:52 PM PST 24
Finished Jan 14 01:56:17 PM PST 24
Peak memory 198292 kb
Host smart-d78b7be2-f685-49d3-817b-35b8aabca7aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2709207788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2709207788
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3234195450
Short name T857
Test name
Test status
Simulation time 33848013 ps
CPU time 0.58 seconds
Started Jan 14 01:41:54 PM PST 24
Finished Jan 14 01:41:55 PM PST 24
Peak memory 194820 kb
Host smart-9ff66dbb-de5d-4235-8007-a7cba0ac0c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234195450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3234195450
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2420469733
Short name T751
Test name
Test status
Simulation time 84812625 ps
CPU time 0.68 seconds
Started Jan 14 01:41:55 PM PST 24
Finished Jan 14 01:41:56 PM PST 24
Peak memory 194244 kb
Host smart-6a4618fe-84be-412d-85ed-4aa58f8230bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420469733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2420469733
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1652262157
Short name T618
Test name
Test status
Simulation time 826438305 ps
CPU time 3.46 seconds
Started Jan 14 01:41:53 PM PST 24
Finished Jan 14 01:41:57 PM PST 24
Peak memory 196748 kb
Host smart-90a16312-55d4-40f4-825c-328e07d85610
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652262157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1652262157
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.4057013878
Short name T835
Test name
Test status
Simulation time 55323539 ps
CPU time 0.66 seconds
Started Jan 14 01:41:54 PM PST 24
Finished Jan 14 01:41:55 PM PST 24
Peak memory 194600 kb
Host smart-bbb55c38-4a59-467f-95f3-788a6a146d00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057013878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.4057013878
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2264681568
Short name T851
Test name
Test status
Simulation time 68090548 ps
CPU time 1.09 seconds
Started Jan 14 01:41:53 PM PST 24
Finished Jan 14 01:41:54 PM PST 24
Peak memory 196912 kb
Host smart-c3bbac7a-c7bf-46e5-b7de-779d5b03f08b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264681568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2264681568
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.249635878
Short name T601
Test name
Test status
Simulation time 46416023 ps
CPU time 1.08 seconds
Started Jan 14 01:41:53 PM PST 24
Finished Jan 14 01:41:55 PM PST 24
Peak memory 197100 kb
Host smart-861898d6-15e5-489c-b42e-33438848e09e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249635878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.249635878
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.942589373
Short name T644
Test name
Test status
Simulation time 149836444 ps
CPU time 1.29 seconds
Started Jan 14 01:41:54 PM PST 24
Finished Jan 14 01:41:56 PM PST 24
Peak memory 197004 kb
Host smart-3923b0f4-4436-43cf-8b12-612f6bccfb6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942589373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
942589373
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2121711590
Short name T617
Test name
Test status
Simulation time 29534365 ps
CPU time 1 seconds
Started Jan 14 01:41:52 PM PST 24
Finished Jan 14 01:41:54 PM PST 24
Peak memory 195900 kb
Host smart-8ca38dbd-0451-42de-90e2-b395cb2e872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121711590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2121711590
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3843166572
Short name T734
Test name
Test status
Simulation time 186668701 ps
CPU time 0.98 seconds
Started Jan 14 01:41:54 PM PST 24
Finished Jan 14 01:41:56 PM PST 24
Peak memory 196156 kb
Host smart-21253de2-9d68-4121-bffb-36a09af0bc26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843166572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3843166572
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2948118577
Short name T674
Test name
Test status
Simulation time 474568846 ps
CPU time 5.65 seconds
Started Jan 14 01:41:57 PM PST 24
Finished Jan 14 01:42:03 PM PST 24
Peak memory 198128 kb
Host smart-9e1cd2fa-8926-4053-b821-06fc815029c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948118577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2948118577
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3562488037
Short name T435
Test name
Test status
Simulation time 103244589 ps
CPU time 1.02 seconds
Started Jan 14 01:41:55 PM PST 24
Finished Jan 14 01:41:57 PM PST 24
Peak memory 195916 kb
Host smart-0c8ef5c0-8658-4320-a0c5-67cd6128e839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562488037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3562488037
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.24500446
Short name T337
Test name
Test status
Simulation time 172112008 ps
CPU time 1.29 seconds
Started Jan 14 01:41:51 PM PST 24
Finished Jan 14 01:41:53 PM PST 24
Peak memory 198104 kb
Host smart-50c172e7-a06f-432d-afdb-3477a1f61b2c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24500446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.24500446
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.4126571778
Short name T341
Test name
Test status
Simulation time 16981481360 ps
CPU time 96.76 seconds
Started Jan 14 01:41:56 PM PST 24
Finished Jan 14 01:43:34 PM PST 24
Peak memory 198256 kb
Host smart-6d96036c-fff9-4e34-be9d-1082363b830f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126571778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.4126571778
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.2563347602
Short name T480
Test name
Test status
Simulation time 13364494951 ps
CPU time 376.31 seconds
Started Jan 14 01:41:57 PM PST 24
Finished Jan 14 01:48:14 PM PST 24
Peak memory 198476 kb
Host smart-d8bcaca8-cc85-42b6-bb29-23383c8be219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2563347602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.2563347602
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1275494715
Short name T476
Test name
Test status
Simulation time 41754631 ps
CPU time 0.55 seconds
Started Jan 14 01:42:06 PM PST 24
Finished Jan 14 01:42:11 PM PST 24
Peak memory 194816 kb
Host smart-c42de48d-0862-4e03-b38d-c8040f3f4754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275494715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1275494715
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2805621578
Short name T280
Test name
Test status
Simulation time 26896248 ps
CPU time 0.85 seconds
Started Jan 14 01:41:55 PM PST 24
Finished Jan 14 01:41:56 PM PST 24
Peak memory 197328 kb
Host smart-0bb0c283-ba4b-4305-b712-d122df84c9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805621578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2805621578
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3158284996
Short name T461
Test name
Test status
Simulation time 538507624 ps
CPU time 16.17 seconds
Started Jan 14 01:41:59 PM PST 24
Finished Jan 14 01:42:15 PM PST 24
Peak memory 197328 kb
Host smart-e9f85d0d-7751-47e3-97ca-94784112bdc8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158284996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3158284996
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.283607873
Short name T654
Test name
Test status
Simulation time 51100586 ps
CPU time 0.79 seconds
Started Jan 14 01:41:57 PM PST 24
Finished Jan 14 01:41:58 PM PST 24
Peak memory 195816 kb
Host smart-6bf17077-7a64-4fae-8441-44ba3631f35c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283607873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.283607873
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3948115773
Short name T613
Test name
Test status
Simulation time 61810661 ps
CPU time 1.09 seconds
Started Jan 14 01:41:55 PM PST 24
Finished Jan 14 01:41:57 PM PST 24
Peak memory 196780 kb
Host smart-a66755e9-1a21-4f3a-94bb-45b19dd2e88e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948115773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3948115773
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1939652244
Short name T572
Test name
Test status
Simulation time 284990223 ps
CPU time 2.89 seconds
Started Jan 14 01:41:55 PM PST 24
Finished Jan 14 01:41:59 PM PST 24
Peak memory 196600 kb
Host smart-d57c2a3a-bf29-45f2-b586-0a3b6209c6eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939652244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1939652244
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2220239954
Short name T541
Test name
Test status
Simulation time 123149719 ps
CPU time 1.47 seconds
Started Jan 14 01:41:58 PM PST 24
Finished Jan 14 01:42:00 PM PST 24
Peak memory 196144 kb
Host smart-bdd2fce7-72c8-4028-a371-54adcd460d68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220239954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2220239954
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3977461386
Short name T438
Test name
Test status
Simulation time 37365189 ps
CPU time 0.99 seconds
Started Jan 14 01:41:55 PM PST 24
Finished Jan 14 01:41:56 PM PST 24
Peak memory 196132 kb
Host smart-45f93191-1629-4fd5-a8ee-e5ab438b68a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977461386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3977461386
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3503346288
Short name T683
Test name
Test status
Simulation time 80730965 ps
CPU time 0.97 seconds
Started Jan 14 01:41:59 PM PST 24
Finished Jan 14 01:42:00 PM PST 24
Peak memory 196840 kb
Host smart-3c73e15c-fb07-4286-8679-e517f6c7f148
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503346288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3503346288
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1844101509
Short name T600
Test name
Test status
Simulation time 395813086 ps
CPU time 4.89 seconds
Started Jan 14 01:41:54 PM PST 24
Finished Jan 14 01:41:59 PM PST 24
Peak memory 198096 kb
Host smart-1da4d027-0183-4573-bb5d-7e80dd978044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844101509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1844101509
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3169325559
Short name T889
Test name
Test status
Simulation time 67779887 ps
CPU time 0.84 seconds
Started Jan 14 01:41:55 PM PST 24
Finished Jan 14 01:41:57 PM PST 24
Peak memory 196056 kb
Host smart-81b53165-918e-4cb0-a3ed-06c85436506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169325559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3169325559
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2016363622
Short name T259
Test name
Test status
Simulation time 39351525 ps
CPU time 1 seconds
Started Jan 14 01:41:53 PM PST 24
Finished Jan 14 01:41:54 PM PST 24
Peak memory 195944 kb
Host smart-54f13e26-96af-45a0-ba33-213a05bc3ee0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016363622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2016363622
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1550464453
Short name T812
Test name
Test status
Simulation time 8061385068 ps
CPU time 48.15 seconds
Started Jan 14 01:42:06 PM PST 24
Finished Jan 14 01:42:59 PM PST 24
Peak memory 198232 kb
Host smart-0188e624-2802-4c62-9013-620d111cf9e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550464453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1550464453
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1800810656
Short name T409
Test name
Test status
Simulation time 63942791382 ps
CPU time 714.28 seconds
Started Jan 14 01:42:12 PM PST 24
Finished Jan 14 01:54:14 PM PST 24
Peak memory 198296 kb
Host smart-b766913d-74a0-4a2c-94c8-e6032a0d21fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1800810656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1800810656
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3070550516
Short name T596
Test name
Test status
Simulation time 35725977 ps
CPU time 0.54 seconds
Started Jan 14 01:42:05 PM PST 24
Finished Jan 14 01:42:11 PM PST 24
Peak memory 194056 kb
Host smart-e7cea1c5-8eac-4250-9794-1193a86959c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070550516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3070550516
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1969785853
Short name T809
Test name
Test status
Simulation time 48402055 ps
CPU time 0.61 seconds
Started Jan 14 01:42:08 PM PST 24
Finished Jan 14 01:42:12 PM PST 24
Peak memory 194656 kb
Host smart-1ce11068-2b2e-4cad-ad53-6c69bd6714bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969785853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1969785853
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2401831981
Short name T246
Test name
Test status
Simulation time 823741486 ps
CPU time 21.85 seconds
Started Jan 14 01:42:08 PM PST 24
Finished Jan 14 01:42:34 PM PST 24
Peak memory 196564 kb
Host smart-2caf8365-244f-4db0-a66a-38b5a19b746a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401831981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2401831981
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.569741329
Short name T448
Test name
Test status
Simulation time 275507524 ps
CPU time 0.94 seconds
Started Jan 14 01:42:08 PM PST 24
Finished Jan 14 01:42:13 PM PST 24
Peak memory 197172 kb
Host smart-1beeb2c5-b07f-4fe1-a151-d71107007a27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569741329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.569741329
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.108208812
Short name T64
Test name
Test status
Simulation time 56290599 ps
CPU time 1.08 seconds
Started Jan 14 01:42:06 PM PST 24
Finished Jan 14 01:42:12 PM PST 24
Peak memory 196196 kb
Host smart-7a6f7a6c-7970-45df-9634-c7b3e56ea712
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108208812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.108208812
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2656610605
Short name T677
Test name
Test status
Simulation time 209162950 ps
CPU time 2.27 seconds
Started Jan 14 01:42:06 PM PST 24
Finished Jan 14 01:42:13 PM PST 24
Peak memory 198188 kb
Host smart-96adb59f-0f13-40cf-964d-c2a6f74634fa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656610605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2656610605
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.669449557
Short name T631
Test name
Test status
Simulation time 298614250 ps
CPU time 1.78 seconds
Started Jan 14 01:42:07 PM PST 24
Finished Jan 14 01:42:12 PM PST 24
Peak memory 196816 kb
Host smart-1bc7a7cc-acc8-4ab9-9006-f5cea944a9d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669449557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
669449557
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.165959362
Short name T672
Test name
Test status
Simulation time 32240935 ps
CPU time 1.18 seconds
Started Jan 14 01:42:11 PM PST 24
Finished Jan 14 01:42:21 PM PST 24
Peak memory 197176 kb
Host smart-5bef44e7-6e80-4493-9a25-435e76fcfc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165959362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.165959362
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2152926208
Short name T416
Test name
Test status
Simulation time 97309136 ps
CPU time 0.94 seconds
Started Jan 14 01:42:13 PM PST 24
Finished Jan 14 01:42:21 PM PST 24
Peak memory 195960 kb
Host smart-b7e437ee-f6da-43d9-a69e-940932ada751
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152926208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2152926208
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1834867325
Short name T716
Test name
Test status
Simulation time 567856478 ps
CPU time 1.93 seconds
Started Jan 14 01:42:03 PM PST 24
Finished Jan 14 01:42:12 PM PST 24
Peak memory 198216 kb
Host smart-63ad4f44-e3b5-4c11-910f-391ba19967c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834867325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1834867325
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2148755731
Short name T655
Test name
Test status
Simulation time 92446487 ps
CPU time 1.07 seconds
Started Jan 14 01:42:12 PM PST 24
Finished Jan 14 01:42:21 PM PST 24
Peak memory 195576 kb
Host smart-c3484208-d1ec-430b-b7b5-04a30e691bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148755731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2148755731
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.4252192178
Short name T538
Test name
Test status
Simulation time 238583102 ps
CPU time 1.23 seconds
Started Jan 14 01:42:11 PM PST 24
Finished Jan 14 01:42:21 PM PST 24
Peak memory 197056 kb
Host smart-06c16c8f-c41c-4089-a95a-e2bb1abd4ca7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252192178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.4252192178
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.815280694
Short name T339
Test name
Test status
Simulation time 2336600491 ps
CPU time 56.12 seconds
Started Jan 14 01:42:12 PM PST 24
Finished Jan 14 01:43:16 PM PST 24
Peak memory 198156 kb
Host smart-39a379e1-516a-4f7d-b708-dce94013f294
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815280694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.815280694
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.883918116
Short name T816
Test name
Test status
Simulation time 134159634383 ps
CPU time 1373.74 seconds
Started Jan 14 01:42:11 PM PST 24
Finished Jan 14 02:05:13 PM PST 24
Peak memory 198436 kb
Host smart-dbf1b587-3dd2-459e-bdeb-f489b4553ca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=883918116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.883918116
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3775465142
Short name T704
Test name
Test status
Simulation time 68121229 ps
CPU time 0.59 seconds
Started Jan 14 01:42:17 PM PST 24
Finished Jan 14 01:42:21 PM PST 24
Peak memory 194292 kb
Host smart-49a712a6-cc07-4c1b-8542-b90e1de4c497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775465142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3775465142
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.217331331
Short name T238
Test name
Test status
Simulation time 57759873 ps
CPU time 0.61 seconds
Started Jan 14 01:42:12 PM PST 24
Finished Jan 14 01:42:20 PM PST 24
Peak memory 194012 kb
Host smart-6431385e-9545-4f63-a0e1-55df66fbfa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217331331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.217331331
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2863156316
Short name T399
Test name
Test status
Simulation time 3366526446 ps
CPU time 26.55 seconds
Started Jan 14 01:42:07 PM PST 24
Finished Jan 14 01:42:37 PM PST 24
Peak memory 198284 kb
Host smart-23d9ba84-1074-49cf-94d8-a5639dffe2a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863156316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2863156316
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.4045100412
Short name T338
Test name
Test status
Simulation time 365076072 ps
CPU time 0.86 seconds
Started Jan 14 01:42:18 PM PST 24
Finished Jan 14 01:42:24 PM PST 24
Peak memory 196156 kb
Host smart-0f9fdc3a-7789-4bc0-a53d-caba4e9a1032
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045100412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.4045100412
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3604173822
Short name T622
Test name
Test status
Simulation time 210225521 ps
CPU time 0.86 seconds
Started Jan 14 01:42:08 PM PST 24
Finished Jan 14 01:42:12 PM PST 24
Peak memory 196396 kb
Host smart-18878557-f6f0-44b5-a442-ea379197b310
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604173822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3604173822
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3055926229
Short name T363
Test name
Test status
Simulation time 261988232 ps
CPU time 2.52 seconds
Started Jan 14 01:42:07 PM PST 24
Finished Jan 14 01:42:13 PM PST 24
Peak memory 198224 kb
Host smart-bbf0f7bd-39de-48f1-a952-5ec023cbfd10
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055926229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3055926229
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3887153448
Short name T382
Test name
Test status
Simulation time 159483817 ps
CPU time 3.13 seconds
Started Jan 14 01:42:07 PM PST 24
Finished Jan 14 01:42:14 PM PST 24
Peak memory 195900 kb
Host smart-0f25a49d-cc18-4cb8-b963-e9abe62ca659
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887153448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3887153448
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3396636650
Short name T418
Test name
Test status
Simulation time 30782970 ps
CPU time 1.1 seconds
Started Jan 14 01:42:11 PM PST 24
Finished Jan 14 01:42:21 PM PST 24
Peak memory 196648 kb
Host smart-7a41e245-cf24-4acf-afb7-e285d5a20d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396636650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3396636650
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.4203471034
Short name T225
Test name
Test status
Simulation time 84263069 ps
CPU time 0.83 seconds
Started Jan 14 01:42:06 PM PST 24
Finished Jan 14 01:42:11 PM PST 24
Peak memory 196508 kb
Host smart-03dec6fc-87cf-4a3e-b57e-a22e79224fb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203471034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.4203471034
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2354821129
Short name T384
Test name
Test status
Simulation time 226213494 ps
CPU time 2.51 seconds
Started Jan 14 01:42:06 PM PST 24
Finished Jan 14 01:42:13 PM PST 24
Peak memory 198060 kb
Host smart-8f9ebafc-f09f-40c3-9e1f-58c94d90bbdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354821129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2354821129
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.293481527
Short name T752
Test name
Test status
Simulation time 111288471 ps
CPU time 0.94 seconds
Started Jan 14 01:42:08 PM PST 24
Finished Jan 14 01:42:13 PM PST 24
Peak memory 196300 kb
Host smart-e10c6cb6-a822-4356-8d0c-b44d26117aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293481527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.293481527
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2531287653
Short name T462
Test name
Test status
Simulation time 672085736 ps
CPU time 1.38 seconds
Started Jan 14 01:42:08 PM PST 24
Finished Jan 14 01:42:14 PM PST 24
Peak memory 198140 kb
Host smart-a10e6844-053a-48b5-8512-acf0bf464c29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531287653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2531287653
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.462117402
Short name T345
Test name
Test status
Simulation time 62517940064 ps
CPU time 160.54 seconds
Started Jan 14 01:42:13 PM PST 24
Finished Jan 14 01:45:01 PM PST 24
Peak memory 198216 kb
Host smart-49e1fd2f-bc73-49b2-ba8c-d10ad96a9eaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462117402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.462117402
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2458770539
Short name T579
Test name
Test status
Simulation time 69795618382 ps
CPU time 1182.54 seconds
Started Jan 14 01:42:15 PM PST 24
Finished Jan 14 02:02:03 PM PST 24
Peak memory 198392 kb
Host smart-65b5384d-414c-4ec5-b162-aa84c9355fd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2458770539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2458770539
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3987594355
Short name T469
Test name
Test status
Simulation time 23910172 ps
CPU time 0.57 seconds
Started Jan 14 01:42:20 PM PST 24
Finished Jan 14 01:42:25 PM PST 24
Peak memory 194320 kb
Host smart-7b3bafb1-fe92-4c91-b9ba-2323b4675e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987594355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3987594355
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1773056459
Short name T799
Test name
Test status
Simulation time 110883643 ps
CPU time 0.7 seconds
Started Jan 14 01:42:13 PM PST 24
Finished Jan 14 01:42:21 PM PST 24
Peak memory 195244 kb
Host smart-35fedcfb-829f-4375-8211-66fc022d1f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773056459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1773056459
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1412818646
Short name T374
Test name
Test status
Simulation time 714574919 ps
CPU time 19.24 seconds
Started Jan 14 01:42:17 PM PST 24
Finished Jan 14 01:42:40 PM PST 24
Peak memory 198176 kb
Host smart-c645c12c-05a7-4935-8361-faf2c4572c63
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412818646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1412818646
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.863778456
Short name T759
Test name
Test status
Simulation time 371520828 ps
CPU time 1.13 seconds
Started Jan 14 01:42:17 PM PST 24
Finished Jan 14 01:42:22 PM PST 24
Peak memory 196796 kb
Host smart-580c838f-dc7a-4c4d-9b5a-51e3d67ed76e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863778456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.863778456
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3174191879
Short name T464
Test name
Test status
Simulation time 39601832 ps
CPU time 0.79 seconds
Started Jan 14 01:42:18 PM PST 24
Finished Jan 14 01:42:24 PM PST 24
Peak memory 196212 kb
Host smart-2e46cbe3-f577-404b-af9e-1568a0f8385d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174191879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3174191879
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3792244780
Short name T543
Test name
Test status
Simulation time 188290152 ps
CPU time 2.16 seconds
Started Jan 14 01:42:12 PM PST 24
Finished Jan 14 01:42:22 PM PST 24
Peak memory 196496 kb
Host smart-1887cc9e-7586-4fcf-93b5-244dd6805552
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792244780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3792244780
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.560036701
Short name T565
Test name
Test status
Simulation time 223997256 ps
CPU time 3.43 seconds
Started Jan 14 01:42:17 PM PST 24
Finished Jan 14 01:42:24 PM PST 24
Peak memory 198136 kb
Host smart-c913ccce-8e6d-4089-b6c8-8d26dd742c4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560036701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
560036701
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.307666525
Short name T593
Test name
Test status
Simulation time 78149927 ps
CPU time 0.9 seconds
Started Jan 14 01:42:14 PM PST 24
Finished Jan 14 01:42:21 PM PST 24
Peak memory 196772 kb
Host smart-859ad61a-8f46-43db-8314-e4a213c8d7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307666525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.307666525
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1025452727
Short name T495
Test name
Test status
Simulation time 59920263 ps
CPU time 1.24 seconds
Started Jan 14 01:42:14 PM PST 24
Finished Jan 14 01:42:22 PM PST 24
Peak memory 198156 kb
Host smart-bd846192-0e28-46d3-8500-be3c73ce350f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025452727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1025452727
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.4049490165
Short name T806
Test name
Test status
Simulation time 64567017 ps
CPU time 0.97 seconds
Started Jan 14 01:42:16 PM PST 24
Finished Jan 14 01:42:22 PM PST 24
Peak memory 196680 kb
Host smart-76438dc2-77d6-43cc-b0fd-e24840c6ff7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049490165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.4049490165
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3183859779
Short name T624
Test name
Test status
Simulation time 320462973 ps
CPU time 1.48 seconds
Started Jan 14 01:42:14 PM PST 24
Finished Jan 14 01:42:22 PM PST 24
Peak memory 196832 kb
Host smart-ffb6e0e6-eb98-4361-9727-dddf7c3d8a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183859779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3183859779
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4186080028
Short name T493
Test name
Test status
Simulation time 61809994 ps
CPU time 0.94 seconds
Started Jan 14 01:42:15 PM PST 24
Finished Jan 14 01:42:21 PM PST 24
Peak memory 195928 kb
Host smart-722abe0b-e62d-4c87-bb94-e518bf150322
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186080028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4186080028
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3660503649
Short name T638
Test name
Test status
Simulation time 4482311318 ps
CPU time 112.89 seconds
Started Jan 14 01:42:17 PM PST 24
Finished Jan 14 01:44:14 PM PST 24
Peak memory 198268 kb
Host smart-f73062c8-a803-45ec-9398-5fc079eb0f86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660503649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3660503649
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1606473161
Short name T656
Test name
Test status
Simulation time 36272498832 ps
CPU time 479.83 seconds
Started Jan 14 01:42:20 PM PST 24
Finished Jan 14 01:50:25 PM PST 24
Peak memory 198320 kb
Host smart-3e8d82e9-ae31-4690-89b5-9d95dda2905d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1606473161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1606473161
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3926496492
Short name T731
Test name
Test status
Simulation time 42103766 ps
CPU time 0.57 seconds
Started Jan 14 01:40:50 PM PST 24
Finished Jan 14 01:40:51 PM PST 24
Peak memory 194252 kb
Host smart-120f9d05-9263-4fca-9262-f1582beaec6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926496492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3926496492
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3605151616
Short name T425
Test name
Test status
Simulation time 114056344 ps
CPU time 0.91 seconds
Started Jan 14 01:40:51 PM PST 24
Finished Jan 14 01:40:53 PM PST 24
Peak memory 196624 kb
Host smart-70945bbe-bf0c-4d0c-b08a-04138c320172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605151616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3605151616
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3322506701
Short name T730
Test name
Test status
Simulation time 626017731 ps
CPU time 18.98 seconds
Started Jan 14 01:40:37 PM PST 24
Finished Jan 14 01:40:57 PM PST 24
Peak memory 196648 kb
Host smart-edf6077a-af0c-4476-91d6-9debe9791b68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322506701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3322506701
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1146032583
Short name T387
Test name
Test status
Simulation time 468944836 ps
CPU time 0.87 seconds
Started Jan 14 01:40:38 PM PST 24
Finished Jan 14 01:40:40 PM PST 24
Peak memory 197680 kb
Host smart-c971c3e8-03bd-4e28-84dc-e9d675db3c8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146032583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1146032583
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2132289845
Short name T673
Test name
Test status
Simulation time 327671348 ps
CPU time 1.19 seconds
Started Jan 14 01:40:48 PM PST 24
Finished Jan 14 01:40:50 PM PST 24
Peak memory 195960 kb
Host smart-7e631106-574f-413e-a760-524d010e466a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132289845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2132289845
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.217306704
Short name T260
Test name
Test status
Simulation time 42370299 ps
CPU time 1.63 seconds
Started Jan 14 01:40:38 PM PST 24
Finished Jan 14 01:40:40 PM PST 24
Peak memory 198240 kb
Host smart-f0a978dc-0c2f-4bb7-ad0d-7a5edd7a01b7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217306704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.217306704
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3778576468
Short name T315
Test name
Test status
Simulation time 284438851 ps
CPU time 2.52 seconds
Started Jan 14 01:40:43 PM PST 24
Finished Jan 14 01:40:47 PM PST 24
Peak memory 196848 kb
Host smart-b555c540-ab15-4881-b503-884a512148b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778576468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3778576468
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.126191094
Short name T718
Test name
Test status
Simulation time 114022673 ps
CPU time 0.78 seconds
Started Jan 14 01:40:38 PM PST 24
Finished Jan 14 01:40:40 PM PST 24
Peak memory 195492 kb
Host smart-da684670-f9d9-49a0-b8c8-5eb6b75d93af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126191094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.126191094
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1085281907
Short name T320
Test name
Test status
Simulation time 209057379 ps
CPU time 0.69 seconds
Started Jan 14 01:40:39 PM PST 24
Finished Jan 14 01:40:41 PM PST 24
Peak memory 195344 kb
Host smart-2ec6f96c-37f8-44c4-92cb-63702042e2a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085281907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1085281907
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2147127755
Short name T563
Test name
Test status
Simulation time 355469401 ps
CPU time 2.4 seconds
Started Jan 14 01:40:42 PM PST 24
Finished Jan 14 01:40:46 PM PST 24
Peak memory 198044 kb
Host smart-4ae3608a-41bf-4ba2-860f-3ec5b0d22df7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147127755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2147127755
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1613150186
Short name T61
Test name
Test status
Simulation time 831670316 ps
CPU time 0.88 seconds
Started Jan 14 01:40:46 PM PST 24
Finished Jan 14 01:40:48 PM PST 24
Peak memory 213560 kb
Host smart-a51f3db7-2f45-41c3-9d09-ce3d4c9d2ba4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613150186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1613150186
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3979049072
Short name T471
Test name
Test status
Simulation time 57291475 ps
CPU time 0.93 seconds
Started Jan 14 01:40:40 PM PST 24
Finished Jan 14 01:40:42 PM PST 24
Peak memory 195912 kb
Host smart-bda9cbb4-3f22-492f-8cc5-761c024d6d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979049072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3979049072
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3950637124
Short name T653
Test name
Test status
Simulation time 149932624 ps
CPU time 1.01 seconds
Started Jan 14 01:40:46 PM PST 24
Finished Jan 14 01:40:48 PM PST 24
Peak memory 195924 kb
Host smart-7ff233b8-ea79-4c27-8f6c-573a24a2d8c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950637124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3950637124
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2263398183
Short name T86
Test name
Test status
Simulation time 33155562700 ps
CPU time 182.26 seconds
Started Jan 14 01:40:39 PM PST 24
Finished Jan 14 01:43:42 PM PST 24
Peak memory 198252 kb
Host smart-bc5310f1-6475-4bd2-89d2-db8d0c90482d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263398183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2263398183
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1945416782
Short name T724
Test name
Test status
Simulation time 38710556 ps
CPU time 0.59 seconds
Started Jan 14 01:42:20 PM PST 24
Finished Jan 14 01:42:25 PM PST 24
Peak memory 194068 kb
Host smart-e2c41082-05c8-43e2-8383-dd578eee4248
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945416782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1945416782
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2333761070
Short name T112
Test name
Test status
Simulation time 32748986 ps
CPU time 0.8 seconds
Started Jan 14 01:42:19 PM PST 24
Finished Jan 14 01:42:25 PM PST 24
Peak memory 195348 kb
Host smart-41728a6d-64c3-41c3-b46c-49c8f03a2bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333761070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2333761070
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.4229980528
Short name T584
Test name
Test status
Simulation time 122083930 ps
CPU time 6.19 seconds
Started Jan 14 01:42:17 PM PST 24
Finished Jan 14 01:42:27 PM PST 24
Peak memory 197036 kb
Host smart-27a8ff6e-301e-442c-9866-b47f681829f8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229980528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.4229980528
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.4176103988
Short name T496
Test name
Test status
Simulation time 44899118 ps
CPU time 0.7 seconds
Started Jan 14 01:42:22 PM PST 24
Finished Jan 14 01:42:26 PM PST 24
Peak memory 194884 kb
Host smart-21dc57c2-7d34-4c90-8168-b17c3bb7ee42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176103988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.4176103988
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3048261191
Short name T606
Test name
Test status
Simulation time 52019106 ps
CPU time 0.9 seconds
Started Jan 14 01:42:18 PM PST 24
Finished Jan 14 01:42:25 PM PST 24
Peak memory 196808 kb
Host smart-7d1b1bad-8874-436a-ab89-e2e8d0b2f212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048261191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3048261191
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2671381878
Short name T577
Test name
Test status
Simulation time 39071947 ps
CPU time 0.92 seconds
Started Jan 14 01:42:18 PM PST 24
Finished Jan 14 01:42:22 PM PST 24
Peak memory 196328 kb
Host smart-fb959d6e-6a18-4416-afa2-0068373ebe6c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671381878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2671381878
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4287788050
Short name T375
Test name
Test status
Simulation time 471752169 ps
CPU time 2.98 seconds
Started Jan 14 01:42:21 PM PST 24
Finished Jan 14 01:42:28 PM PST 24
Peak memory 196640 kb
Host smart-8c0eb01a-956e-41de-a8ed-86fad211f7d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287788050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4287788050
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.131068299
Short name T703
Test name
Test status
Simulation time 36980765 ps
CPU time 1.18 seconds
Started Jan 14 01:42:16 PM PST 24
Finished Jan 14 01:42:22 PM PST 24
Peak memory 197028 kb
Host smart-85b3be64-a781-4002-86a0-ba202d1aad32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131068299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.131068299
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3654288981
Short name T744
Test name
Test status
Simulation time 206182379 ps
CPU time 1.32 seconds
Started Jan 14 01:42:19 PM PST 24
Finished Jan 14 01:42:25 PM PST 24
Peak memory 197064 kb
Host smart-be5fa59c-c6b3-4cdd-941c-8b70598c01bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654288981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3654288981
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1979368913
Short name T234
Test name
Test status
Simulation time 555767139 ps
CPU time 6.36 seconds
Started Jan 14 01:42:20 PM PST 24
Finished Jan 14 01:42:31 PM PST 24
Peak memory 198108 kb
Host smart-7c0828b8-7ec5-40cc-911f-9725254c7541
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979368913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1979368913
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2817102526
Short name T243
Test name
Test status
Simulation time 49619221 ps
CPU time 0.93 seconds
Started Jan 14 01:42:20 PM PST 24
Finished Jan 14 01:42:25 PM PST 24
Peak memory 197068 kb
Host smart-4a147468-0b80-493c-bd9b-37808a95883b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817102526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2817102526
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.57584986
Short name T632
Test name
Test status
Simulation time 179634200 ps
CPU time 1.25 seconds
Started Jan 14 01:42:18 PM PST 24
Finished Jan 14 01:42:25 PM PST 24
Peak memory 196396 kb
Host smart-b5c3c0e2-39a4-4bfc-9ba9-28248719fac5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57584986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.57584986
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.753606228
Short name T589
Test name
Test status
Simulation time 4274753322 ps
CPU time 58.19 seconds
Started Jan 14 01:42:21 PM PST 24
Finished Jan 14 01:43:23 PM PST 24
Peak memory 198204 kb
Host smart-8073f0db-8166-4a5b-850e-ccbca6015a5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753606228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.753606228
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2945979244
Short name T554
Test name
Test status
Simulation time 17254011228 ps
CPU time 201.23 seconds
Started Jan 14 01:42:18 PM PST 24
Finished Jan 14 01:45:45 PM PST 24
Peak memory 198336 kb
Host smart-cd55570a-f6a5-402a-88e0-d877bd0e6476
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2945979244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2945979244
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.246169507
Short name T544
Test name
Test status
Simulation time 27174828 ps
CPU time 0.6 seconds
Started Jan 14 01:42:26 PM PST 24
Finished Jan 14 01:42:28 PM PST 24
Peak memory 194716 kb
Host smart-181077df-e5c7-44d3-bf5f-442bc38b5377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246169507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.246169507
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.860152939
Short name T275
Test name
Test status
Simulation time 230919515 ps
CPU time 0.73 seconds
Started Jan 14 01:42:25 PM PST 24
Finished Jan 14 01:42:27 PM PST 24
Peak memory 194168 kb
Host smart-b73b1861-76a7-4f4e-9869-20208b804c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860152939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.860152939
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.324782688
Short name T358
Test name
Test status
Simulation time 395224656 ps
CPU time 8.68 seconds
Started Jan 14 01:42:26 PM PST 24
Finished Jan 14 01:42:36 PM PST 24
Peak memory 198136 kb
Host smart-4d4658f4-bc19-4556-ad0d-03e43303bd25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324782688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.324782688
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1589065998
Short name T251
Test name
Test status
Simulation time 114780014 ps
CPU time 0.68 seconds
Started Jan 14 01:42:27 PM PST 24
Finished Jan 14 01:42:29 PM PST 24
Peak memory 194752 kb
Host smart-0e3b497d-9856-4618-8189-999040967a19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589065998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1589065998
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2304950229
Short name T784
Test name
Test status
Simulation time 119990568 ps
CPU time 1.12 seconds
Started Jan 14 01:42:28 PM PST 24
Finished Jan 14 01:42:30 PM PST 24
Peak memory 196940 kb
Host smart-6d3c76d2-d109-4c7a-a55e-c99673ce03fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304950229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2304950229
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2715255374
Short name T884
Test name
Test status
Simulation time 88337360 ps
CPU time 2.04 seconds
Started Jan 14 01:42:24 PM PST 24
Finished Jan 14 01:42:28 PM PST 24
Peak memory 198256 kb
Host smart-c5276afb-6d0a-4d2a-a6ae-31789f540488
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715255374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2715255374
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.533860054
Short name T585
Test name
Test status
Simulation time 209795043 ps
CPU time 2.48 seconds
Started Jan 14 01:42:24 PM PST 24
Finished Jan 14 01:42:28 PM PST 24
Peak memory 197252 kb
Host smart-701a1093-99f7-4d84-8da0-9257183a0a4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533860054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
533860054
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.36422308
Short name T866
Test name
Test status
Simulation time 49430513 ps
CPU time 0.71 seconds
Started Jan 14 01:42:20 PM PST 24
Finished Jan 14 01:42:25 PM PST 24
Peak memory 196092 kb
Host smart-cce9d60c-72f8-4c9d-81fa-9152ce3e1ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36422308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.36422308
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.821872515
Short name T710
Test name
Test status
Simulation time 25871335 ps
CPU time 0.94 seconds
Started Jan 14 01:42:21 PM PST 24
Finished Jan 14 01:42:26 PM PST 24
Peak memory 196084 kb
Host smart-62ac4be9-198e-4e5b-be20-b0c715f0f593
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821872515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.821872515
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1171773802
Short name T253
Test name
Test status
Simulation time 108046174 ps
CPU time 4.86 seconds
Started Jan 14 01:42:25 PM PST 24
Finished Jan 14 01:42:31 PM PST 24
Peak memory 198092 kb
Host smart-e58fc6c2-fe2c-4d33-a6b1-a6c8fe8e821f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171773802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1171773802
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3831324096
Short name T582
Test name
Test status
Simulation time 92478240 ps
CPU time 1.17 seconds
Started Jan 14 01:42:20 PM PST 24
Finished Jan 14 01:42:26 PM PST 24
Peak memory 196856 kb
Host smart-0f7d933d-3c9b-4ca6-b3a9-171f6162c5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831324096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3831324096
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3498420169
Short name T566
Test name
Test status
Simulation time 31406840 ps
CPU time 0.94 seconds
Started Jan 14 01:42:22 PM PST 24
Finished Jan 14 01:42:26 PM PST 24
Peak memory 195648 kb
Host smart-8a7a4f1c-d005-4d88-965b-aca05bf1d43f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498420169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3498420169
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.350270782
Short name T258
Test name
Test status
Simulation time 31613180494 ps
CPU time 99.56 seconds
Started Jan 14 01:42:24 PM PST 24
Finished Jan 14 01:44:05 PM PST 24
Peak memory 198136 kb
Host smart-98f81787-4225-4e64-918f-29dcfba1c22a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350270782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.350270782
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1726240301
Short name T689
Test name
Test status
Simulation time 69453932353 ps
CPU time 1136.23 seconds
Started Jan 14 01:42:26 PM PST 24
Finished Jan 14 02:01:24 PM PST 24
Peak memory 198392 kb
Host smart-92d6252f-d0ec-4fdc-b56f-02df4cc7c154
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1726240301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1726240301
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3710285297
Short name T279
Test name
Test status
Simulation time 66763599 ps
CPU time 0.55 seconds
Started Jan 14 01:42:29 PM PST 24
Finished Jan 14 01:42:32 PM PST 24
Peak memory 194788 kb
Host smart-2780a27b-1d21-48b5-8df0-367ca8364332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710285297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3710285297
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2863862925
Short name T636
Test name
Test status
Simulation time 38295163 ps
CPU time 0.68 seconds
Started Jan 14 01:42:28 PM PST 24
Finished Jan 14 01:42:30 PM PST 24
Peak memory 195196 kb
Host smart-afb3fea1-8cf9-4212-9aaf-f2180eca8e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863862925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2863862925
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1145044737
Short name T588
Test name
Test status
Simulation time 638044972 ps
CPU time 19.18 seconds
Started Jan 14 01:42:28 PM PST 24
Finished Jan 14 01:42:48 PM PST 24
Peak memory 198172 kb
Host smart-0e39e898-c856-46d1-bb6b-78e656ae1271
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145044737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1145044737
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3544579481
Short name T535
Test name
Test status
Simulation time 80569585 ps
CPU time 0.96 seconds
Started Jan 14 01:42:28 PM PST 24
Finished Jan 14 01:42:30 PM PST 24
Peak memory 196724 kb
Host smart-5bd1bfc6-8041-4c08-8b09-41b94faf9ab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544579481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3544579481
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1904462378
Short name T329
Test name
Test status
Simulation time 219320743 ps
CPU time 0.98 seconds
Started Jan 14 01:42:27 PM PST 24
Finished Jan 14 01:42:29 PM PST 24
Peak memory 195868 kb
Host smart-11611146-493a-4728-9633-4c19a1588086
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904462378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1904462378
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.378206829
Short name T591
Test name
Test status
Simulation time 136011686 ps
CPU time 1.44 seconds
Started Jan 14 01:42:26 PM PST 24
Finished Jan 14 01:42:29 PM PST 24
Peak memory 197044 kb
Host smart-e0a314f1-fb9b-4c63-9578-fcb20cc69441
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378206829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.378206829
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.915236656
Short name T715
Test name
Test status
Simulation time 130654964 ps
CPU time 2.26 seconds
Started Jan 14 01:42:27 PM PST 24
Finished Jan 14 01:42:31 PM PST 24
Peak memory 197184 kb
Host smart-592a5b31-b19a-411d-be68-afa1f9715fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915236656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
915236656
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2547884731
Short name T348
Test name
Test status
Simulation time 17718713 ps
CPU time 0.74 seconds
Started Jan 14 01:42:25 PM PST 24
Finished Jan 14 01:42:27 PM PST 24
Peak memory 196256 kb
Host smart-1460ab31-955a-4480-aebb-eec6a5cadd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547884731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2547884731
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3970063600
Short name T829
Test name
Test status
Simulation time 35532598 ps
CPU time 1.24 seconds
Started Jan 14 01:42:26 PM PST 24
Finished Jan 14 01:42:29 PM PST 24
Peak memory 198192 kb
Host smart-fcfa2aa3-dd11-44bd-b23d-0807e063177b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970063600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3970063600
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.246593679
Short name T504
Test name
Test status
Simulation time 71231989 ps
CPU time 1.36 seconds
Started Jan 14 01:42:26 PM PST 24
Finished Jan 14 01:42:29 PM PST 24
Peak memory 198128 kb
Host smart-e0a8876e-6b71-48de-b82f-37aeb937af65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246593679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.246593679
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.578101788
Short name T620
Test name
Test status
Simulation time 66005520 ps
CPU time 0.88 seconds
Started Jan 14 01:42:25 PM PST 24
Finished Jan 14 01:42:27 PM PST 24
Peak memory 195820 kb
Host smart-1cb83f64-fe60-48e7-893c-afee2d6301c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578101788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.578101788
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2346977874
Short name T712
Test name
Test status
Simulation time 87971937 ps
CPU time 0.99 seconds
Started Jan 14 01:42:29 PM PST 24
Finished Jan 14 01:42:32 PM PST 24
Peak memory 195892 kb
Host smart-cbe2c8b8-2a79-4570-9c0f-07d65b304e4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346977874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2346977874
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2558627236
Short name T422
Test name
Test status
Simulation time 4851929670 ps
CPU time 125.38 seconds
Started Jan 14 01:42:28 PM PST 24
Finished Jan 14 01:44:35 PM PST 24
Peak memory 198296 kb
Host smart-347763f9-9f0e-4106-9def-590d9f8866e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558627236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2558627236
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.936065295
Short name T456
Test name
Test status
Simulation time 249357134115 ps
CPU time 868.36 seconds
Started Jan 14 01:42:27 PM PST 24
Finished Jan 14 01:56:57 PM PST 24
Peak memory 198376 kb
Host smart-185e1843-93aa-424e-837c-d88152410b0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=936065295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.936065295
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2403399217
Short name T836
Test name
Test status
Simulation time 38867755 ps
CPU time 0.53 seconds
Started Jan 14 01:42:34 PM PST 24
Finished Jan 14 01:42:36 PM PST 24
Peak memory 194016 kb
Host smart-9c2dcb4a-dc7e-40c0-ac67-e2f93c7de80d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403399217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2403399217
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.187155292
Short name T466
Test name
Test status
Simulation time 167486750 ps
CPU time 0.88 seconds
Started Jan 14 01:42:31 PM PST 24
Finished Jan 14 01:42:33 PM PST 24
Peak memory 197420 kb
Host smart-f32ba694-df4e-4f7d-aadf-a3939a618a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187155292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.187155292
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.784180526
Short name T758
Test name
Test status
Simulation time 1122020656 ps
CPU time 17.85 seconds
Started Jan 14 01:42:30 PM PST 24
Finished Jan 14 01:42:50 PM PST 24
Peak memory 197068 kb
Host smart-fee319c0-5be5-4c47-ad9b-6d83e8f370d3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784180526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.784180526
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.4285357768
Short name T545
Test name
Test status
Simulation time 168078419 ps
CPU time 0.59 seconds
Started Jan 14 01:42:33 PM PST 24
Finished Jan 14 01:42:35 PM PST 24
Peak memory 195148 kb
Host smart-b6f53da1-0969-4165-bf8a-5e47bedae83d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285357768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.4285357768
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2013615525
Short name T527
Test name
Test status
Simulation time 23378989 ps
CPU time 0.73 seconds
Started Jan 14 01:42:29 PM PST 24
Finished Jan 14 01:42:32 PM PST 24
Peak memory 194424 kb
Host smart-d242d895-dae5-4ce8-aa16-6945eabf9e6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013615525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2013615525
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.964693376
Short name T783
Test name
Test status
Simulation time 697859713 ps
CPU time 3.05 seconds
Started Jan 14 01:42:30 PM PST 24
Finished Jan 14 01:42:34 PM PST 24
Peak memory 198248 kb
Host smart-e4be80b9-4c7b-4e86-9757-e0c948cfee8e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964693376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.964693376
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.223315450
Short name T386
Test name
Test status
Simulation time 498687188 ps
CPU time 2.7 seconds
Started Jan 14 01:42:32 PM PST 24
Finished Jan 14 01:42:36 PM PST 24
Peak memory 196624 kb
Host smart-3c60f7ac-2872-45d4-ad2d-9d22f8eafd24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223315450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
223315450
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1082216797
Short name T855
Test name
Test status
Simulation time 324807201 ps
CPU time 0.7 seconds
Started Jan 14 01:42:29 PM PST 24
Finished Jan 14 01:42:32 PM PST 24
Peak memory 196184 kb
Host smart-7a9be46f-d3b3-4b21-bb0f-8619624a2335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082216797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1082216797
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2396046598
Short name T807
Test name
Test status
Simulation time 13620054 ps
CPU time 0.59 seconds
Started Jan 14 01:42:28 PM PST 24
Finished Jan 14 01:42:30 PM PST 24
Peak memory 194228 kb
Host smart-49b96f20-fcc9-46ef-8f7b-db4d5738e3b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396046598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2396046598
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1084804809
Short name T804
Test name
Test status
Simulation time 543479700 ps
CPU time 1.89 seconds
Started Jan 14 01:42:33 PM PST 24
Finished Jan 14 01:42:37 PM PST 24
Peak memory 198116 kb
Host smart-101fe8e3-ce80-4972-80b8-5bd1638e638f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084804809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1084804809
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.656592124
Short name T891
Test name
Test status
Simulation time 31998115 ps
CPU time 0.84 seconds
Started Jan 14 01:42:27 PM PST 24
Finished Jan 14 01:42:29 PM PST 24
Peak memory 195260 kb
Host smart-b8f3af82-119e-4692-9781-e60d3e8d91cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656592124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.656592124
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3673540182
Short name T581
Test name
Test status
Simulation time 75378931 ps
CPU time 1.14 seconds
Started Jan 14 01:42:28 PM PST 24
Finished Jan 14 01:42:30 PM PST 24
Peak memory 195696 kb
Host smart-93c7b13a-7d44-41df-821c-fd4fe254ef7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673540182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3673540182
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1346487093
Short name T790
Test name
Test status
Simulation time 16762831973 ps
CPU time 125.99 seconds
Started Jan 14 01:42:30 PM PST 24
Finished Jan 14 01:44:38 PM PST 24
Peak memory 198272 kb
Host smart-d348cd8f-d5dd-4a21-8ee1-f43a5bc6c0a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346487093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1346487093
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1108762349
Short name T887
Test name
Test status
Simulation time 48445399856 ps
CPU time 739.72 seconds
Started Jan 14 01:42:32 PM PST 24
Finished Jan 14 01:54:53 PM PST 24
Peak memory 198480 kb
Host smart-866d26bb-783c-4b50-bbbf-39ea4647ad5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1108762349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1108762349
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.271558109
Short name T48
Test name
Test status
Simulation time 14823237 ps
CPU time 0.57 seconds
Started Jan 14 01:42:32 PM PST 24
Finished Jan 14 01:42:34 PM PST 24
Peak memory 194808 kb
Host smart-147c71c9-3435-4d96-ab17-81850d272204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271558109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.271558109
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2752968886
Short name T410
Test name
Test status
Simulation time 35214016 ps
CPU time 0.79 seconds
Started Jan 14 01:42:32 PM PST 24
Finished Jan 14 01:42:34 PM PST 24
Peak memory 195936 kb
Host smart-4a521890-bec3-4632-8086-56a4208fb231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752968886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2752968886
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2102782373
Short name T332
Test name
Test status
Simulation time 1266986437 ps
CPU time 21.63 seconds
Started Jan 14 01:42:38 PM PST 24
Finished Jan 14 01:43:00 PM PST 24
Peak memory 198168 kb
Host smart-3cce0775-bbb3-4004-975e-db61d2cb004b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102782373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2102782373
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1542341658
Short name T492
Test name
Test status
Simulation time 99369594 ps
CPU time 0.68 seconds
Started Jan 14 01:42:40 PM PST 24
Finished Jan 14 01:42:42 PM PST 24
Peak memory 194776 kb
Host smart-76f94344-cdc3-4c62-b563-dcc9782e4530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542341658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1542341658
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2568730281
Short name T105
Test name
Test status
Simulation time 344227240 ps
CPU time 1.23 seconds
Started Jan 14 01:42:35 PM PST 24
Finished Jan 14 01:42:37 PM PST 24
Peak memory 198148 kb
Host smart-51732b14-a895-4148-8763-b14a37125fa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568730281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2568730281
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3206260225
Short name T820
Test name
Test status
Simulation time 293408828 ps
CPU time 1.94 seconds
Started Jan 14 01:42:36 PM PST 24
Finished Jan 14 01:42:39 PM PST 24
Peak memory 197960 kb
Host smart-70185ed7-9730-439d-a002-86eeac911277
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206260225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3206260225
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3103639376
Short name T649
Test name
Test status
Simulation time 41649640 ps
CPU time 1.21 seconds
Started Jan 14 01:42:35 PM PST 24
Finished Jan 14 01:42:38 PM PST 24
Peak memory 195952 kb
Host smart-55948815-c9e4-40de-ae84-4193a2683838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103639376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3103639376
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1132655527
Short name T754
Test name
Test status
Simulation time 18801803 ps
CPU time 0.7 seconds
Started Jan 14 01:42:37 PM PST 24
Finished Jan 14 01:42:39 PM PST 24
Peak memory 196116 kb
Host smart-02a9e91f-e2e6-4e54-be68-c13b2b0cc7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132655527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1132655527
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.149051356
Short name T318
Test name
Test status
Simulation time 63642803 ps
CPU time 1.26 seconds
Started Jan 14 01:42:37 PM PST 24
Finished Jan 14 01:42:40 PM PST 24
Peak memory 197124 kb
Host smart-43e0e431-0cb1-4308-b0a7-5dbaf74343f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149051356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.149051356
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.751584873
Short name T753
Test name
Test status
Simulation time 175651601 ps
CPU time 2.44 seconds
Started Jan 14 01:42:40 PM PST 24
Finished Jan 14 01:42:44 PM PST 24
Peak memory 198072 kb
Host smart-023c857e-587c-4bff-866e-687e84f97ab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751584873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.751584873
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3725194741
Short name T686
Test name
Test status
Simulation time 30619018 ps
CPU time 0.94 seconds
Started Jan 14 01:42:41 PM PST 24
Finished Jan 14 01:42:44 PM PST 24
Peak memory 196512 kb
Host smart-396f3df8-fe2c-47cd-8618-1740c1de2b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725194741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3725194741
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1990526218
Short name T269
Test name
Test status
Simulation time 128504981 ps
CPU time 1.04 seconds
Started Jan 14 01:42:36 PM PST 24
Finished Jan 14 01:42:38 PM PST 24
Peak memory 195936 kb
Host smart-167db1df-235e-41da-a44b-7bdcc7f18170
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990526218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1990526218
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3620986116
Short name T840
Test name
Test status
Simulation time 2972576689 ps
CPU time 72.99 seconds
Started Jan 14 01:42:32 PM PST 24
Finished Jan 14 01:43:47 PM PST 24
Peak memory 198124 kb
Host smart-fbb30df2-521c-4a7e-ac8f-c9ba89aa71a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620986116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3620986116
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1820739494
Short name T663
Test name
Test status
Simulation time 72867885270 ps
CPU time 598.66 seconds
Started Jan 14 01:42:38 PM PST 24
Finished Jan 14 01:52:37 PM PST 24
Peak memory 198384 kb
Host smart-c8e0aa59-9c51-4d80-b791-7a1913f716e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1820739494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1820739494
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.250857914
Short name T301
Test name
Test status
Simulation time 13049521 ps
CPU time 0.56 seconds
Started Jan 14 01:42:36 PM PST 24
Finished Jan 14 01:42:38 PM PST 24
Peak memory 194320 kb
Host smart-c8e9a21c-996e-4312-9a02-8327e48cc01c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250857914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.250857914
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3102993438
Short name T735
Test name
Test status
Simulation time 55022447 ps
CPU time 0.66 seconds
Started Jan 14 01:42:35 PM PST 24
Finished Jan 14 01:42:37 PM PST 24
Peak memory 194152 kb
Host smart-6cb281b5-b758-472b-95c8-fb1c5f5cec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102993438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3102993438
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1602058012
Short name T705
Test name
Test status
Simulation time 784349831 ps
CPU time 22.13 seconds
Started Jan 14 01:42:38 PM PST 24
Finished Jan 14 01:43:02 PM PST 24
Peak memory 196960 kb
Host smart-210be7dd-d91c-43d8-a79c-424063a9908a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602058012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1602058012
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3766195924
Short name T594
Test name
Test status
Simulation time 65216540 ps
CPU time 0.62 seconds
Started Jan 14 01:42:37 PM PST 24
Finished Jan 14 01:42:39 PM PST 24
Peak memory 194520 kb
Host smart-e32414a3-073f-412c-914c-785c783775fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766195924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3766195924
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3587769982
Short name T252
Test name
Test status
Simulation time 23184653 ps
CPU time 0.66 seconds
Started Jan 14 01:42:37 PM PST 24
Finished Jan 14 01:42:39 PM PST 24
Peak memory 194404 kb
Host smart-30eb97ea-7351-4240-9a51-4e8c0ba3c1f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587769982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3587769982
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.39279494
Short name T288
Test name
Test status
Simulation time 101316342 ps
CPU time 2.19 seconds
Started Jan 14 01:42:34 PM PST 24
Finished Jan 14 01:42:37 PM PST 24
Peak memory 198240 kb
Host smart-2725b548-9a5f-4eb3-8fcd-8123ec7f1843
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39279494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.gpio_intr_with_filter_rand_intr_event.39279494
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1502300440
Short name T309
Test name
Test status
Simulation time 125061527 ps
CPU time 1.15 seconds
Started Jan 14 01:42:39 PM PST 24
Finished Jan 14 01:42:42 PM PST 24
Peak memory 196640 kb
Host smart-f9ebc6b4-cd38-4aad-852d-8deffe45de2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502300440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1502300440
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2422319024
Short name T357
Test name
Test status
Simulation time 48597893 ps
CPU time 1.06 seconds
Started Jan 14 01:42:41 PM PST 24
Finished Jan 14 01:42:44 PM PST 24
Peak memory 196672 kb
Host smart-325b0039-201c-4e83-8dc8-99e601bb8b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422319024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2422319024
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1831309718
Short name T444
Test name
Test status
Simulation time 103294862 ps
CPU time 1.13 seconds
Started Jan 14 01:42:32 PM PST 24
Finished Jan 14 01:42:35 PM PST 24
Peak memory 196852 kb
Host smart-0ce23890-bfea-48f4-ba73-f4553f94ca2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831309718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1831309718
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.984131577
Short name T326
Test name
Test status
Simulation time 1281350987 ps
CPU time 5.15 seconds
Started Jan 14 01:42:36 PM PST 24
Finished Jan 14 01:42:42 PM PST 24
Peak memory 198140 kb
Host smart-f570e087-b3ef-4fab-98ff-9e34f7c15115
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984131577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.984131577
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1078621548
Short name T376
Test name
Test status
Simulation time 74241506 ps
CPU time 1.3 seconds
Started Jan 14 01:42:33 PM PST 24
Finished Jan 14 01:42:35 PM PST 24
Peak memory 195668 kb
Host smart-69b23329-2be3-4533-af71-9cb039a6e198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078621548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1078621548
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1678814499
Short name T599
Test name
Test status
Simulation time 180950991 ps
CPU time 1.04 seconds
Started Jan 14 01:42:37 PM PST 24
Finished Jan 14 01:42:39 PM PST 24
Peak memory 195808 kb
Host smart-66543607-9b24-47c0-b5b5-ff8f01d414c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678814499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1678814499
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2145994926
Short name T432
Test name
Test status
Simulation time 13301614762 ps
CPU time 177.09 seconds
Started Jan 14 01:42:35 PM PST 24
Finished Jan 14 01:45:33 PM PST 24
Peak memory 198244 kb
Host smart-d7833622-eff1-45ec-bd5a-a295a50af7c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145994926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2145994926
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.882404791
Short name T71
Test name
Test status
Simulation time 19563590575 ps
CPU time 256.94 seconds
Started Jan 14 01:42:34 PM PST 24
Finished Jan 14 01:46:52 PM PST 24
Peak memory 198388 kb
Host smart-2bd48eff-12a1-499d-9302-ef9c4ae10c67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=882404791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.882404791
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1802627770
Short name T244
Test name
Test status
Simulation time 54198683 ps
CPU time 0.57 seconds
Started Jan 14 01:42:42 PM PST 24
Finished Jan 14 01:42:45 PM PST 24
Peak memory 194252 kb
Host smart-c5ba941f-aa3a-40b3-8f3a-af3d8cb903b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802627770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1802627770
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3806042405
Short name T826
Test name
Test status
Simulation time 102242692 ps
CPU time 0.83 seconds
Started Jan 14 01:42:41 PM PST 24
Finished Jan 14 01:42:44 PM PST 24
Peak memory 195308 kb
Host smart-63038070-28be-4c71-92df-4253969298bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806042405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3806042405
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3666597655
Short name T762
Test name
Test status
Simulation time 3506544659 ps
CPU time 11.37 seconds
Started Jan 14 01:42:41 PM PST 24
Finished Jan 14 01:42:54 PM PST 24
Peak memory 196760 kb
Host smart-d6548931-998e-4bff-b1d1-5faf28d823c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666597655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3666597655
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.455745780
Short name T369
Test name
Test status
Simulation time 118303875 ps
CPU time 0.68 seconds
Started Jan 14 01:42:40 PM PST 24
Finished Jan 14 01:42:43 PM PST 24
Peak memory 195464 kb
Host smart-4c32a654-e3a5-4245-b5ca-4bced8caef79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455745780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.455745780
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3461487013
Short name T264
Test name
Test status
Simulation time 56297038 ps
CPU time 0.95 seconds
Started Jan 14 01:42:42 PM PST 24
Finished Jan 14 01:42:45 PM PST 24
Peak memory 196924 kb
Host smart-abbd3bec-c42d-434d-b0be-a5f0fe9365f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461487013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3461487013
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3679107998
Short name T750
Test name
Test status
Simulation time 170138272 ps
CPU time 3 seconds
Started Jan 14 01:42:41 PM PST 24
Finished Jan 14 01:42:46 PM PST 24
Peak memory 196952 kb
Host smart-66f51c27-6371-41be-a570-8772528c1a85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679107998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3679107998
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1348949806
Short name T267
Test name
Test status
Simulation time 37384072 ps
CPU time 0.87 seconds
Started Jan 14 01:42:39 PM PST 24
Finished Jan 14 01:42:41 PM PST 24
Peak memory 196512 kb
Host smart-98c2cd32-4425-47ee-8c49-1427dbbacea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348949806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1348949806
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.4009205536
Short name T793
Test name
Test status
Simulation time 56897093 ps
CPU time 1.11 seconds
Started Jan 14 01:42:50 PM PST 24
Finished Jan 14 01:42:53 PM PST 24
Peak memory 198080 kb
Host smart-c7d6a784-17d0-4d9c-bf3a-503126dccbfe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009205536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.4009205536
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2675746547
Short name T781
Test name
Test status
Simulation time 264727335 ps
CPU time 3.18 seconds
Started Jan 14 01:42:41 PM PST 24
Finished Jan 14 01:42:46 PM PST 24
Peak memory 198104 kb
Host smart-0d4696da-f6f0-407c-837a-671cf1fcc6d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675746547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2675746547
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.974253286
Short name T717
Test name
Test status
Simulation time 289167650 ps
CPU time 1.18 seconds
Started Jan 14 01:42:37 PM PST 24
Finished Jan 14 01:42:39 PM PST 24
Peak memory 195760 kb
Host smart-25d58dbf-40ce-4a02-8b60-55bd1ac61e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974253286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.974253286
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2984857399
Short name T880
Test name
Test status
Simulation time 49154100 ps
CPU time 1.09 seconds
Started Jan 14 01:42:37 PM PST 24
Finished Jan 14 01:42:39 PM PST 24
Peak memory 196544 kb
Host smart-50166908-04c2-4865-9be2-64cffa34a535
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984857399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2984857399
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3442505653
Short name T853
Test name
Test status
Simulation time 29255299248 ps
CPU time 184.76 seconds
Started Jan 14 01:42:40 PM PST 24
Finished Jan 14 01:45:46 PM PST 24
Peak memory 198308 kb
Host smart-3cfebcc7-a6ae-4e12-8633-de644732ab3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442505653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3442505653
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.4096324865
Short name T859
Test name
Test status
Simulation time 314587337033 ps
CPU time 1592.42 seconds
Started Jan 14 01:42:48 PM PST 24
Finished Jan 14 02:09:24 PM PST 24
Peak memory 198328 kb
Host smart-06eaa614-8a62-47ec-8f20-8fb341d2f95e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4096324865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.4096324865
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3045404414
Short name T470
Test name
Test status
Simulation time 11100047 ps
CPU time 0.59 seconds
Started Jan 14 01:42:41 PM PST 24
Finished Jan 14 01:42:44 PM PST 24
Peak memory 194276 kb
Host smart-9f6f8b5c-17b3-4111-974a-1e1de55eefb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045404414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3045404414
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3293457906
Short name T372
Test name
Test status
Simulation time 20618576 ps
CPU time 0.76 seconds
Started Jan 14 01:42:40 PM PST 24
Finished Jan 14 01:42:42 PM PST 24
Peak memory 195348 kb
Host smart-66c0a317-356a-47de-ba7a-61387d8b41a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293457906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3293457906
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.4032066248
Short name T518
Test name
Test status
Simulation time 295801007 ps
CPU time 16.14 seconds
Started Jan 14 01:42:50 PM PST 24
Finished Jan 14 01:43:08 PM PST 24
Peak memory 198060 kb
Host smart-3c2b47bd-724c-44c5-99d3-cd7ec96850db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032066248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.4032066248
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3381656599
Short name T294
Test name
Test status
Simulation time 313575603 ps
CPU time 0.84 seconds
Started Jan 14 01:42:47 PM PST 24
Finished Jan 14 01:42:52 PM PST 24
Peak memory 195908 kb
Host smart-56b225d5-24c2-4d44-a21c-60bfa7ab282a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381656599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3381656599
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3826015558
Short name T340
Test name
Test status
Simulation time 34524400 ps
CPU time 0.83 seconds
Started Jan 14 01:42:41 PM PST 24
Finished Jan 14 01:42:44 PM PST 24
Peak memory 195508 kb
Host smart-28e09d52-1330-4c50-9cbd-e2aa6505fe12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826015558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3826015558
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.4229627596
Short name T371
Test name
Test status
Simulation time 42979359 ps
CPU time 1.64 seconds
Started Jan 14 01:42:48 PM PST 24
Finished Jan 14 01:42:53 PM PST 24
Peak memory 196888 kb
Host smart-8c54127e-3d89-4527-a909-4ffca48152ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229627596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.4229627596
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.11093301
Short name T838
Test name
Test status
Simulation time 58530438 ps
CPU time 1.79 seconds
Started Jan 14 01:42:42 PM PST 24
Finished Jan 14 01:42:47 PM PST 24
Peak memory 195872 kb
Host smart-00adae25-f40b-44ed-b1a3-50afb44728bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11093301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.11093301
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3877217401
Short name T696
Test name
Test status
Simulation time 205835128 ps
CPU time 1 seconds
Started Jan 14 01:42:40 PM PST 24
Finished Jan 14 01:42:43 PM PST 24
Peak memory 196060 kb
Host smart-4a73d8c8-5f8f-419e-afb9-ff1ca92d6527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877217401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3877217401
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3675614547
Short name T362
Test name
Test status
Simulation time 68148371 ps
CPU time 1.26 seconds
Started Jan 14 01:42:41 PM PST 24
Finished Jan 14 01:42:45 PM PST 24
Peak memory 195928 kb
Host smart-0d906719-70d7-411f-80d5-b87be0b183ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675614547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3675614547
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.20137359
Short name T291
Test name
Test status
Simulation time 363337063 ps
CPU time 4.37 seconds
Started Jan 14 01:42:48 PM PST 24
Finished Jan 14 01:42:56 PM PST 24
Peak memory 198128 kb
Host smart-9f957049-c8bf-47b2-9534-a004eeb67748
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20137359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand
om_long_reg_writes_reg_reads.20137359
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.912601106
Short name T241
Test name
Test status
Simulation time 21835284 ps
CPU time 0.73 seconds
Started Jan 14 01:42:43 PM PST 24
Finished Jan 14 01:42:46 PM PST 24
Peak memory 194912 kb
Host smart-7ce78d23-1e47-4b91-aaf5-11cff223c540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912601106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.912601106
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3049591945
Short name T832
Test name
Test status
Simulation time 221208677 ps
CPU time 1.13 seconds
Started Jan 14 01:42:42 PM PST 24
Finished Jan 14 01:42:46 PM PST 24
Peak memory 195884 kb
Host smart-e97ecd32-c27c-482a-8fbc-b91b4d338c9e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049591945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3049591945
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2414834274
Short name T604
Test name
Test status
Simulation time 10146703378 ps
CPU time 112.04 seconds
Started Jan 14 01:42:38 PM PST 24
Finished Jan 14 01:44:32 PM PST 24
Peak memory 198292 kb
Host smart-4f5b231e-d135-4a41-94ae-b8cc775a6713
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414834274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2414834274
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1302140894
Short name T722
Test name
Test status
Simulation time 18398257279 ps
CPU time 534.81 seconds
Started Jan 14 01:42:39 PM PST 24
Finished Jan 14 01:51:35 PM PST 24
Peak memory 198408 kb
Host smart-cf168dbb-413d-414f-8d51-19832da2e1a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1302140894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1302140894
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1748631979
Short name T823
Test name
Test status
Simulation time 14332975 ps
CPU time 0.57 seconds
Started Jan 14 01:43:06 PM PST 24
Finished Jan 14 01:43:08 PM PST 24
Peak memory 194800 kb
Host smart-7c3ccc86-2f55-4557-b1b2-c49d7adcc1ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748631979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1748631979
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.387011036
Short name T284
Test name
Test status
Simulation time 49531495 ps
CPU time 0.61 seconds
Started Jan 14 01:42:51 PM PST 24
Finished Jan 14 01:42:54 PM PST 24
Peak memory 194696 kb
Host smart-581089c7-1cb9-4d41-82d8-9650cbebc524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387011036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.387011036
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3798391856
Short name T249
Test name
Test status
Simulation time 1258497735 ps
CPU time 22.52 seconds
Started Jan 14 01:43:10 PM PST 24
Finished Jan 14 01:43:34 PM PST 24
Peak memory 197112 kb
Host smart-0fb66542-a924-41f5-bd6a-8eed8eda4fab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798391856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3798391856
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3678485910
Short name T352
Test name
Test status
Simulation time 411102972 ps
CPU time 1.07 seconds
Started Jan 14 01:43:04 PM PST 24
Finished Jan 14 01:43:06 PM PST 24
Peak memory 196336 kb
Host smart-d6d8b19e-fc69-4e09-95f0-001dc5464e09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678485910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3678485910
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.78636283
Short name T104
Test name
Test status
Simulation time 33131349 ps
CPU time 0.78 seconds
Started Jan 14 01:43:09 PM PST 24
Finished Jan 14 01:43:12 PM PST 24
Peak memory 195692 kb
Host smart-edc477c3-b0f1-4834-be02-b7b3515e3be0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78636283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.78636283
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3222315566
Short name T827
Test name
Test status
Simulation time 25781532 ps
CPU time 1.08 seconds
Started Jan 14 01:43:07 PM PST 24
Finished Jan 14 01:43:10 PM PST 24
Peak memory 196096 kb
Host smart-54de1c45-939d-4af6-974d-658e298d8d26
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222315566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3222315566
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3784816077
Short name T792
Test name
Test status
Simulation time 36460106 ps
CPU time 0.96 seconds
Started Jan 14 01:43:03 PM PST 24
Finished Jan 14 01:43:05 PM PST 24
Peak memory 195632 kb
Host smart-07899441-7c8d-4897-a706-1ce73751b253
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784816077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3784816077
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3944762193
Short name T769
Test name
Test status
Simulation time 70461130 ps
CPU time 1.3 seconds
Started Jan 14 01:42:58 PM PST 24
Finished Jan 14 01:43:00 PM PST 24
Peak memory 198140 kb
Host smart-b311c573-aa6b-42b9-a447-0c319a9541fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944762193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3944762193
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1453832702
Short name T494
Test name
Test status
Simulation time 35990154 ps
CPU time 1.19 seconds
Started Jan 14 01:42:53 PM PST 24
Finished Jan 14 01:42:58 PM PST 24
Peak memory 197124 kb
Host smart-4caa5138-608c-4f3b-a8ad-3a3c0b9b94cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453832702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1453832702
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3897067827
Short name T467
Test name
Test status
Simulation time 181180999 ps
CPU time 2.35 seconds
Started Jan 14 01:43:07 PM PST 24
Finished Jan 14 01:43:12 PM PST 24
Peak memory 198120 kb
Host smart-95bc31cc-b716-417b-be7f-50953b6aac27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897067827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3897067827
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1932817726
Short name T675
Test name
Test status
Simulation time 49810483 ps
CPU time 1.33 seconds
Started Jan 14 01:42:53 PM PST 24
Finished Jan 14 01:42:58 PM PST 24
Peak memory 196808 kb
Host smart-9fa91e2e-fca5-48a6-8eed-853354a6ee17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932817726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1932817726
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.427445255
Short name T239
Test name
Test status
Simulation time 440615849 ps
CPU time 1.37 seconds
Started Jan 14 01:42:51 PM PST 24
Finished Jan 14 01:42:57 PM PST 24
Peak memory 198072 kb
Host smart-4e4bcf8a-3185-4a78-b704-9337d0e86a7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427445255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.427445255
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3347489046
Short name T780
Test name
Test status
Simulation time 13812191224 ps
CPU time 170.93 seconds
Started Jan 14 01:43:06 PM PST 24
Finished Jan 14 01:45:59 PM PST 24
Peak memory 198260 kb
Host smart-8a604d94-04ea-4648-8acf-cdb45a7f12ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347489046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3347489046
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3048582420
Short name T439
Test name
Test status
Simulation time 122455071792 ps
CPU time 1527.89 seconds
Started Jan 14 01:43:03 PM PST 24
Finished Jan 14 02:08:32 PM PST 24
Peak memory 198380 kb
Host smart-e358a4b8-c231-47bf-8d58-0fefc5b14120
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3048582420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3048582420
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.342370572
Short name T50
Test name
Test status
Simulation time 15523368 ps
CPU time 0.56 seconds
Started Jan 14 01:43:14 PM PST 24
Finished Jan 14 01:43:17 PM PST 24
Peak memory 194308 kb
Host smart-306705b7-bc35-45f9-97dd-7ada5bf25608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342370572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.342370572
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2627818209
Short name T498
Test name
Test status
Simulation time 175329921 ps
CPU time 0.83 seconds
Started Jan 14 01:43:09 PM PST 24
Finished Jan 14 01:43:12 PM PST 24
Peak memory 196072 kb
Host smart-3b17544a-6a2f-4bf8-8525-678e8c69d37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627818209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2627818209
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.85785698
Short name T378
Test name
Test status
Simulation time 1188552408 ps
CPU time 15.09 seconds
Started Jan 14 01:43:04 PM PST 24
Finished Jan 14 01:43:21 PM PST 24
Peak memory 196912 kb
Host smart-4f468d80-378a-405c-b9d6-2c3cfe83e7eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85785698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stress
.85785698
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2888553066
Short name T808
Test name
Test status
Simulation time 163832234 ps
CPU time 0.77 seconds
Started Jan 14 01:43:07 PM PST 24
Finished Jan 14 01:43:10 PM PST 24
Peak memory 195980 kb
Host smart-205561a8-c429-475b-87f8-394184456f2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888553066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2888553066
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3478666767
Short name T794
Test name
Test status
Simulation time 79446225 ps
CPU time 0.67 seconds
Started Jan 14 01:43:07 PM PST 24
Finished Jan 14 01:43:10 PM PST 24
Peak memory 195152 kb
Host smart-f2294987-108a-4026-bf3c-19d97aa8362a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478666767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3478666767
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.4264810922
Short name T540
Test name
Test status
Simulation time 95516289 ps
CPU time 3.56 seconds
Started Jan 14 01:43:05 PM PST 24
Finished Jan 14 01:43:11 PM PST 24
Peak memory 198188 kb
Host smart-0ace7713-2a6b-4489-bff4-25a402d3ccb5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264810922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.4264810922
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1108934565
Short name T608
Test name
Test status
Simulation time 333713943 ps
CPU time 3.25 seconds
Started Jan 14 01:43:06 PM PST 24
Finished Jan 14 01:43:12 PM PST 24
Peak memory 198204 kb
Host smart-bf8b3ff6-a9ff-4578-a459-6c3593bec5b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108934565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1108934565
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.707394839
Short name T575
Test name
Test status
Simulation time 250083098 ps
CPU time 0.96 seconds
Started Jan 14 01:43:09 PM PST 24
Finished Jan 14 01:43:12 PM PST 24
Peak memory 195960 kb
Host smart-bafca0d1-fb02-49bb-ab59-3660ab3208c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707394839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.707394839
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3898734898
Short name T513
Test name
Test status
Simulation time 61282067 ps
CPU time 1.32 seconds
Started Jan 14 01:43:04 PM PST 24
Finished Jan 14 01:43:06 PM PST 24
Peak memory 198160 kb
Host smart-828940e1-6473-494e-a56f-c981c1a2250f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898734898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3898734898
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.591364177
Short name T568
Test name
Test status
Simulation time 385376817 ps
CPU time 5.53 seconds
Started Jan 14 01:43:09 PM PST 24
Finished Jan 14 01:43:16 PM PST 24
Peak memory 198136 kb
Host smart-93901c77-cf58-40e5-b83a-98ace66352bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591364177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.591364177
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3818105102
Short name T407
Test name
Test status
Simulation time 202142184 ps
CPU time 1.39 seconds
Started Jan 14 01:43:07 PM PST 24
Finished Jan 14 01:43:11 PM PST 24
Peak memory 198120 kb
Host smart-444a208f-b5fb-467c-9450-fda12d93115c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818105102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3818105102
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1008827111
Short name T254
Test name
Test status
Simulation time 96223120 ps
CPU time 0.79 seconds
Started Jan 14 01:43:03 PM PST 24
Finished Jan 14 01:43:05 PM PST 24
Peak memory 195472 kb
Host smart-a5d7d9a5-827b-414d-bb4d-fe2a49c51800
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008827111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1008827111
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.196572021
Short name T863
Test name
Test status
Simulation time 30639933707 ps
CPU time 218.49 seconds
Started Jan 14 01:43:06 PM PST 24
Finished Jan 14 01:46:48 PM PST 24
Peak memory 198292 kb
Host smart-cc4c2437-3260-4da8-8c30-28345c928514
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196572021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.196572021
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.1417690483
Short name T511
Test name
Test status
Simulation time 155902690800 ps
CPU time 2003.46 seconds
Started Jan 14 01:43:07 PM PST 24
Finished Jan 14 02:16:33 PM PST 24
Peak memory 198428 kb
Host smart-aacab8f5-3688-42c6-a82e-31c9d4d67e5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1417690483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.1417690483
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1651559565
Short name T879
Test name
Test status
Simulation time 15321888 ps
CPU time 0.6 seconds
Started Jan 14 01:40:53 PM PST 24
Finished Jan 14 01:40:54 PM PST 24
Peak memory 194296 kb
Host smart-2e1ad24e-3c00-4a53-981e-dc053bb45d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651559565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1651559565
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2338163818
Short name T626
Test name
Test status
Simulation time 24520802 ps
CPU time 0.66 seconds
Started Jan 14 01:40:46 PM PST 24
Finished Jan 14 01:40:48 PM PST 24
Peak memory 194208 kb
Host smart-a00f9438-4925-490f-af94-5a6276d1f07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338163818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2338163818
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1895524447
Short name T822
Test name
Test status
Simulation time 6504539153 ps
CPU time 9.8 seconds
Started Jan 14 01:40:41 PM PST 24
Finished Jan 14 01:40:52 PM PST 24
Peak memory 196916 kb
Host smart-8525d292-b2b4-408a-bd84-f6137735b010
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895524447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1895524447
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2994185081
Short name T757
Test name
Test status
Simulation time 21095037 ps
CPU time 0.64 seconds
Started Jan 14 01:40:42 PM PST 24
Finished Jan 14 01:40:43 PM PST 24
Peak memory 194348 kb
Host smart-29e0f3d8-0535-4731-ae9c-c650b788ec62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994185081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2994185081
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1577144172
Short name T268
Test name
Test status
Simulation time 138013087 ps
CPU time 1.19 seconds
Started Jan 14 01:40:50 PM PST 24
Finished Jan 14 01:40:51 PM PST 24
Peak memory 195912 kb
Host smart-2e0220b2-85a8-4c38-bf21-27ffafcbbb8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577144172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1577144172
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.457166294
Short name T316
Test name
Test status
Simulation time 303873138 ps
CPU time 1.68 seconds
Started Jan 14 01:40:39 PM PST 24
Finished Jan 14 01:40:41 PM PST 24
Peak memory 198292 kb
Host smart-5005ae1b-b46a-4c13-8531-ddfa27c0cac7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457166294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.457166294
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2005014190
Short name T521
Test name
Test status
Simulation time 65814439 ps
CPU time 1.18 seconds
Started Jan 14 01:40:39 PM PST 24
Finished Jan 14 01:40:41 PM PST 24
Peak memory 197564 kb
Host smart-b540629b-3784-4fc1-8e77-815430eb7cdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005014190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2005014190
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2575103580
Short name T349
Test name
Test status
Simulation time 186844865 ps
CPU time 0.95 seconds
Started Jan 14 01:40:45 PM PST 24
Finished Jan 14 01:40:47 PM PST 24
Peak memory 196096 kb
Host smart-64e5cd90-c555-4099-b21d-1ae9cd77d0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575103580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2575103580
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2873693906
Short name T850
Test name
Test status
Simulation time 32495787 ps
CPU time 0.75 seconds
Started Jan 14 01:40:50 PM PST 24
Finished Jan 14 01:40:52 PM PST 24
Peak memory 195432 kb
Host smart-936ca4a9-32f3-4cb3-b266-dd3727729c45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873693906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2873693906
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1091171229
Short name T702
Test name
Test status
Simulation time 295071288 ps
CPU time 4.62 seconds
Started Jan 14 01:40:48 PM PST 24
Finished Jan 14 01:40:53 PM PST 24
Peak memory 198044 kb
Host smart-5aa140ad-d922-457a-b2f9-9f1993f47d21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091171229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1091171229
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3226996423
Short name T28
Test name
Test status
Simulation time 181550699 ps
CPU time 0.76 seconds
Started Jan 14 01:40:51 PM PST 24
Finished Jan 14 01:40:52 PM PST 24
Peak memory 213576 kb
Host smart-eaee7053-cccb-4bf9-99e8-220ff6a3abf4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226996423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3226996423
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2936414728
Short name T688
Test name
Test status
Simulation time 75059139 ps
CPU time 1.33 seconds
Started Jan 14 01:40:41 PM PST 24
Finished Jan 14 01:40:44 PM PST 24
Peak memory 196812 kb
Host smart-567f70ac-48fb-45a0-8f4b-ac35f3188d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936414728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2936414728
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1198316262
Short name T449
Test name
Test status
Simulation time 145183339 ps
CPU time 1.01 seconds
Started Jan 14 01:40:40 PM PST 24
Finished Jan 14 01:40:41 PM PST 24
Peak memory 195732 kb
Host smart-c25de597-4dc4-4f38-a17f-b5d959fa2496
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198316262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1198316262
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2944479036
Short name T103
Test name
Test status
Simulation time 9001028487 ps
CPU time 122.14 seconds
Started Jan 14 01:40:53 PM PST 24
Finished Jan 14 01:42:56 PM PST 24
Peak memory 198296 kb
Host smart-5afc7fc7-e54c-420f-a856-fd47bbeb4b6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944479036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2944479036
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.350123614
Short name T526
Test name
Test status
Simulation time 270942311218 ps
CPU time 1708.59 seconds
Started Jan 14 01:40:58 PM PST 24
Finished Jan 14 02:09:28 PM PST 24
Peak memory 198412 kb
Host smart-63d1bf0c-435c-4017-87ad-232be355bbe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=350123614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.350123614
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3177013100
Short name T868
Test name
Test status
Simulation time 14057416 ps
CPU time 0.57 seconds
Started Jan 14 01:43:09 PM PST 24
Finished Jan 14 01:43:11 PM PST 24
Peak memory 194968 kb
Host smart-5693bce8-c9ef-4ee9-a989-99896a0b528a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177013100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3177013100
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2462884556
Short name T547
Test name
Test status
Simulation time 55244405 ps
CPU time 0.6 seconds
Started Jan 14 01:43:08 PM PST 24
Finished Jan 14 01:43:10 PM PST 24
Peak memory 194104 kb
Host smart-a401b0a1-950c-4eb5-847e-89dfa7e22972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462884556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2462884556
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3729076981
Short name T713
Test name
Test status
Simulation time 1534158916 ps
CPU time 9.39 seconds
Started Jan 14 01:43:07 PM PST 24
Finished Jan 14 01:43:19 PM PST 24
Peak memory 196980 kb
Host smart-5b7f4c1a-1f2e-4231-86c4-34d5f99acdac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729076981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3729076981
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1425491922
Short name T888
Test name
Test status
Simulation time 151281082 ps
CPU time 1.03 seconds
Started Jan 14 01:43:11 PM PST 24
Finished Jan 14 01:43:14 PM PST 24
Peak memory 197924 kb
Host smart-20a45066-b70f-4318-a90a-df3bcdc4008f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425491922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1425491922
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1409194635
Short name T523
Test name
Test status
Simulation time 39553347 ps
CPU time 0.86 seconds
Started Jan 14 01:43:07 PM PST 24
Finished Jan 14 01:43:10 PM PST 24
Peak memory 196664 kb
Host smart-66c37767-0e14-424c-be81-7857b63e5f8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409194635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1409194635
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3207546222
Short name T502
Test name
Test status
Simulation time 109952407 ps
CPU time 2.29 seconds
Started Jan 14 01:43:09 PM PST 24
Finished Jan 14 01:43:13 PM PST 24
Peak memory 198232 kb
Host smart-d4131143-725a-4d05-ab53-28d31e984363
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207546222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3207546222
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3597158804
Short name T706
Test name
Test status
Simulation time 231490993 ps
CPU time 3.42 seconds
Started Jan 14 01:43:10 PM PST 24
Finished Jan 14 01:43:16 PM PST 24
Peak memory 196640 kb
Host smart-512d3911-750e-434d-bc8e-cb476cc0d2ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597158804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3597158804
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1891172822
Short name T314
Test name
Test status
Simulation time 244895750 ps
CPU time 1.15 seconds
Started Jan 14 01:43:16 PM PST 24
Finished Jan 14 01:43:19 PM PST 24
Peak memory 197224 kb
Host smart-e34eceb6-d2c6-482f-8636-fcd41d1d960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891172822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1891172822
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2671074095
Short name T612
Test name
Test status
Simulation time 217823698 ps
CPU time 1.33 seconds
Started Jan 14 01:43:06 PM PST 24
Finished Jan 14 01:43:10 PM PST 24
Peak memory 198096 kb
Host smart-0ddfaa3e-db02-4cc2-b370-2ed0711278a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671074095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2671074095
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1109442339
Short name T395
Test name
Test status
Simulation time 494520838 ps
CPU time 4.64 seconds
Started Jan 14 01:43:08 PM PST 24
Finished Jan 14 01:43:14 PM PST 24
Peak memory 198100 kb
Host smart-94ce724c-b990-480d-9d8b-42772a26df39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109442339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1109442339
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3249810672
Short name T720
Test name
Test status
Simulation time 225364511 ps
CPU time 1.2 seconds
Started Jan 14 01:43:16 PM PST 24
Finished Jan 14 01:43:19 PM PST 24
Peak memory 196564 kb
Host smart-f0e18a6a-64b3-4549-9972-f040bc4cabe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249810672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3249810672
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.46828621
Short name T300
Test name
Test status
Simulation time 187310376 ps
CPU time 0.8 seconds
Started Jan 14 01:43:09 PM PST 24
Finished Jan 14 01:43:12 PM PST 24
Peak memory 195984 kb
Host smart-b01ef139-85dc-4143-a580-a40316704f5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46828621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.46828621
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2502800973
Short name T741
Test name
Test status
Simulation time 1146998714 ps
CPU time 27.78 seconds
Started Jan 14 01:43:09 PM PST 24
Finished Jan 14 01:43:39 PM PST 24
Peak memory 198268 kb
Host smart-c6a4bf3e-a9c2-4699-b43e-7827b4aa53cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502800973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2502800973
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1125590812
Short name T312
Test name
Test status
Simulation time 182950812196 ps
CPU time 1113.96 seconds
Started Jan 14 01:43:09 PM PST 24
Finished Jan 14 02:01:45 PM PST 24
Peak memory 198432 kb
Host smart-1b52a30b-7523-44f5-a89c-4772877387e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1125590812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1125590812
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.359634218
Short name T659
Test name
Test status
Simulation time 23104186 ps
CPU time 0.56 seconds
Started Jan 14 01:43:13 PM PST 24
Finished Jan 14 01:43:15 PM PST 24
Peak memory 194292 kb
Host smart-dc97c4b2-0a14-4c49-9c1b-c7122cc8df89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359634218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.359634218
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3447364867
Short name T815
Test name
Test status
Simulation time 55744393 ps
CPU time 0.74 seconds
Started Jan 14 01:43:11 PM PST 24
Finished Jan 14 01:43:14 PM PST 24
Peak memory 196204 kb
Host smart-6ca6d426-177f-4481-ad91-c2104b169d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447364867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3447364867
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1809572713
Short name T412
Test name
Test status
Simulation time 593500616 ps
CPU time 15.95 seconds
Started Jan 14 01:43:14 PM PST 24
Finished Jan 14 01:43:33 PM PST 24
Peak memory 198136 kb
Host smart-7ca9cfc6-973c-4abf-ad84-2449f6c2718c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809572713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1809572713
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.334546990
Short name T708
Test name
Test status
Simulation time 268972934 ps
CPU time 0.91 seconds
Started Jan 14 01:43:12 PM PST 24
Finished Jan 14 01:43:15 PM PST 24
Peak memory 195932 kb
Host smart-3cdf5067-7ab2-4918-817a-fd627c05a1c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334546990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.334546990
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2066260748
Short name T603
Test name
Test status
Simulation time 191122874 ps
CPU time 1.28 seconds
Started Jan 14 01:43:12 PM PST 24
Finished Jan 14 01:43:15 PM PST 24
Peak memory 197164 kb
Host smart-a76f01da-a18a-415f-b128-9ca07793bb36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066260748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2066260748
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.4035277221
Short name T873
Test name
Test status
Simulation time 47134251 ps
CPU time 1.86 seconds
Started Jan 14 01:43:11 PM PST 24
Finished Jan 14 01:43:15 PM PST 24
Peak memory 198180 kb
Host smart-71d17540-ccbd-4e73-b600-a79ccd9cafaa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035277221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.4035277221
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1737868045
Short name T261
Test name
Test status
Simulation time 174365616 ps
CPU time 3.16 seconds
Started Jan 14 01:43:14 PM PST 24
Finished Jan 14 01:43:19 PM PST 24
Peak memory 198188 kb
Host smart-6d9b6d69-3d84-4958-b210-30b08b77aac2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737868045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1737868045
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3136184626
Short name T647
Test name
Test status
Simulation time 31899670 ps
CPU time 1.04 seconds
Started Jan 14 01:43:10 PM PST 24
Finished Jan 14 01:43:13 PM PST 24
Peak memory 196100 kb
Host smart-9c396e3e-e7e3-4981-a196-608884ad20f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136184626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3136184626
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2003185207
Short name T510
Test name
Test status
Simulation time 221236178 ps
CPU time 1.1 seconds
Started Jan 14 01:43:14 PM PST 24
Finished Jan 14 01:43:17 PM PST 24
Peak memory 195544 kb
Host smart-86eddc3e-a8ed-4d1e-b830-efd19a88df9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003185207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2003185207
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1615733326
Short name T539
Test name
Test status
Simulation time 312852586 ps
CPU time 3 seconds
Started Jan 14 01:43:14 PM PST 24
Finished Jan 14 01:43:20 PM PST 24
Peak memory 198120 kb
Host smart-b2d823eb-da15-40af-bc46-c1f2caa5111f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615733326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1615733326
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2847843896
Short name T335
Test name
Test status
Simulation time 240488724 ps
CPU time 0.85 seconds
Started Jan 14 01:43:12 PM PST 24
Finished Jan 14 01:43:15 PM PST 24
Peak memory 196476 kb
Host smart-44c57d53-f229-428c-ba54-0a9545d471a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847843896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2847843896
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2839245330
Short name T306
Test name
Test status
Simulation time 155758634 ps
CPU time 1.21 seconds
Started Jan 14 01:43:10 PM PST 24
Finished Jan 14 01:43:14 PM PST 24
Peak memory 197028 kb
Host smart-24e6d1a2-a479-4333-a6ba-cfdeb056cb45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839245330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2839245330
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3730700440
Short name T512
Test name
Test status
Simulation time 51741811772 ps
CPU time 184.23 seconds
Started Jan 14 01:43:14 PM PST 24
Finished Jan 14 01:46:20 PM PST 24
Peak memory 198292 kb
Host smart-3b091dfa-0693-4c08-bf9e-e790f60d7be7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730700440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3730700440
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.42296308
Short name T580
Test name
Test status
Simulation time 722897734408 ps
CPU time 2072.46 seconds
Started Jan 14 01:43:11 PM PST 24
Finished Jan 14 02:17:46 PM PST 24
Peak memory 198404 kb
Host smart-01433f0f-fbfb-4a02-91a5-3932368b51a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=42296308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.42296308
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.636613597
Short name T303
Test name
Test status
Simulation time 18332177 ps
CPU time 0.56 seconds
Started Jan 14 01:43:10 PM PST 24
Finished Jan 14 01:43:13 PM PST 24
Peak memory 194732 kb
Host smart-a9c67c3c-d466-40e2-affb-deb595482265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636613597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.636613597
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3637148626
Short name T671
Test name
Test status
Simulation time 49036077 ps
CPU time 0.72 seconds
Started Jan 14 01:43:11 PM PST 24
Finished Jan 14 01:43:14 PM PST 24
Peak memory 194220 kb
Host smart-1aa3da54-e4af-4a15-9df4-a8ebecbc0319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637148626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3637148626
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3845005655
Short name T423
Test name
Test status
Simulation time 306848125 ps
CPU time 11.1 seconds
Started Jan 14 01:43:11 PM PST 24
Finished Jan 14 01:43:24 PM PST 24
Peak memory 197120 kb
Host smart-71178521-5408-4653-b435-d583d5fc0fc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845005655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3845005655
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.431967238
Short name T798
Test name
Test status
Simulation time 179075227 ps
CPU time 0.79 seconds
Started Jan 14 01:43:12 PM PST 24
Finished Jan 14 01:43:15 PM PST 24
Peak memory 196628 kb
Host smart-de582d8f-33cd-47e4-a299-c57c43921c5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431967238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.431967238
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1839746518
Short name T247
Test name
Test status
Simulation time 138428577 ps
CPU time 1.01 seconds
Started Jan 14 01:43:10 PM PST 24
Finished Jan 14 01:43:13 PM PST 24
Peak memory 196220 kb
Host smart-11367e7b-0a58-4d55-b1b6-952c2ff26d9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839746518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1839746518
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.552565690
Short name T635
Test name
Test status
Simulation time 114420590 ps
CPU time 3.03 seconds
Started Jan 14 01:43:10 PM PST 24
Finished Jan 14 01:43:15 PM PST 24
Peak memory 196660 kb
Host smart-651c5e18-3fa6-4a51-badf-9e5cdfe185b7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552565690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.552565690
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.46930117
Short name T224
Test name
Test status
Simulation time 729384779 ps
CPU time 1.82 seconds
Started Jan 14 01:43:14 PM PST 24
Finished Jan 14 01:43:17 PM PST 24
Peak memory 195344 kb
Host smart-6106fb69-51a7-4916-ad8f-6e636e7317f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46930117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.46930117
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3803842754
Short name T452
Test name
Test status
Simulation time 167384494 ps
CPU time 1.04 seconds
Started Jan 14 01:43:13 PM PST 24
Finished Jan 14 01:43:16 PM PST 24
Peak memory 196036 kb
Host smart-1168b9f0-4b08-4d99-97f5-0ebb666585f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803842754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3803842754
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.889326240
Short name T583
Test name
Test status
Simulation time 100036359 ps
CPU time 0.8 seconds
Started Jan 14 01:43:11 PM PST 24
Finished Jan 14 01:43:14 PM PST 24
Peak memory 197272 kb
Host smart-8ca07d8e-0cdb-4269-b519-c322594020bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889326240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.889326240
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.4104179865
Short name T457
Test name
Test status
Simulation time 345061651 ps
CPU time 5.36 seconds
Started Jan 14 01:43:10 PM PST 24
Finished Jan 14 01:43:18 PM PST 24
Peak memory 198096 kb
Host smart-1de28593-1f11-4308-928c-fb9bba396d9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104179865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.4104179865
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2487695811
Short name T534
Test name
Test status
Simulation time 431909470 ps
CPU time 1.32 seconds
Started Jan 14 01:43:10 PM PST 24
Finished Jan 14 01:43:14 PM PST 24
Peak memory 195720 kb
Host smart-bb6876a1-74c1-401f-8c11-c6b670c3ae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487695811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2487695811
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.220587049
Short name T697
Test name
Test status
Simulation time 253555399 ps
CPU time 1.11 seconds
Started Jan 14 01:43:13 PM PST 24
Finished Jan 14 01:43:17 PM PST 24
Peak memory 195920 kb
Host smart-a10aaf98-df6d-416d-94d5-32edeacd0ce9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220587049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.220587049
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.429931825
Short name T669
Test name
Test status
Simulation time 7141485029 ps
CPU time 169.71 seconds
Started Jan 14 01:43:10 PM PST 24
Finished Jan 14 01:46:02 PM PST 24
Peak memory 198216 kb
Host smart-a13ee3cb-f391-4b44-9e8e-64bf0b877764
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429931825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.429931825
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2931502458
Short name T562
Test name
Test status
Simulation time 59011673391 ps
CPU time 766.57 seconds
Started Jan 14 01:43:09 PM PST 24
Finished Jan 14 01:55:57 PM PST 24
Peak memory 198400 kb
Host smart-520d7705-4ac1-4c1f-a16a-081dd16dac1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2931502458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2931502458
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1684737956
Short name T524
Test name
Test status
Simulation time 20104468 ps
CPU time 0.58 seconds
Started Jan 14 01:43:12 PM PST 24
Finished Jan 14 01:43:15 PM PST 24
Peak memory 194148 kb
Host smart-cc2831cd-c46b-422a-ba1f-48da7fdc7625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684737956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1684737956
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3837500873
Short name T681
Test name
Test status
Simulation time 28301442 ps
CPU time 0.87 seconds
Started Jan 14 01:43:19 PM PST 24
Finished Jan 14 01:43:22 PM PST 24
Peak memory 196392 kb
Host smart-afcb6489-87cc-4b12-85dc-282e8265d4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837500873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3837500873
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.852781516
Short name T845
Test name
Test status
Simulation time 256068301 ps
CPU time 3.58 seconds
Started Jan 14 01:43:19 PM PST 24
Finished Jan 14 01:43:24 PM PST 24
Peak memory 196020 kb
Host smart-7ccd25ad-a51b-4f46-bafd-8f6b493df320
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852781516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.852781516
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1163178004
Short name T676
Test name
Test status
Simulation time 43708478 ps
CPU time 0.74 seconds
Started Jan 14 01:43:13 PM PST 24
Finished Jan 14 01:43:16 PM PST 24
Peak memory 195960 kb
Host smart-b88810dd-ee76-425a-b600-f0e6f81922d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163178004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1163178004
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2464154479
Short name T830
Test name
Test status
Simulation time 90304005 ps
CPU time 1.2 seconds
Started Jan 14 01:43:18 PM PST 24
Finished Jan 14 01:43:21 PM PST 24
Peak memory 195968 kb
Host smart-2a5f339f-bef3-489b-bc9b-3b30b500660e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464154479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2464154479
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1760582616
Short name T383
Test name
Test status
Simulation time 109903099 ps
CPU time 1.87 seconds
Started Jan 14 01:43:10 PM PST 24
Finished Jan 14 01:43:15 PM PST 24
Peak memory 198100 kb
Host smart-a80bf6d6-77f0-4b39-a88e-373e370b8df5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760582616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1760582616
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.81467624
Short name T553
Test name
Test status
Simulation time 56138372 ps
CPU time 1.89 seconds
Started Jan 14 01:43:14 PM PST 24
Finished Jan 14 01:43:18 PM PST 24
Peak memory 196044 kb
Host smart-7c44d6e8-9319-4b04-bf93-301ad58f0e71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81467624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.81467624
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2120063852
Short name T68
Test name
Test status
Simulation time 26190217 ps
CPU time 0.92 seconds
Started Jan 14 01:43:19 PM PST 24
Finished Jan 14 01:43:21 PM PST 24
Peak memory 196160 kb
Host smart-1f8aca34-9b5a-4176-9b43-84288aa9369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120063852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2120063852
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.465696470
Short name T474
Test name
Test status
Simulation time 39887277 ps
CPU time 0.92 seconds
Started Jan 14 01:43:19 PM PST 24
Finished Jan 14 01:43:21 PM PST 24
Peak memory 196172 kb
Host smart-fffb6ad3-e387-4954-acec-74f54849b665
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465696470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.465696470
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1576160462
Short name T586
Test name
Test status
Simulation time 281837033 ps
CPU time 5.87 seconds
Started Jan 14 01:43:19 PM PST 24
Finished Jan 14 01:43:27 PM PST 24
Peak memory 198132 kb
Host smart-320d86ac-c68a-4f8e-919a-94a6c6fbfc62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576160462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1576160462
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.164001807
Short name T360
Test name
Test status
Simulation time 195922908 ps
CPU time 0.98 seconds
Started Jan 14 01:43:14 PM PST 24
Finished Jan 14 01:43:17 PM PST 24
Peak memory 195840 kb
Host smart-8909399b-b2c1-4a52-8c47-25152dca7eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164001807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.164001807
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.902257945
Short name T237
Test name
Test status
Simulation time 582971600 ps
CPU time 1.48 seconds
Started Jan 14 01:43:13 PM PST 24
Finished Jan 14 01:43:17 PM PST 24
Peak memory 196904 kb
Host smart-546cf42e-27f2-4e13-b89a-1726fb9e96ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902257945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.902257945
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.4260582942
Short name T870
Test name
Test status
Simulation time 3044664574 ps
CPU time 75.97 seconds
Started Jan 14 01:43:14 PM PST 24
Finished Jan 14 01:44:32 PM PST 24
Peak memory 198228 kb
Host smart-55d67a67-0293-4580-b2b6-41e10db3f9b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260582942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.4260582942
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2102249627
Short name T842
Test name
Test status
Simulation time 39039259413 ps
CPU time 536.84 seconds
Started Jan 14 01:43:12 PM PST 24
Finished Jan 14 01:52:11 PM PST 24
Peak memory 198412 kb
Host smart-9cbfaed2-a065-49c9-8e79-c6579f771a7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2102249627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2102249627
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2331646494
Short name T775
Test name
Test status
Simulation time 44341116 ps
CPU time 0.57 seconds
Started Jan 14 01:43:18 PM PST 24
Finished Jan 14 01:43:20 PM PST 24
Peak memory 194724 kb
Host smart-d04a1bac-567e-48cf-a7fe-8c81b672a2f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331646494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2331646494
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2036933261
Short name T328
Test name
Test status
Simulation time 38084488 ps
CPU time 0.83 seconds
Started Jan 14 01:43:14 PM PST 24
Finished Jan 14 01:43:17 PM PST 24
Peak memory 196548 kb
Host smart-1ebb6671-c0f8-40c4-870d-4c2099203b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036933261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2036933261
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1723720042
Short name T229
Test name
Test status
Simulation time 6723266219 ps
CPU time 25.25 seconds
Started Jan 14 01:43:13 PM PST 24
Finished Jan 14 01:43:40 PM PST 24
Peak memory 197108 kb
Host smart-e50e87c6-3085-4dba-a3da-a2803fba2b6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723720042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1723720042
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.4092424250
Short name T765
Test name
Test status
Simulation time 212338975 ps
CPU time 0.99 seconds
Started Jan 14 01:43:26 PM PST 24
Finished Jan 14 01:43:28 PM PST 24
Peak memory 196420 kb
Host smart-60198593-ca72-4fdf-b3a7-2b7d64752945
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092424250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.4092424250
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3929253111
Short name T685
Test name
Test status
Simulation time 79781660 ps
CPU time 1.39 seconds
Started Jan 14 01:43:15 PM PST 24
Finished Jan 14 01:43:19 PM PST 24
Peak memory 197292 kb
Host smart-a02ce740-e89d-4cce-994c-656774404090
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929253111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3929253111
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.211576095
Short name T570
Test name
Test status
Simulation time 108614946 ps
CPU time 3.4 seconds
Started Jan 14 01:43:13 PM PST 24
Finished Jan 14 01:43:19 PM PST 24
Peak memory 198260 kb
Host smart-3ceeeb08-41c8-455c-bdd7-c87ca84df808
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211576095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.211576095
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.104085627
Short name T242
Test name
Test status
Simulation time 216113956 ps
CPU time 1.03 seconds
Started Jan 14 01:43:14 PM PST 24
Finished Jan 14 01:43:17 PM PST 24
Peak memory 195488 kb
Host smart-cfb6c344-d7e5-4299-9113-521e8bd802eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104085627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
104085627
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2941773273
Short name T232
Test name
Test status
Simulation time 32459420 ps
CPU time 0.86 seconds
Started Jan 14 01:43:11 PM PST 24
Finished Jan 14 01:43:14 PM PST 24
Peak memory 196156 kb
Host smart-5867098a-7d96-48d5-997d-64222911c2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941773273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2941773273
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.385700971
Short name T869
Test name
Test status
Simulation time 51298042 ps
CPU time 1.01 seconds
Started Jan 14 01:43:15 PM PST 24
Finished Jan 14 01:43:18 PM PST 24
Peak memory 195932 kb
Host smart-be8d3d56-20d5-4511-82a0-49976f567471
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385700971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.385700971
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3277409532
Short name T634
Test name
Test status
Simulation time 181153188 ps
CPU time 3.95 seconds
Started Jan 14 01:43:16 PM PST 24
Finished Jan 14 01:43:22 PM PST 24
Peak memory 198092 kb
Host smart-3d86c2b6-ed52-46c0-bc05-2c8fa1aba7de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277409532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3277409532
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.408495808
Short name T709
Test name
Test status
Simulation time 73603769 ps
CPU time 1.07 seconds
Started Jan 14 01:43:15 PM PST 24
Finished Jan 14 01:43:18 PM PST 24
Peak memory 195868 kb
Host smart-be21ea67-9622-4166-b47f-89db09977edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408495808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.408495808
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1501290718
Short name T270
Test name
Test status
Simulation time 165477288 ps
CPU time 0.93 seconds
Started Jan 14 01:43:15 PM PST 24
Finished Jan 14 01:43:18 PM PST 24
Peak memory 196476 kb
Host smart-5e9d52d8-9b9e-4d45-9a7e-0c7543163de7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501290718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1501290718
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.746264132
Short name T844
Test name
Test status
Simulation time 5452305057 ps
CPU time 134.32 seconds
Started Jan 14 01:43:18 PM PST 24
Finished Jan 14 01:45:35 PM PST 24
Peak memory 198208 kb
Host smart-367e68bf-d6b4-4d39-ab39-5fc6eba7f19e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746264132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.746264132
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.332753621
Short name T658
Test name
Test status
Simulation time 215377613463 ps
CPU time 1333.01 seconds
Started Jan 14 01:43:21 PM PST 24
Finished Jan 14 02:05:36 PM PST 24
Peak memory 198408 kb
Host smart-a1fed202-9085-4821-820f-313afde6b888
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=332753621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.332753621
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1596491318
Short name T871
Test name
Test status
Simulation time 47522989 ps
CPU time 0.57 seconds
Started Jan 14 01:43:20 PM PST 24
Finished Jan 14 01:43:22 PM PST 24
Peak memory 194264 kb
Host smart-eb20dc79-4075-4979-ab97-3a4052c2c234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596491318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1596491318
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2065737889
Short name T485
Test name
Test status
Simulation time 73633021 ps
CPU time 0.84 seconds
Started Jan 14 01:43:18 PM PST 24
Finished Jan 14 01:43:21 PM PST 24
Peak memory 196528 kb
Host smart-da9e4da7-fc8d-465e-8c9e-4577ac32d148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065737889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2065737889
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2351837898
Short name T779
Test name
Test status
Simulation time 2335294533 ps
CPU time 19.82 seconds
Started Jan 14 01:43:21 PM PST 24
Finished Jan 14 01:43:43 PM PST 24
Peak memory 196852 kb
Host smart-44522b49-fb56-45d6-8358-106c41fa0c5c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351837898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2351837898
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2602696199
Short name T522
Test name
Test status
Simulation time 377918366 ps
CPU time 0.85 seconds
Started Jan 14 01:43:20 PM PST 24
Finished Jan 14 01:43:23 PM PST 24
Peak memory 196124 kb
Host smart-5271e770-7ecb-4b2e-8354-50ba5c12ece3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602696199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2602696199
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1980645630
Short name T785
Test name
Test status
Simulation time 111872819 ps
CPU time 0.77 seconds
Started Jan 14 01:43:20 PM PST 24
Finished Jan 14 01:43:23 PM PST 24
Peak memory 195612 kb
Host smart-a6ba15fc-f38c-4a93-b414-58c37b193641
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980645630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1980645630
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.775143351
Short name T621
Test name
Test status
Simulation time 365875645 ps
CPU time 2.09 seconds
Started Jan 14 01:43:19 PM PST 24
Finished Jan 14 01:43:23 PM PST 24
Peak memory 198136 kb
Host smart-82ef8e19-2f4b-4439-b506-96eb6f0e4adb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775143351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.775143351
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.330806770
Short name T453
Test name
Test status
Simulation time 2557189201 ps
CPU time 3.47 seconds
Started Jan 14 01:43:20 PM PST 24
Finished Jan 14 01:43:26 PM PST 24
Peak memory 198240 kb
Host smart-4767a618-ad9e-45db-936c-3fe002c28abd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330806770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
330806770
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2305760800
Short name T723
Test name
Test status
Simulation time 48247013 ps
CPU time 0.71 seconds
Started Jan 14 01:43:19 PM PST 24
Finished Jan 14 01:43:22 PM PST 24
Peak memory 195012 kb
Host smart-cb6ad5ab-ee7b-41ce-8b6f-48f16b2ce961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305760800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2305760800
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3071765405
Short name T760
Test name
Test status
Simulation time 170434128 ps
CPU time 1.09 seconds
Started Jan 14 01:43:17 PM PST 24
Finished Jan 14 01:43:20 PM PST 24
Peak memory 195848 kb
Host smart-1ef856e0-741f-4c08-bd83-c528f763df1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071765405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3071765405
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.168423129
Short name T637
Test name
Test status
Simulation time 97260371 ps
CPU time 4.56 seconds
Started Jan 14 01:43:21 PM PST 24
Finished Jan 14 01:43:28 PM PST 24
Peak memory 198128 kb
Host smart-360c4d0c-f207-444f-b69a-dbcd425a3497
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168423129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.168423129
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2314325745
Short name T576
Test name
Test status
Simulation time 134425196 ps
CPU time 1.23 seconds
Started Jan 14 01:43:16 PM PST 24
Finished Jan 14 01:43:19 PM PST 24
Peak memory 196824 kb
Host smart-1e8c8656-0cd2-4d68-9810-6224760fa3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314325745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2314325745
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.841151356
Short name T299
Test name
Test status
Simulation time 126678748 ps
CPU time 1.38 seconds
Started Jan 14 01:43:21 PM PST 24
Finished Jan 14 01:43:24 PM PST 24
Peak memory 198136 kb
Host smart-26f8e665-95e4-4505-9397-8f9994b42453
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841151356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.841151356
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2432703690
Short name T403
Test name
Test status
Simulation time 8745544455 ps
CPU time 64.06 seconds
Started Jan 14 01:43:18 PM PST 24
Finished Jan 14 01:44:24 PM PST 24
Peak memory 198272 kb
Host smart-8824258b-d37b-4569-bad7-7764184c8941
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432703690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2432703690
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.104110333
Short name T847
Test name
Test status
Simulation time 51603662533 ps
CPU time 1459.24 seconds
Started Jan 14 01:43:19 PM PST 24
Finished Jan 14 02:07:40 PM PST 24
Peak memory 198392 kb
Host smart-a2afc16e-2916-4948-9645-1c2ab7191ed1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=104110333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.104110333
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2195638613
Short name T774
Test name
Test status
Simulation time 197414029 ps
CPU time 0.6 seconds
Started Jan 14 01:43:30 PM PST 24
Finished Jan 14 01:43:32 PM PST 24
Peak memory 193980 kb
Host smart-82c36bc5-6eca-42ae-957e-163d7a49f737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195638613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2195638613
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3385759178
Short name T665
Test name
Test status
Simulation time 34406232 ps
CPU time 0.63 seconds
Started Jan 14 01:43:23 PM PST 24
Finished Jan 14 01:43:26 PM PST 24
Peak memory 194116 kb
Host smart-a3c3fb68-4636-4a9e-b10b-dbc587c1b3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385759178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3385759178
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2221322303
Short name T623
Test name
Test status
Simulation time 1126326570 ps
CPU time 4.68 seconds
Started Jan 14 01:43:22 PM PST 24
Finished Jan 14 01:43:29 PM PST 24
Peak memory 195624 kb
Host smart-e2f99dbb-6b18-48e7-b688-a53e02bbb89e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221322303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2221322303
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1247053227
Short name T501
Test name
Test status
Simulation time 57538400 ps
CPU time 0.63 seconds
Started Jan 14 01:43:20 PM PST 24
Finished Jan 14 01:43:23 PM PST 24
Peak memory 194368 kb
Host smart-f33eba4a-689f-4643-b21e-7b00539eb9b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247053227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1247053227
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1590006297
Short name T890
Test name
Test status
Simulation time 122943584 ps
CPU time 0.95 seconds
Started Jan 14 01:43:22 PM PST 24
Finished Jan 14 01:43:25 PM PST 24
Peak memory 196116 kb
Host smart-b2601a51-c424-4903-a4e6-199b1780bd89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590006297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1590006297
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2087361442
Short name T477
Test name
Test status
Simulation time 63873117 ps
CPU time 2.09 seconds
Started Jan 14 01:43:22 PM PST 24
Finished Jan 14 01:43:26 PM PST 24
Peak memory 196480 kb
Host smart-a4a544ce-7dee-4de3-a40d-498d13450787
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087361442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2087361442
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2913791435
Short name T455
Test name
Test status
Simulation time 329795100 ps
CPU time 1.98 seconds
Started Jan 14 01:43:23 PM PST 24
Finished Jan 14 01:43:27 PM PST 24
Peak memory 196236 kb
Host smart-e164802e-5af9-4eff-bd07-3846cb156bbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913791435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2913791435
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3757594626
Short name T698
Test name
Test status
Simulation time 611597902 ps
CPU time 0.9 seconds
Started Jan 14 01:43:21 PM PST 24
Finished Jan 14 01:43:24 PM PST 24
Peak memory 196044 kb
Host smart-2301b2f0-06bb-492e-8099-06f72a3b9bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757594626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3757594626
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2554117904
Short name T385
Test name
Test status
Simulation time 49575391 ps
CPU time 0.96 seconds
Started Jan 14 01:43:21 PM PST 24
Finished Jan 14 01:43:24 PM PST 24
Peak memory 195884 kb
Host smart-a109dc93-54a1-4bf9-9200-4f582bc5efbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554117904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2554117904
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.630307435
Short name T552
Test name
Test status
Simulation time 304985555 ps
CPU time 3.44 seconds
Started Jan 14 01:43:18 PM PST 24
Finished Jan 14 01:43:23 PM PST 24
Peak memory 198056 kb
Host smart-a50ea932-894b-4e4d-8ce5-8608a8515ee2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630307435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.630307435
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2455624044
Short name T740
Test name
Test status
Simulation time 53325439 ps
CPU time 1.06 seconds
Started Jan 14 01:43:24 PM PST 24
Finished Jan 14 01:43:26 PM PST 24
Peak memory 196216 kb
Host smart-57280ea9-9d4a-4b4a-834f-7ef30afe402b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455624044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2455624044
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2730853543
Short name T532
Test name
Test status
Simulation time 32096012 ps
CPU time 1.07 seconds
Started Jan 14 01:43:22 PM PST 24
Finished Jan 14 01:43:25 PM PST 24
Peak memory 195656 kb
Host smart-e6a70fc3-7d1b-4ba3-b7ff-244e17f26f12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730853543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2730853543
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1920460953
Short name T571
Test name
Test status
Simulation time 48110077778 ps
CPU time 114.87 seconds
Started Jan 14 01:43:24 PM PST 24
Finished Jan 14 01:45:20 PM PST 24
Peak memory 198228 kb
Host smart-6b50c068-4a8b-4eed-b183-0e404720a385
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920460953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1920460953
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2823879639
Short name T772
Test name
Test status
Simulation time 76213230189 ps
CPU time 1052.77 seconds
Started Jan 14 01:43:27 PM PST 24
Finished Jan 14 02:01:01 PM PST 24
Peak memory 198404 kb
Host smart-6614898f-dc1b-43d5-895b-e992aa45ecfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2823879639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2823879639
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.773336638
Short name T468
Test name
Test status
Simulation time 37497896 ps
CPU time 0.55 seconds
Started Jan 14 01:43:26 PM PST 24
Finished Jan 14 01:43:28 PM PST 24
Peak memory 194108 kb
Host smart-23a48a9f-dea7-4336-9346-26f0ef7eaa74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773336638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.773336638
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2599200389
Short name T528
Test name
Test status
Simulation time 26327222 ps
CPU time 0.73 seconds
Started Jan 14 01:43:28 PM PST 24
Finished Jan 14 01:43:30 PM PST 24
Peak memory 195396 kb
Host smart-852f05ed-89b4-41b2-aadc-dcb6eb1a178c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599200389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2599200389
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2826986840
Short name T767
Test name
Test status
Simulation time 3569696990 ps
CPU time 26.36 seconds
Started Jan 14 01:43:27 PM PST 24
Finished Jan 14 01:43:55 PM PST 24
Peak memory 198268 kb
Host smart-4147a86c-d2b6-4652-bdf5-65c84335cda2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826986840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2826986840
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3044958966
Short name T819
Test name
Test status
Simulation time 27656730 ps
CPU time 0.68 seconds
Started Jan 14 01:43:36 PM PST 24
Finished Jan 14 01:43:37 PM PST 24
Peak memory 194592 kb
Host smart-6d8e0bf5-7d31-4332-92ff-1e3d84df4103
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044958966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3044958966
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3055371121
Short name T87
Test name
Test status
Simulation time 115321671 ps
CPU time 1.48 seconds
Started Jan 14 01:43:26 PM PST 24
Finished Jan 14 01:43:29 PM PST 24
Peak memory 197132 kb
Host smart-bac1a04d-eaa4-46d6-b0c7-5cd0a3e9ff37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055371121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3055371121
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.4169773949
Short name T878
Test name
Test status
Simulation time 176312218 ps
CPU time 3.63 seconds
Started Jan 14 01:43:27 PM PST 24
Finished Jan 14 01:43:32 PM PST 24
Peak memory 198272 kb
Host smart-3380277c-5807-4e7a-ace0-efd1c5e5bcaf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169773949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.4169773949
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.275144254
Short name T559
Test name
Test status
Simulation time 245204627 ps
CPU time 2.33 seconds
Started Jan 14 01:43:27 PM PST 24
Finished Jan 14 01:43:30 PM PST 24
Peak memory 197088 kb
Host smart-3f667b02-f66e-428d-9fce-d9c68d60789b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275144254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
275144254
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2060323127
Short name T590
Test name
Test status
Simulation time 48546953 ps
CPU time 0.62 seconds
Started Jan 14 01:43:28 PM PST 24
Finished Jan 14 01:43:30 PM PST 24
Peak memory 194868 kb
Host smart-8579ef10-6b17-4372-952e-b4e334cf720d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060323127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2060323127
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.4289928451
Short name T616
Test name
Test status
Simulation time 22912533 ps
CPU time 0.85 seconds
Started Jan 14 01:43:29 PM PST 24
Finished Jan 14 01:43:31 PM PST 24
Peak memory 196776 kb
Host smart-c4005c43-c79e-4fc5-b9a7-290814c7019d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289928451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.4289928451
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2142861912
Short name T324
Test name
Test status
Simulation time 142870134 ps
CPU time 3.9 seconds
Started Jan 14 01:43:29 PM PST 24
Finished Jan 14 01:43:35 PM PST 24
Peak memory 198120 kb
Host smart-3fe16a94-896e-4bdd-9e99-91daf98df9db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142861912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2142861912
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1509843683
Short name T573
Test name
Test status
Simulation time 221649581 ps
CPU time 0.95 seconds
Started Jan 14 01:43:27 PM PST 24
Finished Jan 14 01:43:29 PM PST 24
Peak memory 196320 kb
Host smart-bcf8e4ab-9872-4386-b6a8-6da2c6f75136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509843683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1509843683
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1984441690
Short name T289
Test name
Test status
Simulation time 41692475 ps
CPU time 0.86 seconds
Started Jan 14 01:43:30 PM PST 24
Finished Jan 14 01:43:32 PM PST 24
Peak memory 195504 kb
Host smart-47ffb199-573e-4eef-a6af-001fb1740fac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984441690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1984441690
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3433702686
Short name T356
Test name
Test status
Simulation time 28241625529 ps
CPU time 164.47 seconds
Started Jan 14 01:43:25 PM PST 24
Finished Jan 14 01:46:10 PM PST 24
Peak memory 198268 kb
Host smart-af172d00-99b6-4123-97b0-10dff04968c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433702686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3433702686
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.1618345359
Short name T500
Test name
Test status
Simulation time 83449453635 ps
CPU time 291.07 seconds
Started Jan 14 01:43:30 PM PST 24
Finished Jan 14 01:48:22 PM PST 24
Peak memory 198400 kb
Host smart-56fcfc2b-c520-4d37-b1c0-372720d7a347
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1618345359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.1618345359
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3441203721
Short name T796
Test name
Test status
Simulation time 22153588 ps
CPU time 0.57 seconds
Started Jan 14 01:43:32 PM PST 24
Finished Jan 14 01:43:34 PM PST 24
Peak memory 194276 kb
Host smart-9725d608-a6ee-440b-a121-4875c405a267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441203721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3441203721
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.787805774
Short name T473
Test name
Test status
Simulation time 52010632 ps
CPU time 0.96 seconds
Started Jan 14 01:43:32 PM PST 24
Finished Jan 14 01:43:33 PM PST 24
Peak memory 196148 kb
Host smart-b6e1873f-1b98-40f5-9a23-a6127d4d2655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787805774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.787805774
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3775794412
Short name T736
Test name
Test status
Simulation time 2999376200 ps
CPU time 26.39 seconds
Started Jan 14 01:43:35 PM PST 24
Finished Jan 14 01:44:03 PM PST 24
Peak memory 197036 kb
Host smart-4a03efd0-d216-4336-9576-dc868d6552a9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775794412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3775794412
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.4102468583
Short name T364
Test name
Test status
Simulation time 81865334 ps
CPU time 1.05 seconds
Started Jan 14 01:43:28 PM PST 24
Finished Jan 14 01:43:30 PM PST 24
Peak memory 196728 kb
Host smart-b76224a2-d235-455b-aab7-abd12ef8a496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102468583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.4102468583
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2995819217
Short name T353
Test name
Test status
Simulation time 123852924 ps
CPU time 1.36 seconds
Started Jan 14 01:43:27 PM PST 24
Finished Jan 14 01:43:30 PM PST 24
Peak memory 197300 kb
Host smart-26950805-81cb-4217-85fd-ee0ebbd34fec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995819217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2995819217
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.4249952257
Short name T394
Test name
Test status
Simulation time 54158349 ps
CPU time 2.11 seconds
Started Jan 14 01:43:36 PM PST 24
Finished Jan 14 01:43:39 PM PST 24
Peak memory 198140 kb
Host smart-a1a94d00-bce4-4728-bd04-f3c8da8d07f4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249952257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.4249952257
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.700917267
Short name T719
Test name
Test status
Simulation time 1229585952 ps
CPU time 1.97 seconds
Started Jan 14 01:43:25 PM PST 24
Finished Jan 14 01:43:28 PM PST 24
Peak memory 197016 kb
Host smart-0b7fa950-35a5-499d-be03-b322f73bb8e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700917267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
700917267
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2952525322
Short name T274
Test name
Test status
Simulation time 41851660 ps
CPU time 1.03 seconds
Started Jan 14 01:43:27 PM PST 24
Finished Jan 14 01:43:29 PM PST 24
Peak memory 196860 kb
Host smart-8d5947b1-7770-4326-a342-4e148cde9ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952525322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2952525322
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3653597192
Short name T406
Test name
Test status
Simulation time 256087106 ps
CPU time 1.27 seconds
Started Jan 14 01:43:36 PM PST 24
Finished Jan 14 01:43:38 PM PST 24
Peak memory 198172 kb
Host smart-36a58eab-b560-4bb1-b191-4e1eb92d7aee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653597192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3653597192
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2071229436
Short name T278
Test name
Test status
Simulation time 95927759 ps
CPU time 4.22 seconds
Started Jan 14 01:43:32 PM PST 24
Finished Jan 14 01:43:37 PM PST 24
Peak memory 198080 kb
Host smart-10301e61-c689-4ecd-857b-1037af39dcf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071229436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2071229436
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2250461196
Short name T430
Test name
Test status
Simulation time 60461595 ps
CPU time 1.08 seconds
Started Jan 14 01:43:29 PM PST 24
Finished Jan 14 01:43:31 PM PST 24
Peak memory 195868 kb
Host smart-22f325a2-d129-4f1e-96a0-9b6bed1fd227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250461196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2250461196
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.877538873
Short name T391
Test name
Test status
Simulation time 736921238 ps
CPU time 1 seconds
Started Jan 14 01:43:30 PM PST 24
Finished Jan 14 01:43:32 PM PST 24
Peak memory 196268 kb
Host smart-d213173b-5eda-43be-80e6-865c885746c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877538873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.877538873
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1669457087
Short name T682
Test name
Test status
Simulation time 8618622454 ps
CPU time 46.31 seconds
Started Jan 14 01:43:29 PM PST 24
Finished Jan 14 01:44:16 PM PST 24
Peak memory 198288 kb
Host smart-62bd5028-12ed-4791-a4ab-b5f45e83574f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669457087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1669457087
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.2599625512
Short name T368
Test name
Test status
Simulation time 178098936311 ps
CPU time 1299.19 seconds
Started Jan 14 01:43:33 PM PST 24
Finished Jan 14 02:05:13 PM PST 24
Peak memory 206544 kb
Host smart-c10b0157-db1f-4876-a138-df577bfa6124
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2599625512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.2599625512
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2337900907
Short name T333
Test name
Test status
Simulation time 18505171 ps
CPU time 0.57 seconds
Started Jan 14 01:43:36 PM PST 24
Finished Jan 14 01:43:37 PM PST 24
Peak memory 193992 kb
Host smart-9f733d03-2b36-4b40-8149-1020c306ed80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337900907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2337900907
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.4112129000
Short name T113
Test name
Test status
Simulation time 72726718 ps
CPU time 0.72 seconds
Started Jan 14 01:43:34 PM PST 24
Finished Jan 14 01:43:36 PM PST 24
Peak memory 195348 kb
Host smart-027ea5e4-a602-4b42-b52e-c95e93bb41e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112129000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.4112129000
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2997040369
Short name T813
Test name
Test status
Simulation time 2739771285 ps
CPU time 25.14 seconds
Started Jan 14 01:43:42 PM PST 24
Finished Jan 14 01:44:08 PM PST 24
Peak memory 198240 kb
Host smart-53857a02-7498-447d-86f2-c7d94a293520
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997040369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2997040369
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.841090467
Short name T317
Test name
Test status
Simulation time 197913859 ps
CPU time 0.88 seconds
Started Jan 14 01:43:34 PM PST 24
Finished Jan 14 01:43:36 PM PST 24
Peak memory 195908 kb
Host smart-bf0ca535-88cb-482c-9dae-30f55a7fcdbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841090467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.841090467
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.795037609
Short name T481
Test name
Test status
Simulation time 299394782 ps
CPU time 1 seconds
Started Jan 14 01:43:33 PM PST 24
Finished Jan 14 01:43:35 PM PST 24
Peak memory 196644 kb
Host smart-6fff1904-d66e-4ea9-b4a5-08a2725bbed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795037609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.795037609
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2801420279
Short name T711
Test name
Test status
Simulation time 268510480 ps
CPU time 2.71 seconds
Started Jan 14 01:43:37 PM PST 24
Finished Jan 14 01:43:41 PM PST 24
Peak memory 198272 kb
Host smart-0b1244aa-1a68-4a84-8fe7-dbb13e86e00f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801420279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2801420279
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2211047389
Short name T777
Test name
Test status
Simulation time 310098115 ps
CPU time 1.93 seconds
Started Jan 14 01:43:34 PM PST 24
Finished Jan 14 01:43:37 PM PST 24
Peak memory 198176 kb
Host smart-b7682fbf-4906-4717-8bb1-67b554b4f803
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211047389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2211047389
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1922860785
Short name T250
Test name
Test status
Simulation time 64390275 ps
CPU time 1 seconds
Started Jan 14 01:43:32 PM PST 24
Finished Jan 14 01:43:34 PM PST 24
Peak memory 196600 kb
Host smart-4802b24b-1f41-4ada-8edb-8a30d5ffd3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922860785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1922860785
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.4150267442
Short name T361
Test name
Test status
Simulation time 52003505 ps
CPU time 1.1 seconds
Started Jan 14 01:43:33 PM PST 24
Finished Jan 14 01:43:35 PM PST 24
Peak memory 196068 kb
Host smart-c364e899-a42c-4548-bbe5-2c1af91b0982
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150267442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.4150267442
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.789402553
Short name T727
Test name
Test status
Simulation time 2644433572 ps
CPU time 6.03 seconds
Started Jan 14 01:43:37 PM PST 24
Finished Jan 14 01:43:44 PM PST 24
Peak memory 197384 kb
Host smart-e03c5cf6-04d1-4cb8-81ce-a2b2007d3134
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789402553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.789402553
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.315235866
Short name T517
Test name
Test status
Simulation time 190834567 ps
CPU time 1.4 seconds
Started Jan 14 01:43:33 PM PST 24
Finished Jan 14 01:43:35 PM PST 24
Peak memory 198072 kb
Host smart-ead95316-c061-4188-8cf7-329fc756b085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315235866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.315235866
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.689275499
Short name T405
Test name
Test status
Simulation time 115914584 ps
CPU time 1.1 seconds
Started Jan 14 01:43:32 PM PST 24
Finished Jan 14 01:43:34 PM PST 24
Peak memory 195676 kb
Host smart-2deb67f8-fd44-42fd-852e-ebde97f0376b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689275499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.689275499
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2281219602
Short name T508
Test name
Test status
Simulation time 14307755521 ps
CPU time 213.5 seconds
Started Jan 14 01:43:34 PM PST 24
Finished Jan 14 01:47:09 PM PST 24
Peak memory 198196 kb
Host smart-a8b49eb6-21e5-443f-9b40-9a310a1313ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281219602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2281219602
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2555545607
Short name T295
Test name
Test status
Simulation time 709893351682 ps
CPU time 841.51 seconds
Started Jan 14 01:43:43 PM PST 24
Finished Jan 14 01:57:45 PM PST 24
Peak memory 206640 kb
Host smart-e4c4f3fa-2d13-4bfc-b67f-b5533cd27d92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2555545607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2555545607
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1995642077
Short name T397
Test name
Test status
Simulation time 24902874 ps
CPU time 0.56 seconds
Started Jan 14 01:40:57 PM PST 24
Finished Jan 14 01:40:59 PM PST 24
Peak memory 194116 kb
Host smart-6946dd96-2c9d-4091-b5db-666a733a4dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995642077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1995642077
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1530430542
Short name T764
Test name
Test status
Simulation time 803107926 ps
CPU time 0.87 seconds
Started Jan 14 01:40:56 PM PST 24
Finished Jan 14 01:40:57 PM PST 24
Peak memory 195708 kb
Host smart-dbc00dd9-90fa-485c-a995-9a25ad78ba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530430542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1530430542
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1192796058
Short name T642
Test name
Test status
Simulation time 825514320 ps
CPU time 14.08 seconds
Started Jan 14 01:40:53 PM PST 24
Finished Jan 14 01:41:08 PM PST 24
Peak memory 198140 kb
Host smart-599f026e-4b1e-45ee-bc93-2b89ca763013
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192796058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1192796058
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.990239279
Short name T488
Test name
Test status
Simulation time 54292351 ps
CPU time 0.83 seconds
Started Jan 14 01:40:55 PM PST 24
Finished Jan 14 01:40:56 PM PST 24
Peak memory 196116 kb
Host smart-555aa72e-b290-47f6-b0ff-b0677a1ddfbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990239279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.990239279
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1814677351
Short name T486
Test name
Test status
Simulation time 88609231 ps
CPU time 0.83 seconds
Started Jan 14 01:40:55 PM PST 24
Finished Jan 14 01:40:56 PM PST 24
Peak memory 195656 kb
Host smart-cf1b4c8a-509a-476e-9dbd-600e5fefcac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814677351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1814677351
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3784175995
Short name T699
Test name
Test status
Simulation time 202278610 ps
CPU time 1.11 seconds
Started Jan 14 01:40:54 PM PST 24
Finished Jan 14 01:40:56 PM PST 24
Peak memory 197400 kb
Host smart-52d5d257-eca6-4b58-b334-88c29b9a68e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784175995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3784175995
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2507386357
Short name T874
Test name
Test status
Simulation time 788227046 ps
CPU time 2.95 seconds
Started Jan 14 01:41:00 PM PST 24
Finished Jan 14 01:41:04 PM PST 24
Peak memory 197120 kb
Host smart-2d3c4105-96c2-4321-af0a-6cc36bd1f783
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507386357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2507386357
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2549620235
Short name T272
Test name
Test status
Simulation time 61525113 ps
CPU time 1.21 seconds
Started Jan 14 01:40:57 PM PST 24
Finished Jan 14 01:40:59 PM PST 24
Peak memory 196172 kb
Host smart-af55d1f5-4b7a-434e-8714-b0d248b6c870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549620235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2549620235
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1579166634
Short name T531
Test name
Test status
Simulation time 43252781 ps
CPU time 0.74 seconds
Started Jan 14 01:40:55 PM PST 24
Finished Jan 14 01:40:57 PM PST 24
Peak memory 195548 kb
Host smart-ad46082f-d25f-45e9-b9a9-4b18a8d2301c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579166634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1579166634
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3161549611
Short name T344
Test name
Test status
Simulation time 1474327263 ps
CPU time 5.86 seconds
Started Jan 14 01:40:59 PM PST 24
Finished Jan 14 01:41:06 PM PST 24
Peak memory 198116 kb
Host smart-6d9fc718-7556-4271-89f6-c861c90dffec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161549611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3161549611
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.4197064420
Short name T60
Test name
Test status
Simulation time 193577314 ps
CPU time 0.93 seconds
Started Jan 14 01:40:56 PM PST 24
Finished Jan 14 01:40:58 PM PST 24
Peak memory 214800 kb
Host smart-f5301369-2e63-4dc5-bcda-35eb9a3bb889
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197064420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.4197064420
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3692720158
Short name T667
Test name
Test status
Simulation time 368890459 ps
CPU time 1.33 seconds
Started Jan 14 01:40:56 PM PST 24
Finished Jan 14 01:40:59 PM PST 24
Peak memory 196912 kb
Host smart-4cd722eb-773e-4106-af0b-0fe79efa3e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692720158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3692720158
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1625191478
Short name T660
Test name
Test status
Simulation time 78636337 ps
CPU time 1.16 seconds
Started Jan 14 01:40:55 PM PST 24
Finished Jan 14 01:40:57 PM PST 24
Peak memory 198152 kb
Host smart-5bbc6d9d-5b5d-46b6-bed5-ab9e7d41ea60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625191478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1625191478
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3427952312
Short name T839
Test name
Test status
Simulation time 12913829565 ps
CPU time 137.29 seconds
Started Jan 14 01:40:58 PM PST 24
Finished Jan 14 01:43:16 PM PST 24
Peak memory 198252 kb
Host smart-9c67e5ca-ee33-43a9-acee-732320ea147e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427952312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3427952312
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1787038395
Short name T85
Test name
Test status
Simulation time 362665038763 ps
CPU time 2330.29 seconds
Started Jan 14 01:40:57 PM PST 24
Finished Jan 14 02:19:49 PM PST 24
Peak memory 198428 kb
Host smart-20cdd219-572f-4afd-897c-a7cdfef975fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1787038395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1787038395
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3667514550
Short name T678
Test name
Test status
Simulation time 46871426 ps
CPU time 0.6 seconds
Started Jan 14 01:43:48 PM PST 24
Finished Jan 14 01:43:49 PM PST 24
Peak memory 194056 kb
Host smart-47e67708-2434-4798-81df-34d375d97851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667514550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3667514550
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.510503273
Short name T864
Test name
Test status
Simulation time 45669567 ps
CPU time 0.79 seconds
Started Jan 14 01:43:50 PM PST 24
Finished Jan 14 01:43:52 PM PST 24
Peak memory 196132 kb
Host smart-3883cb71-bddc-4aaa-9ffb-f102fd8d4579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510503273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.510503273
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2208499638
Short name T366
Test name
Test status
Simulation time 7391526128 ps
CPU time 21.34 seconds
Started Jan 14 01:43:45 PM PST 24
Finished Jan 14 01:44:07 PM PST 24
Peak memory 198268 kb
Host smart-3b98a167-59f5-42c2-a043-0b13908abebc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208499638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2208499638
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2741118645
Short name T883
Test name
Test status
Simulation time 64102856 ps
CPU time 0.74 seconds
Started Jan 14 01:43:52 PM PST 24
Finished Jan 14 01:43:53 PM PST 24
Peak memory 195960 kb
Host smart-82870151-d38b-47cc-8da0-590afdfb5038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741118645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2741118645
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3986702258
Short name T465
Test name
Test status
Simulation time 35961865 ps
CPU time 0.85 seconds
Started Jan 14 01:43:54 PM PST 24
Finished Jan 14 01:43:56 PM PST 24
Peak memory 197224 kb
Host smart-c67b0eda-7180-4a32-8d8b-85d98ac3fd54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986702258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3986702258
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.297279139
Short name T728
Test name
Test status
Simulation time 25521615 ps
CPU time 1.06 seconds
Started Jan 14 01:43:46 PM PST 24
Finished Jan 14 01:43:47 PM PST 24
Peak memory 197644 kb
Host smart-3624349f-b56b-4767-9c7f-04d9a0a1b066
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297279139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.297279139
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.64423642
Short name T701
Test name
Test status
Simulation time 220031231 ps
CPU time 1.68 seconds
Started Jan 14 01:43:47 PM PST 24
Finished Jan 14 01:43:50 PM PST 24
Peak memory 196108 kb
Host smart-bf286987-f1f5-43bd-97a6-279bfb13e1b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64423642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.64423642
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.46796008
Short name T841
Test name
Test status
Simulation time 38828667 ps
CPU time 1.31 seconds
Started Jan 14 01:43:36 PM PST 24
Finished Jan 14 01:43:38 PM PST 24
Peak memory 197044 kb
Host smart-110b7a2c-397f-4103-b20f-8e1e575b1883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46796008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.46796008
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1162543457
Short name T687
Test name
Test status
Simulation time 246444986 ps
CPU time 1.11 seconds
Started Jan 14 01:43:37 PM PST 24
Finished Jan 14 01:43:39 PM PST 24
Peak memory 195928 kb
Host smart-429af433-a86c-47b5-a0e2-0fdf2223e5d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162543457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1162543457
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1490293234
Short name T311
Test name
Test status
Simulation time 136870438 ps
CPU time 1.58 seconds
Started Jan 14 01:43:49 PM PST 24
Finished Jan 14 01:43:52 PM PST 24
Peak memory 198048 kb
Host smart-4415799d-4e3b-4eab-a80c-0be21448176d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490293234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1490293234
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.4036592602
Short name T828
Test name
Test status
Simulation time 54878320 ps
CPU time 1.11 seconds
Started Jan 14 01:43:43 PM PST 24
Finished Jan 14 01:43:45 PM PST 24
Peak memory 195652 kb
Host smart-6ea8b73c-7700-4002-9506-0393b3fd2b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036592602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.4036592602
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.818475687
Short name T233
Test name
Test status
Simulation time 716979608 ps
CPU time 0.81 seconds
Started Jan 14 01:43:34 PM PST 24
Finished Jan 14 01:43:36 PM PST 24
Peak memory 195344 kb
Host smart-98487621-f9f5-4ba2-9dfa-6a9d4911138e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818475687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.818475687
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3841007621
Short name T800
Test name
Test status
Simulation time 12666665196 ps
CPU time 85.24 seconds
Started Jan 14 01:43:46 PM PST 24
Finished Jan 14 01:45:12 PM PST 24
Peak memory 198252 kb
Host smart-1d41c41e-599a-42b8-819c-7684722251cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841007621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3841007621
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.2306455970
Short name T327
Test name
Test status
Simulation time 62954592160 ps
CPU time 804.63 seconds
Started Jan 14 01:43:48 PM PST 24
Finished Jan 14 01:57:14 PM PST 24
Peak memory 198340 kb
Host smart-530188cf-8464-4ade-b499-50ec5de20565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2306455970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.2306455970
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2302285594
Short name T776
Test name
Test status
Simulation time 25482214 ps
CPU time 0.57 seconds
Started Jan 14 01:43:54 PM PST 24
Finished Jan 14 01:43:56 PM PST 24
Peak memory 194784 kb
Host smart-bce71770-97c0-4306-b4b3-fef253094a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302285594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2302285594
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1057257584
Short name T390
Test name
Test status
Simulation time 100388412 ps
CPU time 0.88 seconds
Started Jan 14 01:43:48 PM PST 24
Finished Jan 14 01:43:49 PM PST 24
Peak memory 195820 kb
Host smart-965f0c8e-0fad-4d94-8103-4d89a3ff23f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057257584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1057257584
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1865322714
Short name T707
Test name
Test status
Simulation time 269996123 ps
CPU time 14.17 seconds
Started Jan 14 01:43:45 PM PST 24
Finished Jan 14 01:44:00 PM PST 24
Peak memory 197148 kb
Host smart-34420155-9459-453d-8f5c-25b50e26d0d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865322714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1865322714
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3027375310
Short name T305
Test name
Test status
Simulation time 46909589 ps
CPU time 0.73 seconds
Started Jan 14 01:43:49 PM PST 24
Finished Jan 14 01:43:51 PM PST 24
Peak memory 194644 kb
Host smart-f4f3eafe-95be-4411-a1dc-bf2cd7e699ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027375310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3027375310
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1797636414
Short name T478
Test name
Test status
Simulation time 172599654 ps
CPU time 0.96 seconds
Started Jan 14 01:43:52 PM PST 24
Finished Jan 14 01:43:53 PM PST 24
Peak memory 196612 kb
Host smart-1c2c76ef-8d77-4791-aea0-92501dde78a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797636414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1797636414
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2230058168
Short name T748
Test name
Test status
Simulation time 87649051 ps
CPU time 1.76 seconds
Started Jan 14 01:43:47 PM PST 24
Finished Jan 14 01:43:50 PM PST 24
Peak memory 196424 kb
Host smart-e467a85b-855a-4081-91b0-525ffbe30883
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230058168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2230058168
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3786560152
Short name T354
Test name
Test status
Simulation time 452338111 ps
CPU time 3.06 seconds
Started Jan 14 01:43:48 PM PST 24
Finished Jan 14 01:43:52 PM PST 24
Peak memory 198136 kb
Host smart-41e778f0-a14f-49d9-b95b-69a23fac62fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786560152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3786560152
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3691701837
Short name T555
Test name
Test status
Simulation time 29525722 ps
CPU time 0.75 seconds
Started Jan 14 01:43:44 PM PST 24
Finished Jan 14 01:43:46 PM PST 24
Peak memory 195488 kb
Host smart-2fd38a42-78ef-45ed-ad62-820ab71aaed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691701837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3691701837
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1896755363
Short name T351
Test name
Test status
Simulation time 80271183 ps
CPU time 0.93 seconds
Started Jan 14 01:43:47 PM PST 24
Finished Jan 14 01:43:48 PM PST 24
Peak memory 196248 kb
Host smart-2244fa13-5bb5-466b-84b4-c567ae52b633
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896755363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1896755363
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2510568856
Short name T787
Test name
Test status
Simulation time 1385193490 ps
CPU time 3.32 seconds
Started Jan 14 01:43:47 PM PST 24
Finished Jan 14 01:43:51 PM PST 24
Peak memory 198120 kb
Host smart-4d2e93b1-2b21-450b-a7b1-aa1be402bfb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510568856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2510568856
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1431385410
Short name T885
Test name
Test status
Simulation time 363870269 ps
CPU time 1.3 seconds
Started Jan 14 01:43:48 PM PST 24
Finished Jan 14 01:43:50 PM PST 24
Peak memory 196864 kb
Host smart-e7e8ace1-a5c3-4f56-8c13-703166855df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431385410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1431385410
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1661942182
Short name T515
Test name
Test status
Simulation time 89735594 ps
CPU time 0.93 seconds
Started Jan 14 01:43:49 PM PST 24
Finished Jan 14 01:43:51 PM PST 24
Peak memory 195568 kb
Host smart-a996d844-dd3d-47e3-94c1-449865cbecab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661942182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1661942182
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2301333349
Short name T392
Test name
Test status
Simulation time 7224104473 ps
CPU time 74.4 seconds
Started Jan 14 01:43:53 PM PST 24
Finished Jan 14 01:45:08 PM PST 24
Peak memory 198248 kb
Host smart-4fd9b00b-2f9c-40a8-af0e-ad6ebe0a7eaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301333349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2301333349
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.1404192062
Short name T393
Test name
Test status
Simulation time 30302704551 ps
CPU time 623.38 seconds
Started Jan 14 01:43:56 PM PST 24
Finished Jan 14 01:54:20 PM PST 24
Peak memory 198284 kb
Host smart-0bdfa29c-7061-431e-9b21-297bf4bfde18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1404192062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.1404192062
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2939958695
Short name T298
Test name
Test status
Simulation time 18790700 ps
CPU time 0.57 seconds
Started Jan 14 01:43:58 PM PST 24
Finished Jan 14 01:44:00 PM PST 24
Peak memory 194816 kb
Host smart-12a66b68-20b3-4d96-827d-c1017759c0fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939958695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2939958695
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3670641374
Short name T411
Test name
Test status
Simulation time 109588149 ps
CPU time 0.82 seconds
Started Jan 14 01:43:56 PM PST 24
Finished Jan 14 01:43:57 PM PST 24
Peak memory 195552 kb
Host smart-834ae517-d499-4918-ac94-f3a8658c271e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670641374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3670641374
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3214648289
Short name T330
Test name
Test status
Simulation time 3122765605 ps
CPU time 12.04 seconds
Started Jan 14 01:43:49 PM PST 24
Finished Jan 14 01:44:02 PM PST 24
Peak memory 196972 kb
Host smart-ef80b07d-1fc5-4c07-a6c1-7abda01ebefb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214648289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3214648289
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2311585799
Short name T355
Test name
Test status
Simulation time 494781416 ps
CPU time 1.01 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:43:59 PM PST 24
Peak memory 196492 kb
Host smart-ec7da34e-7d92-44fd-96c5-b53f1b8e81a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311585799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2311585799
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1477267513
Short name T533
Test name
Test status
Simulation time 233660417 ps
CPU time 0.87 seconds
Started Jan 14 01:43:53 PM PST 24
Finished Jan 14 01:43:54 PM PST 24
Peak memory 196844 kb
Host smart-a582e411-dc55-4f34-98c6-4e858629d3bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477267513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1477267513
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3556084067
Short name T263
Test name
Test status
Simulation time 224645482 ps
CPU time 1.98 seconds
Started Jan 14 01:43:50 PM PST 24
Finished Jan 14 01:43:53 PM PST 24
Peak memory 198044 kb
Host smart-9741a8e3-7650-4543-8d4d-018108818131
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556084067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3556084067
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3745428555
Short name T359
Test name
Test status
Simulation time 144111819 ps
CPU time 1.18 seconds
Started Jan 14 01:43:54 PM PST 24
Finished Jan 14 01:43:56 PM PST 24
Peak memory 196544 kb
Host smart-9d544ce3-9c05-4d2a-b062-4d9b506b3254
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745428555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3745428555
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1662389859
Short name T607
Test name
Test status
Simulation time 24677542 ps
CPU time 0.93 seconds
Started Jan 14 01:43:53 PM PST 24
Finished Jan 14 01:43:55 PM PST 24
Peak memory 196084 kb
Host smart-23046fe5-6154-4a4d-9539-79a665de8ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662389859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1662389859
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3482386756
Short name T490
Test name
Test status
Simulation time 53116975 ps
CPU time 1.03 seconds
Started Jan 14 01:43:56 PM PST 24
Finished Jan 14 01:43:58 PM PST 24
Peak memory 196016 kb
Host smart-fd714048-77ac-4458-9b8e-2924021f72c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482386756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3482386756
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.665151513
Short name T283
Test name
Test status
Simulation time 223345697 ps
CPU time 2.42 seconds
Started Jan 14 01:43:55 PM PST 24
Finished Jan 14 01:43:58 PM PST 24
Peak memory 198132 kb
Host smart-e98b746c-764b-4c9f-9cce-e2a79e66106c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665151513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.665151513
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2190159875
Short name T592
Test name
Test status
Simulation time 543275305 ps
CPU time 1.15 seconds
Started Jan 14 01:43:55 PM PST 24
Finished Jan 14 01:43:57 PM PST 24
Peak memory 196372 kb
Host smart-1cd4f7e2-eb1f-4e76-814f-456fbf7d8c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190159875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2190159875
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.4231551425
Short name T546
Test name
Test status
Simulation time 260320457 ps
CPU time 1.13 seconds
Started Jan 14 01:43:56 PM PST 24
Finished Jan 14 01:43:57 PM PST 24
Peak memory 195712 kb
Host smart-5bbba7d1-769b-472d-a685-6b56833ac1da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231551425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.4231551425
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3307856430
Short name T271
Test name
Test status
Simulation time 14730093888 ps
CPU time 100.46 seconds
Started Jan 14 01:43:59 PM PST 24
Finished Jan 14 01:45:41 PM PST 24
Peak memory 198264 kb
Host smart-a01a2dd6-6828-47eb-afb2-4c23083e78fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307856430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3307856430
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.59931264
Short name T72
Test name
Test status
Simulation time 27175815094 ps
CPU time 735.12 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:56:13 PM PST 24
Peak memory 198368 kb
Host smart-e2ebed4d-be6b-4b60-ae59-5a24240cf49a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=59931264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.59931264
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3376942982
Short name T491
Test name
Test status
Simulation time 44049991 ps
CPU time 0.55 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:43:59 PM PST 24
Peak memory 194120 kb
Host smart-8a134af6-3b83-4df0-9997-c3645e250f54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376942982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3376942982
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1533290998
Short name T789
Test name
Test status
Simulation time 167030049 ps
CPU time 0.6 seconds
Started Jan 14 01:43:58 PM PST 24
Finished Jan 14 01:44:01 PM PST 24
Peak memory 194684 kb
Host smart-5a36e872-f13d-42ea-bc90-db7888479b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533290998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1533290998
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3396306785
Short name T281
Test name
Test status
Simulation time 1118217675 ps
CPU time 9.26 seconds
Started Jan 14 01:43:58 PM PST 24
Finished Jan 14 01:44:08 PM PST 24
Peak memory 197132 kb
Host smart-bdd278d1-3825-42c5-b366-2535af50a5f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396306785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3396306785
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.4144215939
Short name T381
Test name
Test status
Simulation time 428469156 ps
CPU time 0.85 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:43:59 PM PST 24
Peak memory 196648 kb
Host smart-a0188f95-1b5b-4d16-848d-8db5f8f4b1ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144215939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.4144215939
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.70494860
Short name T370
Test name
Test status
Simulation time 515296355 ps
CPU time 0.9 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:43:59 PM PST 24
Peak memory 196088 kb
Host smart-9a30bd8e-8526-467a-8f61-1360c4c53104
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70494860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.70494860
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.983880297
Short name T322
Test name
Test status
Simulation time 938683855 ps
CPU time 3.32 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:44:02 PM PST 24
Peak memory 197992 kb
Host smart-5a8a7583-112d-412f-9a21-39fe2bf96167
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983880297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.983880297
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2586149061
Short name T661
Test name
Test status
Simulation time 176937385 ps
CPU time 1.1 seconds
Started Jan 14 01:44:02 PM PST 24
Finished Jan 14 01:44:04 PM PST 24
Peak memory 195640 kb
Host smart-cc90a19d-0356-4b31-b404-223b19477963
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586149061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2586149061
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2248460770
Short name T460
Test name
Test status
Simulation time 57786420 ps
CPU time 0.71 seconds
Started Jan 14 01:43:56 PM PST 24
Finished Jan 14 01:43:58 PM PST 24
Peak memory 195452 kb
Host smart-925f202b-8777-4573-97f7-a891835e6410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248460770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2248460770
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2019135294
Short name T350
Test name
Test status
Simulation time 16008889 ps
CPU time 0.6 seconds
Started Jan 14 01:43:56 PM PST 24
Finished Jan 14 01:43:57 PM PST 24
Peak memory 194980 kb
Host smart-94f1971e-ab65-406b-ada2-1d7a76153910
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019135294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2019135294
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3754764437
Short name T872
Test name
Test status
Simulation time 442868668 ps
CPU time 5.03 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:44:03 PM PST 24
Peak memory 198104 kb
Host smart-69bfef3f-09e3-49d7-b98b-0003609e3dad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754764437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3754764437
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.856556411
Short name T684
Test name
Test status
Simulation time 92153498 ps
CPU time 1.03 seconds
Started Jan 14 01:43:56 PM PST 24
Finished Jan 14 01:43:58 PM PST 24
Peak memory 196616 kb
Host smart-eabfe733-1492-4c7e-acae-a6a2383ca123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856556411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.856556411
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1984045581
Short name T854
Test name
Test status
Simulation time 103995478 ps
CPU time 0.75 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:43:59 PM PST 24
Peak memory 195336 kb
Host smart-6054d726-02ad-45e1-850f-2ba565b5924d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984045581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1984045581
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3188931149
Short name T310
Test name
Test status
Simulation time 8102418316 ps
CPU time 205 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:47:24 PM PST 24
Peak memory 198184 kb
Host smart-f7f24553-a4d0-4c15-a2dd-9581fd81f388
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188931149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3188931149
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2470596723
Short name T641
Test name
Test status
Simulation time 68572911525 ps
CPU time 331.58 seconds
Started Jan 14 01:43:58 PM PST 24
Finished Jan 14 01:49:31 PM PST 24
Peak memory 206656 kb
Host smart-5d8530fa-387b-49e0-a935-f106f69d3f15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2470596723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2470596723
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3610704104
Short name T648
Test name
Test status
Simulation time 83804078 ps
CPU time 0.58 seconds
Started Jan 14 01:43:58 PM PST 24
Finished Jan 14 01:44:01 PM PST 24
Peak memory 194768 kb
Host smart-70707c59-a0d0-44ff-8c5f-1f5800d612bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610704104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3610704104
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3629351197
Short name T761
Test name
Test status
Simulation time 217544854 ps
CPU time 0.74 seconds
Started Jan 14 01:43:56 PM PST 24
Finished Jan 14 01:43:58 PM PST 24
Peak memory 195456 kb
Host smart-9c540c5f-ebde-47c4-9abe-985318682fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629351197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3629351197
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.48607548
Short name T286
Test name
Test status
Simulation time 3800187495 ps
CPU time 15.28 seconds
Started Jan 14 01:44:01 PM PST 24
Finished Jan 14 01:44:17 PM PST 24
Peak memory 196768 kb
Host smart-ec6e1873-97a9-4e41-a1f1-270b782ad61a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48607548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stress
.48607548
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.272225809
Short name T843
Test name
Test status
Simulation time 149002443 ps
CPU time 0.74 seconds
Started Jan 14 01:44:03 PM PST 24
Finished Jan 14 01:44:04 PM PST 24
Peak memory 194712 kb
Host smart-1fe87233-b32a-470e-a7fd-d2b64ce23012
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272225809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.272225809
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.747091348
Short name T282
Test name
Test status
Simulation time 171132455 ps
CPU time 0.99 seconds
Started Jan 14 01:44:00 PM PST 24
Finished Jan 14 01:44:02 PM PST 24
Peak memory 196920 kb
Host smart-544b73e8-9126-4b1e-8a48-4e1c9975c576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747091348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.747091348
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1587060102
Short name T629
Test name
Test status
Simulation time 491429959 ps
CPU time 3.5 seconds
Started Jan 14 01:43:58 PM PST 24
Finished Jan 14 01:44:02 PM PST 24
Peak memory 198180 kb
Host smart-f8be06e2-e6bb-48e8-959f-aa6085e5aaf4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587060102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1587060102
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2873399428
Short name T266
Test name
Test status
Simulation time 195895657 ps
CPU time 1.06 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:44:00 PM PST 24
Peak memory 195740 kb
Host smart-d86f3ead-5083-4ddb-8607-a729d6fb69d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873399428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2873399428
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3424260155
Short name T265
Test name
Test status
Simulation time 36371063 ps
CPU time 1.22 seconds
Started Jan 14 01:43:55 PM PST 24
Finished Jan 14 01:43:57 PM PST 24
Peak memory 195976 kb
Host smart-947a8ca7-207a-4d3a-af03-bfffefe3874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424260155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3424260155
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2069463946
Short name T454
Test name
Test status
Simulation time 36773956 ps
CPU time 0.81 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:44:00 PM PST 24
Peak memory 196660 kb
Host smart-5acefdeb-3418-47d2-ac59-73da068922a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069463946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2069463946
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3798792529
Short name T313
Test name
Test status
Simulation time 393691904 ps
CPU time 5.38 seconds
Started Jan 14 01:43:59 PM PST 24
Finished Jan 14 01:44:05 PM PST 24
Peak memory 198072 kb
Host smart-12f0cdc8-03b0-481e-9dfc-ae9b78b03526
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798792529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3798792529
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2629751491
Short name T70
Test name
Test status
Simulation time 105811998 ps
CPU time 1.12 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:44:00 PM PST 24
Peak memory 196364 kb
Host smart-9df81e66-6713-46b8-8cd0-52ced82d8e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629751491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2629751491
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2333924236
Short name T463
Test name
Test status
Simulation time 285016749 ps
CPU time 1.34 seconds
Started Jan 14 01:43:57 PM PST 24
Finished Jan 14 01:44:00 PM PST 24
Peak memory 196856 kb
Host smart-323cae13-1cae-4603-adc4-941585e75ebb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333924236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2333924236
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2979368442
Short name T509
Test name
Test status
Simulation time 8952985058 ps
CPU time 132.18 seconds
Started Jan 14 01:44:00 PM PST 24
Finished Jan 14 01:46:13 PM PST 24
Peak memory 198200 kb
Host smart-ed16665b-cc3d-4a15-91d2-7a4f5e557556
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979368442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2979368442
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3364298653
Short name T700
Test name
Test status
Simulation time 303971451069 ps
CPU time 1559.85 seconds
Started Jan 14 01:44:03 PM PST 24
Finished Jan 14 02:10:03 PM PST 24
Peak memory 198260 kb
Host smart-a81ce584-008d-4603-b551-1a1f4a3cf594
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3364298653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3364298653
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2266082867
Short name T803
Test name
Test status
Simulation time 38947340 ps
CPU time 0.54 seconds
Started Jan 14 01:44:04 PM PST 24
Finished Jan 14 01:44:06 PM PST 24
Peak memory 192772 kb
Host smart-6b279043-8066-4525-9cf9-a40d4394ce7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266082867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2266082867
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3389414504
Short name T257
Test name
Test status
Simulation time 62637674 ps
CPU time 0.77 seconds
Started Jan 14 01:43:58 PM PST 24
Finished Jan 14 01:44:00 PM PST 24
Peak memory 196132 kb
Host smart-77605a4e-7eab-4d39-adcb-ddfee2e1e677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389414504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3389414504
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.4258730480
Short name T377
Test name
Test status
Simulation time 1647904406 ps
CPU time 19.93 seconds
Started Jan 14 01:44:05 PM PST 24
Finished Jan 14 01:44:26 PM PST 24
Peak memory 198204 kb
Host smart-3db67e01-0c71-46b3-be17-4f45d149cee9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258730480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.4258730480
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.228678249
Short name T443
Test name
Test status
Simulation time 69704304 ps
CPU time 0.93 seconds
Started Jan 14 01:44:05 PM PST 24
Finished Jan 14 01:44:06 PM PST 24
Peak memory 197108 kb
Host smart-9247f676-192f-46b9-9a0a-35104258aa7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228678249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.228678249
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.377824748
Short name T290
Test name
Test status
Simulation time 53736830 ps
CPU time 1.27 seconds
Started Jan 14 01:44:00 PM PST 24
Finished Jan 14 01:44:02 PM PST 24
Peak memory 198204 kb
Host smart-8b17e5d1-da11-4565-ae97-03bddd109cf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377824748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.377824748
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1649608746
Short name T564
Test name
Test status
Simulation time 99068976 ps
CPU time 1.93 seconds
Started Jan 14 01:44:09 PM PST 24
Finished Jan 14 01:44:11 PM PST 24
Peak memory 196512 kb
Host smart-0fbab926-3952-4561-9bc3-488c6af1a8de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649608746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1649608746
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3538780746
Short name T875
Test name
Test status
Simulation time 83064449 ps
CPU time 2.35 seconds
Started Jan 14 01:44:05 PM PST 24
Finished Jan 14 01:44:09 PM PST 24
Peak memory 197344 kb
Host smart-5296b9e8-39a5-44ca-83f2-24effd80dc38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538780746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3538780746
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1586281106
Short name T714
Test name
Test status
Simulation time 32045019 ps
CPU time 0.83 seconds
Started Jan 14 01:44:00 PM PST 24
Finished Jan 14 01:44:02 PM PST 24
Peak memory 197376 kb
Host smart-d1c0deb7-a5d5-47bf-8ae9-c4bd2154a2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586281106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1586281106
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3167259837
Short name T833
Test name
Test status
Simulation time 255474890 ps
CPU time 0.79 seconds
Started Jan 14 01:44:00 PM PST 24
Finished Jan 14 01:44:02 PM PST 24
Peak memory 195532 kb
Host smart-c82f31cb-7ea0-449e-87cd-e219cb3f28c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167259837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3167259837
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2338758995
Short name T643
Test name
Test status
Simulation time 956932852 ps
CPU time 2.09 seconds
Started Jan 14 01:44:06 PM PST 24
Finished Jan 14 01:44:10 PM PST 24
Peak memory 198072 kb
Host smart-b1c2a81d-0a95-4de3-8c44-ade4871fd070
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338758995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2338758995
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1098565251
Short name T551
Test name
Test status
Simulation time 193183813 ps
CPU time 1.37 seconds
Started Jan 14 01:44:05 PM PST 24
Finished Jan 14 01:44:08 PM PST 24
Peak memory 198124 kb
Host smart-a49f7c1a-bcbd-4387-b768-0546d3f9a581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098565251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1098565251
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.889816829
Short name T293
Test name
Test status
Simulation time 80638420 ps
CPU time 1.17 seconds
Started Jan 14 01:44:03 PM PST 24
Finished Jan 14 01:44:05 PM PST 24
Peak memory 195876 kb
Host smart-5b05e041-e656-4e5c-b174-726b1b991a2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889816829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.889816829
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.4127968778
Short name T413
Test name
Test status
Simulation time 4589799590 ps
CPU time 60.31 seconds
Started Jan 14 01:44:04 PM PST 24
Finished Jan 14 01:45:05 PM PST 24
Peak memory 198244 kb
Host smart-474ca06d-b7bd-40ed-845d-2727d9b89110
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127968778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.4127968778
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.3994008021
Short name T788
Test name
Test status
Simulation time 828250558562 ps
CPU time 1120.02 seconds
Started Jan 14 01:44:08 PM PST 24
Finished Jan 14 02:02:49 PM PST 24
Peak memory 198420 kb
Host smart-4413e02f-ed82-4852-93ec-e58289f2b00a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3994008021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.3994008021
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.987432651
Short name T814
Test name
Test status
Simulation time 13005792 ps
CPU time 0.55 seconds
Started Jan 14 01:44:12 PM PST 24
Finished Jan 14 01:44:13 PM PST 24
Peak memory 194104 kb
Host smart-227f82db-c26c-42d9-9b06-d832c4faaf4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987432651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.987432651
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1063492427
Short name T420
Test name
Test status
Simulation time 19933826 ps
CPU time 0.73 seconds
Started Jan 14 01:44:05 PM PST 24
Finished Jan 14 01:44:06 PM PST 24
Peak memory 195248 kb
Host smart-914dbeb9-d27d-4761-bfb7-d22c15d75de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063492427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1063492427
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1253968783
Short name T446
Test name
Test status
Simulation time 1791790814 ps
CPU time 15.87 seconds
Started Jan 14 01:44:09 PM PST 24
Finished Jan 14 01:44:26 PM PST 24
Peak memory 197136 kb
Host smart-20248b86-7aa3-4eec-a568-d7720cd7c756
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253968783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1253968783
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.4012226849
Short name T732
Test name
Test status
Simulation time 470827430 ps
CPU time 1.07 seconds
Started Jan 14 01:44:10 PM PST 24
Finished Jan 14 01:44:12 PM PST 24
Peak memory 198112 kb
Host smart-5b5c97e1-a90f-419d-9739-3adc0d03647c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012226849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.4012226849
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3069240124
Short name T595
Test name
Test status
Simulation time 475504886 ps
CPU time 1.15 seconds
Started Jan 14 01:44:08 PM PST 24
Finished Jan 14 01:44:10 PM PST 24
Peak memory 196144 kb
Host smart-5defca68-d447-4c1b-98ba-8cb7141059b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069240124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3069240124
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.4283167048
Short name T404
Test name
Test status
Simulation time 30588102 ps
CPU time 1.29 seconds
Started Jan 14 01:44:05 PM PST 24
Finished Jan 14 01:44:07 PM PST 24
Peak memory 196936 kb
Host smart-e82cdec8-5c0e-4c94-a0f8-83d8e198eb1d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283167048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.4283167048
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3919465657
Short name T240
Test name
Test status
Simulation time 35857608 ps
CPU time 1.22 seconds
Started Jan 14 01:44:03 PM PST 24
Finished Jan 14 01:44:05 PM PST 24
Peak memory 196972 kb
Host smart-01630a29-5a37-45d1-a02a-83f37fe5b9cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919465657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3919465657
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1101164706
Short name T824
Test name
Test status
Simulation time 30406210 ps
CPU time 1.03 seconds
Started Jan 14 01:44:09 PM PST 24
Finished Jan 14 01:44:11 PM PST 24
Peak memory 196108 kb
Host smart-bbe56f61-5c2a-497a-9ba3-36de22de3964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101164706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1101164706
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2115222351
Short name T666
Test name
Test status
Simulation time 39386703 ps
CPU time 1.1 seconds
Started Jan 14 01:44:03 PM PST 24
Finished Jan 14 01:44:05 PM PST 24
Peak memory 196092 kb
Host smart-94997c43-6fcb-415a-838d-85742348a4bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115222351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2115222351
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2428016970
Short name T619
Test name
Test status
Simulation time 388246041 ps
CPU time 6.17 seconds
Started Jan 14 01:44:05 PM PST 24
Finished Jan 14 01:44:12 PM PST 24
Peak memory 198100 kb
Host smart-2d14bd4e-f98f-47e5-85ce-fb30e72f3a31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428016970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2428016970
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1894117311
Short name T770
Test name
Test status
Simulation time 133011461 ps
CPU time 1.3 seconds
Started Jan 14 01:44:08 PM PST 24
Finished Jan 14 01:44:10 PM PST 24
Peak memory 196820 kb
Host smart-3f859ad2-741e-4c17-9051-a3b8a79b63b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894117311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1894117311
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1231634192
Short name T415
Test name
Test status
Simulation time 103867761 ps
CPU time 1.37 seconds
Started Jan 14 01:44:08 PM PST 24
Finished Jan 14 01:44:10 PM PST 24
Peak memory 195688 kb
Host smart-f93638f7-2025-440c-bb4b-217055287a95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231634192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1231634192
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1727679741
Short name T396
Test name
Test status
Simulation time 20339832919 ps
CPU time 115.02 seconds
Started Jan 14 01:44:09 PM PST 24
Finished Jan 14 01:46:04 PM PST 24
Peak memory 198292 kb
Host smart-21263814-2dd3-4221-9056-1420aad20659
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727679741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1727679741
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3659708471
Short name T451
Test name
Test status
Simulation time 68522275165 ps
CPU time 178.63 seconds
Started Jan 14 01:44:06 PM PST 24
Finished Jan 14 01:47:06 PM PST 24
Peak memory 206632 kb
Host smart-d3dc2e91-7fc9-41e4-9406-0f04e080e10b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3659708471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3659708471
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.560844269
Short name T846
Test name
Test status
Simulation time 40020557 ps
CPU time 0.57 seconds
Started Jan 14 01:44:11 PM PST 24
Finished Jan 14 01:44:12 PM PST 24
Peak memory 194804 kb
Host smart-b4e86f1f-a3c7-4958-87d1-51b42947aff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560844269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.560844269
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1599310007
Short name T743
Test name
Test status
Simulation time 56633519 ps
CPU time 0.72 seconds
Started Jan 14 01:44:15 PM PST 24
Finished Jan 14 01:44:16 PM PST 24
Peak memory 195188 kb
Host smart-2b689e49-5355-41fb-a43d-52de09c59ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599310007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1599310007
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1746194577
Short name T628
Test name
Test status
Simulation time 7145778810 ps
CPU time 20.6 seconds
Started Jan 14 01:44:08 PM PST 24
Finished Jan 14 01:44:29 PM PST 24
Peak memory 197144 kb
Host smart-f2eed767-13e0-44ed-9264-1b40d20cd771
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746194577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1746194577
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3326553683
Short name T877
Test name
Test status
Simulation time 176279964 ps
CPU time 0.7 seconds
Started Jan 14 01:44:09 PM PST 24
Finished Jan 14 01:44:11 PM PST 24
Peak memory 195428 kb
Host smart-850429df-bb8a-4f10-a869-2ee508fc132e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326553683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3326553683
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3255324820
Short name T738
Test name
Test status
Simulation time 123563569 ps
CPU time 0.74 seconds
Started Jan 14 01:44:11 PM PST 24
Finished Jan 14 01:44:12 PM PST 24
Peak memory 196160 kb
Host smart-a7233ae7-4e41-46dc-bca1-c83c3abf5e75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255324820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3255324820
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1872249824
Short name T549
Test name
Test status
Simulation time 29924940 ps
CPU time 1.26 seconds
Started Jan 14 01:44:15 PM PST 24
Finished Jan 14 01:44:17 PM PST 24
Peak memory 196468 kb
Host smart-54895b15-f27a-40b8-85ce-bfb487fb0b71
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872249824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1872249824
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3512131253
Short name T756
Test name
Test status
Simulation time 144949471 ps
CPU time 2.78 seconds
Started Jan 14 01:44:12 PM PST 24
Finished Jan 14 01:44:16 PM PST 24
Peak memory 196664 kb
Host smart-53003b0d-4a46-4941-b6b6-631882b5351e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512131253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3512131253
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.933403847
Short name T365
Test name
Test status
Simulation time 176764932 ps
CPU time 0.73 seconds
Started Jan 14 01:44:10 PM PST 24
Finished Jan 14 01:44:12 PM PST 24
Peak memory 195364 kb
Host smart-6d27eb83-66cb-42e0-b6b6-9a395e5c6672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933403847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.933403847
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1787560431
Short name T380
Test name
Test status
Simulation time 29985707 ps
CPU time 0.8 seconds
Started Jan 14 01:44:07 PM PST 24
Finished Jan 14 01:44:09 PM PST 24
Peak memory 196296 kb
Host smart-d2af59ec-376f-48ed-9941-2d59ee4fec4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787560431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1787560431
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2667294265
Short name T668
Test name
Test status
Simulation time 1596365871 ps
CPU time 4.14 seconds
Started Jan 14 01:44:09 PM PST 24
Finished Jan 14 01:44:14 PM PST 24
Peak memory 198148 kb
Host smart-fe25baad-39ce-44d2-a9a7-f291b20b70df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667294265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2667294265
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2588688453
Short name T739
Test name
Test status
Simulation time 974943977 ps
CPU time 1.32 seconds
Started Jan 14 01:44:14 PM PST 24
Finished Jan 14 01:44:16 PM PST 24
Peak memory 198140 kb
Host smart-22ef96cc-7211-4b25-b266-e4aed713a9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588688453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2588688453
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3437629980
Short name T886
Test name
Test status
Simulation time 120466017 ps
CPU time 0.97 seconds
Started Jan 14 01:44:06 PM PST 24
Finished Jan 14 01:44:08 PM PST 24
Peak memory 195888 kb
Host smart-f991e902-133d-4b8c-b842-8392e30510c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437629980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3437629980
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.862587310
Short name T747
Test name
Test status
Simulation time 89750837089 ps
CPU time 125.55 seconds
Started Jan 14 01:44:06 PM PST 24
Finished Jan 14 01:46:13 PM PST 24
Peak memory 198112 kb
Host smart-93390559-c8cc-4c78-bafc-ec77bc334c51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862587310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.862587310
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3900647856
Short name T525
Test name
Test status
Simulation time 169600616466 ps
CPU time 1303.65 seconds
Started Jan 14 01:44:09 PM PST 24
Finished Jan 14 02:05:53 PM PST 24
Peak memory 198416 kb
Host smart-630623b7-4571-4709-9a12-cc0e79780472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3900647856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3900647856
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.4076654660
Short name T786
Test name
Test status
Simulation time 14361451 ps
CPU time 0.56 seconds
Started Jan 14 01:44:03 PM PST 24
Finished Jan 14 01:44:05 PM PST 24
Peak memory 194808 kb
Host smart-fa3fe822-c268-4842-bc5d-c5caee757168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076654660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.4076654660
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3875050894
Short name T569
Test name
Test status
Simulation time 120728387 ps
CPU time 0.78 seconds
Started Jan 14 01:44:05 PM PST 24
Finished Jan 14 01:44:06 PM PST 24
Peak memory 195404 kb
Host smart-be93455d-debc-4292-8566-6d88971acaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875050894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3875050894
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3539966456
Short name T802
Test name
Test status
Simulation time 159872749 ps
CPU time 8.17 seconds
Started Jan 14 01:44:04 PM PST 24
Finished Jan 14 01:44:13 PM PST 24
Peak memory 198112 kb
Host smart-cc81480a-c4cf-4e5c-ae45-c0bb74db0f8d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539966456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3539966456
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2596928615
Short name T62
Test name
Test status
Simulation time 83356417 ps
CPU time 0.67 seconds
Started Jan 14 01:44:05 PM PST 24
Finished Jan 14 01:44:08 PM PST 24
Peak memory 194596 kb
Host smart-0b29b9a7-d8fe-4801-9e9c-55eae2bcb992
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596928615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2596928615
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2329705748
Short name T285
Test name
Test status
Simulation time 315406715 ps
CPU time 1.27 seconds
Started Jan 14 01:44:06 PM PST 24
Finished Jan 14 01:44:09 PM PST 24
Peak memory 195900 kb
Host smart-331c4667-715f-4c29-a915-03890cdad96a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329705748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2329705748
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1817267378
Short name T755
Test name
Test status
Simulation time 66712144 ps
CPU time 2.61 seconds
Started Jan 14 01:44:04 PM PST 24
Finished Jan 14 01:44:08 PM PST 24
Peak memory 198192 kb
Host smart-0fa2e259-63cf-4c08-8805-6a9bcde06eba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817267378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1817267378
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3091184707
Short name T255
Test name
Test status
Simulation time 339012546 ps
CPU time 1.71 seconds
Started Jan 14 01:44:03 PM PST 24
Finished Jan 14 01:44:05 PM PST 24
Peak memory 196928 kb
Host smart-4b8bf2b9-4187-4a54-9094-0935110feb1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091184707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3091184707
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.594233560
Short name T695
Test name
Test status
Simulation time 232322108 ps
CPU time 1.29 seconds
Started Jan 14 01:44:14 PM PST 24
Finished Jan 14 01:44:16 PM PST 24
Peak memory 198184 kb
Host smart-21b7f555-4b2d-482d-a31a-8ceb1eb0c246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594233560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.594233560
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2065494635
Short name T768
Test name
Test status
Simulation time 29364565 ps
CPU time 1.12 seconds
Started Jan 14 01:44:14 PM PST 24
Finished Jan 14 01:44:16 PM PST 24
Peak memory 196772 kb
Host smart-f3f407be-1c2d-47b4-bd3a-c02d2064cef4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065494635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2065494635
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.953958405
Short name T505
Test name
Test status
Simulation time 3625692435 ps
CPU time 3.89 seconds
Started Jan 14 01:44:09 PM PST 24
Finished Jan 14 01:44:14 PM PST 24
Peak memory 198184 kb
Host smart-359b5edd-c10c-49a2-85c9-96f1a2fd2af6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953958405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.953958405
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1645888850
Short name T693
Test name
Test status
Simulation time 89759194 ps
CPU time 1.29 seconds
Started Jan 14 01:44:14 PM PST 24
Finished Jan 14 01:44:16 PM PST 24
Peak memory 196936 kb
Host smart-a5c7b5ed-aeb3-40f9-9b56-3f594906a94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645888850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1645888850
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.292917612
Short name T65
Test name
Test status
Simulation time 93031960 ps
CPU time 1 seconds
Started Jan 14 01:44:11 PM PST 24
Finished Jan 14 01:44:13 PM PST 24
Peak memory 196488 kb
Host smart-ef236a56-0bbb-45b6-87d2-dd577976c3c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292917612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.292917612
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3676204947
Short name T230
Test name
Test status
Simulation time 1733039333 ps
CPU time 22.1 seconds
Started Jan 14 01:44:04 PM PST 24
Finished Jan 14 01:44:27 PM PST 24
Peak memory 198216 kb
Host smart-75c1fe8e-0a83-47a2-98f6-fabcf056c40c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676204947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3676204947
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.4196131771
Short name T680
Test name
Test status
Simulation time 28999913552 ps
CPU time 258.3 seconds
Started Jan 14 01:44:06 PM PST 24
Finished Jan 14 01:48:25 PM PST 24
Peak memory 198364 kb
Host smart-0be868bf-0781-4d25-9530-b232a6163eb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4196131771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.4196131771
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.540420097
Short name T615
Test name
Test status
Simulation time 13122602 ps
CPU time 0.61 seconds
Started Jan 14 01:44:14 PM PST 24
Finished Jan 14 01:44:15 PM PST 24
Peak memory 194108 kb
Host smart-d2b0d638-412a-45bd-a79c-3e5a2669e90c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540420097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.540420097
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2846003715
Short name T37
Test name
Test status
Simulation time 36428939 ps
CPU time 0.65 seconds
Started Jan 14 01:44:13 PM PST 24
Finished Jan 14 01:44:15 PM PST 24
Peak memory 194160 kb
Host smart-86333776-6e94-4a9d-b488-756cecb37035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846003715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2846003715
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3021723673
Short name T499
Test name
Test status
Simulation time 2505986268 ps
CPU time 19.74 seconds
Started Jan 14 01:44:12 PM PST 24
Finished Jan 14 01:44:32 PM PST 24
Peak memory 198280 kb
Host smart-a6117874-bddf-4ed5-a88f-54f21cdd8d6b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021723673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3021723673
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2219904962
Short name T811
Test name
Test status
Simulation time 50936214 ps
CPU time 0.63 seconds
Started Jan 14 01:44:17 PM PST 24
Finished Jan 14 01:44:18 PM PST 24
Peak memory 194600 kb
Host smart-9b7053dc-a03b-4195-9368-05e9186fc219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219904962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2219904962
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1596208129
Short name T567
Test name
Test status
Simulation time 118100298 ps
CPU time 1.49 seconds
Started Jan 14 01:44:13 PM PST 24
Finished Jan 14 01:44:15 PM PST 24
Peak memory 197384 kb
Host smart-33c3cb7d-5395-480b-805c-e2647a9baf96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596208129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1596208129
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1951377795
Short name T497
Test name
Test status
Simulation time 40804787 ps
CPU time 1.62 seconds
Started Jan 14 01:44:14 PM PST 24
Finished Jan 14 01:44:17 PM PST 24
Peak memory 197028 kb
Host smart-06a240b5-6cac-40e6-8442-5046e8207250
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951377795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1951377795
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3223184343
Short name T574
Test name
Test status
Simulation time 73138379 ps
CPU time 1.35 seconds
Started Jan 14 01:44:13 PM PST 24
Finished Jan 14 01:44:15 PM PST 24
Peak memory 196252 kb
Host smart-70d34530-4a51-4d73-9a0d-b58468be7ee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223184343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3223184343
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1339477464
Short name T536
Test name
Test status
Simulation time 105029301 ps
CPU time 1 seconds
Started Jan 14 01:44:18 PM PST 24
Finished Jan 14 01:44:20 PM PST 24
Peak memory 196128 kb
Host smart-9b6bd069-a4dc-4bc3-947a-73752f47f526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339477464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1339477464
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1321089997
Short name T321
Test name
Test status
Simulation time 124114318 ps
CPU time 1.2 seconds
Started Jan 14 01:44:13 PM PST 24
Finished Jan 14 01:44:14 PM PST 24
Peak memory 196744 kb
Host smart-345633eb-2d3d-41a9-93cd-28451f7a640b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321089997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1321089997
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.638846064
Short name T331
Test name
Test status
Simulation time 103860360 ps
CPU time 1.26 seconds
Started Jan 14 01:44:12 PM PST 24
Finished Jan 14 01:44:14 PM PST 24
Peak memory 198072 kb
Host smart-88fdba44-5331-41fe-ad9f-34420a8f6fb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638846064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.638846064
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3387218025
Short name T849
Test name
Test status
Simulation time 467048634 ps
CPU time 1.15 seconds
Started Jan 14 01:44:16 PM PST 24
Finished Jan 14 01:44:18 PM PST 24
Peak memory 195880 kb
Host smart-48aed3cd-60e5-4f44-858e-4188dd21e2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387218025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3387218025
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1168169738
Short name T691
Test name
Test status
Simulation time 36497739 ps
CPU time 1.05 seconds
Started Jan 14 01:44:13 PM PST 24
Finished Jan 14 01:44:15 PM PST 24
Peak memory 195840 kb
Host smart-a29a918b-0003-4861-ad10-e440ea6db5b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168169738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1168169738
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2034073468
Short name T867
Test name
Test status
Simulation time 68500936889 ps
CPU time 190.15 seconds
Started Jan 14 01:44:15 PM PST 24
Finished Jan 14 01:47:25 PM PST 24
Peak memory 198272 kb
Host smart-8bf49709-339c-4222-921b-ca6b91457f4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034073468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2034073468
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3335215587
Short name T664
Test name
Test status
Simulation time 69341622966 ps
CPU time 1309.32 seconds
Started Jan 14 01:44:14 PM PST 24
Finished Jan 14 02:06:04 PM PST 24
Peak memory 198412 kb
Host smart-0b84da78-f42c-4816-bbb8-12baeaeba3f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3335215587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3335215587
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1016862427
Short name T745
Test name
Test status
Simulation time 34320344 ps
CPU time 0.54 seconds
Started Jan 14 01:41:19 PM PST 24
Finished Jan 14 01:41:20 PM PST 24
Peak memory 194052 kb
Host smart-72765b9d-6aed-418f-be8f-04f18a9a6345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016862427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1016862427
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3898453024
Short name T561
Test name
Test status
Simulation time 94697576 ps
CPU time 0.78 seconds
Started Jan 14 01:40:57 PM PST 24
Finished Jan 14 01:40:58 PM PST 24
Peak memory 196408 kb
Host smart-84f2f7b0-973c-41e0-951c-b1f03e537b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898453024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3898453024
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.124568142
Short name T373
Test name
Test status
Simulation time 767834009 ps
CPU time 26.16 seconds
Started Jan 14 01:41:03 PM PST 24
Finished Jan 14 01:41:30 PM PST 24
Peak memory 195660 kb
Host smart-6bc98e41-458c-4f73-89f5-2b140043ae86
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124568142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.124568142
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1706696527
Short name T726
Test name
Test status
Simulation time 129490059 ps
CPU time 0.66 seconds
Started Jan 14 01:41:09 PM PST 24
Finished Jan 14 01:41:10 PM PST 24
Peak memory 194648 kb
Host smart-99100bdc-b58d-4bc9-aceb-9639e53b1377
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706696527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1706696527
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1118117368
Short name T66
Test name
Test status
Simulation time 97953129 ps
CPU time 0.71 seconds
Started Jan 14 01:40:57 PM PST 24
Finished Jan 14 01:40:59 PM PST 24
Peak memory 195356 kb
Host smart-fcd97394-e719-442c-8b2c-4dfee0e5f94d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118117368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1118117368
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1199955028
Short name T650
Test name
Test status
Simulation time 68828561 ps
CPU time 2.61 seconds
Started Jan 14 01:41:09 PM PST 24
Finished Jan 14 01:41:12 PM PST 24
Peak memory 196500 kb
Host smart-b83418a6-6f3c-48ed-b397-02dd21ac9c5d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199955028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1199955028
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.4282360565
Short name T609
Test name
Test status
Simulation time 80332598 ps
CPU time 2.3 seconds
Started Jan 14 01:41:02 PM PST 24
Finished Jan 14 01:41:05 PM PST 24
Peak memory 195932 kb
Host smart-504fd2f8-0906-416c-9cf5-3cebece5a338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282360565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
4282360565
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3872678806
Short name T297
Test name
Test status
Simulation time 57422994 ps
CPU time 0.71 seconds
Started Jan 14 01:40:55 PM PST 24
Finished Jan 14 01:40:57 PM PST 24
Peak memory 195376 kb
Host smart-a9ed859b-4da9-476e-88ab-10af16593388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872678806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3872678806
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2161395299
Short name T292
Test name
Test status
Simulation time 189460520 ps
CPU time 1.13 seconds
Started Jan 14 01:40:56 PM PST 24
Finished Jan 14 01:40:58 PM PST 24
Peak memory 197216 kb
Host smart-3dd44b98-651e-4f6e-9a6f-db1b202965b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161395299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2161395299
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3014263537
Short name T876
Test name
Test status
Simulation time 259642436 ps
CPU time 4.07 seconds
Started Jan 14 01:41:04 PM PST 24
Finished Jan 14 01:41:09 PM PST 24
Peak memory 198056 kb
Host smart-969cb267-fade-475d-92e3-74c937191954
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014263537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3014263537
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.645420675
Short name T556
Test name
Test status
Simulation time 401155833 ps
CPU time 1.43 seconds
Started Jan 14 01:40:58 PM PST 24
Finished Jan 14 01:41:01 PM PST 24
Peak memory 196864 kb
Host smart-607f5bfe-6a0b-4520-af90-9274c469b0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645420675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.645420675
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2929012548
Short name T440
Test name
Test status
Simulation time 91846957 ps
CPU time 0.94 seconds
Started Jan 14 01:40:56 PM PST 24
Finished Jan 14 01:40:58 PM PST 24
Peak memory 195760 kb
Host smart-d3755377-1045-4724-a69b-513dd35e8b9a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929012548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2929012548
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1339394663
Short name T597
Test name
Test status
Simulation time 11928587702 ps
CPU time 73.27 seconds
Started Jan 14 01:41:08 PM PST 24
Finished Jan 14 01:42:22 PM PST 24
Peak memory 198268 kb
Host smart-e8a870c1-37d1-45f6-b65c-acbd30668415
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339394663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1339394663
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.199208067
Short name T273
Test name
Test status
Simulation time 79377694166 ps
CPU time 1371.96 seconds
Started Jan 14 01:41:06 PM PST 24
Finished Jan 14 02:04:00 PM PST 24
Peak memory 198456 kb
Host smart-af9a6e85-e015-438c-9b2e-afc131afc17d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=199208067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.199208067
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.432854299
Short name T398
Test name
Test status
Simulation time 33430831 ps
CPU time 0.55 seconds
Started Jan 14 01:41:11 PM PST 24
Finished Jan 14 01:41:12 PM PST 24
Peak memory 194108 kb
Host smart-25211f5d-cee3-4d54-b570-6a44249e6cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432854299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.432854299
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.883053241
Short name T805
Test name
Test status
Simulation time 30694977 ps
CPU time 0.68 seconds
Started Jan 14 01:41:05 PM PST 24
Finished Jan 14 01:41:06 PM PST 24
Peak memory 194048 kb
Host smart-159f4c6f-bbae-4fe0-9a52-8f417f818447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883053241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.883053241
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.84818724
Short name T639
Test name
Test status
Simulation time 471903334 ps
CPU time 24.19 seconds
Started Jan 14 01:41:03 PM PST 24
Finished Jan 14 01:41:28 PM PST 24
Peak memory 198184 kb
Host smart-ecebd5e8-3f04-44d1-8e0c-0a3bdf91a329
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84818724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress.84818724
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2769019314
Short name T323
Test name
Test status
Simulation time 58070819 ps
CPU time 0.86 seconds
Started Jan 14 01:41:10 PM PST 24
Finished Jan 14 01:41:12 PM PST 24
Peak memory 195956 kb
Host smart-fba1fda8-55a3-444b-8771-36004f446157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769019314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2769019314
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3225102734
Short name T433
Test name
Test status
Simulation time 220297797 ps
CPU time 1.46 seconds
Started Jan 14 01:41:03 PM PST 24
Finished Jan 14 01:41:05 PM PST 24
Peak memory 195916 kb
Host smart-f69a3d6e-2353-4fd7-bea8-ca8e6601fb61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225102734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3225102734
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1943215379
Short name T117
Test name
Test status
Simulation time 40327105 ps
CPU time 1.58 seconds
Started Jan 14 01:41:03 PM PST 24
Finished Jan 14 01:41:05 PM PST 24
Peak memory 196884 kb
Host smart-b63866f1-6ec6-465b-8ccf-1687e4a7b597
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943215379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1943215379
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1845651407
Short name T605
Test name
Test status
Simulation time 849956558 ps
CPU time 2.96 seconds
Started Jan 14 01:41:02 PM PST 24
Finished Jan 14 01:41:06 PM PST 24
Peak memory 196660 kb
Host smart-5e56a9df-c492-4712-b6ca-8ca60f5ef5c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845651407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1845651407
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3538612523
Short name T414
Test name
Test status
Simulation time 110396984 ps
CPU time 1.05 seconds
Started Jan 14 01:41:03 PM PST 24
Finished Jan 14 01:41:05 PM PST 24
Peak memory 196664 kb
Host smart-75ad5699-c0f6-42a5-9346-18376338a9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538612523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3538612523
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2379109047
Short name T692
Test name
Test status
Simulation time 60746096 ps
CPU time 0.98 seconds
Started Jan 14 01:41:03 PM PST 24
Finished Jan 14 01:41:05 PM PST 24
Peak memory 196796 kb
Host smart-bf0fcff6-695d-418b-83cf-b881f1594088
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379109047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2379109047
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2198857738
Short name T419
Test name
Test status
Simulation time 292604034 ps
CPU time 4.38 seconds
Started Jan 14 01:41:03 PM PST 24
Finished Jan 14 01:41:08 PM PST 24
Peak memory 197200 kb
Host smart-8332a68c-52ba-4868-beb3-4eaff4351972
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198857738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2198857738
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1256873241
Short name T610
Test name
Test status
Simulation time 64018906 ps
CPU time 1.21 seconds
Started Jan 14 01:41:05 PM PST 24
Finished Jan 14 01:41:07 PM PST 24
Peak memory 195668 kb
Host smart-1a4f1647-6f31-435f-9b04-520669493e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256873241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1256873241
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1889966362
Short name T862
Test name
Test status
Simulation time 42433631 ps
CPU time 0.94 seconds
Started Jan 14 01:41:04 PM PST 24
Finished Jan 14 01:41:06 PM PST 24
Peak memory 196692 kb
Host smart-8ac1ad79-71f2-44c2-95e4-2d900f5187ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889966362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1889966362
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.189617271
Short name T442
Test name
Test status
Simulation time 5358674537 ps
CPU time 72.85 seconds
Started Jan 14 01:41:11 PM PST 24
Finished Jan 14 01:42:25 PM PST 24
Peak memory 198272 kb
Host smart-271be35e-fe16-4de0-832b-43c0b5f4b07e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189617271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.189617271
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3715403700
Short name T67
Test name
Test status
Simulation time 99811872631 ps
CPU time 1847.42 seconds
Started Jan 14 01:41:09 PM PST 24
Finished Jan 14 02:11:57 PM PST 24
Peak memory 198364 kb
Host smart-97f0ab6a-f52f-4285-bc74-ef7322eff949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3715403700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3715403700
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3935387443
Short name T782
Test name
Test status
Simulation time 15049224 ps
CPU time 0.62 seconds
Started Jan 14 01:41:09 PM PST 24
Finished Jan 14 01:41:11 PM PST 24
Peak memory 194180 kb
Host smart-4c21b88c-ac7b-4a86-a592-992ac6317558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935387443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3935387443
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4150804475
Short name T882
Test name
Test status
Simulation time 20674079 ps
CPU time 0.69 seconds
Started Jan 14 01:41:15 PM PST 24
Finished Jan 14 01:41:17 PM PST 24
Peak memory 194948 kb
Host smart-a8e85045-1dee-4c74-a25c-ff2a580fdbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150804475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.4150804475
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2021121836
Short name T379
Test name
Test status
Simulation time 3008584364 ps
CPU time 26.66 seconds
Started Jan 14 01:41:10 PM PST 24
Finished Jan 14 01:41:38 PM PST 24
Peak memory 196768 kb
Host smart-fba89d81-ee51-450a-99eb-9495cfb065ec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021121836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2021121836
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.164607843
Short name T625
Test name
Test status
Simulation time 33212879 ps
CPU time 0.74 seconds
Started Jan 14 01:41:13 PM PST 24
Finished Jan 14 01:41:14 PM PST 24
Peak memory 196632 kb
Host smart-2f3fea70-e350-4788-b4b3-d7ff757e86a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164607843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.164607843
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2351610370
Short name T560
Test name
Test status
Simulation time 254957824 ps
CPU time 1.3 seconds
Started Jan 14 01:41:11 PM PST 24
Finished Jan 14 01:41:13 PM PST 24
Peak memory 196236 kb
Host smart-162ab9c7-233d-48ea-9baf-a9b4feed068b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351610370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2351610370
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.266255137
Short name T516
Test name
Test status
Simulation time 188096154 ps
CPU time 2.02 seconds
Started Jan 14 01:41:12 PM PST 24
Finished Jan 14 01:41:15 PM PST 24
Peak memory 198288 kb
Host smart-68925cb9-431a-49cc-b803-734ebc1fc2fb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266255137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.266255137
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3796461541
Short name T514
Test name
Test status
Simulation time 135780390 ps
CPU time 1.66 seconds
Started Jan 14 01:41:15 PM PST 24
Finished Jan 14 01:41:17 PM PST 24
Peak memory 196232 kb
Host smart-75bfce9a-2e7a-4c6b-8bfb-9ad48cad3c5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796461541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3796461541
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.256608515
Short name T831
Test name
Test status
Simulation time 141672231 ps
CPU time 1.14 seconds
Started Jan 14 01:41:11 PM PST 24
Finished Jan 14 01:41:13 PM PST 24
Peak memory 196600 kb
Host smart-ab7db6d2-9529-4e8e-9af9-db2b62c2a961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256608515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.256608515
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1967407919
Short name T633
Test name
Test status
Simulation time 284884840 ps
CPU time 0.98 seconds
Started Jan 14 01:41:12 PM PST 24
Finished Jan 14 01:41:13 PM PST 24
Peak memory 195904 kb
Host smart-3b9a75f0-465d-4696-b3ef-d3c248b60a4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967407919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1967407919
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1547342581
Short name T856
Test name
Test status
Simulation time 193054672 ps
CPU time 2.54 seconds
Started Jan 14 01:41:11 PM PST 24
Finished Jan 14 01:41:14 PM PST 24
Peak memory 198212 kb
Host smart-09f6c04f-5843-4dfd-902a-be7e079922d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547342581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1547342581
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.497440587
Short name T858
Test name
Test status
Simulation time 42412591 ps
CPU time 1.24 seconds
Started Jan 14 01:41:11 PM PST 24
Finished Jan 14 01:41:13 PM PST 24
Peak memory 196832 kb
Host smart-31088b2b-758d-43ab-8b50-8b260f59ac15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497440587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.497440587
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1257499796
Short name T304
Test name
Test status
Simulation time 48379452 ps
CPU time 1.01 seconds
Started Jan 14 01:41:09 PM PST 24
Finished Jan 14 01:41:10 PM PST 24
Peak memory 195904 kb
Host smart-0dce68db-4ed0-40ce-933b-a5e9df35b1c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257499796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1257499796
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.516605525
Short name T662
Test name
Test status
Simulation time 61237635370 ps
CPU time 175.89 seconds
Started Jan 14 01:41:11 PM PST 24
Finished Jan 14 01:44:08 PM PST 24
Peak memory 198248 kb
Host smart-4d9dfd82-64ea-400f-8743-feca38504afa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516605525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.516605525
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2216207030
Short name T640
Test name
Test status
Simulation time 396918802082 ps
CPU time 1926.91 seconds
Started Jan 14 01:41:10 PM PST 24
Finished Jan 14 02:13:18 PM PST 24
Peak memory 198400 kb
Host smart-9ebaa53b-db3a-4a54-b83c-93d4ac37e8e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2216207030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2216207030
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.930470987
Short name T627
Test name
Test status
Simulation time 25927601 ps
CPU time 0.57 seconds
Started Jan 14 01:41:31 PM PST 24
Finished Jan 14 01:41:32 PM PST 24
Peak memory 195080 kb
Host smart-de923fd3-b145-41c0-8e05-517c3282a102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930470987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.930470987
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.545516626
Short name T231
Test name
Test status
Simulation time 26839509 ps
CPU time 0.68 seconds
Started Jan 14 01:41:24 PM PST 24
Finished Jan 14 01:41:25 PM PST 24
Peak memory 194244 kb
Host smart-ff7ba403-49f9-4ea6-bb29-e8df84591158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545516626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.545516626
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1001063737
Short name T475
Test name
Test status
Simulation time 1542410068 ps
CPU time 25.89 seconds
Started Jan 14 01:41:20 PM PST 24
Finished Jan 14 01:41:47 PM PST 24
Peak memory 197140 kb
Host smart-a940779c-824d-43e9-a6a2-d0e2dce02020
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001063737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1001063737
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.4000299094
Short name T389
Test name
Test status
Simulation time 34519050 ps
CPU time 0.69 seconds
Started Jan 14 01:41:25 PM PST 24
Finished Jan 14 01:41:26 PM PST 24
Peak memory 195840 kb
Host smart-aa355330-3d0e-46a8-ba04-0796729ea0e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000299094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.4000299094
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1730371873
Short name T427
Test name
Test status
Simulation time 96583449 ps
CPU time 1.41 seconds
Started Jan 14 01:41:33 PM PST 24
Finished Jan 14 01:41:36 PM PST 24
Peak memory 198212 kb
Host smart-430be787-e5b7-4383-b38d-7e08becca631
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730371873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1730371873
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.426398089
Short name T737
Test name
Test status
Simulation time 357249613 ps
CPU time 3.42 seconds
Started Jan 14 01:41:19 PM PST 24
Finished Jan 14 01:41:23 PM PST 24
Peak memory 198260 kb
Host smart-f3863e12-1f8a-46e1-b3ec-5a68531713dc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426398089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.426398089
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1568535453
Short name T729
Test name
Test status
Simulation time 52126555 ps
CPU time 0.86 seconds
Started Jan 14 01:41:22 PM PST 24
Finished Jan 14 01:41:24 PM PST 24
Peak memory 194572 kb
Host smart-a5d5251e-a35a-41af-9617-f61c5bb77c66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568535453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1568535453
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.123358848
Short name T506
Test name
Test status
Simulation time 33976610 ps
CPU time 0.68 seconds
Started Jan 14 01:41:10 PM PST 24
Finished Jan 14 01:41:12 PM PST 24
Peak memory 195132 kb
Host smart-10b1599a-18a0-4ce6-a477-67338e03d499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123358848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.123358848
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2347357327
Short name T421
Test name
Test status
Simulation time 65823924 ps
CPU time 0.87 seconds
Started Jan 14 01:41:13 PM PST 24
Finished Jan 14 01:41:14 PM PST 24
Peak memory 196104 kb
Host smart-71cd2dfb-c162-486d-a898-41567bddfdff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347357327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2347357327
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2968819158
Short name T109
Test name
Test status
Simulation time 101976648 ps
CPU time 1.79 seconds
Started Jan 14 01:41:22 PM PST 24
Finished Jan 14 01:41:25 PM PST 24
Peak memory 198100 kb
Host smart-7b5730e3-7a16-4acf-bc1e-eddc17ef4b01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968819158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2968819158
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3720003321
Short name T222
Test name
Test status
Simulation time 202462822 ps
CPU time 1.27 seconds
Started Jan 14 01:41:12 PM PST 24
Finished Jan 14 01:41:14 PM PST 24
Peak memory 196848 kb
Host smart-940e59ef-0231-45cc-9436-c311fc6ea9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720003321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3720003321
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2727487387
Short name T431
Test name
Test status
Simulation time 207694799 ps
CPU time 1.52 seconds
Started Jan 14 01:41:14 PM PST 24
Finished Jan 14 01:41:16 PM PST 24
Peak memory 195668 kb
Host smart-ae2bb085-1165-4f44-a0c7-6e9348b6d1c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727487387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2727487387
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1374710192
Short name T429
Test name
Test status
Simulation time 1791085974 ps
CPU time 42.2 seconds
Started Jan 14 01:41:32 PM PST 24
Finished Jan 14 01:42:15 PM PST 24
Peak memory 198176 kb
Host smart-9c771968-0154-4772-9c9b-6f8d60f96e83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374710192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1374710192
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3955275642
Short name T550
Test name
Test status
Simulation time 117821057787 ps
CPU time 2594.81 seconds
Started Jan 14 01:41:31 PM PST 24
Finished Jan 14 02:24:46 PM PST 24
Peak memory 198408 kb
Host smart-dee3380a-07da-4c44-9316-7f7b6ced3c0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3955275642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3955275642
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3615631059
Short name T49
Test name
Test status
Simulation time 36201293 ps
CPU time 0.56 seconds
Started Jan 14 01:41:30 PM PST 24
Finished Jan 14 01:41:31 PM PST 24
Peak memory 194068 kb
Host smart-17a7f3d1-fac0-4b88-9054-2e0289421933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615631059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3615631059
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2372754352
Short name T646
Test name
Test status
Simulation time 21471045 ps
CPU time 0.64 seconds
Started Jan 14 01:41:31 PM PST 24
Finished Jan 14 01:41:32 PM PST 24
Peak memory 194076 kb
Host smart-43546835-9ca3-4693-b2ad-1165b8d074c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372754352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2372754352
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.53477222
Short name T347
Test name
Test status
Simulation time 399478136 ps
CPU time 10.57 seconds
Started Jan 14 01:41:32 PM PST 24
Finished Jan 14 01:41:44 PM PST 24
Peak memory 197004 kb
Host smart-a4a840f0-513a-4777-90e6-0e7c9d7b9931
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53477222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress.53477222
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.524436809
Short name T507
Test name
Test status
Simulation time 144734814 ps
CPU time 0.74 seconds
Started Jan 14 01:41:35 PM PST 24
Finished Jan 14 01:41:36 PM PST 24
Peak memory 195860 kb
Host smart-8b2f4aa5-c7ee-48ee-976f-a6a3313f37ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524436809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.524436809
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.712199969
Short name T763
Test name
Test status
Simulation time 62178336 ps
CPU time 0.69 seconds
Started Jan 14 01:41:29 PM PST 24
Finished Jan 14 01:41:30 PM PST 24
Peak memory 195492 kb
Host smart-32f37831-d853-414e-87a8-a13dbbeedfe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712199969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.712199969
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3557903691
Short name T797
Test name
Test status
Simulation time 69104221 ps
CPU time 2.14 seconds
Started Jan 14 01:41:30 PM PST 24
Finished Jan 14 01:41:33 PM PST 24
Peak memory 198192 kb
Host smart-1b415a45-b351-431f-a031-ae91c19b8674
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557903691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3557903691
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.833989823
Short name T256
Test name
Test status
Simulation time 174938963 ps
CPU time 1.86 seconds
Started Jan 14 01:41:23 PM PST 24
Finished Jan 14 01:41:26 PM PST 24
Peak memory 196244 kb
Host smart-d2876e75-6491-46cb-b9ef-867046fe416f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833989823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.833989823
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1667795098
Short name T519
Test name
Test status
Simulation time 28036495 ps
CPU time 0.82 seconds
Started Jan 14 01:41:32 PM PST 24
Finished Jan 14 01:41:34 PM PST 24
Peak memory 195596 kb
Host smart-e6cfaea6-fc81-4b7a-835b-9febf92b7fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667795098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1667795098
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1606352235
Short name T400
Test name
Test status
Simulation time 38077930 ps
CPU time 0.76 seconds
Started Jan 14 01:41:24 PM PST 24
Finished Jan 14 01:41:26 PM PST 24
Peak memory 195392 kb
Host smart-6953d098-56d4-44f3-8232-e2fad8eaa374
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606352235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1606352235
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3709010290
Short name T503
Test name
Test status
Simulation time 577086220 ps
CPU time 1.83 seconds
Started Jan 14 01:41:30 PM PST 24
Finished Jan 14 01:41:33 PM PST 24
Peak memory 198012 kb
Host smart-bcf9bf8f-71bc-4cf7-bcc1-acd5d5ba78db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709010290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3709010290
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1763637665
Short name T69
Test name
Test status
Simulation time 59134868 ps
CPU time 1.37 seconds
Started Jan 14 01:41:25 PM PST 24
Finished Jan 14 01:41:27 PM PST 24
Peak memory 196396 kb
Host smart-fbe901a9-0cd5-4641-8eff-5da995cd4346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763637665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1763637665
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.809020815
Short name T746
Test name
Test status
Simulation time 28705391 ps
CPU time 0.82 seconds
Started Jan 14 01:41:29 PM PST 24
Finished Jan 14 01:41:31 PM PST 24
Peak memory 196092 kb
Host smart-23c57467-9201-49d9-b582-e43ae2e1272c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809020815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.809020815
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3159787925
Short name T245
Test name
Test status
Simulation time 6763728230 ps
CPU time 83.94 seconds
Started Jan 14 01:41:30 PM PST 24
Finished Jan 14 01:42:55 PM PST 24
Peak memory 198236 kb
Host smart-26034ec2-c8fd-40ee-867e-7a60cfd4ab3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159787925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3159787925
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3444098394
Short name T437
Test name
Test status
Simulation time 309769831344 ps
CPU time 445.47 seconds
Started Jan 14 01:41:31 PM PST 24
Finished Jan 14 01:48:57 PM PST 24
Peak memory 198276 kb
Host smart-2b67067c-e284-44d6-8b3e-beb5ccd7c55e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3444098394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3444098394
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2287394199
Short name T193
Test name
Test status
Simulation time 335551676 ps
CPU time 1.14 seconds
Started Jan 14 12:59:51 PM PST 24
Finished Jan 14 12:59:53 PM PST 24
Peak memory 195532 kb
Host smart-f9a93a7e-c45b-4b9f-bd20-8db426c5d051
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287394199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2287394199
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2322111700
Short name T153
Test name
Test status
Simulation time 158396354 ps
CPU time 0.88 seconds
Started Jan 14 12:59:52 PM PST 24
Finished Jan 14 12:59:54 PM PST 24
Peak memory 194980 kb
Host smart-3bc77dc0-f136-4bbc-9093-9b2af104a9c8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2322111700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2322111700
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.26671412
Short name T154
Test name
Test status
Simulation time 380889336 ps
CPU time 0.71 seconds
Started Jan 14 12:59:51 PM PST 24
Finished Jan 14 12:59:52 PM PST 24
Peak memory 194796 kb
Host smart-ae8e602f-9771-4efb-a643-82a1da7a38ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26671412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.26671412
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.578039781
Short name T205
Test name
Test status
Simulation time 90736594 ps
CPU time 1.09 seconds
Started Jan 14 01:00:00 PM PST 24
Finished Jan 14 01:00:02 PM PST 24
Peak memory 197700 kb
Host smart-16878c92-9908-4eac-ad88-7bed01bd4a51
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=578039781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.578039781
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.751436864
Short name T211
Test name
Test status
Simulation time 228566292 ps
CPU time 1.17 seconds
Started Jan 14 12:59:59 PM PST 24
Finished Jan 14 01:00:01 PM PST 24
Peak memory 196248 kb
Host smart-6c90457b-c69b-4342-b64f-3fd3760fe788
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751436864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.751436864
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2316708665
Short name T189
Test name
Test status
Simulation time 148167066 ps
CPU time 1.14 seconds
Started Jan 14 01:00:00 PM PST 24
Finished Jan 14 01:00:02 PM PST 24
Peak memory 195576 kb
Host smart-0e692473-5669-4514-b3b0-79e579577c3d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2316708665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2316708665
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2677574700
Short name T134
Test name
Test status
Simulation time 22681314 ps
CPU time 0.78 seconds
Started Jan 14 01:00:05 PM PST 24
Finished Jan 14 01:00:06 PM PST 24
Peak memory 195708 kb
Host smart-ecae3bdd-989a-4dc7-9ab3-fbf50fb26841
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677574700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2677574700
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3418529948
Short name T218
Test name
Test status
Simulation time 384943672 ps
CPU time 1.23 seconds
Started Jan 14 01:00:01 PM PST 24
Finished Jan 14 01:00:03 PM PST 24
Peak memory 196196 kb
Host smart-a33d5126-67c9-4012-a97e-901582062ce6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3418529948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3418529948
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1845247543
Short name T162
Test name
Test status
Simulation time 339936903 ps
CPU time 0.99 seconds
Started Jan 14 12:59:57 PM PST 24
Finished Jan 14 12:59:59 PM PST 24
Peak memory 197576 kb
Host smart-e4ada8cf-b957-4182-af3f-99e00f25f061
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845247543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1845247543
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1241905482
Short name T146
Test name
Test status
Simulation time 94864490 ps
CPU time 1.46 seconds
Started Jan 14 12:59:59 PM PST 24
Finished Jan 14 01:00:01 PM PST 24
Peak memory 197580 kb
Host smart-4205e73c-989d-4cc9-b86c-f891e026ada9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1241905482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1241905482
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1618609443
Short name T171
Test name
Test status
Simulation time 38225115 ps
CPU time 0.99 seconds
Started Jan 14 12:59:58 PM PST 24
Finished Jan 14 01:00:00 PM PST 24
Peak memory 195276 kb
Host smart-236e31b0-d1d6-40e7-b463-1d3bfd1395e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618609443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1618609443
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2707651272
Short name T114
Test name
Test status
Simulation time 36693132 ps
CPU time 0.94 seconds
Started Jan 14 12:59:58 PM PST 24
Finished Jan 14 01:00:00 PM PST 24
Peak memory 197120 kb
Host smart-8478cc43-a21a-4702-9e33-526fc33a9515
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2707651272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2707651272
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1282372769
Short name T203
Test name
Test status
Simulation time 207455819 ps
CPU time 1.05 seconds
Started Jan 14 01:00:03 PM PST 24
Finished Jan 14 01:00:05 PM PST 24
Peak memory 195444 kb
Host smart-2bfa5758-c8ba-4829-a118-a14869caea42
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282372769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1282372769
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1121741623
Short name T207
Test name
Test status
Simulation time 217935648 ps
CPU time 1.13 seconds
Started Jan 14 01:00:13 PM PST 24
Finished Jan 14 01:00:15 PM PST 24
Peak memory 197732 kb
Host smart-1adbafc7-7fbb-4bc9-903a-4e766d0d1ea6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1121741623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1121741623
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3920931519
Short name T208
Test name
Test status
Simulation time 52584513 ps
CPU time 1.15 seconds
Started Jan 14 01:00:07 PM PST 24
Finished Jan 14 01:00:09 PM PST 24
Peak memory 196168 kb
Host smart-69c1e8ee-12ae-44af-9e40-4e5325a64f06
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920931519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3920931519
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1537623569
Short name T176
Test name
Test status
Simulation time 164421001 ps
CPU time 1.08 seconds
Started Jan 14 01:00:07 PM PST 24
Finished Jan 14 01:00:09 PM PST 24
Peak memory 197596 kb
Host smart-334eafb0-c84c-4707-81e8-a8fd03468f17
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1537623569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1537623569
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3301854295
Short name T170
Test name
Test status
Simulation time 179491598 ps
CPU time 1.18 seconds
Started Jan 14 01:00:08 PM PST 24
Finished Jan 14 01:00:10 PM PST 24
Peak memory 196336 kb
Host smart-3e574f82-025f-476e-85c7-d5c27afd063f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301854295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3301854295
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1316544087
Short name T192
Test name
Test status
Simulation time 125988283 ps
CPU time 0.85 seconds
Started Jan 14 01:00:10 PM PST 24
Finished Jan 14 01:00:12 PM PST 24
Peak memory 195116 kb
Host smart-dac365b2-98bc-4def-b09c-0b409148badd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1316544087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1316544087
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1516651095
Short name T173
Test name
Test status
Simulation time 81982717 ps
CPU time 0.87 seconds
Started Jan 14 01:00:09 PM PST 24
Finished Jan 14 01:00:11 PM PST 24
Peak memory 195640 kb
Host smart-dcb2ceec-845b-40a2-8701-5f40fd0f8f2b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516651095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1516651095
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.4089953384
Short name T196
Test name
Test status
Simulation time 131442042 ps
CPU time 1.23 seconds
Started Jan 14 01:00:12 PM PST 24
Finished Jan 14 01:00:14 PM PST 24
Peak memory 195300 kb
Host smart-4118febe-5c49-47a0-822a-421bbfe9faad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4089953384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.4089953384
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2111569560
Short name T177
Test name
Test status
Simulation time 60625684 ps
CPU time 0.86 seconds
Started Jan 14 01:00:10 PM PST 24
Finished Jan 14 01:00:12 PM PST 24
Peak memory 194920 kb
Host smart-42bd15d0-d671-4ce3-83dc-4abebfcc3663
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111569560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2111569560
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2447682329
Short name T140
Test name
Test status
Simulation time 51460967 ps
CPU time 1.47 seconds
Started Jan 14 01:00:10 PM PST 24
Finished Jan 14 01:00:13 PM PST 24
Peak memory 197676 kb
Host smart-bd86412b-87b2-4303-a351-70c5c5395650
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2447682329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2447682329
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.347016505
Short name T160
Test name
Test status
Simulation time 160167241 ps
CPU time 1.08 seconds
Started Jan 14 01:00:11 PM PST 24
Finished Jan 14 01:00:12 PM PST 24
Peak memory 197704 kb
Host smart-479de09b-29f1-414e-b1bd-ae42cafa5d64
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347016505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.347016505
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.5020775
Short name T210
Test name
Test status
Simulation time 206462630 ps
CPU time 1.04 seconds
Started Jan 14 12:59:53 PM PST 24
Finished Jan 14 12:59:54 PM PST 24
Peak memory 197672 kb
Host smart-4acfbe25-ee83-422f-bfac-f67e93e2ba56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=5020775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.5020775
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2963917517
Short name T164
Test name
Test status
Simulation time 40370346 ps
CPU time 1.21 seconds
Started Jan 14 12:59:51 PM PST 24
Finished Jan 14 12:59:53 PM PST 24
Peak memory 195264 kb
Host smart-8b2ac498-f71f-4971-9209-b3ba7aace04b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963917517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2963917517
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4044129918
Short name T155
Test name
Test status
Simulation time 260033477 ps
CPU time 1.27 seconds
Started Jan 14 01:00:11 PM PST 24
Finished Jan 14 01:00:13 PM PST 24
Peak memory 196736 kb
Host smart-e1073d0a-5df6-4fc3-99ac-da020da2b2e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4044129918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.4044129918
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.360809015
Short name T158
Test name
Test status
Simulation time 35150726 ps
CPU time 1.01 seconds
Started Jan 14 01:00:11 PM PST 24
Finished Jan 14 01:00:13 PM PST 24
Peak memory 196172 kb
Host smart-737cfc91-2cb0-4d34-9340-752737adb629
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=360809015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.360809015
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1716412998
Short name T139
Test name
Test status
Simulation time 65154870 ps
CPU time 1.11 seconds
Started Jan 14 01:00:06 PM PST 24
Finished Jan 14 01:00:08 PM PST 24
Peak memory 195396 kb
Host smart-b1ec7fde-0117-4e4c-8c8e-cfeb5e55bdad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716412998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1716412998
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3342500290
Short name T217
Test name
Test status
Simulation time 31768566 ps
CPU time 0.81 seconds
Started Jan 14 01:00:15 PM PST 24
Finished Jan 14 01:00:17 PM PST 24
Peak memory 195184 kb
Host smart-026bbe9f-9bc6-42e1-a1d9-bacf4fcedcd9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3342500290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3342500290
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.530457096
Short name T133
Test name
Test status
Simulation time 290722063 ps
CPU time 1.29 seconds
Started Jan 14 01:00:15 PM PST 24
Finished Jan 14 01:00:17 PM PST 24
Peak memory 195684 kb
Host smart-1627fa63-6764-4bae-91db-1d036ae6d12a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530457096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.530457096
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2587508040
Short name T175
Test name
Test status
Simulation time 146682246 ps
CPU time 0.86 seconds
Started Jan 14 01:00:16 PM PST 24
Finished Jan 14 01:00:17 PM PST 24
Peak memory 195964 kb
Host smart-2df4b60e-3633-4811-83f2-8af1c460588e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2587508040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2587508040
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4206929775
Short name T161
Test name
Test status
Simulation time 30309105 ps
CPU time 0.86 seconds
Started Jan 14 01:00:12 PM PST 24
Finished Jan 14 01:00:14 PM PST 24
Peak memory 195148 kb
Host smart-d82c6318-0f3a-4ebf-b78f-b71a547139bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206929775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4206929775
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4249932142
Short name T53
Test name
Test status
Simulation time 359691979 ps
CPU time 1.44 seconds
Started Jan 14 01:00:16 PM PST 24
Finished Jan 14 01:00:19 PM PST 24
Peak memory 196336 kb
Host smart-e6cfe2aa-bf2f-405c-a0d7-734668457b40
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4249932142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.4249932142
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2472652931
Short name T209
Test name
Test status
Simulation time 55651251 ps
CPU time 1.09 seconds
Started Jan 14 01:00:18 PM PST 24
Finished Jan 14 01:00:19 PM PST 24
Peak memory 195564 kb
Host smart-56636184-9e56-4a75-b17c-b8d1f86e6d50
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472652931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2472652931
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4161058425
Short name T157
Test name
Test status
Simulation time 135313384 ps
CPU time 0.89 seconds
Started Jan 14 01:00:14 PM PST 24
Finished Jan 14 01:00:16 PM PST 24
Peak memory 196184 kb
Host smart-f8186445-c131-441b-b93f-f50c03c1d174
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4161058425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.4161058425
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4098930671
Short name T163
Test name
Test status
Simulation time 73467660 ps
CPU time 1.37 seconds
Started Jan 14 01:00:16 PM PST 24
Finished Jan 14 01:00:19 PM PST 24
Peak memory 196284 kb
Host smart-28f0b0e8-1e7f-4eaf-83b8-42e150afad19
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098930671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4098930671
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1435352944
Short name T212
Test name
Test status
Simulation time 65173208 ps
CPU time 1.29 seconds
Started Jan 14 01:00:14 PM PST 24
Finished Jan 14 01:00:16 PM PST 24
Peak memory 197736 kb
Host smart-4f27cf98-ef28-449a-a185-076f8d63ad5c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1435352944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1435352944
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1636381878
Short name T156
Test name
Test status
Simulation time 103015177 ps
CPU time 0.77 seconds
Started Jan 14 01:00:15 PM PST 24
Finished Jan 14 01:00:16 PM PST 24
Peak memory 194060 kb
Host smart-0bff649a-3c4d-4f4c-83ad-0362dcea775b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636381878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1636381878
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3234957563
Short name T174
Test name
Test status
Simulation time 51643288 ps
CPU time 1.35 seconds
Started Jan 14 01:00:19 PM PST 24
Finished Jan 14 01:00:21 PM PST 24
Peak memory 196564 kb
Host smart-25900088-8781-44f0-ab0a-5908be0678ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3234957563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3234957563
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1961797859
Short name T167
Test name
Test status
Simulation time 82211330 ps
CPU time 0.86 seconds
Started Jan 14 01:00:13 PM PST 24
Finished Jan 14 01:00:15 PM PST 24
Peak memory 195112 kb
Host smart-ea5acc3e-95fe-4899-b5c1-7cc6d2441bb3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961797859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1961797859
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1018341606
Short name T197
Test name
Test status
Simulation time 175601564 ps
CPU time 1.07 seconds
Started Jan 14 01:00:16 PM PST 24
Finished Jan 14 01:00:18 PM PST 24
Peak memory 195484 kb
Host smart-55e57f4d-a787-416f-9f25-f67317d096d4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1018341606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1018341606
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.89542048
Short name T202
Test name
Test status
Simulation time 37316275 ps
CPU time 0.85 seconds
Started Jan 14 01:00:15 PM PST 24
Finished Jan 14 01:00:16 PM PST 24
Peak memory 195880 kb
Host smart-90f45c46-3663-4300-8338-09bd9dc612a4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89542048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.89542048
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2662831597
Short name T57
Test name
Test status
Simulation time 190030557 ps
CPU time 0.88 seconds
Started Jan 14 01:00:17 PM PST 24
Finished Jan 14 01:00:19 PM PST 24
Peak memory 196444 kb
Host smart-77c8a5ef-ae46-4154-bfd9-25ae4d3d18b1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2662831597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2662831597
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1575342078
Short name T151
Test name
Test status
Simulation time 92089449 ps
CPU time 0.79 seconds
Started Jan 14 01:00:17 PM PST 24
Finished Jan 14 01:00:19 PM PST 24
Peak memory 194928 kb
Host smart-5392289e-1311-49e8-bc14-1b41bfd1cdd2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575342078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1575342078
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.819570010
Short name T188
Test name
Test status
Simulation time 31969985 ps
CPU time 0.85 seconds
Started Jan 14 12:59:52 PM PST 24
Finished Jan 14 12:59:54 PM PST 24
Peak memory 195944 kb
Host smart-0904d87c-b1e1-4942-ac99-4bb20693efc2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=819570010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.819570010
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1518546777
Short name T135
Test name
Test status
Simulation time 195046675 ps
CPU time 1.34 seconds
Started Jan 14 12:59:51 PM PST 24
Finished Jan 14 12:59:53 PM PST 24
Peak memory 196288 kb
Host smart-a2df5268-3037-4dfa-a0be-2a8ba6921615
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518546777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1518546777
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2774166289
Short name T220
Test name
Test status
Simulation time 32348226 ps
CPU time 1.08 seconds
Started Jan 14 01:00:19 PM PST 24
Finished Jan 14 01:00:21 PM PST 24
Peak memory 196228 kb
Host smart-0d5a1d4a-5ef6-49b3-90e9-5a9e81575651
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2774166289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2774166289
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2995241015
Short name T183
Test name
Test status
Simulation time 53663227 ps
CPU time 1.5 seconds
Started Jan 14 01:00:16 PM PST 24
Finished Jan 14 01:00:18 PM PST 24
Peak memory 196428 kb
Host smart-0f1197f3-da97-4d71-be97-b87b9ff78d7c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995241015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2995241015
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1488281266
Short name T185
Test name
Test status
Simulation time 577713698 ps
CPU time 1.22 seconds
Started Jan 14 01:00:22 PM PST 24
Finished Jan 14 01:00:24 PM PST 24
Peak memory 195336 kb
Host smart-fb978b09-7192-465b-9dea-7137f7cc289d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1488281266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1488281266
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3244761774
Short name T221
Test name
Test status
Simulation time 70241055 ps
CPU time 0.87 seconds
Started Jan 14 01:00:21 PM PST 24
Finished Jan 14 01:00:23 PM PST 24
Peak memory 197524 kb
Host smart-64d94137-3952-4542-846f-8e7cb7a503d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244761774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3244761774
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3632700304
Short name T195
Test name
Test status
Simulation time 132609683 ps
CPU time 1.02 seconds
Started Jan 14 01:00:20 PM PST 24
Finished Jan 14 01:00:22 PM PST 24
Peak memory 195300 kb
Host smart-e9c0b0a6-4a1b-4c62-a028-bc1b0a52e6a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3632700304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3632700304
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2386586026
Short name T206
Test name
Test status
Simulation time 189456596 ps
CPU time 1.06 seconds
Started Jan 14 01:00:22 PM PST 24
Finished Jan 14 01:00:23 PM PST 24
Peak memory 196148 kb
Host smart-cfab71f0-8e65-42f9-b648-551ddb84a3e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386586026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2386586026
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2805222428
Short name T187
Test name
Test status
Simulation time 254594837 ps
CPU time 1.03 seconds
Started Jan 14 01:00:21 PM PST 24
Finished Jan 14 01:00:23 PM PST 24
Peak memory 196564 kb
Host smart-efe28fff-5fab-4d3f-8b84-81255b9f45b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2805222428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2805222428
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2342941851
Short name T150
Test name
Test status
Simulation time 57226038 ps
CPU time 1.11 seconds
Started Jan 14 01:00:28 PM PST 24
Finished Jan 14 01:00:30 PM PST 24
Peak memory 195712 kb
Host smart-cde9c3af-416a-4dec-a74d-3b2f77f4d60d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342941851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2342941851
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.696642403
Short name T149
Test name
Test status
Simulation time 53861558 ps
CPU time 1.39 seconds
Started Jan 14 01:00:29 PM PST 24
Finished Jan 14 01:00:31 PM PST 24
Peak memory 195304 kb
Host smart-0256c42a-eebf-49af-91f7-dcf742d139b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=696642403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.696642403
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1021349986
Short name T54
Test name
Test status
Simulation time 51002509 ps
CPU time 1.29 seconds
Started Jan 14 01:00:30 PM PST 24
Finished Jan 14 01:00:32 PM PST 24
Peak memory 195252 kb
Host smart-f41edbb3-8d1e-4639-bb02-51aefaecd065
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021349986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1021349986
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3251223991
Short name T200
Test name
Test status
Simulation time 160653734 ps
CPU time 0.89 seconds
Started Jan 14 01:00:28 PM PST 24
Finished Jan 14 01:00:30 PM PST 24
Peak memory 195940 kb
Host smart-74386989-da35-4d46-9376-ef6036d1ef69
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3251223991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3251223991
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3112558316
Short name T136
Test name
Test status
Simulation time 45249267 ps
CPU time 1.31 seconds
Started Jan 14 01:00:34 PM PST 24
Finished Jan 14 01:00:36 PM PST 24
Peak memory 197576 kb
Host smart-20c6341d-b57d-4a29-a8ec-dbe2bc528242
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112558316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3112558316
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3001668757
Short name T215
Test name
Test status
Simulation time 36131206 ps
CPU time 1.14 seconds
Started Jan 14 01:00:34 PM PST 24
Finished Jan 14 01:00:36 PM PST 24
Peak memory 195408 kb
Host smart-82f1a736-8113-4430-8ed8-2069d2bcb829
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3001668757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3001668757
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4138457788
Short name T44
Test name
Test status
Simulation time 145711852 ps
CPU time 1.22 seconds
Started Jan 14 01:00:30 PM PST 24
Finished Jan 14 01:00:32 PM PST 24
Peak memory 196648 kb
Host smart-a5cb45e6-dc21-4a74-bf80-ae81de54187c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138457788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4138457788
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2006752603
Short name T178
Test name
Test status
Simulation time 61959209 ps
CPU time 0.96 seconds
Started Jan 14 01:00:31 PM PST 24
Finished Jan 14 01:00:33 PM PST 24
Peak memory 196420 kb
Host smart-44f07df6-cdbe-4e19-aba5-874e29a93c5d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2006752603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2006752603
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1423432347
Short name T137
Test name
Test status
Simulation time 45087189 ps
CPU time 0.94 seconds
Started Jan 14 01:00:29 PM PST 24
Finished Jan 14 01:00:31 PM PST 24
Peak memory 195980 kb
Host smart-1f97bcb5-e3c1-4842-a9d6-d0270dad6eb5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423432347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1423432347
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3199061672
Short name T184
Test name
Test status
Simulation time 37743837 ps
CPU time 0.81 seconds
Started Jan 14 01:00:35 PM PST 24
Finished Jan 14 01:00:36 PM PST 24
Peak memory 195180 kb
Host smart-be80e724-3f14-4184-ad5c-17708b970f7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3199061672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3199061672
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3252144207
Short name T181
Test name
Test status
Simulation time 39590970 ps
CPU time 1.16 seconds
Started Jan 14 01:00:34 PM PST 24
Finished Jan 14 01:00:36 PM PST 24
Peak memory 196220 kb
Host smart-9d1fb748-6e33-48ad-b43a-74c04e8caeab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252144207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3252144207
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.712899081
Short name T145
Test name
Test status
Simulation time 30670515 ps
CPU time 0.94 seconds
Started Jan 14 01:00:34 PM PST 24
Finished Jan 14 01:00:35 PM PST 24
Peak memory 195232 kb
Host smart-174cac22-7c09-4d4e-a16f-0b53128f36c1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=712899081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.712899081
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4013365077
Short name T148
Test name
Test status
Simulation time 241052879 ps
CPU time 1.38 seconds
Started Jan 14 01:00:34 PM PST 24
Finished Jan 14 01:00:36 PM PST 24
Peak memory 195412 kb
Host smart-b9c5e111-98ba-4e2c-a9ff-0679555353b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013365077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4013365077
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1588089756
Short name T190
Test name
Test status
Simulation time 45698116 ps
CPU time 1.03 seconds
Started Jan 14 12:59:49 PM PST 24
Finished Jan 14 12:59:51 PM PST 24
Peak memory 196180 kb
Host smart-ce59e6de-32e7-4da4-be3b-2b02e0639894
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1588089756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1588089756
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.228793243
Short name T43
Test name
Test status
Simulation time 63181883 ps
CPU time 1.07 seconds
Started Jan 14 12:59:49 PM PST 24
Finished Jan 14 12:59:51 PM PST 24
Peak memory 195576 kb
Host smart-e731b35c-c2f4-47ac-8dc8-7971c5b1a5c7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228793243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.228793243
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2077795209
Short name T216
Test name
Test status
Simulation time 113256697 ps
CPU time 0.68 seconds
Started Jan 14 01:00:30 PM PST 24
Finished Jan 14 01:00:31 PM PST 24
Peak memory 194092 kb
Host smart-7350c55f-d470-4ab4-86a1-4e36674a06e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2077795209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2077795209
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4060883186
Short name T142
Test name
Test status
Simulation time 24280666 ps
CPU time 0.7 seconds
Started Jan 14 01:00:29 PM PST 24
Finished Jan 14 01:00:31 PM PST 24
Peak memory 194048 kb
Host smart-e84af056-9bb3-450e-9da9-530082b9050a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060883186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4060883186
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3505182348
Short name T182
Test name
Test status
Simulation time 53428646 ps
CPU time 1.17 seconds
Started Jan 14 01:00:28 PM PST 24
Finished Jan 14 01:00:30 PM PST 24
Peak memory 196192 kb
Host smart-a68811e1-1968-434e-a26f-89277f24c877
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3505182348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3505182348
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.396640378
Short name T159
Test name
Test status
Simulation time 247843030 ps
CPU time 1.2 seconds
Started Jan 14 01:00:31 PM PST 24
Finished Jan 14 01:00:33 PM PST 24
Peak memory 195336 kb
Host smart-1b445275-4be5-40fc-b05a-83f6be0f4a9d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396640378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.396640378
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4185268155
Short name T143
Test name
Test status
Simulation time 79074717 ps
CPU time 1.31 seconds
Started Jan 14 01:00:30 PM PST 24
Finished Jan 14 01:00:32 PM PST 24
Peak memory 196232 kb
Host smart-79f537b1-da4e-4326-a2bb-31f4d1681b3f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4185268155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.4185268155
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4206081652
Short name T58
Test name
Test status
Simulation time 48556396 ps
CPU time 1.06 seconds
Started Jan 14 01:00:35 PM PST 24
Finished Jan 14 01:00:37 PM PST 24
Peak memory 196104 kb
Host smart-6da01065-01db-4a09-9f17-f92625b235dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206081652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4206081652
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.915098540
Short name T214
Test name
Test status
Simulation time 96253354 ps
CPU time 1.27 seconds
Started Jan 14 01:00:32 PM PST 24
Finished Jan 14 01:00:33 PM PST 24
Peak memory 196488 kb
Host smart-fa3dabfc-9166-41fd-a7b2-b0bf4255feaf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=915098540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.915098540
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.826822930
Short name T198
Test name
Test status
Simulation time 46896895 ps
CPU time 1.25 seconds
Started Jan 14 01:00:29 PM PST 24
Finished Jan 14 01:00:31 PM PST 24
Peak memory 196540 kb
Host smart-fc7be5bc-cd43-4b13-b8a2-b58bf5c04fb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826822930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.826822930
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2405687115
Short name T168
Test name
Test status
Simulation time 359557481 ps
CPU time 1.35 seconds
Started Jan 14 01:00:31 PM PST 24
Finished Jan 14 01:00:33 PM PST 24
Peak memory 196652 kb
Host smart-4b1d8e88-403d-4907-be7a-645464a6a1a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2405687115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2405687115
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2744648272
Short name T199
Test name
Test status
Simulation time 57113922 ps
CPU time 1.42 seconds
Started Jan 14 01:00:34 PM PST 24
Finished Jan 14 01:00:36 PM PST 24
Peak memory 197560 kb
Host smart-de7ef6e7-10a9-4f35-9ecf-9721d8fc420b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744648272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2744648272
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.261666901
Short name T169
Test name
Test status
Simulation time 145137286 ps
CPU time 1.16 seconds
Started Jan 14 01:00:30 PM PST 24
Finished Jan 14 01:00:32 PM PST 24
Peak memory 197684 kb
Host smart-34f5a598-d5a8-47c4-9763-b1e1ab4340bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=261666901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.261666901
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1448003160
Short name T186
Test name
Test status
Simulation time 90858041 ps
CPU time 1.47 seconds
Started Jan 14 01:00:37 PM PST 24
Finished Jan 14 01:00:39 PM PST 24
Peak memory 196468 kb
Host smart-604cc631-503d-41d4-96a8-bd70fcc76c1c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448003160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1448003160
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3099089362
Short name T147
Test name
Test status
Simulation time 65600361 ps
CPU time 1.27 seconds
Started Jan 14 01:00:36 PM PST 24
Finished Jan 14 01:00:37 PM PST 24
Peak memory 196448 kb
Host smart-369c1d91-5115-4737-9031-618f9faa9b48
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3099089362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3099089362
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1064507476
Short name T141
Test name
Test status
Simulation time 32376227 ps
CPU time 0.86 seconds
Started Jan 14 01:00:36 PM PST 24
Finished Jan 14 01:00:37 PM PST 24
Peak memory 195804 kb
Host smart-69c53af7-ed44-43cb-a916-cb88e83ad8da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064507476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1064507476
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4225044842
Short name T204
Test name
Test status
Simulation time 91870917 ps
CPU time 1.12 seconds
Started Jan 14 01:00:37 PM PST 24
Finished Jan 14 01:00:39 PM PST 24
Peak memory 197672 kb
Host smart-0fb2976a-72ee-424a-a2fe-395f1a389e13
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4225044842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.4225044842
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2056615387
Short name T165
Test name
Test status
Simulation time 63987286 ps
CPU time 0.93 seconds
Started Jan 14 01:00:36 PM PST 24
Finished Jan 14 01:00:37 PM PST 24
Peak memory 195312 kb
Host smart-94ed9841-6d1f-4e3b-8cda-fb35e6e2112b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056615387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2056615387
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1073180275
Short name T219
Test name
Test status
Simulation time 155211044 ps
CPU time 1.03 seconds
Started Jan 14 01:00:37 PM PST 24
Finished Jan 14 01:00:38 PM PST 24
Peak memory 196108 kb
Host smart-7b40ac65-8f45-47a7-bf3e-e4395c550d66
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1073180275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1073180275
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1141686077
Short name T172
Test name
Test status
Simulation time 162606993 ps
CPU time 0.96 seconds
Started Jan 14 01:00:39 PM PST 24
Finished Jan 14 01:00:40 PM PST 24
Peak memory 195340 kb
Host smart-5d5cd9af-f960-4da2-989d-d4f50c293695
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141686077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1141686077
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1269933011
Short name T213
Test name
Test status
Simulation time 352222195 ps
CPU time 1.37 seconds
Started Jan 14 01:00:39 PM PST 24
Finished Jan 14 01:00:41 PM PST 24
Peak memory 196232 kb
Host smart-e151ed99-45f7-41a7-912b-f95ad1e7dd34
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1269933011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1269933011
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.995946640
Short name T144
Test name
Test status
Simulation time 99201974 ps
CPU time 0.91 seconds
Started Jan 14 01:00:40 PM PST 24
Finished Jan 14 01:00:42 PM PST 24
Peak memory 195240 kb
Host smart-62a47034-b6a6-45b7-9a50-432199a9758b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995946640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.995946640
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2596289821
Short name T201
Test name
Test status
Simulation time 25708469 ps
CPU time 0.83 seconds
Started Jan 14 12:59:49 PM PST 24
Finished Jan 14 12:59:51 PM PST 24
Peak memory 195680 kb
Host smart-250be00c-1f41-4dea-aa9c-c7988e5caa4f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2596289821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2596289821
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2922274343
Short name T55
Test name
Test status
Simulation time 31878802 ps
CPU time 0.87 seconds
Started Jan 14 12:59:49 PM PST 24
Finished Jan 14 12:59:51 PM PST 24
Peak memory 195120 kb
Host smart-8e1af4c6-2bfc-45cb-96cf-d4d9b7554c4b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922274343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2922274343
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1805670709
Short name T179
Test name
Test status
Simulation time 198103425 ps
CPU time 0.97 seconds
Started Jan 14 12:59:48 PM PST 24
Finished Jan 14 12:59:49 PM PST 24
Peak memory 196192 kb
Host smart-a02d1508-51bf-46a3-ba56-f0961584cf41
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1805670709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1805670709
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2612327419
Short name T166
Test name
Test status
Simulation time 172451560 ps
CPU time 0.9 seconds
Started Jan 14 12:59:48 PM PST 24
Finished Jan 14 12:59:49 PM PST 24
Peak memory 196152 kb
Host smart-6fe55c1b-5c69-463b-b4a0-b9063baee551
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612327419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2612327419
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2234192504
Short name T138
Test name
Test status
Simulation time 39363993 ps
CPU time 1.15 seconds
Started Jan 14 12:59:52 PM PST 24
Finished Jan 14 12:59:54 PM PST 24
Peak memory 196136 kb
Host smart-78ac9ce1-e1a7-4e98-a9b7-4b79ea988c17
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2234192504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2234192504
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3542802459
Short name T191
Test name
Test status
Simulation time 439796479 ps
CPU time 1.47 seconds
Started Jan 14 12:59:51 PM PST 24
Finished Jan 14 12:59:53 PM PST 24
Peak memory 196372 kb
Host smart-787bca46-e366-44b9-bb12-0ee8c403de89
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542802459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3542802459
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1842433837
Short name T180
Test name
Test status
Simulation time 49464352 ps
CPU time 1.01 seconds
Started Jan 14 12:59:48 PM PST 24
Finished Jan 14 12:59:50 PM PST 24
Peak memory 196176 kb
Host smart-8be59eae-4eca-4c15-8d2a-b9c3755842f3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1842433837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1842433837
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.366782500
Short name T152
Test name
Test status
Simulation time 35684882 ps
CPU time 1.19 seconds
Started Jan 14 01:00:00 PM PST 24
Finished Jan 14 01:00:02 PM PST 24
Peak memory 196232 kb
Host smart-b596725f-80d0-48d5-9772-524f2c2767af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366782500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.366782500
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3450025918
Short name T194
Test name
Test status
Simulation time 57357653 ps
CPU time 1.09 seconds
Started Jan 14 12:59:58 PM PST 24
Finished Jan 14 12:59:59 PM PST 24
Peak memory 196276 kb
Host smart-ea963503-638b-4b00-96c1-4cb790771d34
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3450025918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3450025918
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1902985607
Short name T56
Test name
Test status
Simulation time 233129855 ps
CPU time 1.07 seconds
Started Jan 14 01:00:00 PM PST 24
Finished Jan 14 01:00:01 PM PST 24
Peak memory 196488 kb
Host smart-0e642121-5a23-4914-8b37-4119a962358b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902985607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1902985607
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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