Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	22802067	1			T23	12		T20	2		T21	30
all_values[1]	22802067	1			T23	12		T20	2		T21	30
all_values[2]	22802067	1			T23	12		T20	2		T21	30
all_values[3]	22802067	1			T23	12		T20	2		T21	30
all_values[4]	22802067	1			T23	12		T20	2		T21	30
all_values[5]	22802067	1			T23	12		T20	2		T21	30
all_values[6]	22802067	1			T23	12		T20	2		T21	30
all_values[7]	22802067	1			T23	12		T20	2		T21	30
all_values[8]	22802067	1			T23	12		T20	2		T21	30
all_values[9]	22802067	1			T23	12		T20	2		T21	30
all_values[10]	22802067	1			T23	12		T20	2		T21	30
all_values[11]	22802067	1			T23	12		T20	2		T21	30
all_values[12]	22802067	1			T23	12		T20	2		T21	30
all_values[13]	22802067	1			T23	12		T20	2		T21	30
all_values[14]	22802067	1			T23	12		T20	2		T21	30
all_values[15]	22802067	1			T23	12		T20	2		T21	30
all_values[16]	22802067	1			T23	12		T20	2		T21	30
all_values[17]	22802067	1			T23	12		T20	2		T21	30
all_values[18]	22802067	1			T23	12		T20	2		T21	30
all_values[19]	22802067	1			T23	12		T20	2		T21	30
all_values[20]	22802067	1			T23	12		T20	2		T21	30
all_values[21]	22802067	1			T23	12		T20	2		T21	30
all_values[22]	22802067	1			T23	12		T20	2		T21	30
all_values[23]	22802067	1			T23	12		T20	2		T21	30
all_values[24]	22802067	1			T23	12		T20	2		T21	30
all_values[25]	22802067	1			T23	12		T20	2		T21	30
all_values[26]	22802067	1			T23	12		T20	2		T21	30
all_values[27]	22802067	1			T23	12		T20	2		T21	30
all_values[28]	22802067	1			T23	12		T20	2		T21	30
all_values[29]	22802067	1			T23	12		T20	2		T21	30
all_values[30]	22802067	1			T23	12		T20	2		T21	30
all_values[31]	22802067	1			T23	12		T20	2		T21	30

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

401596952

1

T23

216

T20

47

T21

537

auto[1]

328069192

1

T23

168

T20

17

T21

423

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133715250

1

T23

281

T20

43

T21

568

auto[1]

595950894

1

T23

103

T20

21

T21

392

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3215641	1			T23	3		T20	2		T21	17
all_values[0]	auto[0]	auto[1]	9324943	1			T23	4		T21	1		T22	2
all_values[0]	auto[1]	auto[0]	952336	1			T23	1		T21	7		T22	5
all_values[0]	auto[1]	auto[1]	9309147	1			T23	4		T21	5		T22	7
all_values[1]	auto[0]	auto[0]	3223308	1			T23	7		T20	1		T21	8
all_values[1]	auto[0]	auto[1]	9347420	1			T21	6		T22	1		T11	5
all_values[1]	auto[1]	auto[0]	947374	1			T23	5		T21	7		T22	4
all_values[1]	auto[1]	auto[1]	9283965	1			T20	1		T21	9		T22	7
all_values[2]	auto[0]	auto[0]	3218071	1			T23	3		T20	1		T21	9
all_values[2]	auto[0]	auto[1]	9303445	1			T23	2		T21	11		T22	3
all_values[2]	auto[1]	auto[0]	955413	1			T23	4		T21	2		T22	7
all_values[2]	auto[1]	auto[1]	9325138	1			T23	3		T20	1		T21	8
all_values[3]	auto[0]	auto[0]	3221198	1			T23	4		T20	1		T21	11
all_values[3]	auto[0]	auto[1]	9307832	1			T23	5		T21	5		T22	9
all_values[3]	auto[1]	auto[0]	954437	1			T23	3		T21	14		T22	6
all_values[3]	auto[1]	auto[1]	9318600	1			T20	1		T1	1		T13	4
all_values[4]	auto[0]	auto[0]	3234550	1			T23	2		T20	1		T21	10
all_values[4]	auto[0]	auto[1]	9339577	1			T21	13		T22	2		T1	1
all_values[4]	auto[1]	auto[0]	945106	1			T23	3		T20	1		T21	6
all_values[4]	auto[1]	auto[1]	9282834	1			T23	7		T21	1		T22	4
all_values[5]	auto[0]	auto[0]	3226315	1			T23	5		T20	2		T21	6
all_values[5]	auto[0]	auto[1]	9340645	1			T21	15		T22	3		T1	1
all_values[5]	auto[1]	auto[0]	948691	1			T23	7		T21	4		T22	5
all_values[5]	auto[1]	auto[1]	9286416	1			T21	5		T1	1		T11	1
all_values[6]	auto[0]	auto[0]	3232396	1			T23	6		T20	1		T21	4
all_values[6]	auto[0]	auto[1]	9383760	1			T23	1		T20	1		T21	9
all_values[6]	auto[1]	auto[0]	955222	1			T23	2		T21	11		T22	4
all_values[6]	auto[1]	auto[1]	9230689	1			T23	3		T21	6		T22	1
all_values[7]	auto[0]	auto[0]	3220872	1			T23	7		T20	1		T21	9
all_values[7]	auto[0]	auto[1]	9307798	1			T20	1		T21	7		T22	9
all_values[7]	auto[1]	auto[0]	946873	1			T23	5		T21	10		T22	2
all_values[7]	auto[1]	auto[1]	9326524	1			T21	4		T22	3		T11	2
all_values[8]	auto[0]	auto[0]	3231812	1			T23	7		T20	1		T21	17
all_values[8]	auto[0]	auto[1]	9276936	1			T23	2		T20	1		T21	7
all_values[8]	auto[1]	auto[0]	954076	1			T23	3		T21	4		T22	2
all_values[8]	auto[1]	auto[1]	9339243	1			T21	2		T22	7		T14	2
all_values[9]	auto[0]	auto[0]	3221602	1			T23	7		T20	2		T21	12
all_values[9]	auto[0]	auto[1]	9363206	1			T21	5		T22	1		T11	5
all_values[9]	auto[1]	auto[0]	948192	1			T23	5		T21	7		T22	2
all_values[9]	auto[1]	auto[1]	9269067	1			T21	6		T22	3		T1	1
all_values[10]	auto[0]	auto[0]	3223528	1			T23	2		T20	1		T21	20
all_values[10]	auto[0]	auto[1]	9279848	1			T22	5		T11	6		T13	6
all_values[10]	auto[1]	auto[0]	954123	1			T23	10		T20	1		T21	8
all_values[10]	auto[1]	auto[1]	9344568	1			T21	2		T22	1		T1	1
all_values[11]	auto[0]	auto[0]	3226915	1			T23	7		T20	1		T21	14
all_values[11]	auto[0]	auto[1]	9346893	1			T21	10		T22	4		T11	8
all_values[11]	auto[1]	auto[0]	964902	1			T23	3		T20	1		T21	6
all_values[11]	auto[1]	auto[1]	9263357	1			T23	2		T22	7		T1	1
all_values[12]	auto[0]	auto[0]	3222088	1			T23	5		T20	1		T21	8
all_values[12]	auto[0]	auto[1]	9304663	1			T23	2		T21	2		T22	2
all_values[12]	auto[1]	auto[0]	953074	1			T23	5		T21	4		T22	3
all_values[12]	auto[1]	auto[1]	9322242	1			T20	1		T21	16		T22	10
all_values[13]	auto[0]	auto[0]	3216622	1			T23	6		T20	1		T21	7
all_values[13]	auto[0]	auto[1]	9335828	1			T23	1		T22	7		T11	9
all_values[13]	auto[1]	auto[0]	961082	1			T23	4		T21	14		T22	2
all_values[13]	auto[1]	auto[1]	9288535	1			T23	1		T20	1		T21	9
all_values[14]	auto[0]	auto[0]	3217256	1			T23	6		T20	1		T21	11
all_values[14]	auto[0]	auto[1]	9324485	1			T23	1		T21	9		T22	4
all_values[14]	auto[1]	auto[0]	949215	1			T23	1		T21	7		T22	3
all_values[14]	auto[1]	auto[1]	9311111	1			T23	4		T20	1		T21	3
all_values[15]	auto[0]	auto[0]	3219411	1			T23	7		T20	1		T21	12
all_values[15]	auto[0]	auto[1]	9334992	1			T20	1		T21	11		T22	13
all_values[15]	auto[1]	auto[0]	950285	1			T23	5		T21	7		T22	2
all_values[15]	auto[1]	auto[1]	9297379	1			T22	3		T1	1		T11	1
all_values[16]	auto[0]	auto[0]	3223374	1			T23	3		T20	1		T21	15
all_values[16]	auto[0]	auto[1]	9317987	1			T23	4		T20	1		T21	7
all_values[16]	auto[1]	auto[0]	950657	1			T23	1		T21	6		T22	1
all_values[16]	auto[1]	auto[1]	9310049	1			T23	4		T21	2		T22	14
all_values[17]	auto[0]	auto[0]	3220691	1			T23	4		T20	1		T21	13
all_values[17]	auto[0]	auto[1]	9361641	1			T21	2		T22	2		T11	5
all_values[17]	auto[1]	auto[0]	955046	1			T23	8		T21	14		T22	5
all_values[17]	auto[1]	auto[1]	9264689	1			T20	1		T21	1		T22	2
all_values[18]	auto[0]	auto[0]	3219539	1			T23	3		T20	1		T21	13
all_values[18]	auto[0]	auto[1]	9315420	1			T23	2		T21	4		T22	4
all_values[18]	auto[1]	auto[0]	969017	1			T23	1		T21	9		T22	2
all_values[18]	auto[1]	auto[1]	9298091	1			T23	6		T20	1		T21	4
all_values[19]	auto[0]	auto[0]	3240381	1			T23	5		T20	1		T21	9
all_values[19]	auto[0]	auto[1]	9366054	1			T23	2		T20	1		T21	11
all_values[19]	auto[1]	auto[0]	946262	1			T23	5		T21	4		T22	17
all_values[19]	auto[1]	auto[1]	9249370	1			T21	6		T22	1		T1	1
all_values[20]	auto[0]	auto[0]	3223950	1			T23	4		T20	1		T21	9
all_values[20]	auto[0]	auto[1]	9304780	1			T23	3		T20	1		T21	6
all_values[20]	auto[1]	auto[0]	958947	1			T23	3		T21	10		T22	7
all_values[20]	auto[1]	auto[1]	9314390	1			T23	2		T21	5		T22	5
all_values[21]	auto[0]	auto[0]	3227840	1			T23	4		T20	1		T21	12
all_values[21]	auto[0]	auto[1]	9312828	1			T23	3		T20	1		T21	11
all_values[21]	auto[1]	auto[0]	953934	1			T23	4		T21	5		T22	9
all_values[21]	auto[1]	auto[1]	9307465	1			T23	1		T21	2		T22	3
all_values[22]	auto[0]	auto[0]	3230893	1			T23	10		T20	2		T21	4
all_values[22]	auto[0]	auto[1]	9295359	1			T23	2		T21	12		T22	4
all_values[22]	auto[1]	auto[0]	961099	1			T21	12		T22	7		T11	4
all_values[22]	auto[1]	auto[1]	9314716	1			T21	2		T22	2		T1	1
all_values[23]	auto[0]	auto[0]	3238135	1			T23	2		T20	1		T21	5
all_values[23]	auto[0]	auto[1]	9331644	1			T20	1		T21	9		T22	6
all_values[23]	auto[1]	auto[0]	961570	1			T23	8		T21	4		T11	3
all_values[23]	auto[1]	auto[1]	9270718	1			T23	2		T21	12		T22	6
all_values[24]	auto[0]	auto[0]	3221112	1			T23	6		T20	1		T21	4
all_values[24]	auto[0]	auto[1]	9313728	1			T23	3		T21	9		T22	1
all_values[24]	auto[1]	auto[0]	943272	1			T23	1		T20	1		T21	10
all_values[24]	auto[1]	auto[1]	9323955	1			T23	2		T21	7		T22	2
all_values[25]	auto[0]	auto[0]	3227365	1			T23	2		T20	1		T21	3
all_values[25]	auto[0]	auto[1]	9288638	1			T21	8		T22	1		T1	1
all_values[25]	auto[1]	auto[0]	969779	1			T23	8		T21	11		T22	9
all_values[25]	auto[1]	auto[1]	9316285	1			T23	2		T20	1		T21	8
all_values[26]	auto[0]	auto[0]	3224060	1			T23	4		T20	1		T21	6
all_values[26]	auto[0]	auto[1]	9295896	1			T23	5		T21	6		T22	9
all_values[26]	auto[1]	auto[0]	944131	1			T23	3		T21	5		T22	1
all_values[26]	auto[1]	auto[1]	9337980	1			T20	1		T21	13		T22	1
all_values[27]	auto[0]	auto[0]	3225639	1			T23	9		T20	2		T21	8
all_values[27]	auto[0]	auto[1]	9318913	1			T23	1		T21	9		T22	9
all_values[27]	auto[1]	auto[0]	952144	1			T23	1		T21	11		T22	6
all_values[27]	auto[1]	auto[1]	9305371	1			T23	1		T21	2		T22	2
all_values[28]	auto[0]	auto[0]	3236326	1			T23	7		T20	1		T21	7
all_values[28]	auto[0]	auto[1]	9308723	1			T23	2		T21	5		T22	7
all_values[28]	auto[1]	auto[0]	942524	1			T23	3		T20	1		T21	8
all_values[28]	auto[1]	auto[1]	9314494	1			T21	10		T22	4		T1	1
all_values[29]	auto[0]	auto[0]	3228319	1			T23	6		T20	1		T21	4
all_values[29]	auto[0]	auto[1]	9356671	1			T23	1		T21	3		T22	4
all_values[29]	auto[1]	auto[0]	951346	1			T23	3		T21	12		T22	8
all_values[29]	auto[1]	auto[1]	9265731	1			T23	2		T20	1		T21	11
all_values[30]	auto[0]	auto[0]	3220480	1			T23	9		T20	1		T21	10
all_values[30]	auto[0]	auto[1]	9330046	1			T23	3		T21	6		T22	1
all_values[30]	auto[1]	auto[0]	951338	1			T21	10		T22	2		T11	2
all_values[30]	auto[1]	auto[1]	9300203	1			T20	1		T21	4		T22	2
all_values[31]	auto[0]	auto[0]	3225050	1			T23	3		T20	2		T21	14
all_values[31]	auto[0]	auto[1]	9351614	1			T23	2		T21	7		T22	10
all_values[31]	auto[1]	auto[0]	959044	1			T23	1		T21	8		T22	1
all_values[31]	auto[1]	auto[1]	9266359	1			T23	6		T21	1		T22	3