Unified Coverage Report :: Group Instance : masked_out_lower_mask_data_cov_obj

Group Instance : masked_out_lower_mask_data_cov_obj_pin4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_lower_mask_data_cov_obj_pin5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin5

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_lower_mask_data_cov_obj_pin6

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin6

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin6

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin6

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_lower_mask_data_cov_obj_pin7

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin7

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin7

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin7

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_lower_mask_data_cov_obj_pin8

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin8

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin8

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin8

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_lower_mask_data_cov_obj_pin9

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin9

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin9

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin9

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin0

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin1

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin10

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin10

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin10

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin10

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin11

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin11

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin11

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin11

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin12

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin12

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin12

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin12

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin13

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin13

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin13

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin13

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin14

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin14

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin14

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin14

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin15

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin15

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin15

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin15

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin2

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin3

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin5

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Group Instance : masked_out_upper_mask_data_cov_obj_pin6

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin6

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin6

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_var1	2	0	2	100.00	100	1	1	2
cp_var2	2	0	2	100.00	100	1	1	2

Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin6

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_var1_var2_cross	4	0	4	100.00	100	1	1	0

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350667

T32

T47

2092

T42

auto[1]

349138

T32

T47

2072

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349793

T32

T47

2170

T42

auto[1]

350012

T32

T47

1994

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174885

T32

T47

1075

T42

auto[0]

auto[1]

175782

T32

T47

1017

T42

auto[1]

auto[0]

174908

T47

1095

T42

T66

1052

auto[1]

174230

T32

T47

977

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349560

T32

T47

2062

T42

auto[1]

350245

T32

T47

2102

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349809

T32

T47

2059

T42

auto[1]

349996

T32

T47

2105

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174757

T32

T47

1000

T42

auto[0]

auto[1]

174803

T47

1062

T42

T66

1044

auto[1]

auto[0]

175052

T32

T47

1059

T42

auto[1]

175193

T32

T47

1043

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349175

T32

T47

2113

T42

auto[1]

350630

T32

T47

2051

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350076

T32

T47

2113

T42

auto[1]

349729

T32

T47

2051

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174490

T47

1073

T42

T66

1086

auto[0]

auto[1]

174685

T32

T47

1040

T42

auto[1]

auto[0]

175586

T32

T47

1040

T42

auto[1]

175044

T32

T47

1011

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349594

T32

T47

2025

T42

auto[1]

350211

T32

T47

2139

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349613

T32

T47

2105

T42

auto[1]

350192

T32

T47

2059

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174385

T32

T47

1014

T42

auto[0]

auto[1]

175209

T32

T47

1011

T42

auto[1]

auto[0]

175228

T32

T47

1091

T42

auto[1]

174983

T32

T47

1048

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349638

T32

T47

2122

T42

auto[1]

350167

T32

T47

2042

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349396

T32

T47

2134

T42

auto[1]

350409

T32

T47

2030

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174660

T32

T47

1074

T42

auto[0]

auto[1]

174978

T32

T47

1048

T42

auto[1]

auto[0]

174736

T32

T47

1060

T42

auto[1]

175431

T32

T47

982

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350555

T32

T47

2106

T42

auto[1]

349250

T32

T47

2058

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350499

T32

T47

2051

T42

auto[1]

349306

T32

T47

2113

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175666

T32

T47

1011

T42

auto[0]

auto[1]

174889

T32

T47

1095

T42

auto[1]

auto[0]

174833

T32

T47

1040

T42

auto[1]

174417

T32

T47

1018

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349675

T32

T47

2116

T42

auto[1]

349771

T32

T47

2035

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350487

T32

T47

2092

T42

auto[1]

348959

T32

T47

2059

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175543

T32

T47

1041

T42

auto[0]

auto[1]

174132

T47

1075

T42

T66

1064

auto[1]

auto[0]

174944

T32

T47

1051

T42

auto[1]

174827

T32

T47

984

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349716

T32

T47

2084

T42

auto[1]

349730

T32

T47

2067

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350172

T32

T47

2055

T42

auto[1]

349274

T32

T47

2096

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175087

T47

1042

T42

T66

1054

auto[0]

auto[1]

174629

T32

T47

1042

T42

auto[1]

auto[0]

175085

T32

T47

1013

T42

auto[1]

174645

T32

T47

1054

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

348990

T32

T47

2062

T42

auto[1]

350456

T32

T47

2089

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349201

T32

T47

2052

T42

auto[1]

350245

T32

T47

2099

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174531

T32

T47

1024

T42

auto[0]

auto[1]

174459

T47

1038

T42

T66

1051

auto[1]

auto[0]

174670

T32

T47

1028

T42

auto[1]

175786

T32

T47

1061

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349401

T32

T47

2101

T42

auto[1]

350045

T32

T47

2050

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349989

T32

T47

2077

T42

auto[1]

349457

T32

T47

2074

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174791

T32

T47

1060

T42

auto[0]

auto[1]

174610

T32

T47

1041

T42

auto[1]

auto[0]

175198

T32

T47

1017

T42

auto[1]

174847

T47

1033

T42

T66

1098

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349707

T32

T47

2061

T42

auto[1]

349739

T32

T47

2090

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349823

T32

T47

2090

T42

auto[1]

349623

T32

T47

2061

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175132

T32

T47

1040

T42

auto[0]

auto[1]

174575

T32

T47

1021

T42

auto[1]

auto[0]

174691

T47

1050

T42

T66

1068

auto[1]

175048

T32

T47

1040

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349173

T32

T47

2115

T42

auto[1]

350273

T32

T47

2036

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349635

T32

T47

2075

T42

auto[1]

349811

T32

T47

2076

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174730

T32

T47

1079

T42

auto[0]

auto[1]

174443

T47

1036

T42

T66

1109

auto[1]

auto[0]

174905

T47

996

T42

T66

1036

auto[1]

175368

T32

T47

1040

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349909

T32

T47

2080

T42

auto[1]

349537

T32

T47

2071

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349170

T32

T47

2121

T42

auto[1]

350276

T32

T47

2030

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174931

T32

T47

1074

T42

auto[0]

auto[1]

174978

T32

T47

1006

T42

auto[1]

auto[0]

174239

T32

T47

1047

T42

auto[1]

175298

T47

1024

T42

T66

1088

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350116

T32

T47

2073

T42

auto[1]

349330

T32

T47

2078

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349488

T32

T47

2050

T42

auto[1]

349958

T32

T47

2101

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175004

T32

T47

1043

T42

auto[0]

auto[1]

175112

T32

T47

1030

T42

auto[1]

auto[0]

174484

T32

T47

1007

T42

auto[1]

174846

T32

T47

1071

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350413

T32

T47

2081

T42

auto[1]

349033

T32

T47

2070

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349527

T32

T47

2070

T42

auto[1]

349919

T32

T47

2081

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175270

T32

T47

1030

T42

auto[0]

auto[1]

175143

T32

T47

1051

T42

auto[1]

auto[0]

174257

T32

T47

1040

T42

auto[1]

174776

T32

T47

1030

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350066

T32

T47

2078

T42

auto[1]

349380

T32

T47

2073

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

348973

T32

T47

1989

T42

auto[1]

350473

T32

T47

2162

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174458

T32

T47

1002

T42

auto[0]

auto[1]

175608

T47

1076

T42

T66

1050

auto[1]

auto[0]

174515

T32

T47

987

T42

auto[1]

174865

T32

T47

1086

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349293

T47

2060

T42

T66

2133

auto[1]

350153

T32

T47

2091

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349795

T32

T47

2150

T42

auto[1]

349651

T32

T47

2001

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174759

T47

1059

T42

T66

1064

auto[0]

auto[1]

174534

T47

1001

T42

T66

1069

auto[1]

auto[0]

175036

T32

T47

1091

T42

auto[1]

175117

T32

T47

1000

T66

1085

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350135

T32

T47

2152

T42

auto[1]

349311

T32

T47

1999

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349935

T32

T47

2010

T42

auto[1]

349511

T32

T47

2141

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174984

T32

T47

1034

T42

auto[0]

auto[1]

175151

T32

T47

1118

T42

auto[1]

auto[0]

174951

T32

T47

976

T42

auto[1]

174360

T32

T47

1023

T42

Summary for Variable cp_var1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350027

T32

T47

2022

T42

auto[1]

349419

T32

T47

2129

T42

Summary for Variable cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_var2

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350183

T32

T47

2049

T42

auto[1]

349263

T32

T47

2102

T42

Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_var1_var2_cross

Bins

cp_var1

cp_var2

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175073

T47

994

T42

T66

1038

auto[0]

auto[1]

174954

T32

T47

1028

T42

auto[1]

auto[0]

175110

T32

T47

1055

T42

auto[1]

174309

T32

T47

1074

T42