Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6844537	1			T23	9		T20	4		T21	28
all_pins[1]	6844537	1			T23	9		T20	4		T21	28
all_pins[2]	6844537	1			T23	9		T20	4		T21	28
all_pins[3]	6844537	1			T23	9		T20	4		T21	28
all_pins[4]	6844537	1			T23	9		T20	4		T21	28
all_pins[5]	6844537	1			T23	9		T20	4		T21	28
all_pins[6]	6844537	1			T23	9		T20	4		T21	28
all_pins[7]	6844537	1			T23	9		T20	4		T21	28
all_pins[8]	6844537	1			T23	9		T20	4		T21	28
all_pins[9]	6844537	1			T23	9		T20	4		T21	28
all_pins[10]	6844537	1			T23	9		T20	4		T21	28
all_pins[11]	6844537	1			T23	9		T20	4		T21	28
all_pins[12]	6844537	1			T23	9		T20	4		T21	28
all_pins[13]	6844537	1			T23	9		T20	4		T21	28
all_pins[14]	6844537	1			T23	9		T20	4		T21	28
all_pins[15]	6844537	1			T23	9		T20	4		T21	28
all_pins[16]	6844537	1			T23	9		T20	4		T21	28
all_pins[17]	6844537	1			T23	9		T20	4		T21	28
all_pins[18]	6844537	1			T23	9		T20	4		T21	28
all_pins[19]	6844537	1			T23	9		T20	4		T21	28
all_pins[20]	6844537	1			T23	9		T20	4		T21	28
all_pins[21]	6844537	1			T23	9		T20	4		T21	28
all_pins[22]	6844537	1			T23	9		T20	4		T21	28
all_pins[23]	6844537	1			T23	9		T20	4		T21	28
all_pins[24]	6844537	1			T23	9		T20	4		T21	28
all_pins[25]	6844537	1			T23	9		T20	4		T21	28
all_pins[26]	6844537	1			T23	9		T20	4		T21	28
all_pins[27]	6844537	1			T23	9		T20	4		T21	28
all_pins[28]	6844537	1			T23	9		T20	4		T21	28
all_pins[29]	6844537	1			T23	9		T20	4		T21	28
all_pins[30]	6844537	1			T23	9		T20	4		T21	28
all_pins[31]	6844537	1			T23	9		T20	4		T21	28

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	135821121	1			T23	243		T20	95		T21	731
values[0x1]	83204063	1			T23	45		T20	33		T21	165
transitions[0x0=>0x1]	49802037	1			T23	42		T20	16		T21	128
transitions[0x1=>0x0]	49801872	1			T23	42		T20	16		T21	128

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	4243141	1			T23	5		T20	4		T21	23
all_pins[0]	values[0x1]	2601396	1			T23	4		T21	5		T22	6
all_pins[0]	transitions[0x0=>0x1]	1608347	1			T23	3		T21	5		T22	3
all_pins[0]	transitions[0x1=>0x0]	1610088	1			T23	4		T21	1		T1	3
all_pins[1]	values[0x0]	4246503	1			T23	9		T20	1		T21	19
all_pins[1]	values[0x1]	2598034	1			T20	3		T21	9		T22	7
all_pins[1]	transitions[0x0=>0x1]	1554895	1			T20	3		T21	7		T22	4
all_pins[1]	transitions[0x1=>0x0]	1558257	1			T23	4		T21	3		T22	3
all_pins[2]	values[0x0]	4246911	1			T23	6		T20	2		T21	20
all_pins[2]	values[0x1]	2597626	1			T23	3		T20	2		T21	8
all_pins[2]	transitions[0x0=>0x1]	1555922	1			T23	3		T21	8		T22	3
all_pins[2]	transitions[0x1=>0x0]	1556330	1			T20	1		T21	9		T22	4
all_pins[3]	values[0x0]	4239835	1			T23	9		T20	1		T21	28
all_pins[3]	values[0x1]	2604702	1			T20	3		T1	3		T11	8
all_pins[3]	transitions[0x0=>0x1]	1560866	1			T20	1		T1	1		T11	3
all_pins[3]	transitions[0x1=>0x0]	1553790	1			T23	3		T21	8		T22	6
all_pins[4]	values[0x0]	4246194	1			T23	3		T20	4		T21	27
all_pins[4]	values[0x1]	2598343	1			T23	6		T21	1		T22	4
all_pins[4]	transitions[0x0=>0x1]	1551627	1			T23	6		T21	1		T22	4
all_pins[4]	transitions[0x1=>0x0]	1557986	1			T20	3		T1	3		T11	6
all_pins[5]	values[0x0]	4248269	1			T23	9		T20	4		T21	23
all_pins[5]	values[0x1]	2596268	1			T21	5		T1	3		T11	3
all_pins[5]	transitions[0x0=>0x1]	1551429	1			T21	4		T1	3		T11	2
all_pins[5]	transitions[0x1=>0x0]	1553504	1			T23	6		T22	4		T11	3
all_pins[6]	values[0x0]	4249546	1			T23	7		T20	4		T21	22
all_pins[6]	values[0x1]	2594991	1			T23	2		T21	6		T22	1
all_pins[6]	transitions[0x0=>0x1]	1553149	1			T23	2		T21	5		T22	1
all_pins[6]	transitions[0x1=>0x0]	1554426	1			T21	4		T1	3		T11	3
all_pins[7]	values[0x0]	4247286	1			T23	9		T20	4		T21	24
all_pins[7]	values[0x1]	2597251	1			T21	4		T22	3		T1	1
all_pins[7]	transitions[0x0=>0x1]	1553581	1			T21	2		T22	2		T1	1
all_pins[7]	transitions[0x1=>0x0]	1551321	1			T23	2		T21	4		T11	8
all_pins[8]	values[0x0]	4234820	1			T23	9		T20	4		T21	26
all_pins[8]	values[0x1]	2609717	1			T21	2		T22	7		T1	1
all_pins[8]	transitions[0x0=>0x1]	1564725	1			T21	2		T22	5		T1	1
all_pins[8]	transitions[0x1=>0x0]	1552259	1			T21	4		T22	1		T1	1
all_pins[9]	values[0x0]	4243748	1			T23	9		T20	4		T21	22
all_pins[9]	values[0x1]	2600789	1			T21	6		T22	3		T1	2
all_pins[9]	transitions[0x0=>0x1]	1551863	1			T21	6		T22	1		T1	2
all_pins[9]	transitions[0x1=>0x0]	1560791	1			T21	2		T22	5		T1	1
all_pins[10]	values[0x0]	4241407	1			T23	9		T20	4		T21	26
all_pins[10]	values[0x1]	2603130	1			T21	2		T22	1		T1	2
all_pins[10]	transitions[0x0=>0x1]	1554393	1			T21	2		T11	6		T13	3
all_pins[10]	transitions[0x1=>0x0]	1552052	1			T21	6		T22	2		T11	4
all_pins[11]	values[0x0]	4247808	1			T23	8		T20	4		T21	28
all_pins[11]	values[0x1]	2596729	1			T23	1		T22	6		T1	2
all_pins[11]	transitions[0x0=>0x1]	1550481	1			T23	1		T22	6		T11	6
all_pins[11]	transitions[0x1=>0x0]	1556882	1			T21	2		T22	1		T11	3
all_pins[12]	values[0x0]	4244476	1			T23	9		T20	3		T21	12
all_pins[12]	values[0x1]	2600061	1			T20	1		T21	16		T22	9
all_pins[12]	transitions[0x0=>0x1]	1556914	1			T20	1		T21	16		T22	4
all_pins[12]	transitions[0x1=>0x0]	1553582	1			T23	1		T22	1		T11	9
all_pins[13]	values[0x0]	4241393	1			T23	8		T20	1		T21	19
all_pins[13]	values[0x1]	2603144	1			T23	1		T20	3		T21	9
all_pins[13]	transitions[0x0=>0x1]	1554073	1			T23	1		T20	2		T21	3
all_pins[13]	transitions[0x1=>0x0]	1550990	1			T21	10		T22	6		T1	5
all_pins[14]	values[0x0]	4241427	1			T23	6		T20	1		T21	25
all_pins[14]	values[0x1]	2603110	1			T23	3		T20	3		T21	3
all_pins[14]	transitions[0x0=>0x1]	1552577	1			T23	2		T22	2		T1	2
all_pins[14]	transitions[0x1=>0x0]	1552611	1			T21	6		T22	4		T11	7
all_pins[15]	values[0x0]	4239476	1			T23	9		T20	4		T21	28
all_pins[15]	values[0x1]	2605061	1			T22	2		T1	1		T11	8
all_pins[15]	transitions[0x0=>0x1]	1556363	1			T22	1		T11	6		T14	1
all_pins[15]	transitions[0x1=>0x0]	1554412	1			T23	3		T20	3		T21	3
all_pins[16]	values[0x0]	4249064	1			T23	5		T20	4		T21	26
all_pins[16]	values[0x1]	2595473	1			T23	4		T21	2		T22	14
all_pins[16]	transitions[0x0=>0x1]	1550443	1			T23	4		T21	2		T22	13
all_pins[16]	transitions[0x1=>0x0]	1560031	1			T22	1		T1	1		T11	5
all_pins[17]	values[0x0]	4248361	1			T23	9		T20	1		T21	27
all_pins[17]	values[0x1]	2596176	1			T20	3		T21	1		T22	2
all_pins[17]	transitions[0x0=>0x1]	1552882	1			T20	3		T21	1		T1	5
all_pins[17]	transitions[0x1=>0x0]	1552179	1			T23	4		T21	2		T22	12
all_pins[18]	values[0x0]	4246692	1			T23	4		T20	1		T21	24
all_pins[18]	values[0x1]	2597845	1			T23	5		T20	3		T21	4
all_pins[18]	transitions[0x0=>0x1]	1553801	1			T23	5		T21	3		T22	7
all_pins[18]	transitions[0x1=>0x0]	1552132	1			T22	1		T1	5		T11	5
all_pins[19]	values[0x0]	4247796	1			T23	9		T20	4		T21	22
all_pins[19]	values[0x1]	2596741	1			T21	6		T22	1		T1	3
all_pins[19]	transitions[0x0=>0x1]	1553301	1			T21	5		T22	1		T1	3
all_pins[19]	transitions[0x1=>0x0]	1554405	1			T23	5		T20	3		T21	3
all_pins[20]	values[0x0]	4242058	1			T23	7		T20	4		T21	23
all_pins[20]	values[0x1]	2602479	1			T23	2		T21	5		T22	5
all_pins[20]	transitions[0x0=>0x1]	1560735	1			T23	2		T21	4		T22	4
all_pins[20]	transitions[0x1=>0x0]	1554997	1			T21	5		T1	2		T11	5
all_pins[21]	values[0x0]	4242366	1			T23	8		T20	4		T21	26
all_pins[21]	values[0x1]	2602171	1			T23	1		T21	2		T22	3
all_pins[21]	transitions[0x0=>0x1]	1552623	1			T21	2		T22	3		T1	2
all_pins[21]	transitions[0x1=>0x0]	1552931	1			T23	1		T21	5		T22	5
all_pins[22]	values[0x0]	4245443	1			T23	9		T20	4		T21	26
all_pins[22]	values[0x1]	2599094	1			T21	2		T22	2		T1	1
all_pins[22]	transitions[0x0=>0x1]	1552390	1			T21	1		T22	2		T1	1
all_pins[22]	transitions[0x1=>0x0]	1555467	1			T23	1		T21	1		T22	3
all_pins[23]	values[0x0]	4247490	1			T23	7		T20	4		T21	17
all_pins[23]	values[0x1]	2597047	1			T23	2		T21	11		T22	6
all_pins[23]	transitions[0x0=>0x1]	1553183	1			T23	2		T21	9		T22	6
all_pins[23]	transitions[0x1=>0x0]	1555230	1			T22	2		T1	1		T11	2
all_pins[24]	values[0x0]	4246563	1			T23	7		T20	4		T21	21
all_pins[24]	values[0x1]	2597974	1			T23	2		T21	7		T22	2
all_pins[24]	transitions[0x0=>0x1]	1554055	1			T23	2		T21	7		T11	2
all_pins[24]	transitions[0x1=>0x0]	1553128	1			T23	2		T21	11		T22	4
all_pins[25]	values[0x0]	4243205	1			T23	7		T20	1		T21	20
all_pins[25]	values[0x1]	2601332	1			T23	2		T20	3		T21	8
all_pins[25]	transitions[0x0=>0x1]	1553573	1			T23	2		T20	3		T21	5
all_pins[25]	transitions[0x1=>0x0]	1550215	1			T23	2		T21	4		T22	2
all_pins[26]	values[0x0]	4237921	1			T23	9		T20	1		T21	15
all_pins[26]	values[0x1]	2606616	1			T20	3		T21	13		T22	1
all_pins[26]	transitions[0x0=>0x1]	1559458	1			T21	8		T1	2		T11	6
all_pins[26]	transitions[0x1=>0x0]	1554174	1			T23	2		T21	3		T22	3
all_pins[27]	values[0x0]	4244715	1			T23	8		T20	4		T21	26
all_pins[27]	values[0x1]	2599822	1			T23	1		T21	2		T22	2
all_pins[27]	transitions[0x0=>0x1]	1554121	1			T23	1		T21	2		T22	2
all_pins[27]	transitions[0x1=>0x0]	1560915	1			T20	3		T21	13		T22	1
all_pins[28]	values[0x0]	4244428	1			T23	9		T20	4		T21	18
all_pins[28]	values[0x1]	2600109	1			T21	10		T22	4		T1	3
all_pins[28]	transitions[0x0=>0x1]	1553362	1			T21	9		T22	3		T1	3
all_pins[28]	transitions[0x1=>0x0]	1553075	1			T23	1		T21	1		T22	1
all_pins[29]	values[0x0]	4250309	1			T23	8		T20	1		T21	17
all_pins[29]	values[0x1]	2594228	1			T23	1		T20	3		T21	11
all_pins[29]	transitions[0x0=>0x1]	1552101	1			T23	1		T20	3		T21	7
all_pins[29]	transitions[0x1=>0x0]	1557982	1			T21	6		T22	2		T15	4
all_pins[30]	values[0x0]	4241235	1			T23	9		T20	1		T21	24
all_pins[30]	values[0x1]	2603302	1			T20	3		T21	4		T22	2
all_pins[30]	transitions[0x0=>0x1]	1558671	1			T21	2		T11	6		T13	2
all_pins[30]	transitions[0x1=>0x0]	1549597	1			T23	1		T21	9		T22	1
all_pins[31]	values[0x0]	4241235	1			T23	4		T20	4		T21	27
all_pins[31]	values[0x1]	2603302	1			T23	5		T21	1		T22	3
all_pins[31]	transitions[0x0=>0x1]	1556133	1			T23	5		T22	3		T13	3
all_pins[31]	transitions[0x1=>0x0]	1556133	1			T20	3		T21	3		T22	2